A dual-operating mode silicon carbide power device structure and manufacturing method thereof

Abstract

The invention discloses a dual-working mode silicon carbide power device structure and a manufacturing method thereof. The power device structure comprises a Bipolar part and a MOSFET part, and specifically comprises an N-type substrate and a collector metal layer arranged at the bottom of the N-type substrate, a P-base region is arranged on the top of the N-type substrate, a plurality of gate oxide layers and a trench gate vertically arranged in the corresponding gate oxide layer are arranged on the P-base region through a groove; a plurality of N+ injection regions and P+ injection regions are arranged in the P-base region, a floating base and an emitter are arranged at positions corresponding to the N+ injection region and the P+ injection region on both sides of the top of the P-base region, and the floating base and the emitter are isolated from each other by an ILD external insulating layer, and the manufacturing of the power device structure comprises the steps of growing an epitaxial layer, growing a field oxide layer, etc., and the process flow is compatible with the process flow of an ordinary silicon carbide MOSFET, and no new steps need to be added.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a dual-operating mode silicon carbide power device structure and a manufacturing method thereof. Background Art

[0002] Silicon carbide (SiC) is a new wide bandgap semiconductor material with excellent physical, chemical and electrical properties. The breakdown electric field strength of silicon carbide is 10 times that of traditional silicon, the thermal conductivity is 3 times that of silicon, and it has a higher switching frequency, which can reduce the loss and volume of energy storage components in the circuit. In theory, silicon carbide devices can work in high-temperature environments and have excellent radiation resistance, which greatly improves their high-temperature stability. This makes power semiconductor devices based on silicon carbide very attractive and promising in high-power and high-temperature application environments. The main advantages of silicon carbide (SiC) devices are wide bandgap and high critical electric field, which can reach a breakdown voltage value 10 times that of silicon devices within the same drift region thickness, thereby greatly reducing the drift region thickness and reducing the on-resistance.

[0003] Compared with traditional silicon IGBT, the advantages of SiC MOSFET are: there is no turn-on inflection point voltage; the high critical electric field (about 10 times that of silicon) allows SiC to greatly reduce the thickness of the drift region at the same voltage; the wide bandgap (3 times that of silicon) makes it easier for SiC to reach the maximum operating junction temperature of 175 degrees or even 200 degrees. Due to these characteristics, SiC can greatly reduce the chip conduction voltage drop and switching loss. At the same time, since SiC MOSFET itself has a body diode, no external parallel reverse recovery diode is required, which greatly improves the integration of the system. However, since the current mainstream device of silicon carbide is MOSFET, it is difficult to achieve a high current density like IGBT. The use of SiC IGBT technology can solve this problem, but due to the wide bandgap characteristics of SiC, the turn-on inflection point voltage is much greater than Si IGBT, and the power consumption will be greatly increased under low current and low load conditions. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a dual-working mode silicon carbide power device structure and a manufacturing method thereof, which can take into account both the on-state voltage drop under low current and the high current carrying capacity and whose manufacturing process is compatible with the process of ordinary silicon carbide MOSFET, in response to the above-mentioned defects of the prior art.

[0005] The objective of the present invention is to achieve the following technical solution: a dual-working mode silicon carbide power device structure, comprising a device structure body, the device structure body comprising a Bipolar part and a MOSFET part, and the Bipolar part and the MOSFET part both comprising an N-type substrate and a collector metal layer arranged at the bottom of the N-type substrate, a P-base region is arranged on the top of the N-type substrate, a plurality of gate oxide layers and a trench gate vertically arranged in the corresponding gate oxide layer are arranged on the P-base region through a groove extending into the N-type substrate; a plurality of N+ injection regions and P+ injection regions extending into the P-base region are arranged on the top of the P-base region, a floating base and an emitter are arranged at positions corresponding to the N+ injection regions and the P+ injection regions on both sides of the top of the P-base region, and the floating base and the emitter are isolated by an ILD outer insulating layer, and the gate oxide layer and the top of the trench gate are isolated from the floating base or the emitter at the corresponding position by an ILD inner insulating layer.

[0006] Furthermore, a plurality of planar gates are arranged on top of the P-base region laterally in the ILD outer insulating layer, and a group of N+ injection regions are respectively arranged at positions corresponding to the left and right ends of the planar gates, and the left and right ends of the planar gates are respectively connected to the N+ injection regions at corresponding positions through the ILD pads.

[0007] Furthermore, the layout layout within the Bipolar part includes a first N+ injection region and a second N+ injection region arranged vertically, and several groups of planar gates arranged horizontally between the two N+ injection regions, and the first N+ injection region between two adjacent planar gates is isolated by a first P+ injection region; the layout layout within the MOSFET part includes a third N+ injection region and a fourth N+ injection region arranged vertically, and a second P+ injection region arranged vertically between the two N+ injection regions.

[0008] Furthermore, the device structure includes at least one group of Bipolar parts and at least two groups of MOSFET parts, and the group number ratio of the MOSFET parts to the Bipolar parts is greater than or equal to 2:1; two adjacent third N+ injection regions and fourth N+ injection regions in the MOSFET parts are separated by a trench gate.

[0009] Furthermore, the Bipolar part is arranged in a frame area surrounded by the trench gate outside the MOSFET part, and the layout layout within the Bipolar part includes a first N+ injection area, a second N+ injection area and a third N+ injection area, and the first N+ injection area and the third N+ injection area are connected by a planar gate, and the upper and lower sides of the first N+ injection area and the second N+ injection area are separated by a first P+ injection area.

[0010] Furthermore, the layout layout within the MOSFET part includes a fourth N+ injection region arranged on the front and rear sides of the MOSFET part respectively, a second P+ injection region arranged within the enclosed area of ​​the fourth N+ injection region, a fifth N+ injection region arranged vertically, a sixth N+ injection region and a third P+ injection region arranged vertically between the two N+ injection regions.

[0011] A method for manufacturing a silicon carbide power device structure, the manufacturing method mainly comprising the following steps:

[0012] 1) Grow an epitaxial layer on the selected N epitaxial silicon substrate, with the resistivity and thickness determined by the breakdown voltage requirement of the device;

[0013] 2) First, the terminal area is photolithographically defined, followed by implantation and activation, and then the field oxide layer is grown;

[0014] 3) Define the active area and perform etching, then photolithography to define the p-base interval in the active area, perform implantation and activation;

[0015] 4) Photolithography defines the trench area and etches the trench, then grows the gate oxide layer both in the trench and on the surface;

[0016] 5) Deposit polysilicon in the trench area and on the surface and dope it, then perform photolithography and etching on the polysilicon to form a trench gate (G1) and a planar gate (G2); the two gates can be realized in the same step without adding new process steps;

[0017] 6) Self-aligned or photolithographic nplus implantation with trench gate and planar gate followed by activation and definition, implantation and activation of pplus contact layer;

[0018] 7) Deposition of dielectric layer; photolithography of contact holes, etching of insulating layer, Ni silicide to form ohmic contact, then sputtering of top metal, photolithography and etching of metal; when defining the metal, it is necessary to note that the floating base of the Bipolar part cannot be connected to the emitter, then depositing the passivation layer, photolithography and etching of the passivation layer, and completing the production of the top structure;

[0019] 8) Finally, the wafer is thinned to a specific thickness and a back metal is deposited to complete the manufacturing process of the silicon carbide power device structure.

[0020] The beneficial technical effect of the present invention is that the silicon carbide power device structure described in the present invention has two working modes, working in MOSFET mode at low current and working in bipolar mode at high current, which can effectively solve the problem of working current density of silicon carbide devices. At the same time, the silicon carbide device in the present invention has two gates, one gate is used to turn on the device, and the other gate is used to speed up the closing of the device in bipolar mode; the manufacturing process of the device structure can use a planar structure or a trench structure, and its specific manufacturing process is fully compatible with ordinary trench or planar SiCMOSFET, and no new process steps need to be added, thereby saving manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic cross-sectional view of the device structure of the present invention;

[0022] Figure 2 is an equivalent circuit diagram of the device structure of the present invention;

[0023] Figure 3 A gate control scheme for the device structure of the present invention;

[0024] Figure 4 A first layout scheme of the device structure of the present invention;

[0025] Figure 5 This is a second layout scheme of the device structure of the present invention;

[0026] Figure 6 This is the third layout scheme of the device structure described in the present invention. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to more clearly understand the objectives, technical solutions and advantages of the present invention, the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0028] In the description of the present invention, it is necessary to understand that the orientation or position relationship indicated by the terms such as "up", "down", "left", "right", "inside", "outside", "horizontal" and "vertical" is based on the orientation or position relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention, rather than indicating or implying that the device or original referred to must have a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0029] like Figure 1-6As shown, a dual-working mode silicon carbide power device structure described in the present invention includes a device structure body, the device structure body includes a Bipolar part and a MOSFET part, and the Bipolar part and the MOSFET part both include an N-type substrate 1 and a collector metal layer 2 arranged at the bottom of the N-type substrate 1, a P-base region 3 is arranged on the top of the N-type substrate 1, and a plurality of gate oxide layers 4 and a trench gate G1 vertically arranged in the corresponding gate oxide layer 4 are arranged on the P-base region 3 through a groove extending into the N-type substrate 1, and a p-type protective layer can be added at the bottom of the groove The bottom of the trench is protected; the top of the P-base region 3 is provided with a plurality of N+ injection regions and P+ injection regions extending into the P-base region 3, a charge storage layer can be added to the bottom of the p-base region 3 to further reduce the on-resistance, and a floating base 5 and an emitter 6 are provided at positions corresponding to the N+ injection region and the P+ injection region on both sides of the top of the P-base region 3, and the floating base 5 and the emitter 6 are isolated from each other by an ILD outer insulating layer 7, and the gate oxide layer 4 and the top of the trench gate G1 are isolated from the floating base 5 or the emitter 6 at the corresponding position by an ILD inner insulating layer 8.

[0030] Reference Figure 1 As shown, a plurality of planar gates G2 arranged on the top of the P-base region 3 are disposed laterally in the ILD outer insulating layer 7, and a group of N+ injection regions are disposed at the positions corresponding to the left and right ends of the planar gate G2, respectively. The left and right ends of the planar gate G2 can be connected to the N+ injection regions at the corresponding positions through the ILD pads 9. By forming the planar gate G2 in a direction different from the trench gate G1, the area occupied by the planar gate can be effectively reduced; the Biploar portion only occupies less than 1 / 3 of the active area of ​​the device, thereby reducing the impact on loss at low current.

[0031] The device structure has two working modes. It mainly works in MOSFET mode. In this way, under low load and low current conditions, the device is in MOSFET working mode, which can give full play to the advantages of low on-resistance. Under high load and overload current conditions, the Bipolar mode starts to work, which can effectively increase the current density. The device can achieve low on-resistance of MOS mode under low current (avoiding high turn-on inflection point voltage) and Bipolar mode under high current. At the same time, the present invention introduces an optional dual-gate concept, which can perform dynamic switching faster.

[0032] Reference Figure 4As shown, the layout layout in the Bipolar part includes a first N+ injection region 10 and a second N+ injection region 11 arranged vertically, and a plurality of groups of planar gates G2 arranged horizontally between the two N+ injection regions, and the first N+ injection region 10 between two adjacent planar gates G2 is isolated by a first P+ injection region 12; the layout layout in the MOSFET part includes a third N+ injection region 13 and a fourth N+ injection region 14 arranged vertically, and a second P+ injection region 15 arranged vertically between the two N+ injection regions. This layout layout scheme arranges the planar gates horizontally and vertically to reduce the occupation of the active area.

[0033] Reference Figure 5 As shown, the device structure includes at least one group of Bipolar parts and at least two groups of MOSFET parts, and the group number ratio of the MOSFET part to the Bipolar part is greater than or equal to 2:1 to reduce the impact on the MOSFET part when the low current is turned on; the two adjacent third N+ injection areas 13 and the fourth N+ injection area 14 in the MOSFET part are separated by a trench gate G1.

[0034] Reference Figure 6 As shown, the Bipolar part is arranged in a frame-shaped area surrounded by the trench gate outside the MOSFET part, and the layout layout in the Bipolar part includes a first N+ injection area 10, a second N+ injection area 11 and a third N+ injection area 13, and the first N+ injection area 10 and the third N+ injection area 13 and the second N+ injection area 11 and the third N+ injection area 13 are connected through a planar gate G2, and the upper and lower sides of the first N+ injection area 10 and the second N+ injection area 11 are separated by a first P+ injection area 12. The layout layout in the MOSFET part includes a fourth N+ injection area 14 arranged on the front and rear sides of the MOSFET part, a second P+ injection area 15 arranged in the area surrounded by the fourth N+ injection area 14, a fifth N+ injection area 16 arranged vertically, a sixth N+ injection area 17 and a third P+ injection area 18 arranged vertically between the two N+ injection areas. In addition, this layout layout scheme can also arrange more MOSFET parts vertically.

[0035] A method for manufacturing a silicon carbide power device structure, the manufacturing method mainly comprising the following steps:

[0036] 1) Grow an epitaxial layer on the selected N epitaxial silicon substrate, with the resistivity and thickness determined by the breakdown voltage requirement of the device;

[0037] 2) First, the terminal area is photolithographically defined, followed by implantation and activation, and then the field oxide layer is grown;

[0038] 3) Define the active area and perform etching, then photolithography to define the p-base interval in the active area, perform implantation and activation;

[0039] 4) Photolithography defines the trench area and etches the trench, then grows the gate oxide layer both in the trench and on the surface;

[0040] 5) Deposit polysilicon in the trench area and on the surface and dope it, then perform photolithography and etching on the polysilicon to form a trench gate G1 and a planar gate G2; the two gates can be realized in the same step without adding new process steps. In addition, the trench gate G1 can be formed with a planar type instead of a trench;

[0041] 6) Self-aligned or photolithographic nplus implantation with trench gate and planar gate followed by activation and definition, implantation and activation of pplus contact layer;

[0042] 7) Deposition of dielectric layer; photolithography of contact holes, etching of insulating layer, Ni silicide to form ohmic contact, then sputtering of top metal, photolithography and etching of metal; when defining the metal, it is necessary to note that the floating base of the Bipolar part cannot be connected to the emitter, then depositing the passivation layer, photolithography and etching of the passivation layer, and completing the production of the top structure;

[0043] 8) Finally, the wafer is thinned to a specific thickness and a back metal is deposited to complete the manufacturing process of the silicon carbide power device structure.

[0044] The present invention can solve the problem of low current density of traditional SiC MOSFET unipolar devices, while avoiding the problems of high on-voltage, slow switching speed, and small reverse safe working area that are easy to generate in traditional SiC IGBT. Since the bipolar transistor in this structure does not have an npnp thyristor structure, the latch effect phenomenon will not occur, and the safe working area is large. The bipolar mode of this device uses p-base as the base region (narrow base), which is different from the traditional IGBT using N-drift as the base region (narrow base). Therefore, the base region mobility in the present invention is much greater than that of conventional IGBT devices, which can effectively improve the bipolar gain.

[0045] Different from IGBT, where BV is BVceo (open-base breakdown voltage). The breakdown voltage of the bipolar structure in this device depends on BVcbo (open-emitter breakdown voltage). The introduction of the bipolar structure will not reduce the breakdown voltage, so the selection of epitaxy can maintain the same resistivity and thickness as ordinary MOSFET, without making additional sacrifices in breakdown voltage and conduction characteristics. Optional G2 provides a channel for fast shutdown and carrier extraction in bipolar mode. Its specific manufacturing process is fully compatible with ordinary trench or planar SiC MOSFET, and no new process steps need to be added, thus saving manufacturing costs.

[0046] The specific embodiments described herein are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A dual-operating mode silicon carbide power device structure, comprising a device structure body, characterized in that: The device structure body includes a Bipolar part and a MOSFET part, and the Bipolar part and the MOSFET part both include an N-type substrate and a collector metal layer arranged at the bottom of the N-type substrate, a P-base region is arranged on the top of the N-type substrate, and a plurality of gate oxide layers and a trench gate vertically arranged in the corresponding gate oxide layer are arranged on the P-base region through a groove extending into the N-type substrate; a plurality of N+ injection regions and P+ injection regions extending into the P-base region are arranged on the top of the P-base region, and a floating base and an emitter are arranged at positions corresponding to the N+ injection regions and the P+ injection regions on both sides of the top of the P-base region, and the floating base and the emitter are isolated from each other by an ILD outer insulating layer, and the tops of the gate oxide layer and the trench gate are isolated from the floating base or the emitter at the corresponding position by an ILD inner insulating layer.

2. The dual-operating mode silicon carbide power device structure according to claim 1, characterized in that: A plurality of planar gates arranged on the top of the P-base region are arranged laterally in the ILD outer insulating layer, and a group of N+ injection regions are respectively arranged at positions corresponding to the left and right ends of the planar gates, and the left and right ends of the planar gates are respectively connected to the N+ injection regions at corresponding positions through ILD pads.

3. The dual-operating mode silicon carbide power device structure according to claim 2, characterized in that: The layout layout in the Bipolar part includes a first N+ injection region and a second N+ injection region arranged vertically, and several groups of planar gates arranged horizontally between the two N+ injection regions, and the first N+ injection region between two adjacent planar gates is isolated by a first P+ injection region; the layout layout in the MOSFET part includes a third N+ injection region and a fourth N+ injection region arranged vertically, and a second P+ injection region arranged vertically between the two N+ injection regions.

4. The dual-operating mode silicon carbide power device structure according to claim 3, characterized in that: The device structure body includes at least one group of Bipolar parts and at least two groups of MOSFET parts, and the group number ratio of the MOSFET parts to the Bipolar parts is greater than or equal to 2:1; two adjacent third N+ injection regions and fourth N+ injection regions in the MOSFET parts are separated by a trench gate.

5. The dual-operating mode silicon carbide power device structure according to claim 2, characterized in that: The Bipolar part is arranged in a frame-shaped area surrounded by the trench gate outside the MOSFET part. The layout layout in the Bipolar part includes a first N+ injection area, a second N+ injection area and a third N+ injection area. The first N+ injection area and the third N+ injection area are connected as well as the second N+ injection area and the third N+ injection area are connected through a planar gate. The upper and lower sides of the first N+ injection area and the second N+ injection area are separated by the first P+ injection area.

6. The dual-operating mode silicon carbide power device structure according to claim 5, characterized in that: The layout layout within the MOSFET part includes a fourth N+ injection region arranged on the front and rear sides of the MOSFET part respectively, a second P+ injection region arranged in the area enclosed by the fourth N+ injection region, a fifth N+ injection region arranged vertically, a sixth N+ injection region and a third P+ injection region arranged vertically between the two N+ injection regions.

7. A method for manufacturing a silicon carbide power device structure according to any one of claims 1 to 6, characterized in that: The production method comprises the following steps: 1) Grow an epitaxial layer on the selected N epitaxial silicon substrate, with the resistivity and thickness determined by the breakdown voltage requirement of the device; 2) First, the terminal area is photolithographically defined, followed by implantation and activation, and then the field oxide layer is grown; 3) Define the active area and perform etching, then photolithography to define the p-base interval in the active area, perform implantation and activation; 4) Photolithography defines the trench area and etches the trench, then grows the gate oxide layer both in the trench and on the surface; 5) Deposit polysilicon in the trench area and on the surface and dope it, then perform photolithography and etching on the polysilicon to form a trench gate (G1) and a planar gate (G2); the two gates are implemented in the same step without adding new process steps; 6) Self-aligned or photolithographic nplus implantation with trench gate and planar gate followed by activation and definition, implantation and activation of pplus contact layer; 7) Deposition of dielectric layer; photolithography of contact holes, etching of insulating layer, Ni silicide to form ohmic contact, then sputtering of top metal, photolithography and etching of metal; when defining the metal, it is necessary to note that the floating base of the Bipolar part cannot be connected to the emitter, then depositing the passivation layer, photolithography and etching of the passivation layer, and completing the production of the top structure; 8) Finally, the wafer is thinned to a specific thickness and a back metal is deposited to complete the manufacturing process of the silicon carbide power device structure.

Images