Device with sensor, controller and corresponding method

Abstract

Embodiments of the present disclosure relate to a device having a sensor, a controller, and a corresponding method. A sensor device, a controller, and a corresponding method are provided. In the sensor device, an analog sensor signal is converted into a first digital signal. A second digital signal is generated based on the first digital signal using a ∑-△ modulator. A pulse-width modulated signal is generated based on the second digital signal.

Description

Technical Field

[0001] The present application relates to a device having a sensor, a controller, and a corresponding method. Some embodiments relate to communication between the device and the controller by means of pulse width modulated signals. Background Art

[0002] Devices with sensors, also referred to below as sensor devices, are used to acquire one or more physical variables. Examples include magnetic field sensors, pressure sensors, temperature sensors, current sensors, voltage sensors, and the like. In most systems, signals representing the acquired physical variables are transmitted to a controller, which further processes the information obtained about the acquired variable or variables. An example of this is automotive applications, where data such as wheel speed, tire pressure, temperature, and the like are acquired using multiple sensors in the vehicle. The acquired information is then transmitted from the sensor devices to one or more controllers, typically referred to as ECUs (Electronic Control Units).

[0003] For this transmission, the variables obtained from the corresponding sensors must be converted into corresponding electrical signals and then transmitted. A method for this is pulse width modulation (PWM), in which signal pulses are transmitted, wherein the duty cycle corresponds to the signal value, for example, in terms of the pulse duration and the total cycle length or the pulse interval. For example, a pulse width modulation (PWM) can be used to transmit a signal with a value of 2. 8 -1=255 different values ​​of pulses for an 8-bit signal, pulses with 255 different pulse durations can be used, for example with 1 to 255 time units depending on the code value.

[0004] For a fixed frequency of the underlying clock signal, which determines the time unit of the pulse width modulated signal, a high resolution results in a low transmission rate, or a low resolution results in a high transmission rate. For example, with an 8 MHz clock signal, the length of the time unit is 125 ms. For a resolution of 14 bits, 2 bits are required for one cycle of the pulse width modulated signal. 14 -1 clock cycle, which corresponds to a cycle time of 2047ms for the transmitted information. At a resolution of 8 bits, 2 8 One clock cycle correspondingly requires a cycle duration of the pulse width modulated signal of 232 μs. As a frequency, this corresponds to approximately 30 kHz instead of approximately 500 Hz in the case of 14-bit resolution.

[0005] The cycle of a pulse width modulated signal (also referred to as PWM duration) is here essentially understood to be the time required for a pulse of maximum duration, for example, 2 for a 14-bit resolution. 14- 1 clock cycle, or 2 for 8-bit resolution 8 -1 clock cycle. Within a cycle, the pulse-width modulated signal is in a first state, such as "high" (e.g., a first voltage, a first current), for a first duration, and in a second state (e.g., a second voltage, a second current), such as "low," for a second duration, and the duty cycle (the ratio of the duration of the first state to the duration of a cycle) indicates the value encoded by the corresponding pulse. When the cycle duration is fixed and known, the same information is also present in the duration of the first state, the duration of the second state, or their ratio. The duration of the first state (e.g., the time the signal is at a high level) is also referred to as the pulse duration below.

[0006] In some applications, such as those regulating a system, not only a high resolution is required for precise regulation, but also a high update rate is required to be able to quickly respond to sudden changes in physical parameters. Summary of the Invention

[0007] A device, a controller and a method according to the present invention are provided.

[0008] According to one embodiment, a device is provided, comprising a sensor configured to output an analog sensor signal. The device further comprises an analog-to-digital converter configured to convert the analog sensor signal into a sigma-delta modulated second digital signal having a bit width of n bits, and a pulse width modulator configured to generate a pulse width modulated signal based on the second digital signal.

[0009] According to one embodiment, a controller is provided that includes an input for receiving a pulse width modulated signal from a sensor device; and a processing circuit configured to generate a first digital received signal based on averaging during k cycles of the pulse width modulated signal, where k is greater than or equal to 2.

[0010] According to another embodiment, a method is provided that includes generating a sigma-delta modulated second digital signal having an n-bit width based on an analog sensor signal, and generating a pulse width modulated signal based on the second digital signal.

[0011] Additionally, a method is provided that includes receiving a pulse width modulated signal generated based on a sigma-delta modulated signal from a sensor device, and generating a first digital signal based on averaging during k cycles of the pulse width modulated signal, where k is greater than or equal to 2.

[0012] The foregoing summary merely provides an overview of some embodiments and should not be construed as limiting. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1is a block diagram of a system according to one embodiment.

[0014] Figure 2 is a diagram of a portion of a device according to one embodiment.

[0015] Figure 3 Example signals are shown to illustrate the embodiments.

[0016] Figure 4 Further example signals are shown to illustrate the embodiments.

[0017] Figure 5 A portion of a device according to one embodiment is shown.

[0018] Figure 6 The application of chopping according to some embodiments is described.

[0019] Figure 7 Signals are shown to illustrate some embodiments.

[0020] Figure 8 A diagram illustrating a system according to one embodiment is shown.

[0021] Figure 9 is a block diagram of a portion of some embodiments.

[0022] Figure 10 Shown for illustration Figure 9 Example signals of an embodiment.

[0023] Figure 11 A system with a current interface according to some embodiments is shown.

[0024] Figure 12 A flow chart illustrating a method according to some embodiments is shown.

[0025] Figure 13 Simulation results are shown for comparing some embodiments with conventional methods.

[0026] Figure 14 is a block diagram of a system according to one embodiment.

[0027] Figure 15 is a block diagram of a system according to one embodiment. DETAILED DESCRIPTION

[0028] Some embodiments are described in more detail below. These embodiments are intended to be illustrative and are not to be construed as limiting. Some embodiments having various features (e.g., components, elements, processes, etc.) are described above. In other embodiments, some of these features may be omitted and / or replaced by alternative features. Furthermore, in addition to the features explicitly described, other features are provided, such as those used in conventional sensor devices and controllers.

[0029] Unless otherwise specified, the connections or couplings described herein or shown in the drawings are electrical connections or couplings. Such connections or couplings may be modified, for example, by adding or omitting components, as long as the basic function of the connection or coupling, such as the transmission of signals, the transmission of information, etc., is not significantly affected.

[0030] Unless otherwise specified, features of different embodiments may be combined with one another. Variations or modifications described for one embodiment may also be applied to other embodiments and will not be described again.

[0031] In the drawings, the same elements are denoted by the same reference numerals, and thus detailed description will not be repeated.

[0032] The numerical values ​​and signal curves specified in this description are for illustration only and should not be understood as limiting, as such numerical values ​​and signal curves may vary depending on the implementation.

[0033] Figure 14 is a block diagram of an apparatus according to one embodiment. Figure 14 The system includes a sensor device 140 and a controller 16. In some embodiments, the sensor device 140 can be integrated on a first chip, and the controller 16 can be integrated on a second chip. In other embodiments, the sensor device 140 can also be designed with multiple chips, and then these chips can be arranged in corresponding packages, for example.

[0034] Sensor device 140 sends a signal to controller 16 that carries information about a physical quantity acquired by sensor 11 of sensor device 140. Various embodiments discussed below are primarily concerned with the generation of such a signal by a sensor device (such as sensor device 140) and the processing of the signal in a controller (such as controller 16).

[0035] exist Figure 14In the embodiment of the present invention, the sensor 11 is a magnetic field sensor in the form of a Hall sensor. This is for illustration only, and other types of sensors may also be used. For example, other types of magnetic field sensors may also be used, such as sensors based on the magnetoresistance effect, for example sensors based on giant magnetoresistance (GMR), tunnel magnetoresistance (TMR) or anisotropic magnetoresistance (AMR). These sensors are also collectively referred to as XMR sensors. Magnetic field sensors are used, for example, in vehicle applications to measure the rotational speed by generating a changing magnetic field by rotation. Other types of sensors different from magnetic field sensors may also be used as sensor 11, such as temperature sensors, pressure sensors, current sensors, voltage sensors or sensors for measuring mechanical stress. Multiple sensors and various types of sensors may also be provided in the device 10.

[0036] Sensor 11 outputs an analog output signal representing the acquired physical variable. In sensor device 140, this analog sensor signal is converted into a sigma-delta modulated second digital signal s2 with a bit width of n bits by means of analog-to-digital converter 141. Here, n is greater than or equal to 1, for example, at least 2, such as 8 or more.

[0037] A sigma-delta modulated signal is understood here to be a signal generated with the aid of a sigma-delta analog-to-digital converter or a digital sigma-delta modulator, in which a resolution greater than the bit width n can be achieved through temporal averaging. This means that even when the analog sensor signal is constant, the value of the second digital signal s2, in particular the value of the least significant bit of the second digital signal s2, can vary over time. Therefore, temporal averaging can achieve a resolution greater than the value of the least significant bit. For example, two alternatives are described below regarding a sigma-delta analog-to-digital converter or a digital sigma-delta modulator.

[0038] The second digital signal s2 is supplied to a pulse width modulator 14, which essentially comprises a counter. For each cycle of the pulse-width modulated signal to be generated, the counter counts until the value represented by the second digital signal s2 is reached, and the pulse width modulator 14 outputs a first value. Once the value of the second digital signal s2 is reached, the second value is output, for example, for the remaining cycles of the pulse-width modulated signal. Therefore, the number of first values ​​outputted represents the value of the second digital signal s2. It should be noted that the digital sigma-delta modulator 13 and the pulse width modulator 14 do not need to be implemented as separate devices, but can instead be implemented in a shared digital circuit, for example, using a digital signal processor or the like.

[0039] The pulse width modulation signal generated by using Σ-Δ modulation in this way can also be called a fractional pulse width modulation signal.

[0040] The signal spwm output by the pulse width modulator 14 is supplied to the interface 15, which thereby generates a pulse width modulated signal on the transmission line. For example, the interface 15 can be a voltage interface, such as a push-pull interface, an open-drain interface or an LVDS (low voltage differential signal) interface, which outputs a first voltage during the period when the signal spwm is at the first value mentioned above, and outputs a second voltage when the signal spwm is at the second value. In the case of using a voltage interface, a so-called ratiometric signal can be realized, in which the pulse duration is independent of the supply voltage. The amplitude of the pulse width modulated signal is proportional to the supply voltage in this case, so that in a possible subsequent analog low-pass filtering (as explained later), the average value obtained from the pulse width modulated signal is proportional to the supply voltage = ratiometric, and can be supplied to a controller having an analog-to-digital converter input, the reference of which is also proportional to the supply voltage. In another embodiment, the interface 15 can also be a current interface, as described later with reference to Figure 11 As elaborated in more detail.

[0041] The signal sent by the interface 15 is received by the controller 16. The controller 16 may include, for example, a microcontroller, a microprocessor or other processing components to evaluate the received signal. Figure 1 In the exemplary embodiment, the controller 16 has a fast path 17 and a slow path 18 for evaluating the received signal. The high-resolution slow path evaluates the received signal over multiple cycles of the pulse-width modulated signal to increase the resolution and, given a sufficient number of cycles, ultimately recovers a signal with m-bit resolution, like the first digital signal. The evaluation over multiple cycles can be achieved by averaging over multiple cycles.

[0042] Fast path 17 evaluates fewer cycles, for example, only one, thus achieving a high update rate. Thus, fast path 17 can be used to detect sudden changes in the physical variable acquired by sensor 11, while slow path 18 provides high resolution. It should be noted that high resolution is generally not required to detect rapid changes, as even large, rapid changes can be detected well with low resolution. Examples of evaluation over multiple cycles and evaluation over a single cycle will also be explained in more detail later.

[0043] Figure 15 One embodiment of a system having a sensor device 150 is shown. Figure 14 A possible implementation of the analog-to-digital converter device 141 is shown, which has a ∑-△ analog-to-digital converter 151 and a digital low-pass filter 152. Figure 15 The system corresponds to Figure 14, and the sensor device 150 corresponds to the sensor device 140, and the remaining components are not explained.

[0044] The sigma-delta analog-to-digital converter 151 receives the analog sensor signal from the sensor 11 and outputs a 1-bit current. The sigma-delta analog-to-digital converter 151 may be a first-order converter or a higher-order converter.

[0045] The 1-bit current is filtered by a digital low-pass filter 152 to generate a second digital signal s2 having a bit width n. The filtering is performed, for example, by using a higher threshold frequency, so that n is below the maximum resolution achievable based on the 1-bit current. This maximum resolution can be achieved by averaging multiple values ​​of the second digital signal (ignoring noise effects, etc.), so that the second digital signal generated in this way is a sigma-delta modulated signal in the sense described above.

[0046] Figure 1 An embodiment of a system having a sensor device 10 is shown. Figure 14 A possible implementation of an analog-to-digital converter device 141 with an analog-to-digital converter 12 and a digital sigma-delta modulator 13 is shown. Figure 1 The system corresponds to Figure 14 , and the sensor device 10 corresponds to the sensor device 140, and the remaining components are not explained.

[0047] In the sensor device 10, the analog sensor signal is converted into a first digital signal s1 with the aid of an analog-to-digital converter 12, which has a bit width of m bits, where m is an integer greater than 1. Typically, m may be between 8 and 16, for example equal to 12 or 14. The higher m is, the higher the resolution of the first digital signal output by the analog-to-digital converter 12.

[0048] The analog-to-digital converter 12 can directly generate a first digital signal s1 having an m-bit width. In another embodiment, a digital low-pass filter 19 can optionally be connected downstream of the analog-to-digital converter 12 at the output of the analog-to-digital converter. The digital low-pass filter increases the output of the analog-to-digital converter 12 to an m-bit width. For example, in this case, the analog-to-digital converter 12 can be a 1-bit sigma-delta analog-to-digital converter that generates a 1-bit current, and the digital low-pass filter 19 can filter the 1-bit current to generate a first digital signal having an m-bit width. Generally, any device that generates a first digital signal s1 having an m-bit width from an analog sensor signal can be used.

[0049] The first digital signal s1 is then fed to a digital sigma-delta modulator 13. Based on the first digital signal s1, the digital sigma-delta modulator 13 generates a second digital signal s2 with a bit width of n bits, where n is an integer greater than m. A sigma-delta modulator is a device that generates a signal with a bit width of n bits from a signal with a bit width of m bits, where at least one feedback coupling signal is subtracted from the signal in the feedforward signal path of the sigma-delta modulator. This digital sigma-delta modulator is essentially constructed like a sigma-delta analog-to-digital converter, with a digital input signal fed instead of an analog input signal. An example will be described later. Even if the bit width of m bits is reduced to n bits, the information of the first digital signal s1 is still present in the second digital signal s2 in principle. When generating a first digital signal s1 with a constant value, the average value of the second digital signal s2 over multiple values ​​corresponds to the value represented by the first digital signal s1. This means that while the first digital signal s1, which can be imprecisely mapped to the second digital signal with n bits, is constant, the value of the second digital signal s2 varies even when the first digital signal is constant. This will also be explained later with the aid of examples. n can be, for example, greater than 6, and the difference between m and n can be, for example, between 2 and 12. In one example, where m is 14, n can be, for example, equal to 12, equal to 10, or equal to 8. Figure 14 As described, the second digital signal s2 is further processed.

[0050] Figure 2 An example of a first-order digital sigma-delta modulator 20 is shown, which can be used, for example, as digital sigma-delta modulator 13 in sensor device 10. Digital sigma-delta modulator 20 receives a first digital signal s1 at the positive input of an accumulator 21. Accumulator 21 outputs a second digital signal s2 having a bit width of n bits. Furthermore, signal s2, which has a delay 22 of one clock pulse, is coupled back to the negative input of accumulator 21. As a result, signal s2 output by accumulator 21 is increased or decreased by the difference between signal s1 and signal s2 from the previous clock pulse cycle. In general, accumulator 21 modulates its output signal according to the difference between its input signals. Second digital signal s2 is then fed to pulse width modulator 14, already discussed. However, as will be explained later, higher-order sigma-delta modulators can also be used.

[0051] Next, refer to Figure 3 and Figure 4 The generation of the pulse-width modulated signal and its evaluation in the controller are explained in more detail.

[0052] Figure 3 An example is shown for a pulse width modulated signal 32, which is for example made use of Figure 1 and Figure 2 The pulse width modulator 14 generates and can then be Figure 1Output of interface 15. Figure 3 In the example of FIG, four cycles 31A to 31D of the pulse width modulated signal 32 are shown in full and the fifth cycle 31E is shown partially.

[0053] exist Figure 3 Examples and follow-up Figure 4 In the example of FIG. 1 , it is assumed that the signal s1 is constant and is fed to a digital Σ-Δ modulator, such as Figure 1 ∑-△ modulator 13 or Figure 2 ∑-△ modulator 20.

[0054] The n-1 most significant bits of the second digital signal s2 correspond here to the n-1 most significant bits of the first digital signal s1, wherein when the mn least significant bits of the first digital signal s1 are not zero, even if the first digital signal s1 is constant, the least significant bit of the second digital signal s2 changes with time, so that the value of the second digital signal s2 corresponds on average to the value of the first digital signal s1.

[0055] To illustrate this effect, Figure 3 and Figure 4 In the example of , it is assumed that the mn least significant bits of the first digital signal s1 are not zero.

[0056] In the pulse width modulation signal 32, the pulse duration (during which the pulse width modulation signal 32 is at a high level) represents the corresponding value of the second digital signal s2. Since the mn least significant bits of the first digital signal s1 are not zero, even if the first digital signal s1 is constant, the pulse duration is not constant. Figure 3 This is shown in cycle 31C, in which the pulse duration is increased by a duration 33 .

[0057] By averaging over multiple cycles, as in Figure 3 As indicated by bracket 34A in the figure, the value of the first digital signal s1 can be reconstructed. In order to accurately reconstruct the value of the first digital signal s1, it must be averaged over a certain number of cycles (assuming that the first digital signal s1 is constant). The number of cycles is related to the difference between m and n. The greater the difference, the more cycles must be averaged. Specifically, it is necessary to average over 2 m-n However, averaging over fewer cycles is also possible.

[0058] This averaging is performed in the controller, e.g. Figure 1The averaging is performed in the slow path 18 of the controller 16. In some embodiments, the averaging can be performed continuously, so that after four cycles 34A, the average value for the four subsequent cycles is obtained, as indicated by bracket 34E. In other embodiments, the averaging can be performed in a sliding manner, as indicated by brackets 34B to 34D. The advantage of using sliding averaging is a higher update rate, which corresponds to the inverse of the duration of cycles 31A to 31E. Averaging also allows for inherent low-pass filtering, so that sudden changes in the first digital signal s1 are only gradually reflected in the value obtained by averaging. This averaging can be performed in the controller 16 by digital filtering, for example, using an infinite impulse response (IIR) filter, a finite impulse response (FIR) filter, a cascaded integrator comb filter (CIC filter), or a digital low-pass filter, with the edge slopes adapted to the desired averaging.

[0059] In order to be able to respond quickly to sudden changes in the output signal of the sensor and therefore in the first digital signal s1, the evaluation of the individual cycles 31A to 31E is carried out in the fast path 17 of the controller 16. Alternatively, averaging over fewer cycles than in the slow path 18 is also possible, for example Figure 3 In the example above, during two cycles.

[0060] Figure 4 Shown with Figure 3 A pulse width modulated signal 42 is similar to the pulse width modulated signal 32 in FIG. , which has a plurality of cycles 40A, 40B, 40C, 40D, .... Figure 4 In the example, the second digital signal s2 is a 10-bit signal with 2 10 = 1024 different pulse durations, from 0 to 1023 time units. In addition, Figure 4 In the example of , the first digital signal s1 is a 12-bit signal, so mn=2.

[0061] In this example, it is necessary to 12-10 =4 to correctly reconstruct the value of the first digital signal s1.

[0062] exist Figure 4 In the example of , the least significant two bits of the first digital signal have the value 01, for example. This results in that, in four consecutive cycles of the pulse width modulated signal 42, the pulse duration in one cycle is extended by one unit. Figure 4In the example shown, the pulses in cycles 40A, 40B, and 40D have a length of 666 time units (out of a maximum of 1023 time units), while the pulse in cycle 40C has a duration of 667 time units. By averaging over the four cycles 40A to 40D, the first digital signal s1 can be reconstructed. By evaluating the individual cycles, changes in the physical parameter acquired by the sensor and in the first digital signal s1 can also be detected quickly, as described.

[0063] If you have already referred to Figure 3 As explained, the averaging can be performed here “segment-wise” during four consecutive cycles, as indicated by bracket 41B, or by means of a sliding average, as indicated by bracket 41C.

[0064] exist Figure 2 In FIG, an example for a first-order sigma-delta modulator is shown. However, sigma-delta modulators of other orders, in particular higher orders, can also be used. An example for a second-order sigma-delta modulator 50 is shown in FIG. Figure 5 It should be noted that although the sigma-delta modulator 50 is shown with discrete components, these components may be implemented, for example, with the aid of a digital signal processor or other suitable digital circuitry.

[0065] The sigma-delta modulator 50 receives a first digital signal s1 at a first positive input of a subtractor 51. The input of the first subtractor 51 is connected to a data input D of a first digital memory 52 having a width of at least m bits, represented here by a sign D flip-flop. Such a memory can be implemented, for example, by a plurality of, for example, at least m, D flip-flops. Other memories, such as RAM, can also be used.

[0066] The data output Q of the first digital memory 52 is routed back to the second positive input of the first subtractor and is also connected to the first positive input of the second subtractor 53. The output of the second subtractor 53 is connected to the data input D of a second digital memory 54 (again represented by a D flip-flop; the description of the first digital memory 52 applies accordingly). The data output Q of the second digital memory 54 is routed back to the second positive input of the second subtractor 53. The digital memories 52 and 54 each output the signal applied to their data input D to their respective data input Q in a controlled manner by a clock signal (not shown), which is located at the clock input of the digital memory.

[0067] The data output Q of the second digital memory 54 is directed to a cutoff circuit 55, which outputs the m most significant bits of the signal supplied thereto as a signal s2. The signal s2 is then weighted using a first weighting factor C1 in a multiplier 56 and supplied to the negative input of the first subtractor 41. Furthermore, the signal is weighted using a second weighting factor C2 in a multiplier 57 and supplied to the negative input of the second subtractor 53.

[0068] Signal s2 is then additionally supplied to the pulse width modulator 14 already discussed.

[0069] In one embodiment, for the sigma-delta modulator 50 , the bit width n of the first digital signal s1 may be equal to 14, and the bit width n of the second digital signal s2 may be equal to 8. Similarly, other values ​​are possible, where the bit width of the second digital signal s2 is set by the number of bits cut off by the cutter 55 .

[0070] The signal-to-noise ratio (SNR) in this method is

[0071]

[0072] Here, OR is the oversampling rate, B is the bit width of the signal s2, and L is the order of the Σ-Δ modulator. In the above example with n=14 and m=8, for example, an 8-bit PWM signal with an update rate of 30 kHz can be generated using the Σ-Δ modulator 50. With a first-order Σ-Δ modulator, a high-resolution 14-bit signal with an update rate of approximately 2.7 kHz can be generated in the receiver, for example, in the controller 16, by averaging, and a signal with an update rate of approximately 7.5 kHz can be generated in a second-order Σ-Δ modulator. The reason for the higher update rate in the case of higher orders is that the deformation of the pulse duration (for example Figure 3 33) is better distributed over the signal in higher order modulators.

[0073] In some embodiments, the analog-to-digital converter (e.g., analog-to-digital converter 12) used to convert the sensor signal to analog-to-digital can be equipped with a chopper device to minimize the offset of the analog-to-digital converter. The chopper signal used for this purpose can be synchronized with the cycle of the pulse width modulation signal. An example of this will be referred to Figure 6 and Figure 7 To explain.

[0074] Figure 6 Show Figure 1 The sensor 11 and the analog-to-digital converter 12 in the embodiment of FIG. Figure 1 As mentioned, the sensor 11 is a Hall sensor in the example shown. Figure 6In the example of , the sensor 11 is operated using the so-called spinning current technology. Here, a bias current from a current source 60 is supplied to the Hall sensor 11 at one terminal, while the opposite terminal is connected to ground 61. The Hall voltage is measured at the two other terminals. For the spinning current technology, as in Figure 6 As shown by the dotted line in FIG, the terminal for delivering the bias current and the terminal for measuring the Hall voltage are interchanged, which can reduce the bias of the sensor 11. Since this involves a known technology, it will not be explained in detail. However, as already mentioned, Figure 1 As mentioned, other types of sensors may be used.

[0075] A first chopper device 63 is provided at the input of the analog-to-digital converter 12, and a second chopper device 64 is provided at the output of the analog-to-digital converter 12. The chopper devices 63, 64 are each operated at a chopper frequency fchop. The analog-to-digital converter 12 operates at a frequency fclock ADC The chopping itself can—without taking into account the synchronization with the pulse-width modulation signal explained below—be implemented in various conventional ways and serves to at least partially compensate for the offset of the analog-to-digital converter 12 .

[0076] exist Figure 7 , curve 70 shows the clock signal fclock ADC As an example, curve 71 shows an example for the chopper frequency fchop, and curve 72 shows an example for the pulse width modulated signal spwm, which, as explained and indicated by 74, can also have a variable pulse duration even when the signal s1 is constant. Figure 6 and Figure 7 In an embodiment of the present invention, the chopper frequency fchop and the pulse width modulation signal spwm are synchronized so that in each cycle of the pulse width modulation signal according to the curve 72 there is an integer number of periods of the chopper frequency fchop, and the beginning and end of a cycle of the pulse width modulation signal according to the curve 72 are synchronized with the edges of the chopper frequency fchop, Figure 7 In the example of FIG, the falling edge occurs, as indicated by the dashed line 73. By synchronizing the chopper frequency fchop with the pulse width modulated signal spwm, so-called intermodulation effects, i.e., interference signals, in the case of which the chopper ripple (with a positive or negative offset of the frequency fchop) can generate beat frequency effects in the signal spwm, can be suppressed. However, in other embodiments, the chopper can also be omitted or synchronized with the pulse width modulated signal spwm.

[0077] In the embodiments discussed above, the averaging is performed in the controller 16, for example in a digital component of the controller 16. In other embodiments, analog low-pass filtering may be performed to perform the averaging. Figure 8 Shown in.

[0078] Figure 8 The system is shown with a sensor device 80 and a controller 81. The sensor device 80 outputs a pulse width modulated signal 84 in the manner described above, ie a pulse width modulated signal based on the output signal of a sigma-delta modulator for reducing the bit width.

[0079] exist Figure 8 An example for such a pulse width modulated signal is shown in curve 84 in FIG.

[0080] In the case of signal 84 , the pulse duration decreases at the end of the illustrated time period, which can correspond, for example, to a smaller value of the physical variable detected by sensor device 80 .

[0081] The pulse width modulated signal 84 is fed to an analog low pass filter 82. Figure 8 In the example shown, the low-pass filter 82 has two resistors and two capacitors. However, this is only an example, and other implementations of the low-pass filter are also possible.

[0082] In this way, an analog signal is generated, which is typically averaged over multiple cycles of the pulse-width modulated signal by low-pass filtering. Curve 85, which matches curve 84, shows an example of such an analog signal. As the pulse duration decreases, analog signal 85 decreases, with a relatively slow drop due to the low-pass filtering (depending on the time constant of the low-pass filter). This signal is then fed to the analog-to-digital converter input of controller 81 and further processed. Low-pass filtering of pulse-width modulated signal 84 increases the resolution—according to the averaging described above.

[0083] Furthermore, as indicated by the dashed line 83, the pulse width modulated signal can optionally be fed to a digital input of the controller 81, for example in order to evaluate the individual cycles of the pulse width modulated signal and thereby form a pulse width modulated signal. Figure 1 A fast path such as the fast path 17 of FIG. 1 is used in which, due to the time constant of the low-pass filter, it is possible to detect severe changes faster than the analog signal passes through the low-pass filter.

[0084] In the embodiments described above, physical variables are acquired by sensors and the acquired variables are ultimately transmitted in a pulse width modulated and coded manner. In some embodiments, additional information can be transmitted on these pulse width modulated signals by means of pulse code modulation. This additional information can be, for example, additional physical variables acquired by additional sensor devices. Figure 9 and Figure 10 To illustrate this with an example.

[0085] Figure 9 is a block diagram of a portion of a sensor device according to one embodiment. The already discussed second digital signal s2 is supplied to a pulse width / pulse code modulator 90, which is generated from the first digital signal by means of sigma-delta modulation, as explained above. Furthermore, a further sensor device 91 generates a further physical variable and provides a corresponding digital signal s3. The further physical variable may be another physical variable that is different from a physical variable that is otherwise acquired by the sensor device, for example, by means of the already discussed sensor 11. The further physical variable may be, for example, temperature. In other embodiments, the further physical variable may be the same physical variable as that typically acquired by the sensor device, thereby providing redundancy. In addition to the further sensor, the further sensor device 91 may also include, for example, a further analog-to-digital converter, so that the third signal s3 may be a digital signal.

[0086] Essentially as described above, the pulse width / pulse code modulator 90 generates a pulse width modulated signal based on the second digital signal s2. However, unlike the previous embodiment, the duration of a cycle of the pulse width modulated signal is now additionally varied in the form of pulse code modulation based on the third digital signal s3. For example, to encode the third signal s3, the first cycle length can represent a logical zero, and the second cycle length can represent a logical one, so that, for example, a 4-bit value can be transmitted during four cycles.

[0087] exist Figure 10 An example for such a combination of pulse width modulation and pulse code modulation is shown in FIG. Figure 3 and Figure 4 As shown, it is assumed that the first digital signal s1 is constant, wherein for the sake of explanation, the first digital signal s1 has the same Figure 4 Same values ​​as in the example.

[0088] Figure 10 The combined PWM / PCM signal 103 is shown during four cycles 104A to 104D. In cycles 104A, 104C and 104D, the length of each cycle is as shown in FIG. Figure 4 As in the example of , there are 1023 time units, which corresponds to Figure 4 , the pulse duration in cycles 104A and 104B is 666 time units (corresponding to Figure 4 40A and 40B), and in the case of loop 104C, the pulse duration is 667 time units (as in Figure 4The length of loop 104B is 1279 time units, and the pulse duration is 832 time units, which is essentially (within the range of accuracy determined by the number of time units) the same as in loops 104A and 104D (and in Figure 4 The same value of the pulses in loop 40B) is encoded.

[0089] Thus, the pulse width modulated signal can be decoded as described above. It is also possible to average over a number of cycles (in this case four cycles), as indicated by bracket 105A. This can be repeated continuously, as indicated by bracket 105B, or by sliding averaging, as indicated by dashed bracket 105C, and as has also been explained above. Furthermore, in a controller (e.g., receiving signal 103), Figure 1 Controller 16 or Figure 8 In the controller 81), the signal is evaluated in the second sensor decoder 100. This second sensor decoder 100 can be implemented by corresponding programming of the digital signal processing of the corresponding controller. Here, the duration of the cycle is evaluated as represented by brackets 101A to 101D. Here, a duration of 1023 time units can represent a logical zero, and a duration of 1279 time units can represent a logical one, so that in the example shown, the value "0100" is transmitted via four cycles. Depending on the resolution required for the transmission of the third signal s3, more or fewer cycles can also be used. Here, a larger number of cycles corresponds to a higher resolution and a lower transmission rate.

[0090] Alternatively or additionally, a range of pulse durations can be provided for transmitting additional information, such as status information. These ranges can include short and / or long pulse durations. Thus, the duration of a cycle for a 10-bit signal may not include 1023 time units, but may instead include, for example, 1123 time units. To regularly transmit signal s2 as described above, pulse durations between 50 and 1073 time units are used. Pulse durations between 0 and 49 time units can, for example, indicate a first type of error, while pulse durations between 1074 and 1123 time units can indicate a second type of error.

[0091] As reference Figure 1 As explained, various types of interfaces 15 can be used, in particular various types of voltage interfaces, wherein the pulse width modulated signal uses two different voltages, for example. As also mentioned, current interfaces can also be used. An example of a current interface is shown in FIG. Figure 11 Shown in.

[0092] Figure 11The system includes a sensor device 110 having a current interface, the sensor device including a first power supply 113, a second power supply 114 and a switch 115. The switch 115 is controlled by a signal spwm generated by a pulse width modulator, such as the pulse width modulator 14 of the above embodiment. Accordingly, the sensor device outputs a current I 传感器 , which varies between a first current level I1 and a second current level I1+I2. Figure 11 Curve 117 shows that this current I 传感器 Examples over time.

[0093] The power supply voltage VDDμP of the controller 111 is used to power the current mirror 112. The current I 传感器 The current is reflected by the current mirror to have two different current levels. 镜 , and is delivered to the resistor 116, where the voltage VCOMP drops. Figure 11 As shown by curve 118 of , voltage VCOMP varies between two voltage values ​​V1 and V2 and may then be supplied to controller 111 and processed there as already discussed.

[0094] Figure 12 A method according to one embodiment is shown. Figure 12 The method can be implemented with the aid of the systems and devices discussed above and will be described with reference to them in order to avoid repetition. Various variants described above (e.g. additional use of pulse code modulation) can be used for Figure 12 However, Figure 12 The method may also be performed using apparatus other than that described.

[0095] In 121, the method comprises generating a sigma-delta modulated second digital signal based on the analog sensor signal. An example of this is generating the second digital signal s2 as described above. Thus, this generation can be performed as follows: Figure 15 In the analog ∑-△ analog-to-digital conversion, followed by digital low-pass filtering; or Figure 1 Through analog-to-digital conversion followed by digital sigma-delta modulation.

[0096] At 122 , the method includes generating a pulse width modulated signal based on the second digital signal as described above.

[0097] The pulse width modulated signal can then be transmitted to a controller, for example, by the sensor device. In 123, the pulse width modulated signal is then received, for example, in the controller. In 124, averaging is performed over a plurality of cycles of the pulse width modulated signal, as described above, to obtain information with high resolution. In addition, in 125, it is also possible to calculate the pulse width modulated signal according to, for example, Figure 1The fast path 17 rapidly updates the received signal based on one or fewer cycles.

[0098] By using such a method, not only can the variables acquired by the sensor device be updated quickly in the controller (in 125 ), but also the acquired variables can be obtained with high resolution (by averaging in 124 ).

[0099] To further illustrate, Figure 13 The simulation results for different embodiments and comparative examples are shown. Figure 13 The achievable resolution is plotted against the achievable update rate in Hertz. Curve 130 shows the characteristics of an embodiment using a second-order sigma-delta modulator, while curve 131 shows the characteristics of an embodiment using a first-order sigma-delta modulator. In both cases, high resolution and high update rate can be simultaneously achieved by using a slow path and a fast path, as described, with the slow path utilizing averaging. The dashed lines illustrate several conventional approaches. In this case, high update rates cannot be achieved simultaneously with high resolution over a wide range, and the corresponding system must be reprogrammed between longer PWM cycles corresponding to high resolution and shorter PWM cycles corresponding to high update rates.

[0100] Some embodiments are defined by the following examples:

[0101] Example 1. A device comprising:

[0102] a sensor configured to output an analog sensor signal;

[0103] an analog-to-digital converter device configured to convert the analog sensor signal into a sigma-delta modulated second digital signal having a bit width of n bits; and

[0104] The pulse width modulator is configured to generate a pulse width modulation signal based on the second digital signal.

[0105] Example 2. The apparatus of Example 1, wherein n is greater than 6.

[0106] Example 3. The device according to example 1 or 2,

[0107] The analog-to-digital converter device includes a ∑-△ analog converter and a low-pass filter, the ∑-△ analog converter is used to generate a bit stream, and the low-pass filter is used to generate a second digital signal based on the bit stream, wherein n is smaller than the resolution achievable based on the bit stream.

[0108] Example 4. The device according to example 1 or 2,

[0109] The analog-to-digital converter device includes an analog-to-digital converter and a digital sigma-delta modulator, wherein the analog-to-digital converter is configured to convert the analog sensor signal into a first digital signal with an m-bit width, and the digital sigma-delta modulator is configured to generate a second digital signal with an n-bit width based on the first digital signal, wherein n <m。

[0110] Example 5. The apparatus of Example 4, wherein m is greater than or equal to 10.

[0111] Example 6. The apparatus of example 4 or 5, wherein mn is between 2 and 12.

[0112] Example 7. The apparatus of any of Examples 4 or 6, wherein the analog-to-digital converter comprises a low-pass filter at an output of the analog-to-digital converter to increase the bit width of the first signal from a previous bit width to m.

[0113] Example 8. The apparatus of any one of Examples 4 to 7, wherein the sigma-delta modulator is an nth order modulator, where n>=1.

[0114] Example 9. The apparatus of any one of Examples 1 to 8, wherein the pulse width modulator comprises a counter.

[0115] Example 10. The apparatus of any one of Examples 1 to 9, further comprising an interface for outputting a pulse width modulated signal (spwm).

[0116] Example 11. The device of example 10, wherein the interface comprises a push-pull interface.

[0117] Example 12. The device of Example 10, wherein the interface comprises an open-drain interface.

[0118] Example 13. The device of Example 10, wherein the interface comprises a low voltage differential signaling interface.

[0119] Example 14. The device of example 10, wherein the interface comprises a current interface.

[0120] Example 15. The apparatus of any one of Examples 10 to 14, further comprising an analog low-pass filter coupled to the output of the interface.

[0121] Example 16. The apparatus according to any one of Examples 1 to 15, further comprising a further sensor device for outputting a third signal, wherein the pulse width modulator is configured to modulate the pulse width modulated signal into a pulse code based on the third signal.

[0122] Example 17. An apparatus according to any one of Examples 1 to 16, wherein the pulse width modulator is configured to generate a pulse width modulated signal having a pulse duration in a first range based on a second digital signal, and to generate a pulse width modulated signal having a pulse duration in a second range based on further information, wherein the second range is different from the first range.

[0123] Example 18. The device of example 17, wherein the further information comprises status information.

[0124] Example 19. The apparatus of any one of Examples 1 to 18, wherein the analog-to-digital converter means has a chopper means operating at a chopper frequency, wherein a cycle of the pulse width modulated signal contains an integer number of periods of the chopper frequency.

[0125] Example 20. A controller comprising:

[0126] an input terminal for receiving a pulse width modulated signal from a sensor device; and

[0127] The processing circuit is configured to generate a first digital received signal based on averaging during k cycles of the pulse width modulated signal, where k is greater than or equal to two.

[0128] Example 21. The controller of Example 20, wherein the processing circuit is further configured to generate a signal value of the second digital received signal based on every p cycles of the pulse width modulated signal, wherein p is less than k.

[0129] Example 22. The controller of Example 21, wherein p is equal to 1.

[0130] Example 23. The controller of any one of Examples 20 to 22, wherein k is greater than or equal to 4.

[0131] Example 24. The controller of any of Examples 20 to 23, wherein averaging comprises sliding averaging.

[0132] Example 25. The controller of any one of Examples 20 to 24, wherein the processing circuit for averaging comprises a finite impulse response filter, a finite impulse response filter, a cascaded integrator comb filter, or a digital low-pass filter.

[0133] Example 26. The controller of any one of Examples 20 to 25, wherein the processing circuit is configured to obtain pulse code modulation information from a modulated pulse duration of the pulse width modulated signal.

[0134] Example 27. A system comprising:

[0135] The apparatus according to any one of Examples 1 to 19, and the controller according to any one of Examples 20 to 26 coupled to the apparatus.

[0136] Example 28. A method comprising:

[0137] generating a sigma-delta modulated second digital signal having a bit width of n bits based on the analog sensor signal, and

[0138] A pulse width modulation signal is generated based on the second digital signal.

[0139] Example 29. The method of Example 28, wherein n is greater than 6.

[0140] Example 30. The method according to Example 28 or 29,

[0141] wherein generating the second digital signal comprises: performing a sigma-delta conversion on the analog sensor signal to generate a bit stream, and

[0142] The bit stream is low-pass filtered to generate a second digital signal having a bit width of n bits, where n is smaller than an achievable resolution based on the bit stream.

[0143] Example 31. The method according to Example 28 or 29,

[0144] Generating the second digital signal includes: converting the analog sensor signal into a first digital signal having a bit width of m bits, and

[0145] The first digital signal is digitally Σ-Δ modulated to generate a second digital signal having a bit width of n bits, wherein n <m。

[0146] Example 32. The method of Example 31, wherein m is greater than or equal to 10.

[0147] Example 33. The method of example 31 or 32, wherein mn is between 2 and 12.

[0148] Example 34. The method of any one of Examples 28 to 33, further comprising outputting a pulse width modulated signal.

[0149] Example 35. The method of Example 34, wherein outputting comprises outputting via a push-pull interface, an open-drain interface, or a low voltage differential signaling interface.

[0150] Example 36. The method of Example 34, wherein outputting comprises outputting via a current interface.

[0151] Example 37. The method of any one of Examples 34 to 36, further comprising performing analog low-pass filtering on the output pulse width modulated signal.

[0152] Example 38. The method of any one of Examples 28 to 37, further comprising pulse code modulating a pulse duration of the pulse width modulated signal based on the additional sensor signal.

[0153] Example 39. A method according to any one of Examples 28 to 37, wherein a pulse width modulated signal having a pulse duration in a first range is generated based on a second digital signal, and wherein a pulse width modulated signal having a pulse duration in a second range is generated based on further information, wherein the second range is different from the first range.

[0154] Example 40. The method of any of Examples 28 to 39, wherein generating the sigma-delta modulated second digital signal comprises chopping with a chopper frequency, wherein a cycle of the pulse width modulated signal contains an integer number of periods of the chopper frequency.

[0155] Example 41. A method comprising:

[0156] receiving a pulse width modulation signal generated based on a sigma-delta modulation signal from a sensor device, and

[0157] The first digital received signal is generated based on averaging during k cycles of the pulse width modulated signal, where k is greater than or equal to two.

[0158] Example 42. The method of Example 41, further comprising:

[0159] A signal value of the second digital signal is generated based on every p cycles of the pulse width modulated signal, where p is less than k.

[0160] Example 43. The method of Example 42, wherein p is equal to 1.

[0161] Example 44. The method of any one of Examples 41 to 43, wherein k is greater than or equal to 4.

[0162] Example 45. The method of any one of Examples 41 to 44, wherein averaging comprises sliding averaging.

[0163] Example 46. The method of any one of Examples 41 to 45, wherein the pulse duration of the pulse width modulated signal is pulse code modulated, the method further comprising pulse code modulating the pulse width modulated signal.

[0164] Therefore, although the additional examples can have various modifications and alternative forms, some specific examples thereof are shown in the drawings and described in detail subsequently. However, this detailed description does not limit the additional examples to the specific forms described. The additional examples can cover all modifications, equivalents, and alternatives that fall within the scope of this disclosure. Like reference numerals in the description of the drawings indicate similar or similar elements that can be implemented in the same or modified form when compared to each other, while providing the same or similar functions.

Claims

1. A sensor device comprising: A sensor (11) configured to output an analog sensor signal; an analog-to-digital converter device (141) configured to convert the analog sensor signal into a sigma-delta modulated second digital signal (s2) having a bit width of n bits; a pulse width modulator configured to generate a pulse width modulated signal based on the second digital signal (s2), The analog-to-digital converter device (141) comprises an analog-to-digital converter (12) and a digital sigma-delta modulator, wherein the analog-to-digital converter is configured to convert the analog sensor signal into a first digital signal (s1) having a bit width of m bits, and the digital sigma-delta modulator is configured to generate a second digital signal (s2) having a bit width of n bits based on the first digital signal (s1), wherein n <m。 2 . The sensor device according to claim 1 , wherein mn is between 2 and 12.

3. The sensor device according to claim 1 or 2, wherein the analog-to-digital converter (12) comprises a digital low-pass filter (19) at the output of the analog-to-digital converter to increase the bit width of the first digital signal (s1) from a previous bit width to m.

4. The sensor device according to claim 1 or 2, further comprising an interface (15) and an analog low-pass filter (82), wherein the interface is used to output the pulse width modulation signal, and the analog low-pass filter is coupled to the output end of the interface (15).

5. The sensor device according to claim 1 or 2, further comprising an additional sensor device (91) for outputting a third signal, wherein the pulse width modulator (90) is configured to modulate the pulse width modulated signal into a pulse code based on the third signal.

6. A sensor device according to claim 1 or 2, wherein the pulse width modulator is configured to generate the pulse width modulated signal having a pulse duration in a first range based on the second digital signal (s2), and to generate the pulse width modulated signal having a pulse duration in a second range based on additional information, wherein the second range is different from the first range, and wherein the additional information is another physical parameter obtained by another sensor device. 7 . The sensor device according to claim 1 , wherein the analog-to-digital converter device comprises a chopper device which operates at a chopper frequency, wherein a cycle of the pulse-width modulated signal contains an integer number of periods of the chopper frequency.

8. A controller comprising: an input terminal for receiving a pulse width modulated signal from the sensor device according to claim 1; as well as A processing circuit is configured to generate a first digital received signal based on averaging during k cycles of the pulse width modulated signal, where k is greater than or equal to two. 9 . The controller of claim 8 , wherein the processing circuit is further configured to generate a signal value of the second digital received signal based on every p cycles of the pulse width modulated signal, where p is less than k.

10. The controller of claim 9, wherein p is equal to 1.

11. The controller according to any one of claims 8 to 10, wherein k is greater than or equal to 4.

12. A controller according to any one of claims 8 to 10, wherein the averaging comprises a sliding average.

13. The controller according to any one of claims 8 to 10, wherein the processing circuit is configured to obtain pulse code modulation information from a modulated pulse duration of the pulse width modulation signal.

14. A method comprising: generating a sigma-delta modulated second digital signal (s2) having a bit width of n bits based on the analog sensor signal, and generating a pulse width modulation signal based on the second digital signal (s2), Performing analog low-pass filtering on the generated pulse width modulation signal, Generating the second digital signal includes: converting the analog sensor signal into a first digital signal (s1) having a width of m bits, and The first digital signal (s1) is digitally Σ-Δ modulated to generate the second digital signal (s2) having a bit width of n bits, wherein n <m。 15 . The method of claim 14 , further comprising pulse code modulating a pulse duration of the pulse width modulation signal based on a further sensor signal.

16. A method according to claim 14 or 15, wherein the pulse width modulated signal having a pulse duration in a first range is generated based on the second digital signal (s2), and wherein the pulse width modulated signal having a pulse duration in a second range is generated based on further information, wherein the second range is different from the first range, and wherein the further information is another physical variable acquired by another sensor device.

17. The method according to claim 14 or 15, wherein generating the sigma-delta modulated second digital signal (s2) comprises chopping at a chopper frequency, wherein a cycle of the pulse width modulated signal contains an integer number of periods of the chopper frequency.

18. A method comprising: receiving a pulse width modulation signal generated based on a sigma-delta modulation signal from the sensor device according to claim 1, A first digital signal (s1) is generated based on averaging during k cycles of the pulse width modulated signal, where k is greater than or equal to 2.

19. The method according to claim 18, further comprising: A signal value of a second digital signal (s2) is generated based on every p cycles of the pulse width modulated signal, where p is less than k.

20. The method according to claim 18 or 19, wherein pulse code modulation is further performed on the pulse duration of the pulse width modulation signal, and the method further comprises performing pulse code modulation on the pulse width modulation signal.

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