3D DRAM structure with high mobility channel

Abstract

A memory device is described. The memory device includes a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers includes a single crystalline silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. A method of forming a stacked memory device is also described.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the fields of electronic devices and electronic device manufacturing. More specifically, embodiments of the present disclosure provide a dynamic random-access memory with a high mobility channel. Background Art

[0002] Electronic devices such as personal computers, workstations, computer servers, mainframes, and other computer-related devices such as printers, scanners, and hard drives use memory devices that provide powerful data storage capabilities while producing low power consumption. There are two main types of random access memory cells that are well suited for use in electronic devices, dynamic and static. Dynamic random access memory (DRAM) can be programmed to store a voltage representing one of two binary values, but requires periodic reprogramming or "refreshing" to maintain this voltage for more than a short period of time. Static random-access memory (SRAM) is so named because it does not require periodic refreshing.

[0003] DRAM memory circuits are manufactured by replicating millions of identical circuit elements, called DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.

[0004] The manufacture of a DRAM cell includes the fabrication of a transistor, a capacitor, and three contacts: one each for the bit line, the word line, and the reference voltage. DRAM manufacturing is a highly competitive industry. There is a constant pressure to reduce the size of individual cells and increase the density of memory cells to allow more memory to be squeezed onto a single memory chip, especially for densities greater than 256 megabits. Limitations to the reduction in cell size include the need for both active and passive word lines to pass through the cell, the size of the cell capacitor, and the compatibility of array devices with non-array devices.

[0005] In order to manufacture transistors for DRAM cells, active semiconductor or memory layers are required. The semiconductor or memory layers formed by deposition are usually polycrystalline or in an amorphous state. Amorphous silicon or polycrystalline silicon has grain boundaries that hinder the electron charge path, resulting in transistor performance degradation. Therefore, a 3D DRAM cell using a single crystal semiconductor or memory layer with a large grain size is required. In addition, a method and apparatus for forming a 3D DRAM device is required. Summary of the invention

[0006] Embodiments of the present disclosure relate to memory devices, methods of forming memory devices, and processing tools for performing the methods. In one or more embodiments, a memory device includes: a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers, each of the memory layers including: a first word line, the first word line including a monocrystalline silicon layer and having a first side adjacent to a first side of the plurality of bit lines and a second side opposite to the first side; a second word line, the second word line including a monocrystalline silicon layer and having a first side adjacent to a second side of the plurality of bit lines and a second side opposite to the first side; at least one first capacitor, the at least one first capacitor including a monocrystalline silicon layer, the at least one first capacitor being adjacent to a second side of the first word line; and at least one second capacitor, the at least one second capacitor including a monocrystalline silicon layer, the at least one second capacitor being adjacent to a second side of the second word line.

[0007] In one or more embodiments, a memory device includes: a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers, each of the memory layers including: a first word line, the first word line including a single crystalline silicon layer and having a first side adjacent to a first side of the plurality of bit lines and a second side opposite to the first side; a second word line, the second word line including a single crystalline silicon layer and having a first side adjacent to a second side of the plurality of bit lines and a second side opposite to the first side; at least one first capacitor, the at least one first capacitor including a metal material and a highly doped silicon layer, the at least one first capacitor being adjacent to the second side of the first word line; and at least one second capacitor, the at least one second capacitor including a metal material and a highly doped silicon layer, the at least one second capacitor being adjacent to the second side of the second word line.

[0008] In one or more embodiments, a method of forming a memory device includes: forming an opening extending through a stack of alternating dielectric layers and memory layers; depositing a crystallizing agent into the opening; crystallizing the memory layer to form a single crystalline silicon layer; forming a plurality of pre-word line extensions by etching at least one trench through the stack of alternating dielectric layers and single crystalline silicon layers and selectively removing the dielectric layers; forming a first word line having a first side and a second side opposite to the first side by depositing a first word line metal on the plurality of pre-word line extensions to electrically connect the plurality of pre-word line extensions; patterning the alternating dielectric layers and single crystalline silicon layers to form a plurality of bit line openings, each bit line opening extending through the alternating dielectric layers and single crystalline silicon layers; depositing a bit line metal in the plurality of bit line openings to form a plurality of bit lines, each bit line having a first side and a second side opposite to the first side, the first side being adjacent to the first side of the first word line; and forming a second word line having a first side and a second side opposite to the first side by depositing a second word line metal on the plurality of pre-word line extensions on the second sides of the plurality of bit lines.

[0009] In one or more embodiments, a processing tool includes: a central transfer station, the central transfer station including a robot configured to move a wafer; a plurality of process stations, each process station connected to the central transfer station and providing a processing area separate from a processing area of ​​an adjacent process station, the plurality of process stations including a crystallizing agent deposition chamber, an annealing chamber, and a crystallizing agent removal chamber; and a controller connected to the central transfer station and the plurality of process stations, the controller being configured to activate the robot so as to move the wafer between the process stations and to control the processes occurring in each of these process stations. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Thus, the manner in which the above-described features of the present disclosure may be understood in detail, a more specific description of the present disclosure briefly summarized above may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure, as the present disclosure may admit of other equally effective embodiments. Embodiments as described herein are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals indicate similar elements.

[0011] FIG1 illustrates a circuit diagram of a DRAM cell block according to the prior art;

[0012] Figure 2A illustrates an isometric view of a memory device stack after forming a step according to one or more embodiments;

[0013] Figure 2B FIG. 1 illustrates a method of performing a multi-functional optical fiber transmission system according to one or more embodiments. Figure 2A a cross-sectional view of a memory device stack;

[0014] Figure 3 illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0015] Figure 4 illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0016] FIG. 5A to FIG. 5C illustrates a cross-sectional view during an annealing process for crystallizing a memory layer according to one or more embodiments;

[0017] Figure 6 illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0018] Fig. 7A illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0019] Figure 7B illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0020] Fig. 8A illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0021] Figure 8B FIG. 1 illustrates a method of performing a multi-functional optical fiber transmission system according to one or more embodiments. Fig. 8A A cross-sectional view of a memory device;

[0022] Fig.9A illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0023] Fig. 9B FIG. 1 illustrates a method of performing a multi-functional optical fiber transmission system according to one or more embodiments. Fig.9A A cross-sectional view of a memory device;

[0024] Fig. 10A illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0025] Fig. 10B FIG. 1 illustrates a method of performing a multi-functional optical fiber transmission system according to one or more embodiments. Fig. 10A A cross-sectional view of a memory device;

[0026] Fig.11A illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0027] Fig. 11B FIG. 1 illustrates a method of performing a multi-functional optical fiber transmission system according to one or more embodiments. Fig.11A A cross-sectional view of a memory device;

[0028] Fig. 12A illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0029] Fig. 12B FIG. 1 illustrates a method of performing a multi-functional optical fiber transmission system according to one or more embodiments. Fig. 12A A cross-sectional view of a memory device;

[0030] Fig. 12C FIG. 1 illustrates a method of performing a multi-functional optical fiber transmission system according to one or more embodiments. Fig. 12B An enlarged cross-sectional view of a memory device;

[0031] Fig.13 illustrates an enlarged cross-sectional view of a memory device according to one or more embodiments;

[0032] Fig.14 illustrates an enlarged cross-sectional view of a memory device according to one or more embodiments;

[0033] Fig.15 illustrates an enlarged cross-sectional view of a memory device according to one or more embodiments;

[0034] Fig.16 illustrates an enlarged cross-sectional view of a memory device according to one or more embodiments;

[0035] Fig.17 illustrates an enlarged cross-sectional view of a memory device according to one or more embodiments;

[0036] Fig.18A illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0037] Fig.18B FIG. 1 illustrates a method of performing a multi-functional optical fiber transmission system according to one or more embodiments. Fig.18A A cross-sectional view of a memory device;

[0038] Fig.19A illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0039] Fig.19B FIG. 1 illustrates a method of performing a multi-functional optical fiber transmission system according to one or more embodiments. Fig.19A A cross-sectional view of a memory device;

[0040] Fig. 20 illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0041] Fig.21 illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0042] Fig. 22 illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0043] Fig.23A illustrates a cross-sectional view of a memory device according to one or more embodiments;

[0044] Fig. 23B FIG. 1 illustrates a method according to one or more alternative embodiments. Fig.23A A cross-sectional view of a memory device;

[0045] Fig.24A illustrates a cross-sectional view of a memory device according to one or more alternative embodiments;

[0046] Fig. 24B FIG. 1 illustrates a method according to one or more alternative embodiments. Fig.24A A cross-sectional view of a memory device;

[0047] Fig.25A illustrates a cross-sectional view of a memory device according to one or more alternative embodiments;

[0048] Fig.25B FIG. 1 illustrates a method according to one or more alternative embodiments. Fig.25A A cross-sectional view of a memory device;

[0049] Fig.26A illustrates a cross-sectional view of a memory device according to one or more alternative embodiments;

[0050] Fig.26B FIG. 1 illustrates a method according to one or more alternative embodiments. Fig.26A A cross-sectional view of a memory device;

[0051] Fig. 27 illustrates a cross-sectional view of a memory device according to one or more alternative embodiments;

[0052] Fig.28 illustrates a cross-sectional view of a memory device according to one or more alternative embodiments;

[0053] Fig.29 illustrates a cross-sectional view of a memory device according to one or more alternative embodiments;

[0054] Fig.30 An illustration of a cluster tool in accordance with one or more implementations. DETAILED DESCRIPTION

[0055] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0056] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactant gas," and the like are used interchangeably to represent any gaseous species that can react with a substrate surface.

[0057] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores a reference bit by either storing a charge packet (i.e., a binary one) or storing no charge (i.e., a binary zero) on a capacitor. The charge is gated onto the capacitor via an access transistor, and the charge is sensed by turning on the same transistor and looking at the voltage perturbation produced by dumping a charge packet on the interconnect line at the transistor output. Thus, a single DRAM cell consists of one transistor and one capacitor. As shown in FIG. 1 , a DRAM device is formed of an array of DRAM cells. The columns on the access transistors are linked by word lines 52a, 52b, and the transistor inputs / outputs are linked by bit lines 54a, 54b, 54c. Historically, DRAM capacitors have evolved from planar polysilicon oxide substrate capacitors to 3D structures that are dispersed into "stacked" capacitors with two plates above the substrate, and "trench" capacitors that use etched cavities in the substrate as common plates.

[0058] Traditionally, DRAM cells have a recessed high work function metal structure in a buried word line structure. In a DRAM device, the bit line is formed in a metal level located above the substrate, while the word line is formed at a polysilicon gate level at the surface of the substrate. In a buried word line (bWL), the word line is buried below the surface of the semiconductor substrate using metal as the gate electrode.

[0059] In one or more embodiments, a memory device having stacked DRAM cells is provided, resulting in an increase in DRAM cell bit density, which is proportional to the number of pairs of films. The DRAM device of one or more embodiments has vertical bit lines, thereby minimizing bit line capacitance and reducing the burden of capacitor capacitance. The DRAM device of one or more embodiments advantageously increases the mobility of highly stacked three-dimensional memory devices. Some embodiments advantageously provide DRAM devices incorporating a metal induced lateral crystallization (MILC) process.

[0060] Exemplary embodiments are described herein with reference to cross-sectional illustrations, which are schematic illustrations of exemplary embodiments (and intermediate structures). As such, variations from the illustrated shapes resulting from, for example, manufacturing techniques and / or tolerances are contemplated. Thus, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but may include deviations in shapes resulting from, for example, manufacturing.

[0061] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, depending on the application, the substrate surface on which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps can also be performed on underlying layers formed on the substrate (as disclosed in more detail below), and the term "substrate surface" is intended to include these underlying layers, as indicated in the context. Thus, for example, where a film / layer or portion of a film / layer has been deposited on a substrate surface, the exposed surface of the most recently deposited film / layer becomes the substrate surface.

[0062] Figure 2A An isometric view illustrating a memory device according to one or more embodiments. Figures 2B to 22 1 is a cross-sectional view illustrating a memory device 100 according to one or more embodiments. Figure 2A , the memory device 100 is formed in a staircase fashion of a stack 102 of alternating dielectric layers 104 and memory layers 106 . Figure 2B for Figure 2A 1. A cross-sectional view of a memory device stack of FIG. 1. In one or more embodiments, there are at least two dielectric layers 104. In one or more embodiments, there are at least two memory layers 106. In other embodiments, there are 2 to 100 dielectric layers 104 and 2 to 100 memory layers 106. Typically, there is one more dielectric layer 104 than memory layer 106, such that the stack 102 is defined on the top and bottom by the dielectric layers 104. As will be appreciated by those skilled in the art, while only two dielectric layers 104 and one memory layer 106 are depicted, the stack 102 may include any number of alternating dielectric layers 104 and memory layers 106.

[0063] As used herein, the term "dielectric layer" refers to a material layer of an electrical insulator that can be polarized in an electric field. In one or more embodiments, the dielectric layer includes one or more of an oxide, a carbon-doped oxide, silicon oxide (SiO), porous silicon dioxide (SiO2), silicon nitride (SiN), silicon oxide / silicon nitride, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, or an organosilicate glass (SiOCH).

[0064] As used herein, the term "memory layer" refers to a material layer in which word lines can be fabricated. In one or more embodiments, the memory layer includes one or more of silicon, doped silicon, amorphous silicon, or polycrystalline silicon. For example, in one or more embodiments, the memory layer is selected from one or more of amorphous silicon, polycrystalline silicon, or IGZO (indium-gallium-zinc oxide). In some embodiments, the dielectric layer includes a material that is etch selective relative to the memory layer.

[0065] Reference Figure 3 , opening 200 through stack 102. In some embodiments, opening 200 includes etching through dielectric layer 104 and memory layer 106. Opening 200 has sidewalls that extend through stack 102, exposing surface 202 of dielectric layer 104 and exposed surface 204 of memory layer 106.

[0066] Reference Figure 4 , a crystallization agent 206 is deposited in the opening 200 to be deposited on the exposed surface 202 of the dielectric layer 104 and the exposed surface 204 of the memory layer 106. The crystallization agent 206 may be deposited by any suitable technique known to a skilled person. The crystallization agent 206 includes a material that can crystallize the memory layer 106 into a single crystalline silicon layer. As used in this manner, the term "single crystalline silicon" refers to a material having greater than or equal to about 50%, 60%, 70%, 80%, 90%, 95%, or 98% of the crystals oriented in the same direction relative to each other.

[0067] The crystallizing agent 206 of some embodiments comprises a material having a lattice constant within ±50% of polysilicon. In some embodiments, the crystallizing agent 206 comprises one or more of nickel (Ni), chromium (Cr), cobalt (Co), palladium (Pd), germanium (Ge), aluminum (Al), or tungsten (W). In some embodiments, the crystallizing agent 206 comprises nickel (Ni) or consists essentially of nickel (Ni). As used in this manner, the term "consisting essentially of..." means that the active component of the crystallizing agent is greater than or equal to about 95%, 98%, 99%, or 99.5% of the material.

[0068] After forming the crystallization agent 206 in the opening 200 to reach the exposed surface 202 of the dielectric layer 104 and the exposed surface 204 of the memory layer 106, the memory device is annealed, such as FIG. 5A to FIG. 5C Annealing the memory device drives the crystallizing agent 206 through the memory layer 106 to crystallize the memory layer 106 to form a single crystalline silicon layer 208. As the annealing time passes, the crystallizing agent / Si interface (e.g., nickel / Si interface; also referred to as region 207 of the crystallizing agent 206) moves downward and the area it passes through becomes the single crystalline silicon layer 208. At the final stage of the annealing, the interface faces the end of the memory layer 106. The amount of crystallizing agent remaining in the single crystalline silicon layer 208 is negligible.

[0069] Annealing the memory device may be accomplished by any suitable technique known to a skilled artisan. For example, annealing may occur in a temperature range of about 300° C. to about 700° C. in an inert atmosphere. In one or more embodiments, annealing may occur at a temperature of about 500° C.

[0070] Figure 5A A region 207 of the crystallization agent 206 is shown, which is approximately one tenth of the length of the memory layer 106. The portion of the memory layer 106 that has been passed by the region 207 of the crystallization agent 206 has been converted into a single crystalline silicon layer 208.

[0071] Figure 5B The memory device is shown after a region 207 of the crystallization agent 206 has been driven through approximately two-thirds of the length of the memory layer 106 .

[0072] Figure 5C The memory device is shown after a region 207 of the crystallization agent 206 has been driven through more than ninety percent of the length of the memory layer 106 .

[0073] In some embodiments, annealing the memory device causes the crystallization agent 206 to move through the memory layer 106 at a rate in a range of about 0.5 μm / hour to about 2.5 μm / hour. In one or more embodiments, the annealing takes about 0.1 hours to about 10 hours to complete. The amorphous silicon or polycrystalline silicon in the memory layer has grain boundaries that hinder the electron charge path, resulting in reduced transistor performance. In some embodiments, annealing the memory device advantageously increases the grain size of the amorphous silicon or polycrystalline silicon in the memory layer 106, thereby forming a single crystalline silicon layer 208.

[0074] Reference Figure 6 , the crystallization agent 206 in the opening 200 is removed. The crystallization agent 206 may be removed by any suitable technique known to a skilled person. Suitable techniques include, but are not limited to, etching and chemical mechanical planarization.

[0075] Reference Fig. 7A and Figure 7B , an oxide filler 210 is deposited in the opening 200, and the oxide filler 210 is planarized so that the oxide filler 210 is substantially coplanar with the top surface 211 of the dielectric layer 104. In one or more embodiments, the oxide filler 210 includes one or more of an oxide, a carbon-doped oxide, silicon oxide (SiO), porous silicon dioxide (SiO2), silicon nitride (SiN), silicon oxide / silicon nitride, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, or an organosilicate glass (SiOCH). The oxide filler 210 may be deposited by any technique known to those skilled in the art, including but not limited to atomic layer deposition or chemical vapor deposition.

[0076] Reference Fig. 8A and Figure 8B , the crystallization agent 206 is removed by etching, and the memory device 100 is etched through the stack 102 to form a pre-word line extension 108 on at least some or each of the single crystalline silicon layers 208. As those skilled in the art will appreciate, the formation of the pre-word line extension 108 will form two portions (portion 300a and portion 300b) in the memory device. In some embodiments, at least some or each of the single crystalline silicon layers 208 has a plurality of pre-word line extensions 108. As those skilled in the art will appreciate, there may be many pre-word line extensions 108 in each single crystalline silicon layer 208, but for simplicity of drawing, only a single pre-word line extension 108 is illustrated. Figure 8B For along Fig. 8A In one or more embodiments, the plurality of pre-wordline extensions 108 are formed by etching at least one trench through the stack 102 of alternating dielectric layers 104 and single crystalline silicon layers 208 and selectively removing the dielectric layers 104 .

[0077] In some embodiments, at least one trench is etched through an opening in a mask (not shown) formed on the stack 102, followed by an anisotropic etching process.

[0078] In order to facilitate viewing of the structure contained in the memory device 100, FIG. 9A to FIG. 21 , the portion 300b is not shown. Fig.9A and Fig. 9B , a gate oxide layer 110 is formed on the pre-word line extension 108 . Fig. 9B For along Fig.9A100b is a cross-sectional view of the gate oxide layer 110 along the axis AA′. The illustrated embodiment shows the gate oxide layer 110 as a conformal layer having a uniform shape. However, the skilled person will recognize that this is for illustrative purposes only and the gate oxide layer 110 can be formed in an isotropic manner so that the gate oxide layer 110 has a rounded appearance.

[0079] In one or more embodiments, the gate oxide layer 110 includes a gate oxide material. In one or more embodiments, the gate oxide layer 110 includes one or more of silicon oxynitride (SiON), silicon oxide, or a high-k dielectric material. Although the term "silicon oxide" may be used to describe the gate oxide layer 110, the skilled person will recognize that the present disclosure is not limited to a particular stoichiometry. For example, the terms "silicon oxide" and "silicon dioxide" may be used to describe a material having silicon and oxygen atoms in any suitable stoichiometric ratio. The same is true for other materials listed in the present disclosure, such as silicon nitride, silicon oxynitride, tungsten oxide, zirconium oxide, aluminum oxide, hafnium oxide, and the like.

[0080] Reference Fig. 10A and Fig. 10B , word lines 114 are formed by depositing word line metal 112 on the plurality of pre-word line extensions 108 and the gate oxide layer 110 . Fig. 10B For along Fig. 10A 100b of the cross-sectional view of the axis AA′. The illustrated embodiment shows the word line metal 112 as a conformal layer having a uniform shape. However, the skilled person will recognize that this is for illustrative purposes only and the gate oxide layer 110 can be formed in an isotropic manner so that the gate oxide layer 110 has a rounded appearance. When the word line metal 112 is deposited on the plurality of pre-word line extensions 108, the pre-word line extensions 108 are electrically connected. In one or more embodiments, the word line metal 112 is deposited on the gate oxide layer 110. In one or more embodiments, the word line metal 112 includes one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). The word line metal 112 is deposited using any of a number of methods known to those skilled in the art, including but not limited to chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0081] As used herein, "atomic layer deposition" or "cyclic deposition" represents the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate or a portion of the substrate is individually exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to adhere and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are considered to be exposed to the substrate in sequence. During a spatial ALD process, different portions of the substrate surface or materials on the substrate surface are simultaneously exposed to two or more reactive compounds, so that any given point on the substrate is not substantially exposed to more than one reactive compound at the same time. As used in this specification and the appended claims, as will be understood by those skilled in the art, the term "substantially" used in this regard means that it is possible that a small portion of the substrate may be exposed to multiple reactive gases simultaneously due to diffusion, and the simultaneous exposure is unexpected.

[0082] In one aspect of a time-domain ALD process, a first reactant gas (i.e., a first precursor or compound A, e.g., an aluminum precursor) is pulsed into a reaction zone followed by a first time delay. Next, a second precursor or compound B (e.g., an oxidant) is pulsed into the reaction zone followed by a second delay. During each time delay, a purge gas (e.g., argon) is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactant compounds or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process so that only the purge gas flows during the time delay between pulses of the reactant compounds. The reactant compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process of pulsing compound A, purge gas, compound B, and purge gas is a cycle. The cycle may start with either compound A or compound B and continue in the corresponding order of the cycle until a film having a predetermined thickness is obtained.

[0083] In an embodiment of a spatial ALD process, a first reactant gas and a second reactant gas (e.g., nitrogen) are delivered to the reaction zone simultaneously, but separated by an inert gas curtain and / or a vacuum curtain. The substrate moves relative to the gas delivery device so that any given point on the substrate is exposed to the first reactant gas and the second reactant gas.

[0084] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to co-flow or where most precursor exposures overlap.

[0085] Plasma enhanced chemical vapor deposition (PECVD) is widely used to deposit thin films due to its cost-effectiveness and diversity of film properties. In the PECVD process, for example, a hydrocarbon source (such as vapor of a gaseous or liquid hydrocarbon) entrained in a carrier gas is introduced into a PECVD chamber. A plasma-initiating gas (usually helium) is also introduced into the chamber. A plasma is then initiated in the chamber to form excited CH radicals. The excited CH radicals chemically bond to the surface of a substrate positioned in the chamber, thereby forming a desired film thereon. Any suitable thin film deposition system may be used to perform the embodiments described herein with reference to the PECVD process. Any device description described herein is illustrative and should not be interpreted or construed as limiting the scope of the embodiments described herein.

[0086] Reference Fig.11A and Fig. 11B , and then a dielectric material 116 is deposited on (and around) the word line 114 . Fig. 11B For along Fig.11A The dielectric material 116 is deposited using any of a number of methods known to those skilled in the art, including but not limited to chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The dielectric material 116 can be the same composition as the dielectric layer 104 or a different composition.

[0087] Reference FIG. 12A to FIG. 12C The alternating dielectric layers 104 and the single crystalline silicon layer 208 having the plurality of word lines 114 are then patterned to form a plurality of bit line openings 118. In one or more embodiments, each bit line opening 118 extends through the alternating dielectric layers 104 and the single crystalline silicon layer 208. Fig. 12B For along Fig. 12A Cross-sectional view 100b along axis AA′. Fig. 12C for Fig. 12B A magnified view of the area / square in 100c.

[0088] Reference Fig.13 , Fig.13 for Fig. 12B In the enlarged view 100c of the area / square 120 in FIG. 1 , the wordline metal 112 is recessed. The recessing of the wordline metal 112 may be performed by any suitable technique known to a skilled person. Recessing the wordline metal 112 results in the top surface 113 of the wordline metal 112 being lower than the top surface 111 of the gate oxide layer 110. Recessing the wordline metal 112 exposes the top surface 111 of the gate oxide layer 110 to the bitline opening 118.

[0089] Reference Fig.14 , Fig.14for Fig. 12B 100c, an oxide 122 is conformally deposited in the plurality of bitline openings 118 and on the exposed surfaces of the dielectric material 116 and on the gate oxide layer 110. In one or more embodiments, the oxide 122 may include any suitable oxide material known to those skilled in the art. In the illustrated embodiment, the oxide 122 is selectively deposited on the dielectric material relative to the gate oxide layer 110. In some embodiments, the oxide 122 is deposited on the gate oxide layer 110 and the dielectric material.

[0090] Reference Fig.15 , Fig.15 for Fig. 12B 100c, oxide 122 is selectively removed so that only a portion of the oxide remains adjacent to wordline metal 112 and gate oxide layer 110. When oxide 122 is selectively removed, a portion of gate oxide layer 110 over pre-wordline extension 108 is also removed, leaving a portion of pre-wordline extension 108 exposed in bitline opening 118. Oxide 122 is selectively removed using any of a number of methods known to those skilled in the art, including but not limited to chemical mechanical polishing (CMP), etching, or the like. In the illustrated embodiment, oxide 122 and gate oxide layer 110 are removed so that a top surface 123 of oxide 122 and a top surface 111 of gate oxide layer 110 are recessed below a top surface 109 of pre-wordline extension 108 by approximately the same amount.

[0091] Reference Fig.16 , Fig.16 for Fig. 12B 100c, a liner 124 is conformally deposited in the plurality of bitline openings 118 and on the exposed surfaces of the dielectric material 116, the gate oxide layer 110, the pre-wordline extensions 108, and the oxide 122. The liner 124 may be deposited by any suitable technique known to a skilled person. The liner 124 may be any suitable material, including but not limited to titanium nitride (TiN) or tantalum nitride (TaN).

[0092] Reference Fig.17 , Fig.17 for Fig. 12B100c of the area / square 120 in FIG. 100c, a bitline metal 126 is deposited in the plurality of bitline openings 118 to form bitlines 128. In one or more embodiments, the bitline metal 126 comprises one or more of WSi, WN, or W. The bitline metal layer 126 may be deposited by any suitable technique known to a skilled person and may be any suitable material. In one or more embodiments, forming the wordline 114 further comprises forming a bitline metal seed layer on the oxide layer 122 before depositing the bitline metal 126.

[0093] Reference Fig.18A and Fig.18B , illustrates the memory device 100 with the dielectric layer 104 removed for ease of viewing. Fig.18B For along Fig.18A The stack 102 has at least one bit line 128 extending through alternating dielectric layers (removed for ease of viewing) and single crystalline silicon layers 208. Each single crystalline silicon layer 208 has at least one word line 114, the at least one word line 114 including a pre-word line extension 108, a gate oxide layer 110, and a first metal layer 112. The at least one word line 114 has a first side 130 adjacent to the bit line 128, and a second side 132 opposite the first side 130.

[0094] Reference Fig.19A and Fig.19B , at least one pre-capacitor extension 134 is formed in the single crystalline silicon layer 208 . Fig.19B For along Fig.19A 100d of the cross-sectional view along the axis BB′ of FIG. 100. The pre-capacitor extension 134 contacts the second side 132 of the word line 114. In one or more embodiments, forming at least one pre-capacitor extension 134 in the single crystalline silicon layer 208 includes forming a mask layer (not shown) on the single crystalline silicon layer 208, and etching the single crystalline silicon layer 208 through the mask layer to form the pre-capacitor extension 134. In one or more embodiments, the method further includes selectively removing a portion of the dielectric layer 104 (not shown for ease of viewing), and doping the pre-capacitor extension 134 to form a bottom electrode.

[0095] exist Fig. 20 middle, Fig. 20 For along Fig.19AIn a cross-sectional view of axis BB′, at least one pre-capacitor extension 134 is first formed into capacitor 140 by depositing a high-k dielectric 136 on the pre-capacitor extension 134. In one or more embodiments, the term "high-k dielectric" represents a material with a high dielectric constant (e.g., compared to silicon dioxide). In one or more embodiments, the high-k dielectric material is selected from one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), vanadium oxide (VO2), titanium oxide (TiO2), tin oxide (SnO2), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO) or niobium oxide (Nb2O5).

[0096] exist Fig.21 middle, Fig.21 For along Fig.19A In a cross-sectional view of axis BB′, capacitor 140 is first formed by depositing a top contact 138 on high-k dielectric 136 on pre-capacitor extension 134. In one or more embodiments, top contact 138 can be any suitable material known to a skilled person. In one or more embodiments, top contact 138 is selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt).

[0097] Reference Fig. 22One or more embodiments provide a memory device 100 including a plurality of bit lines 128 extending through a stack 102 of alternating memory layers 106 and dielectric layers 104. In one or more embodiments, each of the memory layers 106 includes: a single crystalline silicon layer 208; a first word line 114a having a first side 130a adjacent to a first side of the plurality of bit lines 128 and a second side 132a opposite the first side 130a; a second word line 114b having a first side 130b adjacent to a second side of the plurality of bit lines 128 and a second side 132b opposite the first side 130b; and at least one first capacitor 140 adjacent to the second side 132a of the first word line 114a; and at least one second capacitor 140b adjacent to the second side 132b of the second word line 114b. In one or more embodiments, the first word line 114a and the second word line 114b independently include a pre-word line extension 108, wherein the pre-word line extension 108 includes a single crystalline silicon layer 208, a gate oxide layer 110, and a first metal layer 112. In one or more embodiments, the gate oxide layer 110 includes a gate oxide material. In one or more embodiments, the gate oxide layer 110 includes one or more of silicon oxynitride (SiON), silicon oxide, or a high-k dielectric material. In one or more embodiments, the word line first metal layer 112 includes one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). The word line metal 112 is deposited using any of a number of methods known to those skilled in the art, including but not limited to chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0098] In one or more embodiments, the plurality of bit lines 128 include one or more of WSi, WN, or W. In one or more embodiments, the at least one first capacitor 140a and the at least one second capacitor 140b independently include one or more of a high-k dielectric or a metal layer including one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh).

[0099] In one or more embodiments, the first word line 114a and the second word line 114b independently include one or more of a gate oxide layer 136 or a top contact 138. In one or more embodiments, the gate oxide layer 136 includes one or more of silicon oxynitride (SiON), silicon oxide (SiO), or a high-k dielectric material. In one or more embodiments, the top contact 138 includes one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt).

[0100] In one or more embodiments, the memory device 100 includes at least one first word line contact 150 in electrical communication with the first word line 114a, and at least one second word line contact in electrical communication with the second word line 114b. In one or more embodiments, the at least one first word line contact and the at least one second word line contact each extend through the alternating memory layers 106 including the single crystalline silicon layer 208 and the dielectric layer 104 a distance sufficient to terminate at one of the first word line 114a or the second word line 114b.

[0101] FIG. 23A to FIG. 28 One or more alternative implementations are provided. Fig.23A and Fig. 23B , and Fig.19A and Fig.19B The same, except that the dashed lines are drawn to illustrate the dielectric layer 104 , at least one pre-capacitor extension 134 is formed in the single crystalline silicon layer 208 . Fig. 23B For along Fig.23A 100d of the cross-sectional view along the axis BB′ of FIG. The pre-capacitor extension 134 contacts the second side 132 of the word line 114. In one or more embodiments, forming at least one pre-capacitor extension 134 in the single crystalline silicon layer 208 includes forming a mask layer (not shown) on the single crystalline silicon layer 208, and etching the single crystalline silicon layer 208 through the mask layer to form the pre-capacitor extension 134. In one or more embodiments, the method further includes selectively removing a portion of the dielectric layer 104, and doping the pre-capacitor extension 134 to form a bottom electrode.

[0102] exist Fig.24A and Fig. 24BIn the embodiment, the single crystalline silicon layer 208 is conformally doped to form a highly doped silicon layer 212. For example, in one or more embodiments, after a portion of the single crystalline silicon layer 208 is removed to form the pre-capacitor extension 132, the remaining single crystalline silicon layer 208 may be doped by PLAD (plasma doping) or vapor phase doping in a gas environment having phosphorus (P) or arsenic (As). Fig. 24B For along Fig.24A The single-crystal silicon layer 208 remains in the word line 114 .

[0103] Reference Fig.25A and Fig.25B , the highly doped silicon layer 212 is recessed, thereby forming a groove 213 . Fig.25B For along Fig.25A In one or more embodiments, the highly doped silicon layer 212 is grooved. The groove depth is controlled to prevent etching of the word line 114, and thus, a small portion of the highly doped silicon layer 212 remains adjacent to the second side 132 of the word line 114.

[0104] Reference Fig.26A and Fig.26B , depositing metal through the opening 213 to form a second metal material 214. In one or more embodiments, the metal material 214 may be deposited by any technique known to those skilled in the art, including but not limited to physical vapor deposition, atomic layer deposition, or chemical vapor deposition. In one or more embodiments, the metal material 214 includes one or more metals selected from copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh) and the like.

[0105] In other embodiments, metal is deposited through the opening 213 to form a metal nitride material 214. In one or more embodiments, the metal nitride material 214 can be deposited by any technique known to those skilled in the art, including but not limited to physical vapor deposition, atomic layer deposition, or chemical vapor deposition. In one or more embodiments, the nitride metal nitride material 214 includes one or more metal nitrides selected from titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), tungsten silicon nitride (WSiN), and the like.

[0106] Reference Fig. 27 , Fig. 27 For along Fig.26AIn a cross-sectional view of axis BB′, at least one pre-capacitor extension 134 is first formed into capacitor 140 by depositing a high-k dielectric 136 on the pre-capacitor extension 134 including a second metal material 214 and highly doped silicon 212. In one or more embodiments, the term "high-k dielectric" represents a material having a high dielectric constant (e.g., compared to silicon dioxide). In one or more embodiments, the high-k dielectric material is selected from one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), vanadium oxide (VO2), titanium oxide (TiO2), tin oxide (SnO2), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium silicon oxide (HfSiO), or zirconium silicon oxide (ZrSiO) or niobium oxide (Nb2O5).

[0107] exist Fig.28 middle, Fig.28 For along Fig.26A In a cross-sectional view of axis BB′, a capacitor 140 is first formed by depositing a top contact 138 on a high-k dielectric 136 on a pre-capacitor extension 134 including a second metal material 214 and highly doped silicon 212. In one or more embodiments, the top contact 138 can be any suitable material known to a skilled person. In one or more embodiments, the top contact 138 is selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt).

[0108] Reference Fig.29One or more embodiments provide a memory device 100 that includes a plurality of bit lines 128 extending through a stack 102 of alternating memory layers 106 and dielectric layers 104. In one or more embodiments, each of the memory layers 106 includes a single crystalline silicon layer 208, a metal nitride material 214, and highly doped silicon 212. Each of the memory layers 106 includes: a first word line 114a, the first word line 114a includes a single crystalline silicon layer 208 and has a first side 130a adjacent to a first side of a plurality of bit lines 128 and a second side 132a opposite to the first side 130a; a second word line 114b, the second word line 114b includes a single crystalline silicon layer 208 and has a first side 130b adjacent to a second side of the plurality of bit lines 128 and a second side 132b opposite to the first side 130b; and at least one first capacitor 140, the at least one first capacitor 140 includes a metal nitride material 214 and highly doped silicon 212, the at least one first capacitor 140 is adjacent to the second side 132a of the first word line 114a; and at least one second capacitor 140b, the at least one second capacitor 140b includes a metal nitride material 214 and highly doped silicon 212, the at least one second capacitor 140b is adjacent to the second side 132b of the second word line 114b. In one or more embodiments, the second metal nitride material 214 includes one or more metals selected from titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), tungsten silicon nitride (WSiN), and the like.

[0109] In one or more embodiments, the first word line 114a and the second word line 114b independently include a pre-word line extension 108, wherein the pre-word line extension 108 includes a single crystalline silicon layer 208, a gate oxide layer 110, and a first metal layer 112. In one or more embodiments, the gate oxide layer 110 includes a gate oxide material. In one or more embodiments, the gate oxide layer 110 includes one or more of silicon oxynitride (SiON), silicon oxide, or a high-k dielectric material. In one or more embodiments, the word line first metal layer 112 includes one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). The word line metal 112 is deposited using any of a number of methods known to those skilled in the art, including but not limited to chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0110] In one or more embodiments, the plurality of bit lines 128 include one or more of WSi, WN, or W. In one or more embodiments, the at least one first capacitor 140a and the at least one second capacitor 140b independently include one or more of a high-k dielectric or a metal layer including one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh).

[0111] In one or more embodiments, the first word line 114a and the second word line 114b independently include one or more of a gate oxide layer 136 or a top contact 138. In one or more embodiments, the gate oxide layer 136 includes one or more of silicon oxynitride (SiON), silicon oxide (SiO), or a high-k dielectric material. In one or more embodiments, the top contact 138 includes one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt).

[0112] In one or more embodiments, the memory device 100 includes at least one first word line contact 150 in electrical communication with the first word line 114a, and at least one second word line contact in electrical communication with the second word line 114b. In one or more embodiments, the at least one first word line contact and the at least one second word line contact each extend through the alternating memory layers 106 including the single crystalline silicon layer 208 and the dielectric layer 104 a distance sufficient to terminate at one of the first word line 114a or the second word line 114b.

[0113] Additional embodiments of the present disclosure relate to a processing tool 900 for forming the memory devices and methods described herein, such as Fig.30 as shown in .

[0114] The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are positioned within the central transfer station 921, 931 and are configured to move robot blades and wafers to each of the multiple sides.

[0115] The cluster tool 900 includes a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as process stations, connected to a central transfer station. Each processing chamber provides a separate processing area isolated from an adjacent process station. The processing chamber may be any suitable chamber, including but not limited to a pre-cleaning chamber, a buffer chamber, (several) transfer spaces, a wafer orienter / degas chamber, a cryogenic cooling chamber, a deposition chamber, an annealing chamber, an etching chamber, and a crystallizing agent removal chamber. The specific arrangement of the processing chambers and components may vary depending on the cluster tool and should not be considered as limiting the scope of the present disclosure.

[0116] In some embodiments, the cluster tool 900 includes a crystallization agent deposition chamber. The crystallization agent deposition chamber of some embodiments includes one or more of an atomic layer deposition chamber, a plasma enhanced atomic layer deposition chamber, a chemical vapor deposition chamber, a plasma enhanced chemical vapor deposition chamber, or a physical deposition chamber. In some embodiments, the cluster tool 900 includes a pre-clean chamber connected to the central transfer station.

[0117] exist Fig.30 In the embodiment shown in FIG. 1 , the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, those skilled in the art will understand that this represents only one possible configuration.

[0118] The size and shape of the loading chamber 954 and the unloading chamber 956 may vary depending, for example, on the substrates being processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette having a plurality of wafers positioned therein.

[0119] The robot 952 is located within the factory interface 950 and can move between the loading chamber 954 and the unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 to a load lock chamber 960 via the factory interface 950. The robot 952 can also transfer wafers from a load lock chamber 962 to a cassette in the unloading chamber 956 via the factory interface 950. As will be appreciated by those skilled in the art, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960, and a second robot that transfers wafers between the load lock chamber 962 and the unloading chamber 956.

[0120] The cluster tool 900 shown has a first portion 920 and a second portion 930. The first portion 920 is connected to a factory interface 950 via load lock chambers 960, 962. The first portion 920 includes a first transfer chamber 921 having at least one robot 925 positioned therein. The robot 925 is also referred to as a robot-type wafer transport mechanism. The first transfer chamber 921 is centrally positioned relative to the load lock chambers 960, 962, the processing chambers 902, 904, 916, 918, and the buffer chambers 922, 924. The robot 925 of some embodiments is a multi-arm robot that is capable of independently moving more than one wafer at a time. In some embodiments, the first transfer chamber 921 includes more than one robot-type wafer transport mechanism. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Individual wafers are carried on a wafer transport blade located at the distal end of the first robot-type mechanism.

[0121] After processing the wafer in the first portion 920, the wafer may be transferred to the second portion 930 via a pass-through chamber. For example, the chambers 922, 924 may be one-way or two-way pass-through chambers. The pass-through chambers 922, 924 may be used, for example, to cryogenically cool the wafer prior to processing in the second portion 930, or to allow for wafer cooling or post-processing prior to moving back to the first portion 920.

[0122] The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component capable of controlling the processing chambers and the robot. For example, the system controller 990 may be a computer including a central processing unit, memory, appropriate circuits and storage.

[0123] The process may be stored in memory of the system controller 990 generally as a software program that, when executed by the processor, causes the processing chamber to perform the process of the present disclosure. The software program may also be stored and / or executed by a second processor (not shown) that is located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the process may be implemented in software and executed using a computer system, implemented in hardware as, for example, an application specific integrated circuit or other type of hardware implementation, or implemented as a combination of software and hardware. When executed by the processor, the software program transforms a general purpose computer into a special purpose computer (controller) that controls the operation of the chamber so that the process can be performed.

[0124] In some embodiments, the system controller 990 has a configuration for controlling the annealing chamber to anneal the wafer at a temperature in a range of about 300° C. to about 700° C. for a time of about 0.1 hour to about 12 hours. In some embodiments, the controller 990 has a configuration for activating a pre-cleaning chamber to remove an oxide layer from the wafer.

[0125] For simplicity of description, spatially relative terms such as "below," "below," "lower," "above," "upper," and similar terms may be used herein to describe the relationship of one element or feature to another (other) element or feature as illustrated in the figures. It should be understood that these spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, the elements described as "below" or "below" other elements or features will then be oriented "above" the other elements or features. Therefore, the exemplary term "below" can cover orientations above as well as below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0126] Unless otherwise indicated herein or clearly contradictory to the context, in the context of describing the materials and methods discussed herein (especially in the context of the following claims), the use of the terms "a" and "an" and "said" and similar representative words should be interpreted as covering both singular and plural forms. Unless otherwise specified herein, the enumeration of the range of values ​​herein is intended only to be used as a shorthand method for representing each individual value within the range individually, and each individual value is incorporated into this specification as if it were individually described herein. All methods described herein can be performed in any appropriate order, unless otherwise indicated herein or clearly contradictory to the context. Unless otherwise required, the use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the materials and methods, and is not intended to limit the scope. The language in the specification should not be interpreted as indicating that any unclaimed element is essential to the practice of the disclosed materials and methods.

[0127] Throughout this specification, references to "one embodiment", "certain embodiments", "one or more embodiments" or "embodiments" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments are included in at least one embodiment of the present disclosure. Therefore, phrases such as "in one or more embodiments", "in certain embodiments", "in one embodiment" or "in an embodiment" that appear throughout this specification do not necessarily represent the same embodiment of the present disclosure. In one or more embodiments, specific features, structures, materials or characteristics are combined in any appropriate manner. Although the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments only illustrate the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and changes may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, it is intended that the present disclosure includes modifications and changes within the scope of the appended claims and their equivalents.

Claims

1. A memory device, comprising: a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers, each of the memory layers comprising: a first word line including a single crystalline silicon layer and having a first side adjacent to first sides of the plurality of bit lines and a second side opposite to the first side of the first word line, a second word line including a single crystalline silicon layer and having a first side adjacent to the second sides of the plurality of bit lines and a second side opposite to the first side of the second word line, at least one first capacitor, the at least one first capacitor comprising a single crystalline silicon layer, the at least one first capacitor being adjacent to the second side of the first word line, and at least one second capacitor, the at least one second capacitor comprising a single crystalline silicon layer, the at least one second capacitor being adjacent to the second side of the second word line, The single crystalline silicon layer of one or more of the first word line, the second word line, the at least one first capacitor and the at least one second capacitor is formed by a metal induced lateral crystallization process and includes a material having greater than or equal to 50% of crystals oriented in the same direction relative to each other.

2. The memory device of claim 1 , further comprising at least one first word line contact in electrical communication with the first word line and at least one second word line contact in electrical communication with the second word line, wherein the at least one first word line contact and the at least one second word line contact each extend through the alternating memory layers and dielectric layers a distance sufficient to terminate at one of the first word line or the second word line.

3. The memory device of claim 1 , wherein the plurality of bit lines comprise one or more of WSi, WN, or W, and wherein the at least one first capacitor and the at least one second capacitor independently further comprise one or more of a high-k dielectric material or a metal layer, the metal layer comprising one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh).

4. The memory device of claim 1 , wherein the first word line and the second word line independently further comprise one or more of a gate oxide layer or a word line metal, wherein the gate oxide layer comprises one or more of silicon oxynitride (SiON), silicon oxide (SiO), or a high-k dielectric material, and wherein the word line metal comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh).

5. A memory device comprising: a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers, each of the memory layers comprising: a first word line including a single crystalline silicon layer and having a first side adjacent to first sides of the plurality of bit lines and a second side opposite to the first side of the first word line, a second word line including a single crystalline silicon layer and having a first side adjacent to the second sides of the plurality of bit lines and a second side opposite to the first side of the second word line, at least one first capacitor, the at least one first capacitor comprising a metallic material and a highly doped silicon layer, the at least one first capacitor being adjacent to the second side of the first word line, and at least one second capacitor including a metallic material and a highly doped silicon layer, the at least one second capacitor being adjacent to the second side of the second word line, wherein the single crystalline silicon layer of one or more of the first word line and the second word line is formed by a metal induced lateral crystallization process and includes a material having greater than or equal to 50% of crystals oriented in the same direction relative to each other.

6. The memory device of claim 5 , further comprising at least one first word line contact in electrical communication with the first word line and at least one second word line contact in electrical communication with the second word line, wherein the at least one first word line contact and the at least one second word line contact respectively extend through the alternating memory layers and dielectric layers a distance sufficient to terminate at one of the first word line or the second word line.

7. The memory device of claim 6, wherein the plurality of bit lines comprise one or more of WSi, WN, or W, and wherein the at least one first capacitor and the at least one second capacitor independently further comprise one or more of a high-k dielectric material or a metal layer, the metal layer comprising one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh), and wherein the first word line and the second word line independently further comprise one or more of a gate oxide layer or a word line metal.

8. The memory device of claim 7, wherein the gate oxide layer comprises one or more of silicon oxynitride (SiON), silicon oxide (SiO), or a high-k dielectric material, and wherein the word line metal comprises one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh).

9. A method of forming a memory device, the method comprising the steps of: forming an opening extending through the stack of alternating dielectric and memory layers; depositing a crystallization agent into the opening; crystallizing the memory layer to form a single-crystal silicon layer; forming a plurality of pre-wordline extensions by etching at least one trench through a stack of alternating dielectric layers and single crystalline silicon layers and selectively removing the dielectric layers; forming a first word line having a first side and a second side opposite the first side by depositing a first word line metal on the plurality of pre-word line extensions to electrically connect the plurality of pre-word line extensions; patterning the alternating dielectric layers and single crystal silicon layers to form a plurality of bit line openings, each bit line opening extending through the alternating dielectric layers and single crystal silicon layers; depositing a bitline metal in the plurality of bitline openings to form a plurality of bitlines, each bitline having a first side and a second side opposite the first side, the first side being adjacent to the first side of the first wordline; and A second word line having a first side and a second side opposite the first side is formed by depositing a second word line metal on the plurality of pre-word line extensions on the second side of the plurality of bit lines.

10. The method of claim 9, wherein the at least one trench is etched through an opening in a mask formed on the stack.

11. The method of claim 9, further comprising forming at least one first word line contact in electrical communication with the first word line and at least one second word line contact in electrical communication with the second word line.

12. The method of claim 11, wherein the at least one first word line contact and the at least one second word line contact each extend through the alternating memory and dielectric layers a distance sufficient to terminate at one of the first word line or the second word line.

13. The method of claim 9, wherein the step of forming the first word line further comprises the following steps: Prior to depositing the first wordline metal, an oxide layer is formed on the pre-wordline extension.

14. The method of claim 13, wherein the step of forming the first word line further comprises the following steps: Before depositing the bit line metal, a bit line metal seed layer is formed on the oxide layer.

15. The method of claim 9, further comprising the steps of: forming at least one pre-capacitor extension in the memory layer, the pre-capacitor extension contacting the second side of the first word line; And forming a capacitor on the at least one pre-capacitor extension.

16. The method of claim 15, wherein the step of forming the at least one pre-capacitor extension comprises the steps of: A portion of the single crystalline silicon layer on the second side of the first word line is selectively removed, the second side being adjacent to the first sides of the plurality of bit lines; and wherein the step of forming the capacitor comprises the steps of depositing one or more of a high-k dielectric material or a word line metal on the at least one pre-capacitor extension.

17. The method of claim 15, wherein the step of forming the at least one pre-capacitor extension comprises the steps of: The single crystalline silicon layer is conformally doped to form a highly doped silicon layer on the second side of the first word line adjacent to the first side of the plurality of bit lines, the highly doped silicon layer is recessed to form a groove, and a metal material is deposited in the groove; and wherein the step of forming the capacitor comprises the steps of depositing one or more of a high-k dielectric material or a word line metal on the at least one pre-capacitor extension.

18. The method of claim 15, further comprising the steps of: selectively removing a portion of the memory layer on the second side of the second word line to form at least one second pre-capacitor extension; And forming a second capacitor on the at least one second pre-capacitor extension.

19. The method of claim 18, wherein the step of forming the at least one second pre-capacitor extension comprises the steps of: A portion of the single crystalline silicon layer on the second side of the second word line is selectively removed, the second side being adjacent to the first sides of the plurality of bit lines; and wherein the step of forming the second capacitor comprises the steps of depositing one or more of a high-k dielectric material or a word line metal on the at least one second pre-capacitor extension.

20. The method of claim 18, wherein the step of forming the at least one second pre-capacitor extension comprises the steps of: The single crystalline silicon layer is conformally doped to form a highly doped silicon layer on the second side of the second word line adjacent to the first side of the plurality of bit lines, the highly doped silicon layer is recessed to form a groove, and a metal nitride material is deposited in the groove; and wherein the step of forming the second capacitor comprises the steps of: depositing one or more of a high-k dielectric material or a word line metal on the second pre-capacitor extension.

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