Sensor chips and electronic devices

Abstract

Provided are a sensor chip and electronic device having improved characteristics of a SPAD pixel having an avalanche photodiode element. The sensor chip is provided with: a pixel array portion having a pixel area in which a plurality of pixels are arranged in a matrix shape; an avalanche photodiode element that amplifies carriers respectively by providing a high electric field region to the pixel; an inter-pixel separation portion that insulates and separates each pixel in a semiconductor substrate having the avalanche photodiode element formed therein from another pixel adjacent thereto; and wirings that are respectively provided on a wiring layer stacked on a surface on a side opposite to a light receiving surface of the semiconductor substrate so as to cover at least the high electric field region. The pixel array portion has a dummy pixel area located near the peripheral edge of the pixel area. The cathode potential and the anode potential of each avalanche photodiode element arranged in the dummy pixel area are equal to each other, or the cathode potential and / or the anode potential are floating.

Description

Technical Field

[0001] The present invention relates to a sensor chip and an electronic device, and particularly to a sensor chip and an electronic device that enable characteristic enhancement of a SPAD pixel. Background Art

[0002] Nowadays, distance image sensors that measure distance using the ToF (time of flight) method are attracting attention. In such distance image sensors, for example, a pixel array can be used in which a plurality of SPAD (single photon avalanche diode) pixels, each including an avalanche photodiode element, are formed and arranged on a plane using CMOS (complementary metal oxide semiconductor) semiconductor integration technology. In each SPAD pixel, when a voltage much greater than the breakdown voltage is applied, when a photon is input to a high electric field PN junction region, avalanche amplification occurs. Detecting the time period when current instantaneously flows when avalanche amplification occurs enables high-precision distance measurement.

[0003] For example, Patent Document 1 describes a sensor chip in which SPAD pixels are arranged in an array in a predetermined pixel area. In the sensor chip of Patent Document 1, a peripheral area is provided outside an image area, and a pad area is provided outside the peripheral area.

[0004] List of citations

[0005] Patent Literature

[0006] Patent Document 1: International Publication No. WO 2018 / 074530 Summary of the Invention

[0007] Technical problem to be solved by the invention

[0008] However, when SPAD pixels are arranged in an array on a sensor chip, the periodicity of the SPAD pixels may collapse in areas near the peripheral edges of the pixel area. If the periodicity of the SPAD pixels collapses, the characteristics of the SPAD device may become abnormal, which may lead to bias variations and current increases that affect the characteristics of the entire sensor chip.

[0009] The present invention has been created in view of this problem, and provides a sensor chip and electronic device that achieve characteristic enhancement of SPAD pixels each including an avalanche photodiode.

[0010] Solutions to technical problems

[0011] To address the aforementioned issues, a sensor chip according to one aspect of the present invention includes: a pixel array section including a pixel region in which a plurality of pixels are arranged in rows and columns; an avalanche photodiode element that amplifies carriers via a high electric field region provided for each pixel; an inter-pixel isolation section that insulates and separates each pixel from an adjacent pixel in a semiconductor substrate in which the avalanche photodiode element is formed; and wiring arranged in a wiring layer so as to at least cover the high electric field region, the wiring layer being laminated on a surface opposite to a light-receiving surface of the semiconductor substrate. Furthermore, the pixel array section includes a dummy pixel region located near the outer edge of the pixel region, and the cathode and anode potentials of the avalanche photodiode elements arranged in the dummy pixel region are the same, or at least one of the cathode and anode potentials is in a floating state.

[0012] Furthermore, an electronic device according to another aspect of the present invention includes a sensor chip, the sensor chip comprising a pixel array portion including a pixel region in which a plurality of pixels are arranged in rows and columns; an avalanche photodiode element that amplifies carriers via a high electric field region provided for each pixel; an inter-pixel separator that insulates and separates each pixel from another adjacent pixel in a semiconductor substrate in which the avalanche photodiode element is formed; and wiring arranged in a wiring layer so as to cover at least the high electric field region, the wiring layer being laminated on a surface opposite to a light-receiving surface of the semiconductor substrate. Furthermore, the pixel array portion includes a dummy pixel region located near a peripheral edge of the pixel region, and the avalanche photodiode element arranged in the dummy pixel region has a cathode potential and an anode potential that are the same potential, or at least one of the cathode potential and the anode potential is in a floating state. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic diagram showing the configuration of the SPAD pixel formation surface of the sensor chip according to the first embodiment of the present invention.

[0014] Figure 2 is a block diagram showing a configuration example of a sensor chip according to the first embodiment of the present invention.

[0015] Figure 3 is a cross-sectional view of a SPAD pixel of the sensor chip according to the first embodiment of the present invention, illustrating a configuration example of the SPAD pixel.

[0016] Figure 4 is a cross-sectional view of a SPAD pixel of the sensor chip according to the first embodiment of the present invention, illustrating a configuration example of the SPAD pixel.

[0017] Figure 5is a cross-sectional view of a SPAD pixel of a sensor chip according to a second embodiment of the present invention, illustrating a configuration example of the SPAD pixel.

[0018] Figure 6 is a circuit diagram showing a configuration example of a sensor chip according to a third embodiment of the present invention.

[0019] Figure 7 is a cross-sectional view of a SPAD pixel of a sensor chip according to a third embodiment of the present invention, illustrating a configuration example of the SPAD pixel.

[0020] Figure 8 is a block diagram showing a configuration example of a sensor chip according to a fourth embodiment of the present invention.

[0021] Figure 9 is a circuit diagram showing a configuration example of a sensor chip according to a fifth embodiment of the present invention.

[0022] Figure 10 is a cross-sectional view of a SPAD pixel of a sensor chip according to a fifth embodiment of the present invention, illustrating a configuration example of the SPAD pixel.

[0023] Figure 11 is a circuit diagram showing a configuration example of a sensor chip according to a sixth embodiment of the present invention.

[0024] Figure 12 is a cross-sectional view of a SPAD pixel of a sensor chip according to a sixth embodiment of the present invention, illustrating a configuration example of the SPAD pixel.

[0025] Figure 13 is a block diagram showing a configuration example of a distance image sensor as an electronic device using the sensor chip according to the present invention. Specific implementation plan

[0026] The present invention will be described below using embodiments, but the following embodiments do not limit the invention set forth in the claims of this specification. Furthermore, not all combinations of features described in the following embodiments are essential for solving the problems set forth in this specification. Furthermore, the accompanying drawings schematically illustrate the invention set forth in the claims of this specification, and the dimensions of various parts, such as width and thickness, differ from actual dimensions, and the ratios between these dimensions also differ from actual ratios.

[0027] Hereinafter, various configurations according to various embodiments of the present invention will be described with reference to the accompanying drawings.

[0028] 1. First Implementation Method

[0029] Will use Figures 1 to 4The sensor chip according to the first embodiment is described.

[0030] <Configuration Example of Sensor Chip>

[0031] Figure 1 is a schematic diagram showing the configuration of the SPAD pixel formation surface of the sensor chip 10 . Figure 2 (A) is a block diagram showing a configuration example of a sensor chip 10 to which the present technology is applied. Figure 2 (B) and Figure 2 (C) are circuit diagrams showing the configurations of the respective SPAD pixels 21 and 22 included in the sensor chip 10 .

[0032] like Figure 1 As shown, the pixel array section 11 includes a pixel area A1 , a peripheral area A2 provided outside the pixel area A1 , and a pad area A3 formed outside the peripheral area A2 .

[0033] The pixel area A1 is a light receiving surface for receiving light collected by an optical system (not shown). In the pixel area A1, a plurality of SPAD pixels 21 and a plurality of SPAD pixels 22 are arranged in rows and columns.

[0034] In the pad region A3, there are formed a plurality of wiring electrode pads (hereinafter referred to as electrode pads) 23. The electrode pads 23 are used to connect the sensor chip 10 to an external device (not shown), for example.

[0035] The peripheral region A2 is a region between the pixel region A1 and the pad region A3. The peripheral region A2 includes, for example, an n-type semiconductor region and a p-type semiconductor region, and the p-type semiconductor region is connected to the ground (GND).

[0036] like Figure 2 As shown in FIG. 1A , the sensor chip 10 includes a bias voltage application section 12 and a pixel array section 11 .

[0037] The bias voltage applying section 12 applies a bias voltage to each of the plurality of SPAD pixels 21 arranged in the pixel array section 11 .

[0038] The pixel area A1 of the pixel array section 11 includes a reference pixel area RA located at the center of the pixel area A1 and a dummy pixel area DA located near a peripheral edge of the pixel area A1 and surrounding the reference pixel area RA.

[0039] The SPAD pixel 21 is a pixel arranged in the reference pixel area RA. This SPAD pixel 21 is an effective SPAD pixel (hereinafter referred to as a reference pixel) that outputs a received light signal (APD OUT) having a pulse waveform whose starting point corresponds to the arrival time of one photon. Note that Figure 2 (A) shows a case where 48 SPAD pixels 21 are arranged in a matrix of 6 pixels in the vertical direction×8 pixels in the horizontal direction, but this arrangement is merely an example and does not limit any appropriate arrangement.

[0040] On the other hand, the SPAD pixel 22 is a pixel arranged in the dummy pixel area DA. The dummy pixel area DA is located near the outer edge of the pixel array section 11 and is an area where the process of forming the SPAD pixel 22 may be unstable. For the SPAD pixel 22 that has been formed in the dummy pixel area DA, shape collapse and arrangement periodicity collapse may occur. Therefore, such a SPAD pixel 22 is made into an invalid SPAD pixel (hereinafter referred to as a dummy pixel) that does not function as an ordinary SPAD pixel (that is, it does not output the above-mentioned received light signal (APDOUT)). Note that Figure 2 (A) shows a case where 72 SPAD pixels 22 are arranged in the dummy pixel area DA, but this arrangement is merely an example and does not limit any appropriate arrangement. In the actual sensor chip 10, the number of SPAD pixels 22 arranged in the dummy pixel area DA is configured to be sufficiently smaller than the number of SPAD pixels 21 arranged in the reference pixel area RA.

[0041] Due to the arrangement of the peripheral area A2 and pad area A3 near the pixel area A1 where SPAD pixels 21 and 22 are arranged in rows and columns, the shape collapse and periodicity of the arrangement of SPAD pixels 22 occur. When forming SPAD pixels 21 and 22, a resist film with openings is formed on pixel area A1 to inject impurity ions into the SPAD pixel formation area. The resist film formed on the peripheral area A2 and pad area A3 does not include openings corresponding to the formation positions of SPAD pixels 21 and 22, and therefore has a larger amount of resist material than the resist film formed on pixel area A1. Therefore, the resist film formed on the peripheral area A2 and pad area A3 may deform due to its own weight. Due to this deformation of the resist film, which serves as a mask when injecting impurity ions, process defects may occur. In other words, process defects may occur in the opening portion formed slightly inward of the peripheral area A2 and pad area A3 (i.e., the portion near the peripheral edge of pixel area A1). Therefore, for the SPAD pixels 22 that have been formed in the dummy pixel area DA, shape collapse and arrangement periodicity collapse may occur.

[0042] Therefore, the sensor chip 10 has been configured to make the SPAD pixels 22 formed in the area near the outer edge of the pixel area A1 into pseudo pixels, and thus only use the outputs of the SPAD pixels 21 formed in the central area of ​​the pixel area A1, the sensor chip 10 is able to obtain good characteristics.

[0043] Hereinafter, the SPAD pixel 21 as a reference pixel and the SPAD pixel 22 as a dummy pixel will be described in detail.

[0044] (Circuit Configuration of Reference Pixel)

[0045] like Figure 2 As shown in (B), the SPAD pixel 21 as a reference pixel includes a SPAD element 31 , a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 32 , and an inverter 33 .

[0046] The anode of the SPAD element 31 is connected to the bias voltage applying section 12, and the cathode is connected to the source terminal of the quenching resistor 32, which will be described later. The anode of the SPAD element 31 is supplied with a bias voltage VB from the bias voltage applying section 12. The SPAD element 31 is an avalanche photodiode element that forms an avalanche multiplication region by supplying a large negative voltage to its cathode and is capable of avalanche multiplying electrons generated by the incidence of one photon.

[0047] The quenching resistor 32 is connected in series to the SPAD element 31. The source terminal of the quenching resistor 32 is connected to the cathode of the SPAD element 31, and the drain terminal thereof is connected to a power supply (not shown). The quenching resistor 32 can be formed by a transistor or a resistor. For example, a p-type MOSFET can be used. The drain terminal of the quenching resistor 32 is supplied with an excitation voltage V from the power supply. E When the voltage generated by the electrons that have avalanche-multiplied in the SPAD element 31 reaches the negative voltage VBD, the quenching resistor 32 performs quenching to restore the voltage to the initial voltage. When the cathode voltage of the SPAD element 31 reaches the negative voltage VBD, the quenching resistor 32 performs quenching by emitting the electrons that have multiplied in the SPAD element 31.

[0048] The input terminal of the inverter 33 is connected to the cathode of the SPAD element 31 and the source terminal of the quenching resistor 32, and the output terminal thereof is connected to an operation processing unit not shown provided in a subsequent stage. The inverter 33 is, for example, a CMOS inverter. The inverter 33 outputs a received light signal based on the electrons multiplied in the SPAD element 31. More specifically, the inverter 33 shapes the voltage generated by the electrons multiplied in the SPAD element 31. In addition, the inverter 33 outputs the received light signal (APDOUT) to the operation processing unit, and the received light signal is, for example, Figure 2 (B) shows the pulse waveform, whose starting point corresponds to the arrival time of a photon.

[0049] (Circuit Configuration of Pseudo Pixel)

[0050] like Figure 2As shown in FIG. 2C , the SPAD pixel 22 as a dummy pixel includes a SPAD element 31, a p-type MOSFET (metal oxide semiconductor field effect transistor) 32, and an inverter 33, similarly to the SPAD pixel 21. The SPAD pixel 22 differs from the SPAD pixel 21 in that wiring is different.

[0051] The anode of the SPAD element 31 is connected to the bias voltage application unit 12, while the cathode of the SPAD element 31 is not connected to the source terminal of the quenching resistor 32 and is in a floating state. Specifically, the cathode potential of the SPAD element 31 of each SPAD pixel 22 formed in the dummy pixel area DA included in the pixel area A1 and located near the peripheral edge of the pixel area A1 is placed in a floating state. Therefore, the cathode of the SPAD element 31 is not supplied with a large negative voltage and is essentially non-functional.

[0052] Specifically, the above configuration makes it possible to prevent the occurrence of a phenomenon in which breakdown continuously occurs in the SPAD element 31 of the SPAD pixel 22, causing a bias change and a current increase that affect external devices connected to the sensor chip 10. The above configuration makes it possible to suppress, in the sensor chip 10, an increase in the power consumption of the sensor chip 10 due to the flow of a large current in the SPAD element 31 of the SPAD pixel 22. Furthermore, the above configuration makes it possible to suppress, in the sensor chip 10, a reduction in sensing accuracy caused by a drop in the anode potential of the SPAD pixel 21 caused by the flow of a large current in the SPAD element 31.

[0053] The source terminal of the quenching resistor 32 is not connected to the cathode of the SPAD element 31 and is in a floating state. Therefore, the quenching resistor 32 is configured not to perform quenching.

[0054] The input terminal of the inverter 33 is not connected to the cathode of the SPAD element 31 and the source terminal of the quenching resistor 32 and is in a floating state. Therefore, the inverter 33 is configured not to output the received optical signal (APD OUT).

[0055] In the sensor chip 10, as Figure 2 As shown in the example of (A), in the SPAD pixels 21 and SPAD pixels 22 arranged in rows and columns, the anodes of multiple SPAD pixels 21 arranged in each row direction and the anodes of multiple SPAD pixels 22 arranged in each row direction are connected to each other through corresponding common wiring.

[0056] According to the sensor chip 10 configured as described above, received light signals are output for each SPAD pixel 21 and provided to a subsequent processing unit. For example, the processing unit calculates the distance to the subject by performing distance calculation based on the timing of the arrival of a single photon and the occurrence of a pulse on each received light signal from the SPAD pixel 21. Furthermore, based on the calculated distances, a distance image is generated in which the distances to the subject detected by the multiple SPAD pixels 21 are arranged on a plane.

[0057] At this time, since the received light signal is not output from the SPAD pixel 22 , the SPAD pixel 22 does not contribute to the generation of the above-mentioned distance image.

[0058] (Structure of reference pixel)

[0059] Will use Figure 2 (B) and Figure 3 A configuration example of the SPAD pixel 21 as a reference pixel formed in the sensor chip 10 will be described. Figure 3 is a cross-sectional view of the SPAD pixel 21 , which shows a configuration example of the SPAD pixel 21 .

[0060] like Figure 3 As shown, the reference pixel area RA of the sensor chip 10 has a stacked layer structure in which a sensor substrate 41 , a sensor-side wiring layer 42 , and a logic-side wiring layer 43 are stacked, and an unshown logic circuit substrate is stacked on the logic-side wiring layer 43 .

[0061] In the logic circuit substrate, for example, Figure 2 (A) shows the bias voltage applying unit 12, multiple quenching resistors 32, multiple inverters 33, etc. The sensor substrate 41 and the logic circuit substrate are electrically connected to each other through the sensor side wiring layer 42 and the logic side wiring layer 43 serving as wiring layers. For example, the sensor chip 10 can be manufactured by the following manufacturing method: after the sensor side wiring layer 42 has been arranged to face the sensor substrate 41 and the logic side wiring layer 43 has been arranged to face the logic circuit substrate, Figure 3 The sensor side wiring layer 42 and the logic side wiring layer 43 are bonded together (the surface indicated by the dotted line).

[0062] For example, the sensor substrate 41 is a semiconductor substrate obtained by slicing single crystal silicon. In the sensor substrate 41, the concentration of p-type or n-type impurities is controlled, and the SPAD elements 31 for each SPAD pixel 21 are formed. Figure 3The downward surface of the sensor substrate 41 is configured as a light receiving surface for receiving light, and the surface opposite to the light receiving surface (ie Figure 2 The sensor-side wiring layer 42 is stacked on the upward surface of the sensor substrate 41.

[0063] In the sensor side wiring layer 42 and the logic side wiring layer 43, wiring for supplying applied voltage from the bias voltage applying section 12 to the SPAD element 31, wiring for taking out electrons generated in the SPAD element 31 from the sensor substrate 41, and any other types of wiring are formed.

[0064] The SPAD element 31 includes an N-well 51, a P-type diffusion layer 52, an N-type diffusion layer 53, a hole accumulation layer 54, a pinning layer 55, and a high-concentration P-type diffusion layer 56 formed in the sensor substrate 41. Furthermore, in the SPAD element 31, an avalanche multiplication region 57 is formed by a depletion layer formed in a region connected to the P-type diffusion layer 52 and the N-type diffusion layer 53.

[0065] The N-well 51 is formed by controlling the impurity concentration of the sensor substrate 41 to be n-type, and forms an electric field that transfers electrons generated by photoelectric conversion in the SPAD element 31 to the avalanche multiplication region 57. Here, a P-well can be formed instead of the N-well 51 by controlling the impurity concentration of the sensor substrate 41 to be p-type.

[0066] The P-type diffusion layer 52 is located near the surface of the sensor substrate 41 and on the back side of the N-type diffusion layer 53 ( Figure 3 A thick P-type diffusion layer (P+) is formed on the lower side of the SPAD element 31 and is formed to pass through substantially the entire surface of the SPAD element 31.

[0067] The N-type diffusion layer 53 is located near the surface of the sensor substrate 41 and opposite to the front surface side of the P-type diffusion layer 52 ( Figure 3 A thick N-type diffusion layer (N+) is formed on the upper side of the sensor substrate 41 and is formed to pass through substantially the entire surface of the SPAD element 31. In addition, in order to be connected to the contact electrode 71 to supply a negative voltage for forming the avalanche multiplication region 57, the N-type diffusion layer 53 is configured so that a portion thereof has a protruding shape formed to reach the surface of the sensor substrate 41.

[0068] The hole accumulation layer 54 is a P-type diffusion layer (P) formed to surround the side and bottom surfaces of the N-well 51 and accumulate holes. Furthermore, the hole accumulation layer 54 is electrically connected to the anode of the SPAD element 31 to enable bias adjustment. This configuration increases the hole concentration of the hole accumulation layer 54 and strengthens the pinning of the pinning layer 55, thereby suppressing the occurrence of, for example, dark current.

[0069] The pinning layer 55 is a thick P-type diffusion layer (P+) formed on a surface further outward than the hole accumulation layer 54 (i.e., on the rear surface of the sensor substrate 41 and the side surface in contact with the insulating film 62), and similar to the hole accumulation layer 54, suppresses the occurrence of, for example, dark current.

[0070] The high-concentration P-type diffusion layer 56 is a thick P-type diffusion layer (P++) formed near the surface of the sensor substrate 41 to surround the outer edge of the N-well 51 and is used to connect to the contact electrode 72 for electrically connecting the hole accumulation layer 54 to the anode of the SPAD element 31.

[0071] The avalanche multiplication region 57 is a high electric field region at the interface between the P-type diffusion layer 52 and the N-type diffusion layer 53 , where a large negative voltage is applied to the N-type diffusion layer 53 and multiplies electrons generated by one incident photon entering the SPAD element 31 .

[0072] The sensor chip 10 includes inter-pixel separators 63 formed between adjacent SPAD elements 31. These inter-pixel separators 63 are formed using a dual structure of a metal film 61 and an insulating film 62. For example, the inter-pixel separators 63 are formed so as to penetrate from the rear surface to the front surface of the sensor substrate 41. The inter-pixel separators 63 electrically and optically separate the SPAD elements 31 from adjacent SPAD elements 31.

[0073] The metal film 61 is a film containing a metal (for example, tungsten) that reflects light.

[0074] The insulating film 62 is a film having insulating properties and containing SiO 2 or the like.

[0075] For example, the inter-pixel separation portion 63 is formed by being embedded in the sensor substrate 41 in a state where the insulating film 62 covers the surface of the metal film 61 .

[0076] In the sensor-side wiring layer 42 , contact electrodes 71 to 73 , metal wirings 74 to 76 , contact electrodes 77 to 79 , and metal pads 80 to 82 are formed.

[0077] The contact electrode 71 connects the N-type diffusion layer 53 to the metal wiring 74 . The contact electrode 72 connects the high-concentration P-type diffusion layer 56 to the metal wiring 75 . The contact electrode 73 connects the metal film 61 to the metal wiring 76 .

[0078] like Figure 3 As shown, for example, the metal wiring 74 is formed wider than the avalanche multiplication region 57 to cover at least the avalanche multiplication region 57. Figure 3 As shown by the white arrows, the metal wiring 74 reflects the light that has passed through the SPAD element 31 toward the SPAD element 31 .

[0079] like Figure 3 As shown, for example, metal wiring 75 is formed to surround the outer peripheral edge of metal wiring 74 and overlap with high-concentration P-type diffusion layer 56. For example, metal wiring 76 is formed to be connected to metal film 61 at each of the four corners of SPAD pixel 21.

[0080] Contact electrode 77 connects metal wiring 74 to metal pad 80. Contact electrode 78 connects metal wiring 75 to metal pad 81. Contact electrode 79 connects metal wiring 76 to metal pad 82.

[0081] The metal pads 80 to 82 serve to electrically connect and mechanically bond the metal pads 101 to 103 formed in the logic-side wiring layer 43 to the corresponding metal pads 80 to 82 themselves to be bonded to each other through the metal (Cu) forming the respective metal pad pairs.

[0082] In the logic-side wiring layer 43 , electrode pads 91 to 93 , an insulating layer 94 , contact electrodes 95 to 100 , and metal pads 101 to 103 are formed.

[0083] The electrode pads 91 to 93 are each connected to a corresponding logic circuit substrate not shown, and an insulating layer 94 insulates the electrode pads 91 to 93 from one another.

[0084] Contact electrodes 95 and 96 connect electrode pad 91 to metal pad 101 , contact electrodes 97 and 98 connect electrode pad 92 to metal pad 102 , and contact electrodes 99 and 100 connect electrode pad 93 to metal pad 103 .

[0085] Metal pad 101 is bonded to metal pad 80 , metal pad 102 is bonded to metal pad 81 , and metal pad 103 is bonded to metal pad 82 .

[0086] For example, such a wiring structure as described above enables electrode pad 91 to be connected to N-type diffusion layer 53 via contact electrodes 95 and 96, metal pad 101, metal pad 80, contact electrode 77, metal wiring 74, and contact electrode 71. Therefore, in SPAD pixel 21, a large negative voltage to be applied to N-type diffusion layer 53 can be supplied from the logic circuit substrate to electrode pad 91.

[0087] Furthermore, the electrode pad 92 is connected to the high-concentration P-type diffusion layer 56 via the contact electrodes 97 and 98, the metal pad 102, the metal pad 81, the contact electrode 78, the metal wiring 75, and the contact electrode 72. Thus, in the SPAD pixel 21, the anode of the SPAD element 31 to be electrically connected to the hole accumulation layer 54 is connected to the electrode pad 92, and this configuration enables bias adjustment of the hole accumulation layer 54 via the electrode pad 92.

[0088] Furthermore, a connection configuration is made such that electrode pad 93 is connected to metal film 61 via contact electrodes 99 and 100, metal pad 103, metal pad 82, contact electrode 79, metal wiring 76, and contact electrode 73. Therefore, in SPAD pixel 21, a bias voltage supplied from the logic circuit substrate to electrode pad 93 can be applied to metal film 61.

[0089] Furthermore, in the SPAD pixel 21, as described above, the metal wiring 74 is formed wider than the avalanche multiplication region 57 so as to cover at least the avalanche multiplication region 57, and the metal film 61 is formed so as to penetrate the sensor substrate 41. That is, the SPAD pixel 21 is formed to establish a reflective structure in which all structures of the SPAD element 31 except the light incident surface are surrounded by the metal wiring 74 and the metal film 61. This configuration enables the SPAD pixel 21 to prevent the occurrence of optical crosstalk and improve the sensitivity of the SPAD element 31 through the light reflection effect of the metal wiring 74 and the metal film 61.

[0090] Furthermore, the SPAD pixel 21 is capable of bias adjustment by a connection structure in which the side and bottom surfaces of the N-well 51 are surrounded by the hole accumulation layer 54, and the hole accumulation layer 54 is electrically connected to the anode of the SPAD element 31. Furthermore, by applying a bias voltage to the metal film 61 of the inter-pixel separation portion 63, the SPAD pixel 21 is capable of forming an electric field that assists carriers to the avalanche multiplication region 57.

[0091] (Configuration of pseudo pixels)

[0092] Will use Figure 2 (C) and Figure 4 A configuration example of the SPAD pixel 22 as a dummy pixel formed in the sensor chip 10 will be described. Figure 4 is a cross-sectional view of the SPAD pixel 22 , which shows a configuration example of the SPAD pixel 22 .

[0093] like Figure 4 As shown, like the reference pixel area RA, the dummy pixel area DA has a stacked-layer structure in which the sensor substrate 41 , the sensor-side wiring layer 42 , and the logic-side wiring layer 43 are stacked.

[0094] Like the SPAD pixel 21 , the SPAD pixel 22 includes a SPAD element 31 , a quenching resistor 32 , and an inverter 33 .

[0095] Furthermore, in the sensor-side wiring layer 42 , contact electrodes 72 and 73 , metal wirings 74 to 76 , contact electrodes 77 to 79 , and metal pads 80 to 82 are formed.

[0096] Furthermore, in the logic-side wiring layer 43 , electrode pads 91 to 93 , an insulating layer 94 , contact electrodes 95 to 100 , and metal pads 101 to 103 are formed.

[0097] like Figure 2 As shown in FIG. 5C , the difference between the SPAD pixel 22 and the SPAD pixel 21 is that the cathode of the SPAD element 31 is not connected to the source terminal of the quenching resistor 32 and is in a floating state.

[0098] like Figure 4 As shown, the SPAD pixel 22 differs from the SPAD pixel 21 in that, in order to keep the cathode potential of the SPAD element 31 in a floating state, no contact electrode 71 is provided, and the SPAD element 31 is not electrically connected to the metal wiring 74. The rest of the configuration is similar to that of the SPAD pixel 21.

[0099] SPAD elements, which are avalanche photodiodes, have recently been used as image sensors and are required to have characteristics superior to those of conventional elements. Avalanche photodiodes are larger than typical photodiodes. Therefore, when forming avalanche photodiodes as SPAD pixels, a large amount of resist material is used, which can cause deformation of the shape of the mask formed with the resist material. Therefore, using the configuration of the sensor chip according to the present invention, the SPAD pixels formed near the peripheral edge of the pixel array section, where formation abnormalities are likely to occur, are made inactive pixels, further enhancing the characteristics of the sensor chip 10.

[0100] <Effects of the First Embodiment>

[0101] The sensor chip 10 according to the first embodiment and having been constructed in the above-described manner produces the following effects.

[0102] (1) The sensor chip 10 is configured so that the SPAD pixels 22, which may experience shape collapse and arrangement periodicity collapse, do not output received light signals (APD OUT). Therefore, the sensor chip 10 can output only received light signals from the highly stable SPAD pixels 21. This configuration makes it possible to calculate the distance to the subject based solely on the received light signals from the highly stable SPAD pixels 21, thereby generating a highly accurate distance image.

[0103] (2) The sensor chip 10 is configured to be able to suppress a large current from flowing in the SPAD pixels 22. This configuration can suppress an increase in power consumption of the entire sensor chip 10 due to a large current flowing in the SPAD pixels 22.

[0104] (3) The sensor chip 10 is configured to suppress a large current from flowing in the SPAD pixel 22. This configuration can suppress a decrease in sensing accuracy due to a decrease in the anode potential of the SPAD pixel 21 caused by a large current flowing in the SPAD pixel 22.

[0105] (4) The sensor chip 10 is configured to suppress the occurrence of a large current in the SPAD pixel 22. This configuration suppresses the occurrence of crosstalk in the SPAD pixel 21 of the reference pixel area RA due to the occurrence of a large current in the SPAD pixel 22, thereby improving the sensitivity of the SPAD element 31 of the SPAD pixel 21.

[0106] 2. Second Implementation Plan

[0107] Will refer to Figures 2 to 4 and use Figure 5 A sensor chip according to the second embodiment is described below. The sensor chip 10A according to the second embodiment is different from the sensor chip 10 according to the first embodiment in that the sensor chip 10A includes SPAD pixels 22A as dummy pixels instead of the SPAD pixels 22 .

[0108] Each portion of this SPAD pixel 22A except for the portion related to this difference is formed in a similar manner to the SPAD pixel 22 of the sensor chip 10 according to the first embodiment.

[0109] (Circuit Configuration of Pseudo Pixel)

[0110] Next, the difference between the SPAD pixel 22A and the SPAD pixel 21 will be described.

[0111] The anode of the SPAD element 31 of the SPAD pixel 22A, which serves as a dummy pixel, is not connected to the bias voltage application unit 12 and is in a floating state. Furthermore, the cathode of the SPAD element 31 is not connected to the source terminal of the quenching resistor 32 and is in a floating state. Specifically, both the cathode and anode potentials of the SPAD element 31 of each SPAD pixel 22A formed in the dummy pixel area DA located near the outer edge of the pixel area A1 and included in the pixel area A1 are in a floating state. Consequently, a large negative voltage is not supplied to the cathode of the SPAD element 31, and the SPAD element 31 is essentially non-functional.

[0112] (Configuration of pseudo pixels)

[0113] Will use Figure 5 A configuration example of the SPAD pixel 22A as a dummy pixel of the sensor chip 10A will be described. Figure 5 : is a cross-sectional view of the SPAD pixel 22A, which shows a configuration example of the SPAD pixel 22A.

[0114] Like the SPAD pixels 21 and 22 , the SPAD pixel 22A includes a SPAD element 31 , a quenching resistor 32 , and an inverter 33 .

[0115] Furthermore, in the sensor-side wiring layer 42 , a contact electrode 73 , metal wirings 74 to 76 , contact electrodes 77 to 79 , and metal pads 80 to 82 are formed.

[0116] The configuration of the logic-side wiring layer 43 is similar to that of the SPAD pixel 22 .

[0117] like Figure 5 As shown, in the SPAD pixel 22A, in order to make the cathode potential of the SPAD element 31 in a floating state, no contact electrode is provided for connecting the SPAD element 31 to the metal wiring 74. In addition, in the SPAD pixel 22A, in order to make the anode potential of the SPAD element 31 in a floating state, no contact electrode is provided for connecting the SPAD element 31 to the metal wiring 75.

[0118] <Effects of the Second Embodiment>

[0119] The sensor chip 10A according to the second embodiment and having been configured in the above-described manner produces effects similar to those of (1) to (4) in the first embodiment.

[0120] (Variation)

[0121] In the sensor chip, in order to make the SPAD pixels already formed in the dummy pixel area DA into dummy pixels, it is sufficient to make at least one of the cathode potential and the anode potential into a floating state.

[0122] In the first and second embodiments, the sensor chip 10 in which the cathode potential of each SPAD pixel 22 formed in the pseudo pixel area DA is in a floating state and the sensor chip 10A in which both the cathode potential and the anode potential are in a floating state have been described respectively, but the present invention is not limited to the above configuration.

[0123] That is, for the SPAD pixel of the sensor chip, a configuration can be adopted in which the cathode potential of each SPAD element 31 is in a floating state. In this case, the SPAD pixel has the following configuration: Figure 2 In the SPAD pixel 21 shown, the contact electrode 71 is provided but the contact electrode 72 is not provided.

[0124] 3. The third implementation plan

[0125] Will refer to Figures 2 to 4 And use Figure 6 and Figure 7 A sensor chip according to a third embodiment will be described. A sensor chip 10B according to the third embodiment differs from the sensor chip 10 according to the first embodiment in that the sensor chip 10B includes a SPAD pixel 22B as a dummy pixel instead of the SPAD pixel 22. Furthermore, the SPAD pixel 21 serving as a reference pixel is formed in a manner similar to the SPAD pixel 21 of the sensor chip 10 according to the first embodiment.

[0126] (Circuit Configuration of Pseudo Pixel)

[0127] Next, the difference between the SPAD pixel 22B and the SPAD pixel 21 will be described.

[0128] like Figure 6 As shown, the anode of the SPAD element 31 of the SPAD pixel 22B, which serves as a dummy pixel, is connected to the bias application unit 12, but the cathode of the SPAD element 31 is not connected to the source terminal of the quenching resistor 32. Furthermore, the cathode and anode of the SPAD element 31 are short-circuited. That is, the cathode and anode potentials of each SPAD element 31 formed in the dummy pixel area DA near the peripheral edge of the pixel area A1 are made equal. Consequently, a large negative voltage is not supplied to the cathode of the SPAD element 31, and the SPAD element 31 is essentially non-functional.

[0129] The respective portions other than the above-described portions in the SPAD pixel 22B are formed in a manner similar to that of the SPAD pixel 22 of the sensor chip 10 according to the first embodiment.

[0130] (Configuration of pseudo pixels)

[0131] Will use Figure 7 A configuration example of the SPAD pixel 22B as a dummy pixel of the sensor chip 10B will be described. Figure 7 2B is a cross-sectional view of the SPAD pixel 22B, which shows a configuration example of the SPAD pixel 22B.

[0132] Like the SPAD pixels 21 and 22 , the SPAD pixel 22B includes a SPAD element 31 , a quenching resistor 32 , and an inverter 33 .

[0133] Furthermore, in the sensor-side wiring layer 42 , contact electrodes 71 to 73 , a metal wiring 74B, a metal wiring 76 , contact electrodes 78 and 79 , and metal pads 80 to 82 are formed.

[0134] The configuration of the logic-side wiring layer 43 is similar to that of the SPAD pixel 22 .

[0135] like Figure 7As shown, in SPAD pixel 22B, contact electrodes 71 and 72 are connected to a single metal wiring 74B to equalize the cathode and anode potentials of SPAD element 31. This configuration short-circuits the cathode and anode of SPAD element 31. Furthermore, in SPAD pixel 22B, no contact electrode is provided for connecting metal wiring 74B to metal pad 80, and thus SPAD element 31 is not electrically connected to quenching resistor 32 and inverter 33.

[0136] <Effects of the Third Embodiment>

[0137] The sensor chip 10B according to the third embodiment and having been configured in the above-described manner produces effects similar to those of (1) to (4) in the first embodiment.

[0138] 4. Fourth Implementation Plan

[0139] Will refer to Figures 2 to 4 and use Figure 8 (A) to Figure 8 (C) A sensor chip according to the fourth embodiment is described.

[0140] The sensor chip 10C according to the fourth embodiment differs from the sensor chip 10 according to the first embodiment in that the sensor chip 10C includes SPAD pixels 21C as reference pixels instead of the SPAD pixels 21 and includes SPAD pixels 22C as dummy pixels instead of the SPAD pixels 22 .

[0141] (Circuit Configuration of Pseudo Pixel)

[0142] Next, the difference between the overall configuration of the SPAD pixel 21C and the SPAD pixel 22C and the overall configuration of the SPAD pixel 21 and the SPAD pixel 22 will be described.

[0143] The respective configurations of the SPAD pixel 21C and the SPAD pixel 22C are similar to those of the SPAD pixel 21 and the SPAD pixel 22B. Figure 8 As shown in (B), the wiring for the SPAD element 31, the quenching resistor 32, and the inverter 33 in the SPAD pixel 22C is also similar to the wiring in the SPAD pixel 22B.

[0144] exist Figure 8In (A), the anodes of the SPAD pixels 21C arranged in each row of the plurality of SPAD pixels 21C arranged in rows and columns are connected to each other via corresponding shared wiring, and the anodes of the SPAD pixels 22C arranged in each row of the plurality of SPAD pixels 22C arranged in rows and columns are connected to each other via corresponding shared wiring. That is, the sensor chip 10C differs from the sensor chip 10 according to the first embodiment in that the anodes of the plurality of SPAD pixels 21C and the anodes of the plurality of SPAD pixels 22C are separated from each other.

[0145] <Effects of the Fourth Embodiment>

[0146] The sensor chip 10C according to the fourth embodiment and having been configured in the above-described manner produces the following effects in addition to (1) to (4) in the first embodiment.

[0147] (5) In the sensor chip 10C, the anodes of the SPAD pixels 21C and 22C are separated from each other. Therefore, even if a large current flows through the SPAD pixels 22C in the dummy pixel area DA, the large current does not affect the SPAD pixels 21C in the reference pixel area. This configuration prevents a decrease in the anode potential of the SPAD pixels 21C and, therefore, prevents a decrease in the sensing accuracy of the sensor chip 10C.

[0148] 5. Fifth Implementation Plan

[0149] Will refer to Figures 2 to 4 and use Figure 9 and Figure 10 Next, a sensor chip according to a fifth embodiment will be described. A sensor chip 10D according to the fifth embodiment differs from the sensor chip 10 according to the first embodiment in that the sensor chip 10D includes a SPAD pixel 22D in which the anode and cathode of the SPAD element 31 are short-circuited in the logic-side wiring layer 43. Furthermore, a SPAD pixel 21 serving as a reference pixel is formed in a manner similar to the SPAD pixel 21 of the sensor chip 10 according to the first embodiment.

[0150] (Circuit Configuration of Pseudo Pixel)

[0151] Next, the difference between the SPAD pixel 22D and the SPAD pixel 21 will be described.

[0152] like Figure 9As shown, the anode of the SPAD element 31 of the SPAD pixel 22D, which serves as a dummy pixel, is connected to the bias application unit 12. Furthermore, the cathode of the SPAD element 31 is connected to the source terminal of the quenching resistor 32, but is not connected to the inverter 33. Furthermore, the cathode and anode of the SPAD element 31 are short-circuited in the logic-side wiring layer 43. That is, the cathode and anode potentials of the individual SPAD elements formed in the dummy pixel area DA, which is included in the pixel area A1 and located near the peripheral edge of the pixel area A1, are made the same. Therefore, a large negative voltage is not supplied to the cathode of the SPAD element 31, and the SPAD element 31 is essentially non-functional.

[0153] (Configuration of pseudo pixels)

[0154] Will use Figure 10 A configuration example of the SPAD pixel 22D as a dummy pixel of the sensor chip 10D will be described. Figure 10 2 is a cross-sectional view of the SPAD pixel 22D, which shows a configuration example of the SPAD pixel 22D.

[0155] Like the SPAD pixels 21 and 22 , the SPAD pixel 22D includes a SPAD element 31 , a quenching resistor 32 , and an inverter 33 .

[0156] The configuration of the sensor-side wiring layer 42 is similar to that of the SPAD pixel 22 of the first embodiment.

[0157] In the logic-side wiring layer 43 , an electrode pad 91D, an electrode pad 93 , an insulating layer 94 , contact electrodes 95 to 100 , and metal pads 101 to 103 are formed.

[0158] like Figure 10 As shown, in the SPAD pixel 22D, contact electrodes 95 to 98 are connected to a single electrode pad 91D to equalize the cathode and anode potentials of the SPAD element 31. With this configuration, the cathode and anode of the SPAD element 31 are short-circuited in the logic-side wiring layer 43. Furthermore, in the logic-side wiring layer 43, wiring for the SPAD pixel 22D is formed such that the SPAD element 31 and the quenching resistor 32 are not connected to the inverter 33.

[0159] <Effects of the Fifth Embodiment>

[0160] The sensor chip 10D according to the fifth embodiment and having been configured in the above-described manner produces effects similar to those of (1) to (4) in the first embodiment.

[0161] 6. Sixth Implementation Plan

[0162] Will refer to Figures 2 to 4 and use Figure 11 and Figure 12 Next, a sensor chip according to a sixth embodiment will be described. A sensor chip 10E according to the sixth embodiment differs from the sensor chip 10 according to the first embodiment in that the sensor chip 10E includes a SPAD pixel 22E as a dummy pixel instead of the SPAD pixel 22. Furthermore, the SPAD pixel 21 serving as a reference pixel is formed in a manner similar to the SPAD pixel 21 of the sensor chip 10 according to the first embodiment.

[0163] (Circuit Configuration of Pseudo Pixel)

[0164] Next, the difference between the SPAD pixel 22E and the SPAD pixel 21 will be described.

[0165] like Figure 11 As shown, the SPAD pixel 22E serving as a dummy pixel is different from the SPAD pixel 21 in that the SPAD pixel 22E includes a SPAD element 31 but does not include a quenching resistor 32 and an inverter 33 .

[0166] Furthermore, in the sensor-side wiring layer 42 , contact electrodes 71 to 73 , metal wirings 74E and 76 , contact electrodes 78 and 79 , and metal pads 80 to 82 are formed.

[0167] The configuration of the logic-side wiring layer 43 is similar to that of the SPAD pixel 22 .

[0168] The anode of each SPAD element 31 is connected to the bias voltage application unit 12, and the cathode is not connected to the source terminal of the quenching resistor 32 but is connected to the anode. Specifically, the cathode and anode potentials of each SPAD element 31 formed in the dummy pixel area DA located near the outer edge of the pixel area A1 are set to the same potential. Consequently, a large negative voltage is not applied to the cathode of each SPAD element 31, and the SPAD element 31 is essentially non-functional.

[0169] Furthermore, although the inverter 33 is not provided in the logic-side wiring layer 43, the anode and cathode potentials of the SPAD element 31 are made equal by short-circuiting the anode and cathode of the SPAD element 31. This configuration prevents current from flowing through each SPAD pixel 22E, thereby more reliably preventing degradation of the characteristics of the sensor chip 10E.

[0170] Here, the anode and cathode of the SPAD element 31 may each be placed in a floating state.

[0171] (Configuration of pseudo pixels)

[0172] Will use Figure 12A configuration example of the SPAD pixel 22E as a dummy pixel of the sensor chip 10E will be described. Figure 12 2 is a cross-sectional view of the SPAD pixel 22E, which shows a configuration example of the SPAD pixel 22E.

[0173] In the SPAD pixel 22E, as described above, the SPAD element 31 is formed in the sensor substrate 41 .

[0174] Furthermore, in the sensor-side wiring layer 42 , contact electrodes 71 to 73 , metal wirings 74E and 76 , contact electrodes 78 and 79 , and metal pads 80 to 82 are formed.

[0175] In the logic-side wiring layer 43 , electrode pads 92 and 93 , an insulating layer 94 , contact electrodes 97 to 100 , and metal pads 102 and 103 are formed.

[0176] like Figure 12 As shown, in the SPAD pixel 22E, the contact electrodes 71 and 72 are connected to a single metal wiring 74E in order to make the cathode potential and the anode potential of the SPAD element 31 the same potential. In addition, in the SPAD pixel 22E, no wiring is provided that is included in the logic-side wiring layer 43 and electrically connected to the cathode of the SPAD element 31.

[0177] <Effects of the Sixth Embodiment>

[0178] The sensor chip 10E according to the sixth embodiment and having been configured in the above-described manner produces effects similar to those of (1) to (4) in the first embodiment.

[0179] 7. Configuration examples of electronic devices

[0180] Figure 13 1 is a block diagram showing a configuration example of a distance image sensor as an electronic device using the sensor chip 10 .

[0181] like Figure 13 As shown, the distance image sensor 201 includes an optical system 202, a sensor chip 10, an image processing circuit 203, a monitor 204, and a memory 205. The distance image sensor 201 can acquire a distance image based on the distance to the subject by receiving light (modulated light or pulsed light) generated by reflection of light emitted toward the subject by a light source device 211 on the surface of the subject.

[0182] The optical system 202 includes one or more lenses, and guides image light (incident light) from various objects to the sensor chip 10 so that an image is formed on the light receiving surface (sensor portion) of the sensor chip 10 .

[0183] As the sensor chip 10 , one of the sensor chips 10 according to the above-described respective embodiments is applied, and a distance signal showing a distance obtained from a received light signal (APD OUT) outputted from the sensor chip 10 is supplied to the image processing circuit 203 .

[0184] The image processing circuit 203 performs image processing for constructing a distance image based on the distance signal provided by the sensor chip 10 , and provides and displays the distance image (image data) obtained through the image processing on the monitor 204 or provides and stores (records) in the memory 205 .

[0185] In the distance image sensor 201 constructed in this manner, the use of one of the aforementioned sensor chips 10 enables calculation of the distance to the subject based solely on the received light signals from the highly stable SPAD pixels 21, thereby generating a highly accurate distance image. In other words, the distance image sensor 201 is capable of acquiring a more accurate distance image.

[0186] 8. Examples of image sensor usage

[0187] For example, as described below, the above-mentioned image sensor can be used in various situations such as sensing visible light, infrared light, ultraviolet light, and X-rays.

[0188] - Devices for capturing images for viewing, such as digital cameras and mobile devices with camera functionality.

[0189] - Devices used for transportation, such as on-vehicle sensors for capturing images of the front, rear, surroundings, interior, etc. of a vehicle for purposes such as safe driving such as automatic stopping and identifying the driver's condition; surveillance cameras for monitoring moving vehicles and roads; distance measurement sensors for measuring the distance between vehicles, etc.

[0190] - Devices for home appliances, such as televisions, refrigerators, and air conditioners, to capture images of user gestures and perform operations on the device based on these gestures.

[0191] - Devices used in medical care, for example, endoscopes and devices for angiography by receiving infrared light.

[0192] - Devices for security, for example, surveillance cameras for crime prevention purposes and cameras for identity authentication purposes.

[0193] - Devices for beauty care, for example, skin measuring instruments for photographing the skin and microscopes for photographing the scalp.

[0194] -Devices for sports, such as action cameras and wearable cameras for sports use.

[0195] -Devices used in agriculture, such as cameras for monitoring the condition of fields and crops.

[0196] It should be noted that the present technology can have the following configurations. (1)

[0198] A sensor chip, comprising:

[0199] a pixel array section including a pixel region in which a plurality of pixels are arranged in rows and columns;

[0200] an avalanche photodiode element that amplifies carriers through a high electric field region provided for each pixel;

[0201] an inter-pixel separator that insulates and separates each pixel in the semiconductor substrate on which the avalanche photodiode element is formed from another adjacent pixel; and

[0202] a wiring arranged in a wiring layer stacked on a surface opposite to a light receiving surface of the semiconductor substrate so as to cover at least the high electric field region,

[0203] wherein the pixel array section includes a dummy pixel region located near a peripheral edge of the pixel region, and

[0204] A cathode potential and an anode potential of the avalanche photodiode element arranged in the dummy pixel region are the same potential, or at least one of the cathode potential and the anode potential is in a floating state. (2)

[0206] The sensor chip according to (1), wherein a cathode and an anode of the avalanche photodiode element arranged in the dummy pixel region are short-circuited. (3)

[0208] The sensor chip according to (1) or (2), further comprising:

[0209] a sensor substrate in which the avalanche photodiode element is formed;

[0210] a logic circuit substrate having a quenching resistor and an inverter formed therein; and

[0211] a wiring layer including a sensor-side wiring layer arranged opposite to the sensor substrate and a logic-side wiring layer arranged opposite to the logic circuit substrate, and electrically connecting the sensor substrate and the logic circuit substrate to each other,

[0212] A cathode and an anode of the avalanche photodiode element arranged in the dummy pixel region are short-circuited in the logic-side wiring layer. (4)

[0214] The sensor chip according to any one of (1) to (3),

[0215] wherein the pixel array section includes a reference pixel region located at the center of the pixel region,

[0216] anodes of the plurality of avalanche photodiode elements arranged in the reference pixel region are connected to one another via a common wiring,

[0217] Anodes of the plurality of avalanche photodiode elements arranged in the dummy pixel region are connected to each other via a common wiring, and

[0218] Anodes of the plurality of avalanche photodiode elements arranged in the reference pixel region and anodes of the plurality of avalanche photodiode elements arranged in the dummy pixel region are separated from each other. (5)

[0220] The sensor chip according to any one of (1) to (4),

[0221] The pixels arranged in the reference pixel area include:

[0222] the avalanche photodiode element;

[0223] a quenching resistor connected in series to the avalanche photodiode element; and

[0224] an inverter that outputs a received light signal based on electrons that have been multiplied in the avalanche photodiode element, and

[0225] Each pixel arranged in the reference pixel area includes: the avalanche photodiode element, and does not include: the quenching resistor connected in series with the avalanche photodiode element; and the inverter that outputs the received light signal based on electrons that have been multiplied in the avalanche photodiode element. (6)

[0227] An electronic device comprising:

[0228] A sensor chip comprising:

[0229] a pixel array portion including a pixel region in which a plurality of pixels are arranged in rows and columns;

[0230] an avalanche photodiode element that amplifies carriers through a high electric field region provided for each pixel;

[0231] an inter-pixel separator that insulates and separates each pixel in the semiconductor substrate on which the avalanche photodiode element is formed from another adjacent pixel; and

[0232] a wiring arranged in a wiring layer stacked on a surface opposite to a light receiving surface of the semiconductor substrate so as to cover at least the high electric field region,

[0233] wherein the pixel array section includes a dummy pixel region located near a peripheral edge of the pixel region, and

[0234] A cathode potential and an anode potential of the avalanche photodiode element arranged in the dummy pixel region are the same potential, or at least one of the cathode potential and the anode potential is in a floating state.

[0235] The scope of the present invention is not limited to the embodiments shown and described above as examples, and also includes all embodiments that produce the same effects as those intended by the present invention. In addition, the scope of the present invention is not limited to the combination of features of the present invention defined by the claims of this specification, but can be defined by each desired combination of specific features among all the individual features disclosed.

[0236] Reference Signs List

[0237] 10, 10A, 10B, 10C, 10D, 10E: sensor chips

[0238] 11: Pixel array unit

[0239] 12: Bias voltage applying unit

[0240] 21, 21C, 22, 22A, 22B, 22C, 22D, 22E: SPAD pixels

[0241] 23: Electrode pad

[0242] 31:SPAD components

[0243] 32: Quenching resistor

[0244] 33: Inverter

[0245] 41:Sensor substrate

[0246] 42: Sensor side wiring layer

[0247] 43: Logic side wiring layer

[0248] 51:N well

[0249] 52: P-type diffusion layer

[0250] 53:N-type diffusion layer

[0251] 54: Hole accumulation layer

[0252] 55: Pinning layer

[0253] 56: High concentration P-type diffusion layer

[0254] 57: Avalanche Multiplication Zone

[0255] 61:Metal film

[0256] 62: Insulation film

[0257] 63: Inter-pixel separation unit

[0258] 71, 72, 73: contact electrodes

[0259] 74, 74B, 74E, 75, 76: Metal wiring

[0260] 77, 78, 79: contact electrodes

[0261] 80, 81, 82, 101, 102, 103: Metal pads

[0262] 91, 91D, 92, 93: electrode pads

[0263] 94: Insulation layer

[0264] 95, 96, 97, 98, 99, 100: contact electrodes

[0265] A1: Pixel area

[0266] A2: Peripheral area

[0267] A3: pad area

[0268] DA: pseudo pixel area

[0269] RA: Reference pixel area.

Claims

1. A sensor chip, comprising: a pixel array portion including a pixel region in which a plurality of pixels are arranged in rows and columns; an avalanche photodiode element that amplifies carriers via a high electric field region provided for each of the pixels; an inter-pixel separator that insulates and separates each of the pixels in the semiconductor substrate on which the avalanche photodiode element is formed from other adjacent pixels; and a wiring arranged in a wiring layer stacked on a surface opposite to a light receiving surface of the semiconductor substrate so as to cover at least the high electric field region, wherein the pixel array section includes a dummy pixel region located near a peripheral edge of the pixel region, and A cathode potential and an anode potential of the avalanche photodiode element arranged in the dummy pixel region are the same potential, or at least one of the cathode potential and the anode potential is in a floating state.

2. The sensor chip according to claim 1, wherein The cathode and anode of the avalanche photodiode element arranged in the dummy pixel region are short-circuited.

3. The sensor chip according to claim 1 or 2, comprising: a sensor substrate in which the avalanche photodiode element is formed; a logic circuit substrate having a quenching resistor and an inverter formed therein; and a wiring layer including a sensor-side wiring layer arranged opposite to the sensor substrate and a logic-side wiring layer arranged opposite to the logic circuit substrate, and electrically connecting the sensor substrate and the logic circuit substrate to each other, Here, a cathode and an anode of the avalanche photodiode element arranged in the dummy pixel region are short-circuited in the logic-side wiring layer.

4. The sensor chip according to claim 1 or 2, wherein: The pixel array section includes a reference pixel area located at the center of the pixel area, Anodes of the plurality of avalanche photodiode elements arranged in the reference pixel region are connected to each other via a common wiring, Anodes of the plurality of avalanche photodiode elements arranged in the dummy pixel region are connected to each other via a common wiring, respectively, and Anodes of the plurality of avalanche photodiode elements arranged in the reference pixel region and anodes of the plurality of avalanche photodiode elements arranged in the dummy pixel region are separated from each other.

5. The sensor chip according to claim 1 or 2, wherein: The pixels arranged in the reference pixel area include: the avalanche photodiode element, a quenching resistor connected in series to the avalanche photodiode element, and an inverter that outputs a received light signal based on electrons that have been multiplied in the avalanche photodiode element, and The pixel arranged in the dummy pixel area includes the avalanche photodiode element and does not include a quenching resistor connected in series with the avalanche photodiode element and an inverter that outputs a received light signal based on electrons that have been multiplied in the avalanche photodiode element. 6 . An electronic device comprising the sensor chip according to claim 1 .

Images