Full pad coverage boundary scan

Abstract

The present invention relates to full pad coverage boundary scan. In the described example, an integrated circuit (200) includes a functional circuit (214) and a test circuit (212). A set of pads (P 0 ‑P 4 ) is operable in a first state to communicate a test signal to the test circuit (212), and in a second state to communicate an input / output signal to the functional circuit (214). 0 ‑P 4 ) of the second set of pads (P 5 ‑P 9 ) is operable in the second state to communicate a test signal to the test circuit (212) for testing the state of the device associated with the set of pads (P) in the second state. 0 ‑P 4 ) associated with the signal.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with invention name “Full Pad Coverage Boundary Scanning”, application number 201780031966.3 and application date May 1, 2017. Technical Field

[0003] The invention relates to boundary scanning of integrated circuits and printed circuit boards. Background Art

[0004] Boundary scan is a method and related circuit processing for testing logic, memory, and other circuits on an integrated circuit (IC) or printed circuit board (PCB). Typically, for boundary scan, four or five pins are included on the IC, each of which corresponds to a corresponding dedicated test access port (TAP) signal for testing the interconnects on the IC or the PCB to which the IC is assembled. Specifically, the TAP signal can be used to determine whether the IC is working properly, whether it is connected to the PCB, and also for debugging by observing the state of the IC pins or measuring voltages. Testing can be achieved at the time of manufacturing, such as by automated test equipment (ATE), and subsequent testing in the field (e.g., after the device has been sold or is in the market). Additional details and standardization related to boundary scan are developed by the Joint Test Action Group (JTAG) and specified in the IEEE 1149 standard and its .x substandards.

[0005] As further background, FIG1 illustrates an electrical block diagram of an IC 10 having a conventional boundary scan architecture. For simplicity, the IC 10 is shown as including a test access port TAP controller 12 for interfacing with TAP signals and associated with JTAG testing, and an IC functional circuit 14, sometimes referred to as a core, which is a general depiction of the various circuit functions of the IC 10, in addition to JTAG testing. The IC 10 also includes a number of I / O pads P0 through P1. 15 , shown at various locations around the perimeter of the device. Pads P0 to P4 carry corresponding and known JTAG TAP related signals, as shown in Table 1 below.

[0006] Table 1

[0007] <![CDATA[ Pinout ]]> <![CDATA[ JTAG Signals ]]> <![CDATA[ Function ]]> <![CDATA[P0]]> TDO Test data output <![CDATA[P1]]> TRST Test reset <![CDATA[P2]]> TMS Test mode selection <![CDATA[P3]]> TCK Test Clock <![CDATA[P4]]> TDI Test data input

[0008] As indicated in Table 1, pad P4 allows input of JTAG test data, and pad P0 allows output thereof, while the remaining pads P1 to P3 provide signals to the TAP controller 12. Instruction register 16 stores the current JTAG instruction, typically used to indicate the action to be taken on the received signal (e.g., defining to which data register the signal should be passed). Bypass register 18 is a single bit register that allows TDI to bypass the cell chain C0 to C1. 15 , so as to pass directly from input to output. ID register 20 is used to store an ID code and version number for IC 10, thereby allowing IC 10 to be linked to a file storing boundary scan configuration information for IC 10.

[0009] Except for JTAG related pads P0 to P4, the rest of the IC pads P5 to P 15 Each of the boundary scan cells C5 to C 15 14. Such pads therefore represent I / Os of IC 10, in conjunction with their intended operation to be implemented by functional circuit 14. However, in conjunction with JTAG testing, scanning cells C5 to C 15 Each of the scan cells is connected to at least one other scan cell, thereby forming a scan chain. For JTAG purposes, data can be input to each cell by a corresponding pad, or captured from functional circuit 14 in each cell, and then such data can be shifted successively along the chain so that from the last such cell C 15 The output is TDO information. Thus, in this manner, I / O connectivity and data status from functional circuit 14 can be evaluated to confirm proper operation of IC 10.

[0010] The techniques described above have proven to be effective in IC and PCB testing across many architectures, but the IEEE 1149.x standard requires that the JTAG pads themselves are not connected to corresponding scan units. Therefore, in the example of FIG. 1 , pads P0 to P4 are not connected to such corresponding units. However, such mandates impose restrictions. Summary of the invention

[0011] In the described examples, an integrated circuit includes a functional circuit and a test circuit. The integrated circuit also includes a set of pads operable in a first state to communicate a test signal to the test circuit and operable in a second state to communicate an input / output signal to the functional circuit. The integrated circuit also includes a second set of pads, different from the set of pads, operable in the second state to communicate a test signal to the test circuit for testing signals associated with the set of pads in the second state. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 is an electrical block diagram of an IC 10 having a conventional boundary scan architecture.

[0013] Figure 2a An electrical block diagram of IC 200 is depicted according to an example embodiment and in a first switching state for receiving a first set of JTAG test signals.

[0014] Figure 2b Draw Figure 2a 0048] Electrical block diagram of IC 200 of and in a second switching state for receiving a second set of JTAG test signals.

[0015] Figure 3 A flow chart illustrating an example method 300 of operation of IC 200 is shown.

[0016] Figure 4 An electrical block diagram of an alternative example embodiment IC 200' is shown.

[0017] Figure 5 The drawing can be used for Figure 4 The unit C of the unit in IC 200′ x structure. DETAILED DESCRIPTION

[0018] Figure 2a and 2b FIG. 1 is an electrical block diagram of an IC 200 according to an example embodiment. The IC 200 includes various functional blocks comparable to those described above in connection with FIG. 1 . For clarity, the reference numeral 200 is added to FIG. 1 . Figure 2a and 2b Thus, in conjunction with processing JTAG signals and IC functionality, IC 200 includes TAP controller 212, functional circuits (or cores) 214, instruction registers 216, bypass registers 218, and ID registers 220. However, in conjunction with example embodiments, such blocks operate in conjunction with one set of JTAG signals from two different corresponding sets of pads (e.g., pins). Figure 2a The first set of such JTAG signals is shown in FIG. 1 with subscript 0 on pads P0 through P4. Figure 2b , a second set of such JTAG signals are shown with subscript 1 on pads P5 through P9. Thus, as described below, IC 200 is operable in two different states, each state being implemented with a different switching signal path, wherein Figure 2a indicates the first such state indicated in a binary sense as state 0, and wherein Figure 2b A second such state is indicated which is indicated in a binary sense as state 1. As described below, such states may be implemented by a state machine or equivalent control whereby the two states combined allow a full JTAG boundary scan of all pads of IC 200 .

[0019] For more details, refer to Figure 2a , IC 200 includes several pads P0 to P 15 , so that the example IC 200 is a 16-pin device. In addition, there is a corresponding boundary scan cell C0 to C1 for each pad. 15 , thereby forming a boundary cell scan chain. Thus, in the example embodiment, each device pad has a corresponding boundary scan cell for reasons further described below, in contrast to conventional techniques where fixed JTAG pads do not have corresponding boundary scan cells (such as represented in the example of FIG. 1 ).

[0020] As described above, Figure 2a , which are used to receive a first set of JTAG signals, as summarized in Table 2 below.

[0021] Table 2

[0022] <![CDATA[ pad ]]> <![CDATA[ JTAG Signals ]]> <![CDATA[P0]]> <![CDATA[TDO0]]> <![CDATA[P1]]> <![CDATA[TRST0]]> <![CDATA[P2]]> <![CDATA[TMS0]]> <![CDATA[P3]]> <![CDATA[TCK0]]> <![CDATA[P4]]> <![CDATA[TDI0]]>

[0023] Furthermore, each of the pads P0 to P4 of Table 2 is connected to the corresponding switching elements S0 to S4 so that Figure 2a In the first state shown, each such switching element interconnects the pads so that their respective JTAG signals are properly routed to implement JTAG testing. Thus, in this first state: (i) pads P1 through P3 are connected to TAP controller 212; (ii) pad P0 is connected to receive data from boundary scan cell C1; and (iii) pad P1 through P3 are connected to TAP controller 212. 15 Receiving data as TDO0, the last cell in the sequence of cells forming a boundary chain is Figure 2a and (iii) pad P4 is connected so that its TDI0 signal can be transmitted via the multiplexer 222 and the switching element S 222 The signal is input to the boundary scan chain, starting from boundary scan cell C5, and is also connected to instruction register 216, bypass register 218 and ID register 220.

[0024] like Figure 2a The IC 200 shown in FIG. 2 also includes a second set of pads, namely pads P5 to P9, each of which is connected to a respective switching element S5 to S9, such that in the first state, as shown in FIG. Figure 2a As shown in , each such switching element interconnects the pad to a corresponding boundary scan cell in the scan cell chain, as summarized in Table 3 below.

[0025] Table 3

[0026] <![CDATA[ pad ]]> <![CDATA[ unit ]]> <![CDATA[P5]]> <![CDATA[C5]]> <![CDATA[P6]]> <![CDATA[C6]]> <![CDATA[P7]]> <![CDATA[C7]]> <![CDATA[P8]]> <![CDATA[C8]]> <![CDATA[P9]]> <![CDATA[C9]]>

[0027] Furthermore, in the first state, each of the boundary cells C5 to C9 provides a dedicated through connectivity path between the corresponding pads, through the cells, to the functional circuit 214. In this regard, “dedicated” indicates that each boundary pad allows only through connectivity between one corresponding pin and the functional circuit 214. Thus, such connectivity allows a signal from a pad or functional circuit 214 to be captured in the corresponding cell, and then the signal can be shifted to the next consecutive cell in a sequential manner so that the signal is ultimately provided from the scan cell chain as output data TDO.

[0028] IC 200 also includes pads other than those in the first or second set of pads, where such additional pads may therefore be considered a third set of pads that are not operable to receive JTAG signals. Figure 2a In the example of FIG. 1 , this third set of pads is shown as pads P 10 To P 15 Each pad in the third set of pads is preferably directly connected (ie, without switching elements as in the first and second sets of pads) to a corresponding and dedicated pass-through boundary scan cell in the chain, as summarized in Table 4 below.

[0029] Table 4

[0030] <![CDATA[ pad ]]> <![CDATA[ unit <!-- 3 -->]]> <![CDATA[P 10 ]]> <![CDATA[C 10 ]]> <![CDATA[P 11 ]]> <![CDATA[C 11 ]]> <![CDATA[P 12 ]]> <![CDATA[C 12 ]]> <![CDATA[P 13 ]]> <![CDATA[C 13 ]]> <![CDATA[P 14 ]]> <![CDATA[C 14 ]]> <![CDATA[P 15 ]]> <![CDATA[C 15 ]]>

[0031] Thus, dedicated connectivity paths between corresponding pads, through cells, and to functional circuits 214 allow signals from pads or functional circuits 214 to be captured in corresponding cells, and then the signals can be shifted to the next consecutive cells in a sequential manner so that the signals are ultimately provided from the scan cell chain as output data TDO.

[0032] Finish Figure 2a , boundary cell C 15 The output is also to the input of the demultiplexer, which has a first output which, for the 0 state, connects the demultiplexer input to pad P0 via switching element S0, so that in said state cell C 15 The output of the demultiplexer is connected to pad P0. For reasons described later, the demultiplexer also has a second output, which connects the demultiplexer input to the boundary scan cell C0 for the 1 state. In addition, each of the outputs of the instruction register 216, the bypass register 218 and the ID register 220 is connected to the input of the multiplexer, which has a first output, which connects the demultiplexer input to the input of the multiplexer for the 0 state. Therefore, as described above, the latter has its input connected to pin P0 (as TDO0) during the 0 state, so that during this state, the output of the register can be connected to pin P0.

[0033] For more details, refer to Figure 2b, showing IC 200 in a second state, indicated by the numeral 1 corresponding to the various switch positions and the position of the demultiplexer selection. Thus, in this regard, the Figure 2a The signal path of the scan chain of the boundary cell is switched to Figure 2b , thereby establishing that the scan chain is configurable in the sense that in a first state, signals from a first set of pads (e.g., P0 to P4) are not passed to the corresponding boundary cells, and in a second state, signals from a second set of pads (e.g., P5 to P9) are not passed to the corresponding boundary cells. Figure 2b , the second set of pads receives a second set of JTAG signals, as summarized in Table 5 below.

[0034] Table 5

[0035] <![CDATA[ pad ]]> <![CDATA[ JTAG Signals ]]> <![CDATA[P5]]> <![CDATA[TDO1]]> <![CDATA[P6]]> <![CDATA[TRST1]]> <![CDATA[P7]]> <![CDATA[TMS1]]> <![CDATA[P8]]> <![CDATA[TCK1]]> <![CDATA[P9]]> <![CDATA[TDI1]]>

[0036] Each second state JTAG signal is connected to a corresponding switching element so that in the second state, Figure 2b , each such switching element interconnects the pads so that their respective JTAG signals are routed appropriately to implement JTAG testing. In addition, routing bypasses the boundary scan cells to which such pads were specifically connected in state 0 (i.e., cells C5 to C9). Thus, in this second state: (i) pads P6 to P8 are connected to TAP controller 212; (ii) pad P5 is connected to receive data as TDO1 from boundary scan cell C4 via multiplexer 222 and switch element S5, forming the last cell in the sequence of cells in the boundary chain as shown. Figure 2b and (iii) pad P9 is connected so that its TDI1 signal can be input to the boundary scan chain via multiplexer 228, from the boundary scan unit C 10 Start, and the signal is also connected to the instruction register 216, bypass register 218 and ID register 220.

[0037] like Figure 2b As shown in FIG. 6 , IC 200 also includes a first set of pads. However, due to a change in connectivity to the configurable scan chain of the boundary cells, each pad in the first set of pads, namely pads P0 to P4, is in a second state, which is connected to a corresponding boundary scan cell in the scan cell chain via a corresponding switching element S0 to S4, as summarized in Table 6 below.

[0038] Table 6

[0039] <![CDATA[ pad ]]> <![CDATA[ unit ]]> <![CDATA[P0]]> <![CDATA[C0]]> <![CDATA[P1]]> <![CDATA[C1]]> <![CDATA[P2]]> <![CDATA[C2]]> <![CDATA[P3]]> <![CDATA[C3]]> <![CDATA[P4]]> <![CDATA[C4]]>

[0040] Furthermore, each of the boundary cells C0 to C4 is also connected to the functional circuit 214 .

[0041] Finish Figure 2b , IC 200 again includes pads other than those in the first or second set of pads, where such additional pads may therefore be considered a third set of pads that are not operable to receive JTAG signals. Thus, as in Figure 2a In the example of Figure 2b is shown as pad P 10 To P 15 , each pad is directly connected to a corresponding boundary scan cell in the chain, as summarized in Table 4 above.

[0042] Figure 3 A flow chart of an example method 300 of operation of IC 200 is depicted. Method 300 may be implemented by a state machine included as part of TAP controller 212 or by other circuits and controls, either solely on IC 200 or partially external thereto, such as with automated test equipment (ATE). Method 300 initiates with a JTAG test initiation step 310, where such testing may be, by way of example, at the manufacturer's location, such as via ATE, or later in the field, at the IC level or PCB level. In an example embodiment, step 310 may occur when IC 200 is powered on, i.e., as part of a power-on reset procedure.

[0043] After step 310, method 300 continues to step 320. In step 320, IC 200 operates in the first state 0 described above, in which case switching elements, multiplexing and demultiplexing are performed as described above. Figure 2a . At the same time, a first set of JTAG signals (e.g., four or five signals per modern standards) are applied to a first set of pads that are not connected to a corresponding dedicated pass boundary chain unit in a given state, and each of the JTAG signals is appropriately routed based on a specific signal and as described above. Thus, Table 2 above provides an example of this first set of JTAG signals. With such connectivity, the remaining pads on IC 200 (which in this example are pads P5 through P6) are then routed to the IC 200. 15 ) performs JTAG testing, thereby testing those pads in conjunction with the corresponding cells shown in Tables 3 and 4. Thus, pad P4 can introduce TDI data into the boundary scan chain, which is configured in state 0 to start with cell C5 and continue through cells C 15 , and the signal state may be: transferred between the cell and functional circuit 214; and proceeding along the configurable scan chain and generated as TDO data output via pad P0. Other JTAG tests may also be implemented during and using the configuration boundary chain of step 320.

[0044] After step 320, method 300 continues to step 330. In step 330, IC 200 operates in the second state 1 described above, in which case switching elements, multiplexing and demultiplexing are performed as described above. Figure 2b . At the same time, a second set of JTAG signals (e.g., four or five signals according to modern standards) is applied to a second set of pads that are different from the first set and are not connected to the corresponding dedicated pass boundary chain unit in a given state, wherein this second set of JTAG signals is also based on the signals and is appropriately routed as described above. Therefore, Table 5 above provides an example of this second set of JTAG signals. With this connectivity, JTAG testing is then performed on at least those pads that are JTAG connected in state 0, which are pads P0 to P4. In addition, using Figure 2b The configuration may be relative to the third set of pads (ie, pads P 10 To P 15 ) to repeat the test (or perform an alternative test). Thus, pad P9 can introduce TDI data into the boundary scan chain, which is configured in state 1 to operate with cell C 10 Start, continue through C 15 , and continues back to and including cells C0 to C4, but excluding cells corresponding to those pads that receive JTAG signals (i.e., C5 to C9). Thus, after step 330: (a) in step 320, the first group of pads is used to receive JTAG signals to test pads that are not in the first group; and (b) in step 330, a second group of pads different from the first group of pads is used to receive JTAG signals to test the first group of pads.

[0045] After step 330, method 300 continues to step 340. In step 340, the second set of pads of IC 200 are reconfigured back to the state 0 configuration, after which IC 200 can be operated according to the device specification and the pad assignment for each pad. Thus, in this regard, the second set of pads for IC 200 can be dual-purpose pads, used as JTAG pads during testing (in state 1 testing). After the reconfiguration in step 340, those pads are connected to functional circuit 214 through corresponding scan units. Thereafter, method 300 ends in step 350.

[0046] Figure 4An alternative example embodiment IC 200' is depicted that shares various functional and structural aspects with IC 200 described above. Thus, generally speaking, the IC is provided with: (i) a first set of pads operable in a first state to communicate test signals to a test circuit and in a second state to communicate input / output signals to a functional circuit; and (ii) a second set of pads, distinct from the first set of pads, operable in a second state to communicate test signals to the test circuit for testing signals associated with the first set of pads in the second state. However, for IC 200', multiple sets of alternating pads are facilitated by a switching circuit 230 to which both sets of pads are connected, whereby the switching circuit 230 can communicate signals between the pads and the functional circuit 214 and the tap controller 212. In addition, the tap controller 212 is operable to bidirectionally communicate with any of the instruction register 216, the bypass register 218, and the ID register 220, so that both sets of pads (one for the first state and one for the second state) allow the JTAG signals to be multiplexed in the circuit 230 so that a single output set of JTAG signals drives the TAP logic (e.g., by coupling it to the tap controller 212, which can then further communicate with the ID register 220, the bypass register 218, and the instruction register 216 as needed) and supports any other JTAG functionality. In this regard, various alternatives for implementing the necessary switching devices in both the circuit 230 and the controller 212 are possible. Also for the IC 200', a specific unit structure may be implemented to replace Figure 2a and 2b The switching and multiplexing equipment shown in Figure 5 Further described.

[0047] Figure 5 The drawing can be used for Figure 4 The units C0 to C in IC 200′ 15 The output of any of the and the cell C of the serial chain path x The structure of the present invention, wherein the equivalent circuit or part thereof can also be implemented for its input path. x With the structure of the entire boundary scan chain across different configurations of shared pads, the additional structure as now described ensures that values ​​shifted between cells corresponding to respective pads for JTAG do not propagate and affect the pads. x Contains the following input or control signals:

[0048] parallel_input: data from a function pin multiplexing module (which may be included as part of function circuit 214), whereby a signal related to the function usage (e.g., SPI, UART, ...) is multiplexed as part of the function pin multiplexing module, and this signal is the first data input to multiplexer 240, where the second data input to multiplexer 240 is the data from the previous cell C in the scan chain. x-1 In addition, parallel_input is input as the first data input to the multiplexer 242 , wherein the second data input to the multiplexer 242 is the output of the multiplexer 244 .

[0049] ·parallel_input_tpm: data from the test pin multiplexing module, whereby signals related to test use cases (e.g. scan, dmled, ....) are multiplexed as part of the test pin multiplexing module, and this signal is the first data input to multiplexer 244, where the second data input to multiplexer 242 is the output of multiplexer 246.

[0050] top_bsc_shift: controls multiplexer 240 to switch between parallel_input signal or the signal from the previous cell C in the scan chain. x-1 Select between the shift data.

[0051] clock_dr: clocks the serial register flip-flop 248 to clock in data from the output of the multiplexer 240 and outputs data to the latch output register flip-flop 250 .

[0052] top_bsc_update: clocks the latch output register flip-flop 250 to clock in data from the output of the serial register flip-flop 248 while outputting the first data value input to the multiplexer 246 .

[0053] top_bsc_output_mode: a signal that specifies the external test mode of the boundary scan cell driving I / O, and this signal is the first data input to the multiplexer 252 .

[0054] • test_path_select: control signal input to multiplexer 252 to select parallel_input_tmp output to pad to implement Design for Test (DFT) test path related to scan / dmled / PBIST etc.

[0055] In addition, with Unit C xAssociated is a four-bit data register 254, wherein its four bits are connected as follows:

[0056] b0: Control of the multiplexer 241 .

[0057] b1: The second data value input to the multiplexer 252 .

[0058] b2: Control of the multiplexer 246 .

[0059] b3: The second data value input to the multiplexer 246 .

[0060] Unit C x The operation is as follows. Figure 2a and 2b IC 200 of FIG. 2 depicts switches and some multiplexers so that: in one state, a first set of pads can be used for JTAG pins; and a second set of pads couples signals to the corresponding cells. In that case, for the first set, the switches allow certain cells to be bypassed. While providing comparable results, in IC 200′, for Figure 5 , Unit C x Non-JTAG test or other data may be output to the pads for one state, and JTAG scan chain data may be output to the pads for the other state. Specifically, bits in register 254 are programmed (or alternatively hard-coded) to select either the path from "parallel_input_tpm" or the path of latch_out register 250 (i.e., by controlling multiplexer 246), so that the selected selection may then be passed to the pads through multiplexer 242. Thus, serial register 248 is part of the boundary scan chain in both states, making the entire boundary scan chain the same across different configurations, while register 254 (or hard-coded) values ​​ensure that the shifted-in values ​​in serial register 248 do not propagate to and affect the pads when not needed. Specifically, in a first state where a first set of pads are used for JTAG testing, each cell C corresponding to such pads is x The serial register 248 of will get some shifted-in value from the previous cell in the chain, but that value will not propagate to the pad, so the pad continues to function as required by the test (i.e., by providing parallel_input_tpm to the pad instead). In a second state where the second set of pads is used for JTAG testing, the serial register value in the cell corresponding to the first set of JTAG pads is allowed to propagate (via register 250 and multiplexers 246, 244, and 242) to each respective pad, thereby ensuring that they are controllable and testable through boundary scan testing.

[0061] In view of the above description, example embodiments provide improvements in boundary scan of ICs and printed circuit boards (PCBs). Specifically, example embodiment ICs allow for sharing pads such that: in a first state, the pads can be used for JTAG testing, wherein during the state, the pins are bypassed or otherwise not connected to the configurable scan chain (although the TDI and TDO pads are connected in series for inputting and outputting data from the chain, rather than passing the data to the functional circuit 214); and in a second state, the pads are used for non-JTAG signals, which are connected to dedicated corresponding scan cells, and additional pads are used for JTAG testing of dual-purpose pads during the second state. Thus, a set of IC pads can be used for a second function other than JTAG testing, for example, for a functional interface such as input / output for a universal asynchronous receiver / transmitter (UART), or as a serial peripheral interface (SPI). Thus, for a low pad count device such as a low power RF device, a first set of pads may be shared for two different functions, one function being JTAG and the other function being unrelated to JTAG, wherein the pads (and associated signals and functions) themselves may still be JTAG tested in a state where the pads are not used as JTAG pads, and a second set of JTAG pads may be temporarily enabled via a configurable scan chain. References to "low pad count" may vary based on the application or other considerations, and thus example embodiments may be less than 64 pads, less than 32 pads, or less than 16 pads. Such an approach reduces device cost because the number of pads may be reduced, or full JTAG testing of all pads may be enabled in a relatively low pad count device. Thus, example embodiments allow 100% input / output test coverage on devices that share JTAG pads for functional interfaces, which may be an important requirement for certain (e.g., safety, automotive) qualifications. Furthermore, for devices with dual-purpose pads, board testing typically requires two different access protocols, one of which is JTAG, and scan chain JTAG testing is not allowed for dual-purpose pads because there are no corresponding boundary cells for such pads (e.g., in the example of FIG. 1 ), whereas an example embodiment may eliminate the dual requirement.

[0062] Figure 2a and 2b One example of a switching configuration is depicted to create a configurable scan chain of boundary cells in order to bypass the pass connectivity of selected cells for JTAG testing in respective different states, but various alternatives are possible. For example, while the example embodiment is shown as including 16 pads, various other numbers of pads may be implemented. Furthermore, example embodiments may be created to include or exclude an optional TRST (test reset) JTAG signal.

[0063] Modifications to the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. An integrated circuit, comprising: Functional circuit; Test circuits; a first set of pads operable in a first state to communicate a first set of test signals to the test circuit, and operable in a second state to communicate input / output signals to said functional circuit; and a second set of pads, different from the first set of pads, operable in the second state to communicate a second set of test signals to the test circuit for testing signals associated with the first set of pads in the second state, wherein the first group of test signals in the first state and the second group of test signals in the second state include JTAG signals, and Wherein said first set of pads comprises dual purpose pads.

2. The integrated circuit of claim 1 , wherein the test circuit comprises a configurable scan chain comprising a plurality of scan cells, wherein each scan cell of the plurality of scan cells is associated with a respective pad of one of the first set of pads and the second set of pads.

3. The integrated circuit of claim 2, and further comprising: circuitry for configuring the configurable scan chain in the first state such that the first set of pads communicate the first set of test signals that bypass corresponding scan cells in the configurable scan chain; and circuitry for configuring the configurable scan chain in the second state so that the second set of pads conveys the second set of test signals, which bypass corresponding scan cells in the configurable scan chain and are used to test boundary cells connected to corresponding pads in the first set of pads in the second state.

4. The integrated circuit of claim 2 , wherein each of the plurality of scan units comprises: A serial register for receiving serial link data; and circuit for preventing serial chain data in the serial register from reaching pads corresponding to the serial register when the scan unit is operated to convey the second set of test signals to the test circuit for testing signals associated with the first set of pads in the second state.

5. The integrated circuit of claim 1, wherein the first set of pads includes pads for communicating JTAG test signals at one time, and pads for communicating UART signals at another time.

6. The integrated circuit of claim 1, wherein the first set of pads includes pads for communicating JTAG test signals at one time, and pads for communicating SPI signals at another time.

7. The integrated circuit of claim 1, wherein the first set of pads includes pads for communicating JTAG test signals at one time, and pads for communicating functional interface signals at another time.

8. The integrated circuit of claim 1, wherein a total number of pads for the integrated circuit is equal to 16 or fewer pads.

9. The integrated circuit of claim 1, wherein a total number of pads for the integrated circuit is equal to 32 pads or less.

10. The integrated circuit of claim 1, wherein a total number of pads for the integrated circuit is equal to 64 pads or less.

11. A method for testing the operability of a circuit, comprising: In a first state, applying a first set of test signals to a first set of pads of an integrated circuit, the integrated circuit comprising functional circuitry and test circuitry, and for communicating the first set of test signals to the test circuitry; and in a second state, applying a second set of test signals to a second set of pads of the integrated circuit, the second set of pads being different from the first set of pads, and communicating the second set of test signals to the test circuit for testing signals associated with the first set of pads; wherein the first set of test signals in the first state and the second set of test signals in the second state include JTAG signals; and Wherein said first set of pads comprises dual purpose pads.

12. The method of claim 11, wherein the test circuit comprises a configurable scan chain comprising a plurality of scan cells, wherein each scan cell of the plurality of scan cells is associated with a respective pad of one of the first set of pads and the second set of pads.

13. The method according to claim 12, and further comprising: configuring the configurable scan chain in the first state such that the first set of pads communicate the first set of test signals that bypass corresponding scan cells in the configurable scan chain; and The configurable scan chain is configured in the second state so that the second set of pads conveys the second set of test signals that bypass corresponding scan cells in the configurable scan chain and are used to test boundary cells connected to corresponding pads in the first set of pads in the second state.

14. The method according to claim 12, wherein each of the plurality of scanning units comprises: A serial register for receiving serial link data; and circuit for preventing serial chain data in the serial register from reaching pads corresponding to the serial register when the scan unit is operated to convey the second set of test signals to the test circuit for testing signals associated with the first set of pads in the second state.

15. The method of claim 11, wherein the first set of pads includes pads for communicating JTAG test signals at one time, and pads for communicating UART signals at another time.

16. The method of claim 11, wherein the first set of pads includes pads for communicating JTAG test signals at one time, and pads for communicating SPI signals at another time.

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