Systems and methods for decoding error correction codes using historical decoding information

Abstract

Systems and methods are provided for decoding data read from a non-volatile storage device. One method can include receiving a chunk of data read from a physical location of a non-volatile storage device and searching a memory for storing soft information associated with the physical location using a unique identifier associated with the physical location. The soft information can be generated from one or more previous decoding processes of previous data from the physical location. The method can further include retrieving the soft information identified by the unique identifier associated with the physical location from the memory, decoding the chunk of data with the soft information indicative of reliability of bits in the chunk of data, and updating the soft information using decoding information generated in the decoding process.

Description

Technical Field

[0001] This disclosure relates to decoding data encoded with parity data, and more particularly to decoding encoded data using historical information collected from previous decoding operations. Background Technology

[0002] A common problem in many data communication or storage systems is data corruption, for example, due to noise during write / read operations in the communication channel or storage system. One technique to address data corruption is the use of error-correcting codes (ECC) or forward error-correcting codes (FEC). ECC and FEC add redundant or parity data to the user data so that even if many errors are introduced (depending on the capabilities of the error-correcting codes used), such as during transmission on memory or during corruption, the user data can be recovered by the receiver or reader.

[0003] Over the years, many different coding schemes have been developed, such as Hamming codes, Reed-Solomon codes, and Turbo codes. Currently, low-density parity-check (LDPC) codes are widely used. However, all of these error-correcting codes are computationally complex, and the techniques for using these error-correcting codes still need improvement. Summary of the Invention

[0004] The methods disclosed herein may include a method comprising: receiving a data chunk read from a physical location of a non-volatile storage device; and searching in memory for soft information associated with the physical location using a unique identifier associated with the physical location. The soft information may be generated based on one or more previous decoding processes of previous data from the physical location. The method may further include: retrieving from the memory the soft information identified by the unique identifier associated with the physical location; decoding the data chunk using the soft information indicating the reliability of bits in the data chunk; and updating the soft information using decoding information generated during the decoding process.

[0005] According to one embodiment, the data group may be a data block, and the unique identifier associated with the physical location may be the physical data block address (PDA) of the block.

[0006] According to one embodiment, the soft information may include reliability information corresponding to each bit, which may be generated based on whether the corresponding bit is flipped and the flipping frequency during the one or more previous decoding processes.

[0007] According to one embodiment, the soft information may include reliability information for the entire data block.

[0008] According to one embodiment, the reliability information for the entire data block may include information that one logical state is more reliable than another logical state.

[0009] According to one embodiment, the memory may use a unique identifier associated with the physical location as an index to store the soft information.

[0010] According to one embodiment, the method may further include using a caching algorithm to cache the soft information.

[0011] The embodiment may further include a storage system controller, which may include a decoder, a soft information acquirer, and a soft information generator. The decoder may be configured to receive and decode data chunks read from a physical location of a non-volatile storage device. The soft information acquirer may be configured to search for soft information associated with the physical location in memory using a unique identifier associated with the physical location, and to acquire the soft information identified by the unique identifier associated with the physical location from the memory. The soft information may be generated based on one or more previous decoding processes of previous data from the physical location, and the decoder may be further configured to decode the data chunks using the soft information indicating the reliability of bits in the data chunks. The soft information generator may be configured to update the soft information using decoding information generated during the decoder's decoding of the data chunks.

[0012] This disclosure may also include a non-volatile machine-readable medium having executable instructions, wherein, when the executable instructions are executed by a storage controller, the storage controller receives a data chunk read from a physical location of a non-volatile storage device, searches for soft information associated with the physical location in memory using a unique identifier associated with the physical location, retrieves the soft information identified by the unique identifier associated with the physical location from the memory, decodes the data chunk with the soft information indicating the reliability of bits in the data chunk, and updates the soft information using decoding information generated during the decoding process. The soft information may be generated based on one or more previous decoding processes of previous data from the physical location. Brief description of the attached figures

[0013] Figure 1 A non-volatile storage system according to one embodiment of the present disclosure is illustrated schematically.

[0014] Figure 2A , Figure 2B and Figure 2CThe effect of a shift in the threshold voltage value of a NAND flash memory cell according to one embodiment of the present disclosure is illustrated schematically.

[0015] Figure 3 The illustration schematically shows historical information about each bit according to one embodiment of the present disclosure.

[0016] Figure 4 This illustration schematically shows how historical information is stored in memory according to one embodiment of the present disclosure.

[0017] Figure 5 This is a flowchart of a process for decoding data blocks according to one embodiment of the present disclosure. Detailed Implementation

[0018] Specific embodiments according to this application will now be described in detail with reference to the accompanying drawings. For consistency, the same elements in the various figures are indicated by the same reference numerals.

[0019] This disclosure provides apparatus, systems, and methods for decoding error-correcting code (ECC) encoded data stored in a non-volatile memory (NVM) storage device. Figure 1 A non-volatile memory system 100 according to one embodiment of the present disclosure is schematically illustrated. The non-volatile memory system 100 may include an ECC decoding controller 102, one or more ECC decoders 104, a raw data buffer 106, an ECC data interface 108, a NAND interface controller 110, a plurality of NAND devices 112, a soft information manager 114, a soft information generator 116, a soft information acquirer 118, and memory 120. The plurality of NAND devices 112 may be coupled to the NAND interface controller 110 via one or more channels. In one embodiment, a channel may include more than one NAND device. The raw data buffer 106 may include one or more buffer modules, and the memory 120 may also include one or more memory modules.

[0020] In various embodiments, one or more ECC decoders 104 may include decoder circuitry for hard-decision decoding and soft-decision decoding. For example, ECC decoder 104 may include one or more hard-decision decoders and one or more soft-decision decoders. The decoder circuitry for hard-decision decoding may be any suitable hard-decision decoder implementing a hard-decision algorithm, including but not limited to bit-flipping algorithms or any other hard-decision techniques yet to be developed. And the decoder circuitry for soft-decision decoding may be any suitable soft-decision decoder implementing a soft-decision algorithm, including but not limited to any conventional soft-decision algorithm based on industry-known confidence propagation (e.g., the product algorithm (“SPA”), the min-sum algorithm, the random decoding algorithm, or variations thereof) or any other soft-decision algorithm yet to be developed. For example, in one embodiment, one or more ECC decoders 104 may include a min-sum decoder that can operate in both single hard-decision (HD) mode and multi-bit information soft-decision (SD) mode. In one embodiment, soft information obtained from memory 120 may be used by decoder circuitry at one or more ECC decoders 104 for soft-decision decoding.

[0021] It should be noted that in some embodiments, other soft information can also be obtained from the NAND device and used for soft decision decoding, such as regular soft information obtained by reading the same data from the NAND device multiple times. For example, in one embodiment, if soft information cannot be obtained from memory 120, regular soft information can be obtained from the NAND device and sent to the soft information manager 114. The soft information manager 114 can forward the regular soft information to the decoder circuitry for soft decision decoding at one or more ECC decoders 104.

[0022] In one embodiment, the non-volatile storage system 100 may be a solid-state drive (SSD). Furthermore, in one embodiment, the ECC decoding controller 102, one or more ECC decoders 104, raw data buffer 106, ECC data interface 108, soft information manager 114, soft information generator 116, soft information acquirer 118, and NAND interface controller 110 may be integrated into a single storage system controller chip (e.g., an integrated circuit (IC) chip), while the memory 120 and multiple NAND devices 112 may be coupled to the storage system controller chip. In another embodiment, the memory 120 may also be integrated into the storage system controller chip.

[0023] The ECC decoding controller 102 may be a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), or an application-specific integrated circuit (ASIC). In some embodiments, when performing a read operation, the ECC decoding controller 102 may receive an ECC task start signal with one or more parameters. The ECC decoding controller 102 may send a signal to the ECC data interface 108 to cause the ECC data interface 108 to place one or more data chunks received from the NAND device 112 into the raw data buffer 106. It should be noted that the term "chunk" as used herein may refer to data of a certain size stored in the storage system 100 such that the physical location of the data in the storage system 100 can be associated with a unique identifier. In one embodiment, a chunk may be a data block that may include one or more ECC codewords, and the physical location of the chunk may be uniquely identified by its Physical Data Block Address (PDA).

[0024] One or more ECC decoders 104 can decode each data block obtained from NAND device 112. During or after the decoding operation, decoding information can be generated and sent to soft information generator 116. For example, during the decoding operation, some bits may be flipped while others are not. This can be useful decoding information. Soft information generator 116 can receive a signal from ECC decoding controller 102 indicating that the ECC decoding task has been completed, and can generate soft information for the corresponding block from the decoding information. The generated soft information can be stored in memory 120. In some embodiments, the soft information generated in soft information generator 116 can indicate the reliability of each bit in the corresponding block. For example, a data block may contain many bits, and the decoding operation may change the values ​​of some bits but not all bits. It can be assumed that those bits with changed values ​​during the ECC decoding operation may be error-prone and therefore may be marked as less reliable compared to other bits whose values ​​did not change during the decoding operation.

[0025] Whenever one or more ECC decoders 104 decode a data block from a specific location of the NAND device 112, decoding information can be generated in those one or more ECC decoders 104. In some embodiments, each time one or more data blocks from a specific location of the NAND device 112 are decoded by one or more ECC decoders 104, the soft information generator 116 can retrieve the generated soft information from memory 120 and update the soft information using the newly generated decoding information. Therefore, the soft information stored in memory 120 can be cumulative and referred to as historical information. For example, after performing some decoding operations on data from a physical location, the soft information may show that, historically, the values ​​of some bits may have changed more frequently than those of other bits, while some bits may never change their values. Therefore, the soft information can accordingly indicate the reliability of the bits from that physical location in the spectrum, such that those bits with the most frequently changing values ​​are the least reliable, while those bits with values ​​that have never changed are the most reliable.

[0026] Soft information can be used in future decoding processes as data blocks from the same physical location of NAND device 112 are read and updated in each future decoding process that uses data from the same location. It should be noted that the soft information can be generated by hardware or software. In various embodiments, the soft information generator 116 can be implemented in hardware or software. For example, in one embodiment, the soft information generator 116 can be implemented as software that executes in a processor.

[0027] The memory 120 used to store soft information can be static random access memory (SRAM), double data rate RAM, or MRAM, or any memory that can have a much shorter read latency than the NAND device. Therefore, in this embodiment, soft information can be obtained from memory 120 much faster than conventional methods of obtaining soft information from the NAND device, such as by rereading data blocks from the NAND device. Furthermore, in at least one embodiment, because they come from different paths and can be performed in parallel, obtaining soft information from memory 120 and reading raw data from the NAND device can be performed simultaneously. For example, when the NAND interface controller 110 receives a signal to begin reading data from the physical location of the NAND device 112, the ECC decoding controller 102 can send a signal to the soft information acquirer 118 to begin searching for and acquiring soft information associated with the physical location. This parallelism helps avoid the overhead of reading any soft information from the NAND device.

[0028] In various embodiments, soft information generated from historical decoding information can be applied to the entire data block or each bit of the data block in future decoding processes. Figure 2A , Figure 2B and Figure 2C The illustration schematically shows the effect of threshold voltage offset of NAND flash memory cells and how soft information from historical decoding information can be applied to the entire data block according to embodiments of this disclosure. Figure 2A , Figure 2B and Figure 2C The horizontal axis in the diagram can be the threshold voltage of the memory cell in the NAND device. Figure 2A , Figure 2B and Figure 2C The vertical axis in the diagram can be the probability distribution function of the threshold voltage of the memory cell.

[0029] Figure 2A Curve 202 in the diagram can indicate the reading of the first logic state, such as logic 1. Figure 2A Curve 204 in the diagram can indicate the readout of a second logic state, such as logic 0. The term "readout" as used herein can refer to the readout voltage of any given memory cell, and can be determined by comparing this readout voltage with a reference voltage V. ref Comparisons are used to assign a logical state to any given bit.

[0030] As in Figure 2A As shown, curve 202 can have an extension exceeding the reference voltage V. ref The tail 208 enters a region that can be considered to be in a second logic state, and curve 204 can have a tail 206 extending beyond the reference voltage Vref entering a region that can be considered to be in a first logic state. That is, a correct logic state with bits read in tail 206 can be a second logic state, but because these bit threshold voltages are less than the reference voltage Vref, ... ref Therefore, they can be considered as the first logic state. Meanwhile, a correct logic state with bits read from tail 208 can also be the first logic state, but because these bit threshold voltages are greater than the reference voltage V... ref Therefore, they can be considered as second logical states.

[0031] In this embodiment, during the decoding process, incorrectly marked bits can be corrected. That is, during decoding, bits that may be incorrectly marked as logic state one and have a readout in section 206 can be flipped to logic state two, and bits that may be incorrectly marked as logic state two and have a readout in section 208 can be flipped to logic state one. When the threshold voltage does not shift, such as in Figure 2A Similarly, the sizes of tail 206 and 208 can be close, and the number of corrections from logic state one to logic state two can be close to the number of corrections from logic state two to logic state one.

[0032] In various embodiments, the threshold voltage of the memory cell can be offset. For example, with increased use (e.g., increased P / E cycles), the cell's threshold voltage may tend to shift to the right. That is, the reference voltage V ref It may not be in a good position where the sizes of the 206 and 208 at the rear are close. Figure 2B This shows that the threshold voltage for logic state one can be shifted slightly to the right, therefore, Figure 2A The curve 202 becomes Figure 2B Curve 202A in the diagram. A rightward shift of the threshold voltage for logic state one may lead to... Figure 2A The tail section 208 becomes Figure 2B The tail section 208A. Because the offset of curve 202A is to the right, therefore in Figure 2B In the middle, tail 208A can be larger than tail 208, therefore tail 208A can be larger than tail 206. That is to say, in Figure 2B In this case, the number of read voltage bits in tail 208A can be greater than the number in tail 206.

[0033] The impact of threshold voltage offset is a correction for potential imbalances between two logic states. In at least one embodiment, two toggle counters can be used. During the decoding of a data block, one toggle counter can record how many bits toggle from a first logic state to a second logic state (e.g., "1" to "0"), while the other toggle counter can record how many bits toggle from the second logic state to the first logic state (e.g., "0" to "1"). The difference between the counts of the two toggle counters can provide additional information about the NAND device, which can be used to improve ECC decoding performance.

[0034] For example, in Figure 2B In this context, the threshold voltage of logic state one can be offset by increasing, and the toggle count from logic state two (e.g., logic 0) to logic state one (e.g., logic 1) can be greater than the toggle count from logic state one (e.g., logic 1) to logic state two (e.g., logic 0). Based on the difference between the toggle counts, bits with read values ​​of logic state one and bits with read values ​​of logic state two can be assigned different reliability levels. For example, for data from a physical location, if the soft information indicates more toggles from logic state one to logic state two (e.g., logic 1 to 0) than from logic state two to logic state one (e.g., logic 0 to 1), then logic state two is likely reliable, and bits with read values ​​in logic state two (e.g., logic 0) are likely more reliable than bits with read values ​​in logic state one (e.g., logic 1).

[0035] It should be noted that Figure 2B An example is shown where the threshold voltage for logic state one is offset by a large margin. Figure 2C Another example is shown where the threshold voltage of logic state one is shifted to the left (e.g., becomes smaller), therefore, Figure 2A The curve 202 becomes Figure 2C Curve 202B in the diagram. A left shift of the threshold voltage for logic state one can lead to... Figure 2A The tail section 208 becomes Figure 2C The tail portion 208B. Because the shift of curve 202B is to the left, therefore in Figure 2C In the middle, tail 208B can be smaller than tail 208, therefore tail 208B can be smaller than tail 206. That is, in Figure 2C In this case, the number of bits in tail 208B for reading voltage can be less than the number in tail 206.

[0036] because Figure 2C In this context, the threshold voltage of logic state one can be offset to reduce, so the toggle count from logic state two (e.g., logic 0) to logic state one (e.g., logic 1) can be less than the toggle count from logic state one (e.g., logic 1) to logic state two (e.g., logic 0). Figure 2C In the example, a bit with a read value in logic state two (e.g., logic 0) may be more reliable than a bit with a read value in logic state one (e.g., logic 1).

[0037] It should be noted that Figure 2B and Figure 2C The threshold voltage offset shown is merely an exemplary example. In some other embodiments, the threshold voltage of logic state two may also be offset to the left or right. Furthermore, the shapes of curves 202 and 204 may change during the offset; for example, curves 202 and / or 204 may become lower, wider, or include both.

[0038] Figure 3 The illustration schematically shows historical information about individual bits according to one embodiment of the present disclosure. At time t, a data block 302 from the physical location of the NAND device 112 can be decoded. Multiple errors can be corrected during the decoding process, and a vector 304 can be generated using markers indicating which bits(s) of the data block 302 have been flipped. In one embodiment, the vector 304 can have the same size as the block of data 302, and the markers at positions 306.1 and 306.2 in the vector 304 can be “1”, corresponding to the positions of the flipped bits in the data 302.

[0039] At time t+k, data block 308 at the same location from NAND device 112 can be decoded. Information from the previous decoding at time t can be used, which may indicate that bits at positions 306.1 and 306.2 may be less reliable than other bits. During the decoding process, multiple errors can be corrected at time t+k, and vector 310 can be generated using markers indicating which bits(s) of data block 308 have been flipped. Vector 310 may have a "1" at position 316.1, the position of which can match the position of the bit(s) in data block 308 that has been flipped. In one embodiment, vector 310 may be an updated version of vector 304 after updating vector 304 with a new decoding operation at time t+k. In some embodiments, vectors (e.g., 304 and 310) may be referred to as error vectors.

[0040] It should be noted that, although Figure 3 The diagram shows that two errors were corrected at time t and one error at time t+k. However, typically, many bits of a data block can be corrected with a single decoding operation. Furthermore, soft information can indicate that individual bits of a data block can have different levels of reliability, and the reliability of each bit can change over time. For example, based on historical information, the bit at position 306.1 may be less reliable than the bit at position 306.2, and the bit at position 306.2 may be less reliable than other bits that were never found to have errors at decoding times t and t+k.

[0041] Figure 4 The illustration schematically shows how soft information is stored in memory 120 according to one embodiment of the present disclosure. In one embodiment, memory 120 may use a unique identifier as an index to store soft information in different storage locations. Figure 4 As shown, NAND device 112 may include NAND devices 112.1 to 112.N, where N is a positive integer greater than 1. Each storage location may be associated with a unique identifier, and the unique identifier may be used as an index to soft information stored in memory 120. For example, NAND device 112.1 may have a data block stored at location 404.1, NAND device 112.2 may have a data block stored at location 404.2 and another data block stored at location 404.3, and NAND device 112.N may have a data block stored at location 404.M, where M is greater than 3. A storage location may refer to an identifiable unit of a NAND device of a specific size. In one embodiment, a physical location may be the physical location of a data block, and the unique identifier may be its Physical Data Block Address (PDA).

[0042] In memory 120, soft information for data stored at location 404.1 can be maintained at 408.1 and associated with an index value, which can be a unique identifier associated with location 404.1. Soft information for data stored at location 404.2 can be maintained at 408.2 and associated with another index value, which can be a unique identifier associated with location 404.2. Soft information for data stored at location 404.3 can be maintained at 408.3 and associated with its own index value, which can be a unique identifier associated with location 404.3. Similarly, soft information for data stored at location 404.M can be maintained at 408.M and associated with its own index value, which can be a unique identifier associated with location 404.M.

[0043] In some embodiments, due to size limitations, memory 120 may not be able to store soft information for all storage locations of the NAND device 112. That is, if soft information for many physical locations needs to be stored, the required memory size may exceed the size of memory 120. In some embodiments, a caching method can be used. For example, instead of storing soft information for all NAND storage locations, soft information for a subset of NAND storage locations (e.g., T locations) can be stored in memory 120. There are several ways to select the T storage locations. Any existing or future caching algorithm can be used. For example, these T storage locations could be recently read or recently erroneous storage locations. In embodiments where only soft information for a subset of storage locations is stored, memory 120 may also store unique identifiers for these storage locations.

[0044] Figure 5 This is a flowchart of a process 500 for decoding a data block using soft information from historical decoding information, according to one embodiment. In block 502, a data block read from a physical location of a non-volatile storage device may be received. For example, one or more ECC decoders 104 may receive block data from a NAND device 112. In block 504, soft information associated with the physical location may be searched in memory using a unique identifier associated with that physical location. In one embodiment, for example, soft information may be generated based on one or more previous decoding processes of previous data from the physical location and stored in memory (e.g., memory 120). In block 506, soft information identified by a unique identifier associated with the physical location may be retrieved from memory. In one embodiment, for example, a soft information retriever 118 may be configured to search memory 120 for soft information associated with the physical location using a unique identifier associated with the physical location and retrieve the identified soft information from memory 120.

[0045] In block 508, a data block can be decoded using soft information indicating the reliability of bits in the data block. In one embodiment, one or more ECC decoders 104 may include at least one decoder configured to decode the block using soft information retrieved from memory 120, which indicates the reliability of bits in the data block. In block 510, the soft information can be updated using decoding information generated during the decoding process. In one embodiment, the soft information may be initially generated by the soft information generator 116 when a block of data from a physical location is read and no soft information associated with that physical location is found in memory 120. Subsequently, the soft information can be updated by the soft information generator 116 whenever a data block from the same physical location is decoded. The updated soft information can be put back into memory 120 for future decoding of data from the same physical location.

[0046] The processes disclosed in the embodiments (including process 500) can be implemented by software (e.g., executable on a computer processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), or both), hardware (e.g., a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)), firmware, or any suitable combination of the three).

[0047] In one embodiment, for example, some or all of the disclosed methods and operations may be implemented using software, consisting of computer-executable instructions, stored on one or more computer-readable storage media. The one or more computer-readable storage media may include non-transitory computer-readable media (e.g., removable or non-removable disks, magnetic tapes or cassettes, solid-state drives (SSDs), hybrid hard disk drives, CD-ROMs, CD-RWs, DVDs, or any other tangible storage media), volatile storage components (e.g., DRAM or SRAM), or non-volatile storage components (e.g., hard disk drives). The computer-executable instructions may be executed by a computer processor (e.g., CPU, GPU, or both) of a computer (e.g., any commercial computer, including smartphones or other mobile devices that include computer hardware). Any computer-executable instructions used to implement the disclosed techniques, as well as any data created and used during the implementation of the disclosed embodiments, may be stored on one or more computer-readable media (e.g., non-transitory computer-readable media). Such software can be executed, for example, on a single local computing device (e.g., any suitable commercial computer or mobile device) or in a network environment using one or more networked computers (e.g., via the Internet, WAN, LAN, client-server network (e.g., cloud computing network) or other such networks).

[0048] Embodiments according to this disclosure can be implemented for any type of ECC code, such as, but not limited to, rectangular parity check, LDPC, and Hamming codes.

[0049] While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The aspects and embodiments disclosed herein are for illustrative purposes and are not intended to be limiting; the true scope and spirit are indicated by the appended claims.

Claims

1. A method for decoding error-correcting codes using historical decoding information, characterized in that, include: Receive data blocks read from the physical location of a non-volatile storage device; Using a unique identifier associated with the physical location, search in memory for soft information associated with the physical location, the soft information being generated based on one or more previous decoding processes of previous data from the physical location; Retrieve the soft information identified by the unique identifier associated with the physical location from the memory; The data block is decoded using the soft information indicating the reliability of the bits in the data block; and The soft information and the decoding information generated during the decoding process of the data block are used to generate updated soft information associated with the physical location, and the updated soft information is stored in the memory.

2. The method according to claim 1, characterized in that, The data block is a data block, and the unique identifier associated with the physical location is the physical data block address (PDA) of the data block.

3. The method according to claim 1, characterized in that, The soft information includes reliability information for each bit, which is generated based on whether the corresponding bit is flipped and the flipping frequency during the one or more previous decoding processes.

4. The method according to claim 1, characterized in that, The soft information includes reliability information for the entire data block.

5. The method according to claim 4, characterized in that, The reliability information for the entire data block includes information that one logical state is more reliable than another logical state.

6. The method according to claim 1, characterized in that, The memory uses a unique identifier associated with the physical location as an index to store the soft information.

7. The method according to claim 1, characterized in that, Also includes: Use a caching algorithm to cache the soft information.

8. The method according to claim 1, characterized in that, The method further includes: Receive another data block read from the physical location Retrieve the updated soft information from the memory; The updated soft information is used to decode the other data block.

9. The method according to claim 1, characterized in that, The decoding information includes whether each bit in the data block is flipped during the decoding process of the data block.

10. The method according to claim 1, characterized in that, The decoding information includes the number of bits in the data block that flips from a first logical state to a second logical state during the decoding process of the data block, and the number of bits in the data block that flips from a second logical state to a first logical state during the decoding process of the data block.

11. A storage system controller, characterized in that, include: A decoder is configured to receive and decode data blocks read from the physical location of a non-volatile storage device. The soft information acquirer is configured as follows: Using a unique identifier associated with the physical location, search in memory for soft information associated with the physical location, the soft information being generated based on one or more previous decoding processes of previous data from the physical location; and The decoder is further configured to: retrieve the soft information identified by the unique identifier associated with the physical location from the memory, wherein the decoder is configured to: decode the data block with the soft information indicating the reliability of the bits in the data block; and A soft information generator is configured to use the soft information and decoding information generated during the decoding of the data block by the decoder to generate updated soft information associated with the physical location, and to store the updated soft information in the memory.

12. The storage system controller according to claim 11, characterized in that, The data block is a data block, and the unique identifier associated with the physical location is the physical data block address (PDA) of the data block.

13. The storage system controller according to claim 11, characterized in that, The soft information includes reliability information for each bit, which is generated based on whether the corresponding bit is flipped and the flipping frequency during the one or more previous decoding processes.

14. The storage system controller according to claim 11, characterized in that, The soft information includes reliability information for the entire data block.

15. The storage system controller according to claim 14, characterized in that, The reliability information for the entire data block includes information that one logical state is more reliable than another logical state.

16. The storage system controller according to claim 11, characterized in that, The memory uses a unique identifier associated with the physical location as an index to store the soft information.

17. The storage system controller according to claim 11, characterized in that, The soft information is cached in the memory using a caching algorithm.

18. The storage system controller according to claim 11, characterized in that, The decoder is also configured to: Receive another data block read from the physical location Retrieve the updated soft information from the memory; The updated soft information is used to decode the other data block.

19. The storage system controller according to claim 11, characterized in that, The decoding information includes whether each bit in the data block is flipped during the decoding process of the data block.

20. The storage system controller according to claim 11, characterized in that, The decoding information includes the number of bits in the data block that flips from a first logical state to a second logical state during the decoding process of the data block, and the number of bits in the data block that flips from a second logical state to a first logical state during the decoding process of the data block.

21. A non-transitory machine-readable medium having executable instructions, characterized in that, When the executable instructions are executed by the storage controller, the storage controller performs the following operations: Receive data blocks read from the physical location of a non-volatile storage device; Using a unique identifier associated with the physical location, search in memory for soft information associated with the physical location, the soft information being generated based on one or more previous decoding processes of previous data from the physical location; Retrieve the soft information identified by the unique identifier associated with the physical location from the memory; The data block is decoded using the soft information indicating the reliability of the bits in the data block; and The soft information and the decoding information generated during the decoding process of the data block are used to generate updated soft information associated with the physical location, and the updated soft information is stored in the memory.

22. The non-transitory machine-readable medium according to claim 21, characterized in that, The data block is a data block, and the unique identifier associated with the physical location is the physical data block address (PDA) of the data block.

23. The non-transitory machine-readable medium according to claim 21, characterized in that, The soft information includes reliability information for each bit, which is generated based on whether the corresponding bit is flipped and the flipping frequency during the one or more previous decoding processes.

24. The non-transitory machine-readable medium according to claim 21, characterized in that, The soft information includes reliability information for the entire data block.

25. The non-transitory machine-readable medium according to claim 24, characterized in that, The reliability information for the entire data block includes information that one logical state is more reliable than another logical state.

26. The non-transitory machine-readable medium according to claim 21, characterized in that, The memory uses a unique identifier associated with the physical location as an index to store the soft information.

27. The non-transitory machine-readable medium according to claim 21, characterized in that, When the executable instructions are executed by the storage controller, the storage controller performs the following operations: Receive another data block read from the physical location Retrieve the updated soft information from the memory; The updated soft information is used to decode the other data block.

28. The non-transitory machine-readable medium according to claim 21, characterized in that, The decoding information includes whether each bit in the data block is flipped during the decoding process of the data block.

29. The non-transitory machine-readable medium according to claim 21, characterized in that, The decoding information includes the number of bits in the data block that flips from a first logical state to a second logical state during the decoding process of the data block, and the number of bits in the data block that flips from a second logical state to a first logical state during the decoding process of the data block.

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