Packaged semiconductor device and method of making a packaged semiconductor device

Abstract

A method for making a packaged semiconductor device includes: providing a plurality of semiconductor dies, which are arranged in an array on a carrier so that a first side of the semiconductor dies faces the carrier and an empty space is arranged beside each semiconductor die; arranging a substrate including a plurality of conductive elements over the plurality of semiconductor dies so that the conductive elements are arranged in corresponding empty spaces beside each semiconductor die; molding over the plurality of semiconductor dies to form a molded body; and singulating the packaged semiconductor devices from the molded body by cutting through the molded body.

Description

Technical Field

[0001] The present disclosure generally relates to a packaged semiconductor device and a method for making a packaged semiconductor device. Background Art

[0002] A packaged semiconductor device may include a semiconductor die encapsulated by a molded body. The semiconductor die may include electrical contacts arranged at a first side, such as a bottom side, of the packaged semiconductor device. One or more vertical interconnect structures may be used to redirect one or more electrical contacts of the semiconductor die or other electronic components to a second side, such as a top side, of the packaged semiconductor device opposite to the first side. Providing electrical contacts on two opposite sides of a packaged semiconductor device may, for example, enable stacking of devices, which may aid in continued miniaturization efforts for electronic components. However, during the manufacture of packaged semiconductor devices, the additional processing steps of providing such vertical interconnect structures may increase overall manufacturing time and manufacturing costs. For these and other reasons, improved packaged semiconductor devices and improved methods for manufacturing packaged semiconductor devices may be needed. Summary of the invention

[0003] Various aspects relate to a method for making a packaged semiconductor device, the method comprising: providing a plurality of semiconductor dies, the semiconductor dies being arranged in an array on a carrier such that a first side of the semiconductor dies faces the carrier and such that an empty space is arranged beside each semiconductor die; arranging a substrate including a plurality of conductive elements over the plurality of semiconductor dies such that the conductive elements are arranged in corresponding empty spaces beside each semiconductor die; molding over the plurality of semiconductor dies to form a molded body; and singulating the packaged semiconductor device from the molded body by cutting through the molded body.

[0004] Various aspects relate to a packaged semiconductor device comprising: a semiconductor die including a first side and an opposite second side; a molded body encapsulating the semiconductor die and including the first side and the opposite second side; a first redistribution layer arranged on the first side of the semiconductor die and the first side of the molded body; and a conductive element arranged in the molded body beside the semiconductor die, wherein the conductive element extends from the first redistribution layer at least to a plane including the second side of the semiconductor die. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The accompanying drawings show a number of examples and together with the description are used to explain the principles of the present disclosure. Other examples and many expected advantages of the present disclosure will be readily understood as they become better understood by reference to the following detailed description. The elements of the accompanying drawings are not necessarily to scale with respect to each other. The same or similar reference numerals represent the same or similar parts.

[0006] Figure 1 A cross-sectional view of a packaged semiconductor device is shown.

[0007] Figure 2 A cross-sectional view of another packaged semiconductor device including conductive elements extending to a point within the perimeter of the semiconductor die is shown.

[0008] Figure 3 A cross-sectional view of another packaged semiconductor device is shown in which the conductive element includes a conductive trace deposited on an insulating portion.

[0009] Figure 4 A cross-sectional view of a packaged semiconductor device including a redistribution layer on opposite sides of a molding body is shown.

[0010] Figure 5A-5G Cross-sectional views of a packaged semiconductor device are shown at various stages of fabrication according to an exemplary method for fabricating a packaged semiconductor device.

[0011] Figure 6 is a flow chart of an exemplary method for making a packaged semiconductor device. DETAILED DESCRIPTION

[0012] In the following detailed description, directional terms such as "top", "bottom", "left", "right", "upper", "lower", etc. are used with reference to the orientation of the figures being described. Because components of the present disclosure can be positioned in many different orientations, the directional terms are used for illustrative purposes only. It should be understood that other examples can be utilized and that structural or logical changes can be made.

[0013] In addition, although the specific features or aspects of the examples can be disclosed only for one embodiment in several embodiments, such features or aspects can be combined with one or more other features or aspects of other embodiments, which may be desirable and advantageous for any given or specific application, unless otherwise specifically noted or unless technically limited. In addition, with respect to the terms "comprising", "having", "with" or other variations thereof used in the specific embodiments or claims, these terms are intended to include meanings in a manner similar to the term "comprising". The terms "coupling" and "connection" and their derivatives can be used. It should be understood that these terms can be used to represent that two elements cooperate or interact with each other, regardless of whether they are in direct physical or electrical contact, or they are not in direct contact with each other. Intermediate elements or intermediate layers can be provided between "combining", "attaching" or "connecting" elements. However, "combining", "attaching" or "connecting" elements may also be in direct contact with each other. Similarly, the term "exemplary" is only meant as an example, not the best or optimal.

[0014] The semiconductor dies referred to further below may be of different types, may be manufactured by different technologies, and may include, for example, integrated circuits, optoelectronic or electromechanical circuits, logic integrated circuits, control circuits, etc.

[0015] The packaged semiconductor devices described below may include one or more semiconductor dies. For example, one or more semiconductor power dies may be included. In addition, one or more logic integrated circuits may be included in these devices. The logic integrated circuit may be configured as an integrated circuit for controlling other semiconductor dies, such as an integrated circuit of a power semiconductor die. The logic integrated circuit may be implemented as a logic die.

[0016] Figure 1 A packaged semiconductor device 100 is shown, which includes a semiconductor die 110 , a molding body 120 , a first redistribution layer 130 , and a conductive element 140 .

[0017] The semiconductor die 110 includes a first side 111 and an opposite second side 112. The molded body 120 at least partially encapsulates the semiconductor die 110 and includes a first side 121 and an opposite second side 122. A first redistribution layer 130 is arranged on the first sides 111, 121 of the semiconductor die 110 and the molded body 120. The conductive element 140 is arranged in the molded body 120 beside the semiconductor die 110 and extends from the first redistribution layer 130 to at least a second plane 160 including the second side 112 of the semiconductor die 110.

[0018] The semiconductor die 110 may, for example, include electrical contacts on the first side 111, but not on the second side 112. According to another example, the semiconductor die 110 may include electrical contacts on both the first side 111 and the second side 112. The second side 112 may, for example, be the back side of the semiconductor die 110. The semiconductor die 110 may be a thin die, which means that a backside grinding process is used to reduce the thickness of the semiconductor die 110. The thickness of the semiconductor die 110 measured between the first side 111 and the second side 112 may, for example, be in the range of 50 μm to 800 μm, such as about 100 μm, about 200 μm, or about 500 μm.

[0019] The first redistribution layer 130 may include an insulating material 134 and a plurality of conductive traces 136. The insulating material 134 may, for example, include a laminate material or an oxide layer. The conductive traces 136 may be coupled to electrical contacts of the semiconductor die 110 at the first side 111 of the semiconductor die. At least some of the electrical contacts may be redistributed by the conductive traces 136 to corresponding points outside the periphery of the semiconductor die 110 (a fan-out configuration). The first side 131 of the first redistribution layer facing away from the semiconductor die 110 may be configured with solder balls attached to the ends of the conductive traces 136. The second side 132 of the first redistribution layer 130, the first side 111 of the semiconductor die 110, and the lower ends of the conductive elements 140 may be arranged in a first plane 150.

[0020] The molding body 120 may completely cover the lateral side of the semiconductor die 110 between the first side 111 and the second side 112. According to one example, the first side 111 and / or the second side 112 are not covered by the molding body. The lower side of the molding body 120 may be coplanar with the first side 111 of the semiconductor die 110. The upper side of the molding body 120 may be arranged in the second plane 160.

[0021] The conductive element 140 may have any suitable shape and any suitable lateral dimensions. The conductive element 140 may also be referred to as a "vertical interconnect structure" or a "molded via". The conductive element 140 may include any suitable conductor, such as a metal such as aluminum, copper, or iron, or a metal alloy containing one of these metals. The conductive element 140 may be a single solid, such as a single metal piece such as a lead frame component. According to another example, the conductive element 140 may alternatively include an insulating portion and a conductive trace deposited on the insulating portion, such as a semiconductor wafer portion having a metallization or a plastic or polymer portion having a metallization. The conductive element 140 may be arranged laterally spaced apart at a distance from the semiconductor die 110, such as a distance of 1 mm, 5 mm, or more.

[0022] The conductive element 140, in particular the lower end of the conductive element 140, may be coupled (e.g., by a solder joint or by a conductive glue) to the conductive trace 136 of the first redistribution layer 130 and thereby to the electrical contact of the semiconductor die 110. The conductive element 140 may be configured as a via, in particular a molded via, and may be configured to redirect the electrical contact of the semiconductor die 110 toward the upper side of the packaged semiconductor device 100. In case the packaged semiconductor device 100 includes more than one conductive element 140, each conductive element 140 may be coupled to a different conductive trace 136 and thereby to a different electrical contact of the semiconductor die 110.

[0023] The conductive element 140 can, for example, be configured to act as an electromagnetic shielding structure or a part of a shielding structure for the semiconductor die 110, for example to act as an antenna or a part of an antenna, such as a radar antenna, to act as an RF structure or a part of an RF structure, or to act as a part of a redistribution structure of the packaged semiconductor device 100.

[0024] According to one example, the conductive element 140 is a thin piece, which means that a grinding process is used to reduce the thickness of the conductive element (the thickness is measured perpendicular to the first plane 150 and the second plane 160). The grounding surface of the conductive element 140 can be its upper end arranged in or above the second plane 160.

[0025] According to an example, the packaged semiconductor device 100 may include more than one conductive element 140, such as two, three, four or more conductive elements. Figure 1 As shown, two conductive elements 140 may be arranged on opposite lateral sides of the semiconductor die 110 . Furthermore, the packaged semiconductor device 100 may include more than one semiconductor die 110 , and one or more conductive elements 140 may be arranged next to each semiconductor die 110 .

[0026] Figure 2 Another packaged semiconductor device 200 is shown, which may be similar or identical to the packaged semiconductor device 100 except for the differences described below.

[0027] In the semiconductor device 200, the conductive element 140 extends from the first redistribution layer 130 (i.e., from the first plane 150) to the second plane 160 including the second side 112 of the semiconductor die 110, and further extends to the third plane 210 disposed above the second plane 160. Therefore, in the packaged semiconductor device 200, the thickness of the conductive element 140 is greater than the thickness of the semiconductor die 110.

[0028] Furthermore, in the packaged semiconductor device 200, the conductive element 140 extends laterally from a first point beside the semiconductor die 110 to a second point located above the second side 112 of the semiconductor die 110 and within the perimeter 113 of the semiconductor die 110. In particular, the conductive element 140 may cross the perimeter 113 of the semiconductor die above the second plane 150.

[0029] According to one example, the conductive element 140 includes an inclined portion 141. The inclined portion 141 may be arranged at an angle in the range of 30° to 80°, for example, about 45°, relative to the first side 111 and the second side 112 of the semiconductor die 110. The inclined portion 141 may extend from the first plane 150 to the second plane 160. Figure 2However, it is also possible that the conductive element 140 has a different shape in which the inclined portion 141 extends only over a portion of the distance between the first plane 150 and the second plane 160 .

[0030] The conductive element 140 may further include one or more horizontal portions 142 parallel to the first side 111 and the second side 112 of the semiconductor die 110. For example, the horizontal portions 142 may be arranged at the upper end and the lower end of the conductive element 140. According to one example, only the horizontal portions 142 cross the perimeter 113 of the semiconductor die 110. According to another example, the inclined portion 141 crosses the perimeter and the horizontal portion 142 at the upper end of the conductive element 140 is completely arranged within the perimeter 113 of the semiconductor die 110.

[0031] According to one example, the conductive element 140 includes a horizontal portion 142 at an upper end thereof, and the horizontal portion 142 is exposed from the molded body 120 in the third plane 210 .

[0032] The conductive element 140 may cover only a portion of the surface area of ​​the second side 112 of the semiconductor die 110 , or it may completely cover the surface area of ​​the second side 112 , for example if the conductive element 140 is configured for electromagnetic shielding of the semiconductor die 110 .

[0033] The conductive element 140 including the inclined portion 141 and the horizontal portion 142 may be fabricated, for example, by punching or bending a lead frame.

[0034] Figure 3 A packaged semiconductor device 300 is shown, which may be similar or identical to the semiconductor devices 100 and 200 except for the differences described below.

[0035] In the packaged semiconductor device 300, the conductive element 140 includes an insulating portion 310 and a conductive trace 320 arranged on the insulating portion 310. The conductive trace 320 may be deposited on the insulating portion 310, for example, by plating, spraying, dispensing, vapor deposition, etc. The conductive trace 320 may be produced, for example, using photolithography and / or laser structuring.

[0036] According to one example, the insulating portion 310 includes a "laser-activatable portion" that includes an electrically insulating material such as a ceramic or epoxy resin and an additive, for example, in the form of an organic metal complex. The additive may undergo a physicochemical reaction caused by laser irradiation. The energy of the laser can produce a laser-activated area on the surface of the laser-activatable portion, which includes exposed metal complexes that can serve as seeds for the metal plating process. Those surface areas that are not irradiated by the laser do not contain exposed metal complexes and therefore will not receive metal plating.

[0037] The insulating part 310 may, for example, include a semiconductor material, such as Si, and it may be part of a semiconductor wafer. According to another example, the insulating part 310 may, for example, include plastic or a polymer. In this case, the insulating part 310 may have the same or different material composition as the molded body 120.

[0038] The insulating portion 310 may include a grounding surface 311, wherein a grinding process is used to thin the insulating portion 310. The grinding process may be used to expose the conductive trace 320. The grounding surface 311 may be coplanar with a portion of the conductive trace 320. Figure 2 As depicted, conductive trace 320 may include angled portion 141 and one or more horizontal portions 142 .

[0039] Figure 4 Another packaged semiconductor device 400 is shown, which may be similar or identical to packaged semiconductor devices 100 , 200 , and 300 , except for the differences described below.

[0040] The packaged semiconductor device 400 includes a second redistribution layer 410 opposite to the first redistribution layer 130. In the case where the packaged semiconductor device 400 is similar to the packaged semiconductor device 100, the second redistribution layer 410 may be arranged in the second plane 160 ( Figure 4 In the case where the packaged semiconductor device 400 is similar to the packaged semiconductor devices 200 and 300 , the second redistribution layer 410 may be arranged in the third plane 210 (see Figure 4 ).

[0041] The second redistribution layer 410 may be electrically coupled to the one or more conductive elements 140, for example, by a solder joint or a conductive glue. The second redistribution layer 410 may include the same material or material composition as the first redistribution layer 130. However, the first redistribution layer 130 and the second redistribution layer 410 may also include different materials or material compositions. The first and / or second redistribution layers 130, 410 may each include a single layer or a multi-layer structure.

[0042] The second redistribution layer 410 may, for example, be configured to allow stacking of semiconductor devices, i.e., another semiconductor device may be arranged on top of the second redistribution layer 410 and electrically connected to the second redistribution layer 410, for example, via solder balls ("package stacking"). It is also possible that any other suitable electrical components, such as capacitors or resistors, are arranged on the second redistribution layer 410 and coupled to the second redistribution layer 410.

[0043] Since the second redistribution layer 410 covers the back side of the packaged semiconductor device 400 , the conductive element 140 does not need to be exposed to the outside at the back side of the packaged semiconductor device 400 .

[0044] FIG. 5A to FIG. 5G The packaged semiconductor device 200 is shown at various stages of fabrication according to an exemplary method for fabricating a packaged semiconductor device. Similar methods may be used to fabricate the packaged semiconductor devices 100, 300, and 400.

[0045] Figure 5A A plurality of semiconductor dies 110 are shown arranged on a carrier, such as a temporary carrier 510. The plurality of semiconductor dies 110 may, for example, be arranged in a matrix or array form. The temporary carrier 510 may, for example, include an adhesive tape. The semiconductor dies 110 are arranged at a predetermined distance relative to each other so that at least one conductive element 140 may be placed next to each semiconductor die 110. Arranging the plurality of semiconductor dies 110 on the temporary carrier 510 may include using a pick-and-place process.

[0046] like Figure 5B As shown, a plurality of conductive elements 140 are arranged on a temporary carrier 510 next to the semiconductor die 110. When the conductive elements 140 are arranged on the temporary carrier 510, they may all be part of a common substrate 520. In other words, arranging the plurality of conductive elements 140 on the temporary carrier 510 may include providing a single common substrate 520 and placing the single common substrate 520 on the temporary carrier 510. The common substrate 520 may, for example, include a panel, a metal component, in particular a lead frame, a semiconductor wafer or a plastic or polymer body.

[0047] As described above, the advantage of using a common substrate 520 to provide multiple conductive elements 140 is that a parallel process is used instead of a serial pick-and-place process. This can reduce the manufacturing time and manufacturing cost of the packaged semiconductor device.

[0048] like Figure 5CAs shown, a singulation process may be used to singulate individual conductive elements 140 from a common substrate 520. The singulation process may require cutting through the common substrate 520 or grinding the common substrate 520 to singulate the individual conductive elements 140. After singulation, the conductive elements 140 may be held in place, for example, by tape of a temporary carrier 510.

[0049] refer to Figure 5C The described singulation process is not mandatory. The conductive element 140 can also be singulated at a later stage of production. For example, the following reference Fig. 5F The grinding process described further above is used to singulate the conductive elements 140. In particular, this can be done in the case where the common substrate 510 is a semiconductor wafer or a plastic or polymer body. However, in the case where the common substrate 510 is a metal component such as a lead frame, it may be necessary to perform the grinding process described in reference to FIG. Figure 5C A dedicated singulation process is described.

[0050] like Figure 5D As shown, a molding process may be used to make the molded body 120. The plurality of semiconductor dies 110 and the plurality of conductive elements 140 may be partially or completely encapsulated. Figure 5C In the case of a singulation process, the common substrate 520 still exists and can be fully or partially encapsulated. The conductive elements 140 and / or the rest of the common substrate 520 may include openings for allowing the molding material to flow through to produce a molded body 120 without voids.

[0051] The molding material may completely cover the semiconductor die 110 and / or the conductive element 140. After the molding process, the molding material may be cured, for example, by a heating process. Before thinning, the molded body 120 may have a greater thickness than the conductive element 140, and the initial second side 122' of the molded body 120 may be arranged above the third plane 210. After the molding process, the molding material may also not extend to a plane above the third plane 210. For example, a film-assisted molding process may be used, in which the conductive element 140 is covered by a film in the third plane, and the film is removed after curing the molding material, thereby exposing the conductive element 140 in the third plane 210.

[0052] Figure 5D The structure including the semiconductor die 110 , the conductive element 140 , and the molded body 120 shown in FIG. 1 may be referred to as a “reconstructed wafer” or a “reconstructed panel”.

[0053] like Figure 5E As shown, the reconstituted wafer or panel is removed from the temporary carrier 510 and the first redistribution layer 130 is fabricated using any suitable technique. This may, for example, include providing an insulating material, drilling through holes in the insulating material, depositing a conductive material, and structuring the conductive material to form conductive traces.

[0054] like Fig. 5F As shown, a thinning process is used to expose the conductive elements 140 at the second side 122 of the molded body 120. The thinning process may, for example, include grinding the molded body at the initial second side 122' and / or grinding the common substrate 520. As described above, the thinning process may also be used to singulate the individual conductive elements 140 from the common substrate 520. In other words, the singulation of the conductive elements 140 and the exposure of the conductive elements 140 from the molded body 120 may be accomplished by a single common processing step.

[0055] After the thinning process, further processing steps may be performed, for example, a cleaning process may be performed to remove grinding waste, a second redistribution layer 410 may be formed on the second side 122 of the molded body 120 , and so on.

[0056] like Figure 5G As shown, the individual packaged semiconductor devices 200 can be singulated from the reconstituted wafer or reconstituted panel by cutting along scribe lines 530. According to one example, the conductive elements 140 are still part of the common substrate 520 at this stage and are singulated from the common substrate 520 by cutting through the common substrate 520 along scribe lines 530.

[0057] Figure 6 is a flow chart of a method 600 for fabricating a packaged semiconductor device. The method 600 may be used, for example, to fabricate the packaged semiconductor devices 100, 200, 300, and 400.

[0058] Method 600 includes: in step 601, an operation of providing a plurality of semiconductor dies, wherein the semiconductor dies are arranged in an array on a carrier such that a first side of the semiconductor dies faces the carrier and an empty space is arranged next to each semiconductor die; in step 602, an operation of arranging a substrate including a plurality of conductive elements on top of the plurality of semiconductor dies such that the conductive elements are arranged in corresponding empty spaces next to each semiconductor die; in step 603, an operation of molding on top of the plurality of semiconductor dies to form a molded body; and in step 604, an operation of singulating the packaged semiconductor device from the molded body by cutting through the molded body.

[0059] Method 600 may include an optional operation of molding over the substrate and thinning the molded body to expose the conductive element on a second side of the molded body, the second side facing away from the carrier. Method 600 may include an optional operation of forming a first redistribution layer on the first side of the semiconductor die and the first side of the molded body, the first redistribution layer being electrically coupled to the conductive element. Method 600 may also include an optional operation of forming a structured conductive layer on the second side of the molded body, the second side of the molded body facing away from the carrier, and the structured conductive layer being electrically coupled to the conductive element. The structured conductive layer may, for example, include a second redistribution layer, an electromagnetic shielding structure, or an antenna.

[0060] Example

[0061] Hereinafter, a packaged semiconductor device and a method for fabricating a packaged semiconductor device will be further described using specific examples.

[0062] Example 1 is a method for making a packaged semiconductor device, the method comprising: providing a plurality of semiconductor dies, the semiconductor dies being arranged in an array on a carrier so that a first side of the semiconductor dies faces the carrier and an empty space is arranged beside each semiconductor die; arranging a substrate including a plurality of conductive elements over the plurality of semiconductor dies so that the conductive elements are arranged in corresponding empty spaces beside each semiconductor die; molding over the plurality of semiconductor dies to form a molded body; and singulating the packaged semiconductor device from the molded body by cutting through the molded body.

[0063] Example 2 is the method of Example 1, wherein each conductive element extends from a first plane including a first side of the semiconductor die to a second plane including a second side of the semiconductor die opposite the first side.

[0064] Example 3 is the method of Example 1 or 2, further comprising molding over the substrate, and thinning the molded body to expose the conductive element on a second side of the molded body, the second side facing away from the carrier.

[0065] Example 4 is the method according to Example 1 or 2, further comprising: covering the substrate with a film, and molding over the film-covered substrate.

[0066] Example 5 is a method according to any of the preceding examples, wherein the substrate is a lead frame.

[0067] Example 6 is a method according to any of the preceding examples, wherein the substrate comprises a metallized polymer or semiconductor wafer.

[0068] Example 7 is a method according to any of the preceding examples, further comprising forming a first redistribution layer on the first side of the semiconductor die and the first side of the molding body, the first redistribution layer being electrically coupled to the conductive element.

[0069] Example 8 is the method according to any of the preceding examples, further comprising forming a structured electrically conductive layer on a second side of the molded body, the second side of the molded body facing away from the carrier, and the structured electrically conductive layer is electrically coupled to the conductive element.

[0070] Example 9 is the method of Example 8, wherein the structured conductive layer comprises a second redistribution layer, an electromagnetic shielding structure, or an antenna.

[0071] Example 10 is a packaged semiconductor device comprising: a semiconductor die including a first side and an opposite second side; a molded body encapsulating the semiconductor die and including a first side and an opposite second side; a first redistribution layer arranged on the first side of the semiconductor die and the first side of the molded body; and a conductive element arranged in the molded body next to the side of the semiconductor die, wherein the conductive element extends from the first redistribution layer at least to a plane including the second side of the semiconductor die.

[0072] Example 11 is a packaged semiconductor device according to Example 10, wherein the conductive element is a lead frame portion, a metal-plated polymer portion, or a metal-plated semiconductor die.

[0073] Example 12 is a packaged semiconductor device according to example 10 or 11, wherein the conductive element extends from a first point beside the side of the semiconductor die to a second point located above a second side of the semiconductor die and within a perimeter of the semiconductor die.

[0074] Example 13 is a packaged semiconductor device according to any of Examples 10-12, wherein the conductive element includes a sloped portion.

[0075] Example 14 is the packaged semiconductor device according to Example 13, wherein the inclined portion has an angle in a range of 30° to 80° with respect to the first side and the second side of the semiconductor die.

[0076] Example 15 is a packaged semiconductor device according to any of Examples 10-14, wherein the conductive element is exposed from the molded body at the second side of the molded body.

[0077] Example 16 is a packaged semiconductor device according to any of Examples 10-15, wherein the conductive element forms or is part of an antenna or an electromagnetic shielding structure.

[0078] Example 17 is a packaged semiconductor device according to any of Examples 10-16, further comprising: a second redistribution layer disposed on the second side of the molding body, the second redistribution layer being electrically coupled to the conductive element.

[0079] Example 18 is an apparatus comprising means for performing the method according to any of Examples 1-9.

[0080] Although the present disclosure has been shown and described in conjunction with one or more embodiments, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the above-described components or structures (assemblies, devices, circuits, systems, etc.), unless otherwise specified, the terms used to describe such components (including references to "devices") are intended to correspond to any component or structure (e.g., functionally equivalent) that performs the specified function of the described component, even if structurally not equivalent to the disclosed structure that performs that function in the exemplary embodiments shown herein of the present disclosure.

Claims

1. A method for making a packaged semiconductor device, the method comprising: providing a plurality of semiconductor dies arranged in an array on a carrier such that a first side of the semiconductor dies faces the carrier and an opposite second side of the semiconductor dies faces away from the carrier, and such that an empty space is arranged beside each semiconductor die, disposing a substrate including a plurality of conductive elements over and beside the plurality of semiconductor dies such that the conductive elements are arranged in corresponding empty spaces beside each semiconductor die, molding over the plurality of semiconductor dies to form a molded body, and singulating the packaged semiconductor components from the molded body by cutting through the molded body, wherein each conductive element extends from a first point beside the corresponding semiconductor die side to a second point located above the second side of the corresponding semiconductor die and within the perimeter of the corresponding semiconductor die; wherein the molded body extends directly between the second side of the semiconductor die and the conductive element; wherein the conductive element covers only a portion of the surface area of ​​the second side of the semiconductor die; and The conductive element is exposed from the molded body at a second point on the second side of the molded body.

2. The method according to claim 1, wherein: Each conductive element extends from a first plane including the first side of the semiconductor die to a second plane including the second side of the semiconductor die.

3. The method according to claim 1 or 2, wherein: The method further comprises: molded over the substrate, and The molded body is thinned to expose the conductive element on a second side of the molded body, the second side facing away from the carrier.

4. The method according to claim 1 or 2, wherein: The method further comprises: covering the substrate with a film, and Molded over the substrate covering the film.

5. The method according to claim 1 or 2, wherein: The substrate is a lead frame.

6. The method according to claim 1 or 2, wherein: The substrate includes a metallized polymer or a semiconductor wafer.

7. The method according to claim 1 or 2, wherein: The method further comprises: A first redistribution layer is formed on a first side of the semiconductor die and a first side of the molding body, the first redistribution layer being electrically coupled to the conductive element.

8. The method according to claim 1 or 2, wherein: The method further comprises: A structured electrically conductive layer is formed on a second side of the molded body, which second side faces away from the carrier, the structured electrically conductive layer being electrically coupled to the electrically conductive element.

9. The method according to claim 8, wherein: The structured conductive layer includes a second redistribution layer, an electromagnetic shielding structure or an antenna.

10. A packaged semiconductor device comprising: a semiconductor die comprising a first side and an opposite second side, a molded body encapsulating the semiconductor die and comprising a first side and an opposite second side, a first redistribution layer arranged on a first side of the semiconductor die and a first side of the molding body, and an electrically conductive element which is arranged in the molded body laterally beside the semiconductor die, wherein the conductive element extends from the first redistribution layer to at least a plane above the second side of the semiconductor die; wherein the conductive element further extends from a first point beside the side of the semiconductor die to a second point above a second side of the semiconductor die and within a perimeter of the semiconductor die; wherein the conductive element is electrically coupled to the first redistribution layer and electrically coupled to a contact of the semiconductor die via the first redistribution layer; wherein the molded body extends directly between the second side of the semiconductor die and the conductive element; wherein the conductive element covers only a portion of the surface area of ​​the second side of the semiconductor die; and The conductive element is exposed from the molded body at a second point on the second side of the molded body.

11. The packaged semiconductor device according to claim 10, wherein: The conductive element is a lead frame portion, a metallized polymer portion, or a metallized semiconductor die.

12. The packaged semiconductor device according to any one of claims 10 to 11, wherein: The conductive element includes an inclined portion.

13. The packaged semiconductor device according to claim 12, wherein: The inclined portion has an angle in the range of 30° to 80° with respect to the first side and the second side of the semiconductor die.

14. The packaged semiconductor device according to any one of claims 10 to 11 and 13, wherein: The conductive element forms or is part of an antenna or an electromagnetic shielding structure.

15. The packaged semiconductor device according to any one of claims 10 to 11 and 13, wherein: The packaged semiconductor device further comprises: A second redistribution layer is arranged on the second side of the molded body, the second redistribution layer being electrically coupled to the conductive element.

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