Defect detection structure and method for detecting defects in semiconductor dies

Abstract

A semiconductor device includes: a semiconductor die, a defect detection structure, and an input / output circuit. The semiconductor die includes: a central region and a peripheral region surrounding the central region. The peripheral region includes a lower left region, an upper left region, an upper right region, and a lower right region. The defect detection structure is formed in the peripheral region. The defect detection structure includes: a first conductive loop passing through the lower left region, a second conductive loop passing through the lower right region, a third conductive loop passing through the lower left region and the upper left region, a fourth conductive loop passing through the lower right region and the upper right region, and a shielding loop for shielding electrical interference between the first conductive loop to the fourth conductive loop. The input / output circuit is electrically connected to end nodes of the first conductive loop, the second conductive loop, the third conductive loop, and the fourth conductive loop.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2020 - 0040758, filed with the Korean Intellectual Property Office (KIPO) on April 3, 2020, the disclosure of which is hereby incorporated by reference in its entirety. Technical field

[0003] Example embodiments generally relate to semiconductor integrated circuits, and more particularly, to semiconductor integrated circuits having a structure that supports detection of defects therein and methods for operating such a structure. Background art

[0004] Generally, integrated circuits are manufactured by forming repetitive patterns in wafers of semiconductor material. The wafers can be diced or cut into a plurality of semiconductor die, and the individual semiconductor die can be packaged into semiconductor chips. During the dicing and packaging processes, cracks may occur in the semiconductor die. To reduce the yield of defective products, semiconductors are inspected to detect cracks. Summary of the invention

[0005] Some example embodiments may provide a defect detection structure for a semiconductor die and a semiconductor device including the defect detection structure to enhance the detection ability for various types of crack intrusion and other defects.

[0006] Some example embodiments may provide a method for detecting defects in a semiconductor die to enhance the detection ability for various types of crack intrusion.

[0007] According to an example embodiment, a semiconductor device includes: a semiconductor die, a defect detection structure, and an input / output circuit. The semiconductor die includes: a central region forming a semiconductor integrated circuit and a peripheral region surrounding the central region. The peripheral region includes: a lower - left region, an upper - left region, an upper - right region, and a lower - right region. The defect detection structure is formed in the peripheral region. The defect detection structure includes: a first conductive loop passing through the lower - left region, a second conductive loop passing through the lower - right region, a third conductive loop passing through the lower - left region and the upper - left region, and a fourth conductive loop passing through the lower - right region and the upper - right region. A shielding loop is also provided for at least partially shielding electrical interference between the first conductive loop to the fourth conductive loop. The input / output circuit is electrically connected to corresponding end nodes of the first conductive loop, the second conductive loop, the third conductive loop, and the fourth conductive loop.

[0008] According to an example embodiment, a defect detection structure is formed in a peripheral region of a semiconductor die, the peripheral region of the semiconductor die surrounding a central region of the semiconductor die in which a semiconductor integrated circuit is formed, the defect detection structure including: a first conductive loop passing through a lower left corner region of the peripheral region, a second conductive loop passing through a lower right corner region of the peripheral region, a third conductive loop passing through the lower left corner region and an upper left corner region of the peripheral region, and a fourth conductive loop passing through the lower right corner region and an upper right corner region of the peripheral region. A shielding loop is advantageously provided for at least partially shielding electrical interference between the first conductive loop to the fourth conductive loop.

[0009] According to an example embodiment, a method of detecting a defect in a semiconductor die including a central region and a peripheral region, a semiconductor integrated circuit being formed in the central region and the peripheral region surrounding the central region. The peripheral region includes: a lower left corner region, an upper left corner region, an upper right corner region, and a lower right corner region. A defect detection structure is also provided in the peripheral region. The defect detection structure includes: a first conductive loop passing through the lower left corner region, a second conductive loop passing through the lower right corner region, a third conductive loop passing through the lower left corner region and the upper left corner region, a fourth conductive loop passing through the lower right corner region and the upper right corner region, and a shielding loop for at least partially shielding electrical interference between the first conductive loop to the fourth conductive loop. The method includes: applying a test input signal to an input terminal node of the defect detection structure; receiving first to fourth test output signals from first to fourth output terminal nodes of the first conductive loop to the fourth conductive loop; and determining the presence and location of a defect in the semiconductor die based on the test input signal and the first to fourth test output signals.

[0010] The defect detection structure, semiconductor device, and associated method according to an example embodiment can use a plurality of conductive loops and a shielding loop formed in a peripheral region to accurately detect various types of crack intrusions, where the peripheral region surrounds a central region in which a semiconductor integrated circuit is formed. The defect detection structure, semiconductor device, and associated method according to an example embodiment can improve the detection ability of cracks and some other defects in a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The example embodiments of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0012] Figure 1 is a top view showing a layout of a semiconductor device according to an example embodiment.

[0013] Figure 2A 、 Figure 2B and Figure 2C is a diagram showing a conductive circuit included in a defect detection structure according to an exemplary embodiment.

[0014] Figure 3 is a diagram showing a semiconductor device according to an exemplary embodiment.

[0015] Figure 4 is a perspective view showing a defect detection structure according to an exemplary embodiment.

[0016] Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D is showing Figure 4 a top view of the layout of the conductive layer of the defect detection structure.

[0017] Fig. 6A and Figure 6B is showing Figure 4 a cross-sectional view of the vertical structure of the defect detection structure.

[0018] Fig. 7A and Figure 7B is a cross-sectional view showing a semiconductor device including a defect detection structure according to an exemplary embodiment and including Figure 4 .

[0019] Fig. 8A and Figure 8B is a perspective view showing a defect detection structure according to an exemplary embodiment.

[0020] Fig.9A 、 Fig. 9B 、 Fig. 9C and Fig.9D is a cross-sectional view of the vertical structure of the defect detection structure according to an exemplary embodiment.

[0021] Fig. 10A 、 Fig. 10B and Fig. 10C is a diagram showing the electrical noise shielding effect of a defect detection structure according to an exemplary embodiment.

[0022] Fig.11 is a diagram showing a semiconductor device according to an exemplary embodiment.

[0023] Fig.12 is a perspective view showing a defect detection structure according to an exemplary embodiment.

[0024] Fig.13A and Fig. 13B is showing Fig.12 a cross-sectional view of the vertical structure of the defect detection structure.

[0025] Fig.14is a flowchart showing a method of detecting a defect in a semiconductor die according to an exemplary embodiment.

[0026] Fig.15 is a block diagram showing a test system according to an exemplary embodiment.

[0027] Fig.16 is a circuit diagram showing an input / output circuit included in a semiconductor die according to an exemplary embodiment.

[0028] Fig.17 is showing Fig.16 a timing diagram of test signals for the input / output circuit.

[0029] Fig.18 is a circuit diagram showing an input / output circuit included in a semiconductor die according to an exemplary embodiment.

[0030] Fig.19 is showing Fig.18 a timing diagram of test signals for the input / output circuit.

[0031] Fig. 20 and Fig.21 are diagrams for describing defect detection in a semiconductor device according to an exemplary embodiment.

[0032] Fig. 22 is a diagram showing a semiconductor device according to an exemplary embodiment.

[0033] Fig.23 and Fig.24 is a perspective view showing a defect detection structure according to an exemplary embodiment.

[0034] Fig.25 is a block diagram showing a memory cell array included in a NAND flash memory device, where the NAND flash memory device may be integrated in a semiconductor device.

[0035] Fig.26 is showing Fig.25 an equivalent circuit diagram of a memory block in the memory cell array.

[0036] Fig. 27 is a block diagram showing a mobile system according to an exemplary embodiment. DETAILED DESCRIPTION

[0037] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, in which some exemplary embodiments are shown. In the drawings, like reference numerals always denote like elements. Repeated descriptions may be omitted.

[0038] Figure 1 is a top view showing a layout of a semiconductor device according to an exemplary embodiment. Refer to Figure 1, the semiconductor device 100 includes at least one semiconductor die SD. The semiconductor die SD includes: a central region CREG and a peripheral region PREG surrounding the central region CREG. Various semiconductor integrated circuits can be formed in the central region CREG according to the type or kind of the semiconductor device 100. For example, the semiconductor device 100 can be a semiconductor memory device and / or a memory integrated circuit as shown in Fig.25 and Fig.26 , and can be formed in the central region CREG of the semiconductor die SD.

[0039] A defect detection structure CDST according to an example embodiment for detecting defects such as cracks can be formed in the peripheral region PREG. The defect detection structure CDST can be formed in a plurality of conductive layers, and can be formed as an annular three-dimensional structure in the peripheral region PREG to surround the central region CREG, and the plurality of conductive layers are arranged in the vertical direction Z perpendicular to the row direction and the column direction.

[0040] In some example embodiments, the semiconductor device 100 can include a single semiconductor die. In this case, as shown in Fig. 7A and Figure 7B , the defect detection structure CDST can be formed using the conductive layers in a single semiconductor die. In some other example embodiments, the semiconductor device 100 can include a plurality of semiconductor dies. In this case, the defect detection structure CDST can be formed using the conductive layers distributed in the plurality of semiconductor dies.

[0041] As will be described below, the defect detection structure CDST can include a first conductive loop, a second conductive loop, a third conductive loop, a fourth conductive loop, and a shielding loop. The first conductive loop passes through the lower left corner region CLB of the peripheral region PREG. The second conductive loop passes through the lower right corner region CRB of the peripheral region PREG. The third conductive loop passes through the lower left corner region CLB and the upper left corner region CLU of the peripheral region PREG. The fourth conductive loop passes through the lower right corner region CRB and the upper right corner region CRU of the peripheral region PREG.

[0042] The shielding loop can shield the electrical interference between the first conductive loop to the fourth conductive loop. Electrical interference refers to the phenomenon that the voltage or signal on one wire affects the voltage or signal on another wire due to the parasitic capacitance and / or parasitic inductance between the wires. Electrical interference can include the effects caused by the capacitive coupling and / or inductive coupling between the wires.

[0043] The defect detection structure CDST and the semiconductor device 100 including the defect detection structure CDST according to example embodiments may accurately detect various types of crack intrusion using a plurality of conductive loops and shielding loops formed in a peripheral region PREG surrounding a central region CREG where a semiconductor integrated circuit is formed.

[0044] In the following, for the convenience of illustration and description, an orthogonal set of an X-axis, a Y-axis, and a Z-axis is used to describe the exemplary embodiment. The X-axis, the Y-axis, and the Z-axis are used for three perpendicular directions along three directions, and are not limited to specific directions. The X-direction corresponds to a first horizontal direction or a row direction, the Y-direction corresponds to a second horizontal direction or a column direction, and the Z-direction corresponds to a vertical direction. If no additional description is involved, the Z-direction indicates a vertical direction perpendicular to the conductive layer.

[0045] The portion of the peripheral area PREG between the lower left area CLB and the lower right area CRB may be referred to as an end node area ENR. The portion of the peripheral area PREG between the lower left area CLB and the upper left area CLU may be referred to as a first edge area ERG1, the portion of the peripheral area PREG between the lower right area CRB and the upper right area CRU may be referred to as a second edge area ERG2, and the portion of the peripheral area PREG between the upper left area CLU and the upper right area CRU may be referred to as a third edge area ERG3.

[0046] In the present disclosure, "up", "down", "left" and "right" are not used to indicate specific fixed positions, but to indicate relative positions. Therefore, with respect to the defect detection structure CDST disclosed herein, example embodiments may include a bilaterally symmetrical structure, an up-and-down symmetrical structure, a rotational structure, etc.

[0047] Figure 2A , Figure 2B and Figure 2C is a diagram illustrating a conductive loop included in a defect detection structure according to example embodiments. Figure 2A A first conductive loop LP1 and a second conductive loop LP2 are shown, and Figure 2B A third conductive loop LP3 and a fourth conductive loop LP4 are shown. Figure 2C A shielding loop SLP is shown.

[0048] refer to Figure 2A, the first conductive loop LP1 passes through the lower left corner region CLB, and the second conductive loop LP2 passes through the lower right corner region CRB. The first conductive loop LP1 extends along the peripheral region PREG from the input terminal node ENI in the end node region ENR between the lower left corner region CLB and the lower right corner region CRB through the lower left corner region CLB to the first edge region ERG1 between the lower left corner region CLB and the upper left corner region CLU, and returns from the first edge region ERG1 to the first output terminal node ENO1 in the end node region ENR. In contrast, the second conductive loop LP2 extends along the peripheral region PREG from the input terminal node ENI through the lower right corner region CRB to the second edge region ERG2 between the lower right corner region CRB and the upper right corner region CRU, and returns from the second edge region ERG2 to the second output terminal node ENO2 in the end node region ENR.

[0049] Reference Figure 2B , the third conductive loop LP3 passes through the lower left corner region CLB and the upper left corner region CLU, and the fourth conductive loop LP4 passes through the lower right corner region CRB and the upper right corner region CRU. The third conductive loop LP3 extends along the peripheral region PREG from the input terminal node ENI through the lower left corner region CLB and the upper left corner region CLU to the third edge region ERG3 between the upper left corner region CLU and the upper right corner region CRU, and returns from the third edge region ERG3 to the third output terminal node ENO3 in the end node region ENR. In contrast, the fourth conductive loop LP4 passes through the lower right corner region CRB and the upper right corner region CRU, extends along the peripheral region PREG from the input terminal node ENI to the third edge region ERG3, and returns from the third edge region ERG3 to the fourth output terminal node ENO4 in the end node region ENR. Therefore, some or all of the terminal nodes of the first to fourth conductive loops LP1 - LP4, that is, some or all of the input terminal node ENI and the first to fourth output terminal nodes ENO1 - ENO4, can be located in the end node region ENR. In addition, the first to fourth conductive loops LP1 - LP4 can be electrically connected through the common input terminal node ENI.

[0050] Reference Figure 2C , the annular shielding loop SLP can extend along the peripheral region PREG by passing through the lower left corner region CLB, the upper left corner region CLU, the lower right corner region CRB, and the upper right corner region CRU. In some example embodiments, as Figure 2C shown, the shielding loop SLP can be separated / cut in the third edge region ERG3 such that the shielding loop SLP operates as an open circuit. In some example embodiments, the shielding loop SLP can be cut into a plurality of electrically disconnected loop segments. In some example embodiments, as Fig.24 As shown, the shielding loop SLP can be a closed loop.

[0051] During a test operation for detecting a defect in a semiconductor device, a constant bias voltage VB can be applied to the shielding loop SLP. As shown, the bias voltage VB can be a ground voltage, but the exemplary embodiments are not limited thereto.

[0052] In some exemplary embodiments, as Figure 2C shown, the bias voltage VB can be applied through a plurality of bias nodes SN1 to SN5 on the shielding loop SLP. When the shielding loop SLP includes a plurality of electrically disconnected loop segments, each loop segment can include at least one bias node to which the bias voltage VB is applied. The number and position of the bias nodes can be determined in consideration of the positions of the respective expected cracks, the resistive voltage drop of the shielding loop SLP, and the like.

[0053] Figure 3 is a diagram showing a semiconductor device according to an exemplary embodiment. Referring to Figure 3 , the semiconductor device 101 can include: an annular defect detection structure formed in a peripheral region PREG of a semiconductor die and an input / output circuit IOC 200. The defect detection structure can include a first conductive loop LP1, a second conductive loop LP2, a third conductive loop LP3, a fourth conductive loop LP4, and a shielding loop SLP. The first conductive loop LP1 passes through the lower left corner region CLB, the second conductive loop LP2 passes through the lower right corner region CRB, the third conductive loop LP3 passes through the lower left corner region CLB and the upper left corner region CLU, and the fourth conductive loop LP4 passes through the lower right corner region CRB and the upper right corner region CRU. The shielding loop SLP shields the electrical interference LP1 to LP4 between the first conductive loop to the fourth conductive loop.

[0054] End nodes ENI and ENO1 to ENO4 of the first conductive loop to the fourth conductive loop LP1 to LP4 can be electrically connected to the input / output circuit 200 via input / output leads LIO. The input / output leads LIO can be formed at different positions according to the input / output circuit 200 and the positions of the end nodes ENI and ENO1 to ENO4. Exemplary embodiments of the input / output circuit 200 will be described below with reference to Fig.16 and Fig.18 description of the exemplary embodiments of the input / output circuit 200.

[0055] As Figure 3As shown, the horizontal line of the first conductive loop LP1 extending from the input terminal node ENI to the first edge region ERG1 may partially overlap with the horizontal line of the third conductive loop LP3 extending from the input terminal node ENI to the third edge region ERG3, and the horizontal line of the second conductive loop LP2 extending from the input terminal node ENI to the second edge region ERG2 may partially overlap with the horizontal line of the fourth conductive loop LP4 extending from the input terminal node ENI to the third edge region ERG3.

[0056] For ease of explanation, the shielding loop SLP is represented by a dashed line in Figure 3 As will be described below, the first part of the shielding loop SLP may be disposed at a position for shielding the electrical interference between the horizontal lines of the first conductive loop LP1 and the third conductive loop LP3, and the second part of the shielding loop SLP may be disposed at a position for shielding the electrical interference between the horizontal lines of the second conductive loop LP2 and the fourth conductive loop LP4.

[0057] Hereinafter, an exemplary embodiment of a defect detection structure included in the semiconductor device 101 to be described below with reference to Figures 4 to 9D will be described. Specifically, Figure 3 FIG. Figure 4 shows a perspective view of a defect detection structure according to an exemplary embodiment, while Figure 5A , Figure 5B , Figure 5C and Figure 5D are top views showing the layout of the conductive layers of the defect detection structure of Figure 4 , and Fig. 6A and Figure 6B are cross-sectional views showing the vertical structure of the defect detection structure of Figure 4 .

[0058] Figure 5A shows the layout of the first conductive layer CL1, Figure 5B shows the layout of the second conductive layer CL2, Figure 5C shows the layout of the fourth conductive layer CL4, and Figure 5D shows the layout of the third conductive layer CL3. Fig. 6A shows a cross-sectional view along line A-A' of Figure 1 , and Figure 6B shows a cross-sectional view along line B-B' of Figure 1 .

[0059] Referring to Figures 4 to 6B , the defect detection structure 10 may include a first horizontal line HL1, a second horizontal line HL2, a third horizontal line HL3, a fourth horizontal line HL4, a fifth horizontal line HL5, a sixth horizontal line HL6, a first vertical line VL1, a second vertical line VL2, a third vertical line VL3, and / or a fourth vertical line VL4.

[0060] A first horizontal line HL1 is formed in the first conductive layer CL1. The annular first horizontal line HL1 extends along the peripheral region PREG by passing through the lower left corner region CLB, the upper left corner region CLU, the upper right corner region CRU, and the lower right corner region CRB. The first horizontal line HL1 is cut in the third edge region ERG3 located between the upper left corner region CLU and the upper right corner region CRU. Similarly, a second horizontal line HL2 is formed in the second conductive layer CL2. The second horizontal line HL2 extends from the first output end node ENO1 in the end node region ENR located between the lower left corner region CLB and the lower right corner region CRB through the lower left corner region CLB to the first edge region ERG1 between the lower left corner region CLB and the upper left corner region CLU. Additionally, a third horizontal line HL3 is also formed in the second conductive layer CL2. The third horizontal line HL3 extends from the second output end node ENO2 in the end node region ENR through the lower right corner region CRB to the second edge region ERG2 between the lower right corner region CRB and the upper right corner region CRU.

[0061] A fourth horizontal line HL4 is formed in the fourth conductive layer CL4. The fourth horizontal line HL4 extends from the third output end node ENO3 in the end node region ENR through the lower left corner region CLB and the upper left corner region CLU to the third edge region ERG3. A fifth horizontal line HL5 is also formed in the fourth conductive layer CL4. The fifth horizontal line HL5 extends from the fourth output end node ENO4 in the end node region ENR through the lower right corner region CRB and the upper right corner region CRU to the third edge region ERG3. Finally, a sixth horizontal line HL6 is formed in the third conductive layer CL3. The annular sixth horizontal line HL6 extends along the peripheral region PREG by passing through the lower left corner region CLB, the upper left corner region CLU, the upper right corner region CRU, and the lower right corner region CRB. The sixth horizontal line HL6 is in the third edge region ERG3.

[0062] The first vertical line VL1 connects the first horizontal line HL1 and the second horizontal line HL2 in the first edge region ERG1, and the second vertical line VL2 connects the first horizontal line HL1 and the third horizontal line HL3 in the second edge region ERG2. The third vertical line VL3 connects the first horizontal line HL1 and the fourth horizontal line HL4 in the third edge region ERG3, and the fourth vertical line VL4 connects the first horizontal line HL1 and the fifth horizontal line HL5 in the third edge region ERG3.

[0063] Figure 3 The first conductive loop LP1 in includes: a part of the first horizontal line HL1, the first vertical line VL1, and the second horizontal line HL2. Figure 3The second conductive loop LP2 therein includes: a part of the first horizontal line HL1, the second vertical line VL2, and the third horizontal line HL3. Figure 3 The third conductive loop LP3 therein includes: a part of the first horizontal line HL1, the third vertical line VL3, and the fourth horizontal line HL4. Figure 3 The fourth conductive loop LP4 therein includes: a part of the first horizontal line HL1, the fourth vertical line VL4, and the fifth horizontal line HL5. Figure 3 The shielding loop SLP therein includes the sixth horizontal line HL6. During a test operation for detecting defects of a semiconductor device, a constant bias voltage VB can be applied to the shielding loop SLP.

[0064] Therefore, the first conductive loop LP1 and the second conductive loop LP2 can be formed using the first conductive layer CL1 and the second conductive layer CL2, the shielding loop SLP can be formed using the third conductive layer CL3 and the third conductive loop LP3, and the fourth conductive loop LP4 can be formed using the first conductive layer CL1 and the fourth conductive layer CL4.

[0065] The first part of the shielding loop SLP can be disposed at a position for shielding electrical interference between the horizontal line of the first conductive loop LP1 and the horizontal line of the third conductive loop LP3. As Figure 4 and Fig. 6A shown, the left half of the sixth horizontal line HL6 corresponding to the shielding loop SLP can be arranged to overlap with the second horizontal line HL2 and the fourth horizontal line HL4 in the vertical direction Z.

[0066] The second part of the shielding loop SLP can be disposed at a position for shielding electrical interference between the horizontal line of the second conductive loop LP2 and the horizontal line of the fourth conductive loop LP4. As Figure 4 and Figure 6B shown, the right half of the sixth horizontal line HL6 corresponding to the shielding loop SLP can be arranged to overlap with the third horizontal line HL3 and the fifth horizontal line HL5 in the vertical direction Z.

[0067] Fig. 7A and Figure 7B are cross-sectional views of a semiconductor device showing a defect detection structure including Figure 4 therein. Fig. 7A and Figure 7B show cross-sectional views along the line A - A' in Figure 1 therein. Although not shown, the cross-sectional view along the line B - B' in Figure 1 is symmetric with respect to the cross-sectional views in Fig. 7A and Figure 7B respectively on both sides. Descriptions that are repetitive with Figures 1 to 6B will be omitted.

[0068] Refer to Fig. 7A , a conductive layer can be used on a bottom semiconductor substrate SUB (in which an active circuit system is embedded) to form a defect detection structure. The first conductive layer CL1 can correspond to a polysilicon layer PL, the second conductive layer CL2 can correspond to a first metal layer ML1 above the polysilicon layer PL, the third conductive layer CL3 can correspond to a second metal layer ML2 above the first metal layer ML1, and the fourth conductive layer CL4 can correspond to a third metal layer ML3 above the second metal layer ML2. For the sake of convenience of description, Fig. 7A a polysilicon layer PL and three metal layers ML1, ML2, and ML3 are shown, but a semiconductor device may include two or more polysilicon layers and three or more metal layers.

[0069] The vertical lines VL1 and VL3 can include: vertical contact portions for electrically connecting the horizontal lines HL1, HL2, and HL4 formed in the polysilicon layer PL, the first metal layer ML1, and the third metal layer ML3. In some example embodiments, an intermediate conductive layer may exist between the polysilicon layer PL and the third metal layer ML3. In this case, each of the vertical lines VL1 and VL3 may include a plurality of vertical contact portions. During a test operation for detecting defects in a semiconductor device, a constant bias voltage VB can be applied to the sixth horizontal line HL6 corresponding to the shielding loop SLP.

[0070] Reference Figure 7B , the defect detection structure can be formed using a conductive layer above the semiconductor substrate SUB and a metal layer below the lower surface of the semiconductor substrate SUB. The first conductive layer CL1 can correspond to a lower metal layer MB below the semiconductor substrate SUB, the second conductive layer CL2 can correspond to a first metal layer ML1 above the polysilicon layer PL, the third conductive layer CL3 can correspond to a second metal layer ML2 above the first metal layer ML1, and the fourth conductive layer CL4 can correspond to a third metal layer ML3 above the second metal layer ML2.

[0071] The vertical lines VL1 and VL3 can include: vertical contact portions and through-silicon vias TSV1 and TSV2 that penetrate the semiconductor substrate SUB to electrically connect the horizontal lines HL1, HL2, and HL4 formed in the lower metal layer MB, the first metal layer ML1, and the third metal layer ML3. During a test operation for detecting defects in a semiconductor device, a constant bias voltage VB can be applied to the sixth horizontal line HL6 corresponding to the shielding loop SLP.

[0072] Reference Fig. 7A and Figure 7BDescribes two exemplary embodiments of a defect detection structure using conductive layers above and below a semiconductor substrate SUB. It will be readily understood that the defect detection structure according to the exemplary embodiments can be implemented using various combinations of conductive layers.

[0073] Fig. 8A and Figure 8B are perspective views showing the defect detection structures according to the exemplary embodiments. In the Fig. 8A defect detection structure 11 of Figure 8B and the Figures 4 to 6B defect detection structure 12 of

[0074] Reference Fig. 8A shows that the shielding loop SLP of the defect detection structure 11 may include a plurality of horizontal lines HLa and HLb, which may be formed in a plurality of conductive layers respectively, and the horizontal lines HLa and HLb may be electrically connected. Fig. 8A Shows two horizontal lines HLa and HLb as an example. According to the exemplary embodiments, the shielding loop SLP may include three or more horizontal lines respectively formed in three or more conductive layers. During the test operation, a constant bias voltage VB may be applied to the shielding loop SLP through one or more bias nodes.

[0075] Reference Figure 8B shows that the defect detection structure 12 may include a plurality of shielding loops provided at respective positions. As an example, Fig. 9B shows two shielding loops, namely, a first shielding loop SLPc and a second shielding loop SLPd. According to the exemplary embodiments, the defect detection structure may include three or more shielding loops. The first shielding loop SLPc may include a horizontal line HLc, and the second shielding loop SLPd may include a horizontal line HLd. In some exemplary embodiments, each of the first shielding loop SLPc and the second shielding loop SLPd may be implemented using a plurality of horizontal lines respectively formed in a plurality of conductive layers as described in reference Fig. 8A During the test operation, a constant bias voltage VB may be applied to each of the first shielding loop SLPc and the second shielding loop SLPd through one or more bias nodes.

[0076] At least a part of the shielding loop may be provided at a position for shielding the electrical interference between two horizontal lines respectively included in the first conductive loop to the fourth conductive loop. For example, as Figure 8B shown, the left half of the first shielding loop SLPc may be as in reference Figures 4 to 6Bis disposed between two horizontal lines HL1 and HL2 of the first conductive loop LP1, and the right half of the first shielding loop SLPc can be as described in the reference Figures 4 to 6B is disposed between two horizontal lines HL1 and HL3 of the second conductive loop LP2.

[0077] Fig.9A , Fig. 9B , Fig. 9C and Fig.9D are cross-sectional views of the vertical structure of a defect detection structure according to an exemplary embodiment. 9A to 9D shows a cross-sectional view taken along Figure 1 line A-A' in Figure 1 . Although not shown, the cross-sectional view taken along 9A to 9D line B-B' in 9A to 9D is symmetric to the cross-sectional view of Fig. 6A . The basic structure of

[0078] is substantially the same as that of 9A to 9D and the repeated description is omitted. Fig. 6A As described in Fig.9A , a single horizontal line forming a conductive loop and / or a shielding loop can extend in the vertical direction Z across two conductive layers. In some exemplary embodiments, the first horizontal line HL1 formed in the first conductive layer CL1 of Fig. 6A can extend in the vertical direction Z, for example, in a structure that crosses two conductive layers CL1-1 and CL1-2 as shown in

[0079] . The first horizontal line HL1 in Fig. 6A can include a first lower horizontal line HL1-1 formed in the first lower conductive layer CL1-1, a first upper horizontal line HL1-2 formed in the first upper conductive layer CL1-2, and a vertical line VL connecting the first lower horizontal line HL1-1 and the first upper horizontal line HL1-2. Fig. 9B In some exemplary embodiments, the sixth horizontal line HL6 formed in the third conductive layer CL3 of Fig. 6A can extend in the vertical direction Z, for example, in a structure that crosses two conductive layers CL3-1 and CL3-2 as shown in

[0080] . The sixth horizontal line HL6 in Fig. 6A can include a sixth lower horizontal line HL6-1 formed in the third lower conductive layer CL3-1, a sixth upper horizontal line HL3-2 formed in the third upper conductive layer CL3-2, and a vertical line VL connecting the sixth lower horizontal line HL6-1 and the sixth upper horizontal line HL6-2. Fig. 9CThe structure shown spans two conductive layers CL4-1 and CL4-2. Fig. 6A The fourth horizontal line HL4 in the embodiment may include a fourth lower horizontal line HL4-1 formed in the fourth lower conductive layer CL4-1, a fourth upper horizontal line HL4-2 formed in the fourth upper conductive layer CL4-2, and a vertical line VL connecting the fourth lower horizontal line HL4-1 and the fourth upper horizontal line HL4-2.

[0081] Fig.9D Shown with Fig.9A and Fig. 9C The example embodiments correspond to the combinations of the example embodiments. Fig.9D As shown, in Fig. 6A The first horizontal line HL1 formed in the first conductive layer CL1 may extend in the vertical direction Z, for example, across the structure of the two conductive layers CL1-1 and CL1-2, and Fig. 6A The fourth horizontal line HL4 formed in the fourth conductive layer CL4 in FIG. 4 may extend in the vertical direction Z, for example, a structure spanning two conductive layers CL4 - 1 and CL4 - 2 . Fig. 6A The first horizontal line HL1 in the embodiment may include a first lower horizontal line HL1-1 formed in the first lower conductive layer CL1-1, a first upper horizontal line HL1-2 formed in the first upper conductive layer CL1-2, and a vertical line VL connecting the first lower horizontal line HL1-1 and the first upper horizontal line HL1-2. Fig. 6A The fourth horizontal line HL4 in the fourth lower conductive layer CL4-1 may include a fourth lower horizontal line HL4-1 formed in the fourth lower conductive layer CL4-1, a fourth upper horizontal line HL4-2 formed in the fourth upper conductive layer CL4-2, and a vertical line VL connecting the fourth lower horizontal line HL4-1 and the fourth upper horizontal line HL4-2. Therefore, a crack may be detected more accurately by extending at least one horizontal line forming a conductive loop and / or a shielding loop in the vertical direction Z.

[0082] Fig. 10A , Fig. 10B and Fig. 10C is a diagram illustrating a noise shielding effect of a defect detection structure according to example embodiments. Fig. 10A , Fig. 10B and Fig. 10C A capacitor with a dotted line for indicating electrical interference between two conductive lines, and waveforms of a test input signal TSI and test output signals TSO1 and TSO3 of the conductive lines are shown. Fig. 10A , Fig. 10B and Fig. 10C Defect detection structure and reference Figures 4 to 9D The defect detection structures described are essentially the same.

[0083] refer to Fig. 10A and Fig. 10B, the first horizontal line HL1 can be cut / interrupted by the slit, so that the fourth horizontal line HL4 can be electrically floating. When, as Fig. 10A shown, the shielding circuit is not included, due to the electrical interference between the second horizontal line HL2 and the fourth horizontal line HL4, the first test output signal TSO1 on the second horizontal line HL2 can affect the fourth horizontal line HL4 in the floating state. Therefore, noise can be induced in the third test output signal TSO3 on the fourth horizontal line HL4.

[0084] As Fig. 10B shown, a part of the shielding circuit SLP can be disposed at a position for shielding the electrical interference between the second horizontal line HL2 for shielding the first conductive circuit and the fourth horizontal line HL4 for shielding the third conductive circuit. In this case, even if electrical interference occurs between the second horizontal line HL2 and the shielding circuit SLP, a very weak ripple-like noise will be induced on the shielding circuit SLP due to the application of the bias voltage to the shielding circuit SLP. The ripple noise on the shielding circuit SLP may hardly affect the fourth horizontal line HL4, and can prevent or reduce the noise of the third test output signal TSO3 on the fourth horizontal line HL4.

[0085] Referring to Fig. 10C , the first horizontal line HL1 and the second horizontal line HL2 can be cut by the slit, so that the second horizontal line HL2 and the fourth horizontal line HL4 may be electrically floating. As Fig. 10C shown, a part of the shielding circuit SLPc can be disposed at a position for shielding the electrical interference between the first horizontal line HL1 and the second horizontal line HL2, and a part of the shielding circuit SLPd can be disposed at a position for shielding the electrical interference between the second horizontal line HL2 and the fourth horizontal line HL4. In this case, even if electrical interference occurs between the second horizontal line HL2 and the shielding circuit SLPc, a very weak ripple-like noise will be induced on the shielding circuit SLPc due to the application of the bias voltage to the shielding circuit SLPc. The ripple noise on the shielding circuit SLPc may hardly affect the fourth horizontal line HL2, and can prevent or reduce the noise of the first test output signal TSO1 on the second horizontal line HL2.

[0086] Fig.11 is a diagram showing a semiconductor device according to an exemplary embodiment. Referring to Fig.11, the semiconductor device 102 may include: an annular defect detection structure and an input / output circuit IOC 200 formed in a peripheral region PREG of a semiconductor die. The defect detection structure includes a first conductive loop LP1, a second conductive loop LP2, a third conductive loop LP3, a fourth conductive loop LP4, and a shielding loop SLP. The first conductive loop LP1 passes through a lower left corner region CLB, the second conductive loop LP2 passes through a lower right corner region CRB, the third conductive loop LP3 passes through the lower left corner region CLB and an upper left corner region CLU, and the fourth conductive loop LP4 passes through the lower right corner region CRB and an upper right corner region CRU. In addition, the shielding loop SLP electrically shields electrical interference LP1-LP4 between the first conductive loop to the fourth conductive loop.

[0087] End nodes ENI and ENO1-ENO4 of the first conductive loop to the fourth conductive loop LP1-LP4 may be connected to the input / output circuit 200 via input / output leads LIO. The input / output leads LIO may be formed at different positions according to the positions of the input / output circuit 200 and the end nodes ENI and ENO1-ENO4. Below, reference will be made to Fig.19 and Fig.21 to describe an exemplary embodiment of the input / output circuit 200. In addition, when compared with Figure 3 a structure (in which portions of some horizontal lines overlap other horizontal lines), Fig.11 the first conductive loop to the fourth conductive loop LP1-LP4 of

[0088] may be implemented using different horizontal lines, respectively. Fig.12 、 Fig.13A and Fig. 13B to describe Fig.11 exemplary embodiments of the defect detection structure included in the semiconductor device 102 of Fig.12 shows a perspective view of the defect detection structure according to an exemplary embodiment, and Fig.13A and Fig. 13B are cross-sectional views showing the vertical structure of the defect detection structure of Fig.12 . Descriptions that are repetitive with Figures 1 to 3 will be omitted. Fig.13A shows a cross-sectional view taken along line A-A' of Figure 1 , and Fig. 13B shows a cross-sectional view taken along line B-B' of Figure 1 .

[0089] Referring to Fig.12 、 Fig.13A and Fig. 13B, the defect detection structure 13 may include a first horizontal line HL1, a second horizontal line HL2, a third horizontal line HL3, a fourth horizontal line HL4, a fifth horizontal line HL5, a sixth horizontal line HL6, a seventh horizontal line HL7, a first vertical line VL1, a second vertical line VL2, a third vertical line VL3, a fourth vertical line VL4, and a fifth vertical line VL5.

[0090] The first horizontal line HL1 is formed in the first conductive layer CL1. The first horizontal line HL1 extends from a first edge region ERG1 between the lower left corner region CLB and the upper left corner region CLU to a second edge region ERG2 between the lower right corner region CRB and the upper right corner region CRU by passing through the lower left corner region CLB and the lower right corner region CRB. Additionally, the second horizontal line HL2 is formed in the second conductive layer CL2. The second horizontal line HL2 extends from a first output end node ENO1 in an end node region ENR between the lower left corner region CLB and the lower right corner region CRB to the first edge region ERG1 by passing through the lower left corner region CLB.

[0091] The third horizontal line HL3 is formed in the second conductive layer CL2. The third horizontal line HL3 extends from a second output end node ENO2 in the end node region ENR to the second edge region ERG2 by passing through the lower right corner region CRB. Additionally, the fourth horizontal line HL4 is formed in the fourth conductive layer CL4. The annular fourth horizontal line HL4 extends along the peripheral region PREG by passing through the lower left corner region CLB, the upper left corner region CLU, the upper right corner region CRU, and the lower right corner region CRB. The fourth horizontal line HL4 is cut in a third edge region ERG3 between the upper left corner region CLU and the upper right corner region CRU.

[0092] The fifth horizontal line HL5 is formed in the fifth conductive layer CL5. The fifth horizontal line HL5 extends from a third output end node ENO3 in the end node region ENR to the third edge region ERG3 by passing through the lower left corner region CLB and the upper left corner region CLU. Additionally, the sixth horizontal line HL6 is formed in the fifth conductive layer CL5. The sixth horizontal line HL6 extends from a fourth output end node ENO4 in the end node region ENR to the third edge region ERG3 by passing through the lower right corner region CRB and the upper right corner region CRU.

[0093] The seventh horizontal line HL7 is formed in the third conductive layer CL3. The annular seventh horizontal line HL7 extends along the peripheral region PREG by passing through the lower left corner region CLB, the upper left corner region CLU, the upper right corner region CRU, and the lower right corner region CRB.

[0094] The first vertical line VL1 connects the first horizontal line HL1 and the second horizontal line HL2 in the first edge region ERG1. The second vertical line VL2 connects the first horizontal line HL1 and the third horizontal line HL3 in the second edge region ERG2. The third vertical line VL3 connects the fourth horizontal line HL4 and the fifth horizontal line HL5 in the third edge region ERG3. The fourth vertical line VL4 connects the fourth horizontal line HL4 and the sixth horizontal line HL6 in the third edge region ERG3. The fifth vertical line VL5 connects the first horizontal line HL1 and the fourth horizontal line HL4 in the end node region ENR.

[0095] Fig.11 The first conductive loop LP1 in includes a part of the first horizontal line HL1 and the second horizontal line HL2. Fig.11 The second conductive loop LP2 in

[0095] includes a part of the first horizontal line HL1 and the third horizontal line HL3. Fig.11 The third conductive loop LP3 in Fig.11 includes a part of the fourth horizontal line HL4 and the fifth horizontal line HL5. Fig.11 The fourth conductive loop LP4 in Fig.11 includes a part of the fourth horizontal line HL4 and the sixth horizontal line HL6. Fig.11 The shielding loop SLP in Fig.11 includes the seventh horizontal line HL7. During a test operation for detecting defects in a semiconductor device, a constant bias voltage VB can be applied to the seventh horizontal line HL7.

[0096] Therefore, the first conductive loop LP1 and the second conductive loop LP2 can be formed using the first conductive layer CL1 and the second conductive layer CL2, the shielding loop SLP can be formed using the third conductive layer CL3 and the third conductive loop LP3, and the fourth conductive loop LP4 can be formed using the fourth conductive layer CL4 and the fifth conductive layer CL5.

[0097] Fig.14 is a flowchart showing a method for detecting defects in a semiconductor die according to an exemplary embodiment. As described above, the semiconductor die SD can include a central region CREG in which a semiconductor integrated circuit is formed and a peripheral region PREG surrounding the central region CREG. Refer to Fig.14 , a defect detection structure is formed in the peripheral region of the semiconductor die, and the defect detection structure includes: a first conductive loop passing through the lower left corner region of the peripheral region PREG, a second conductive loop passing through the lower right corner region of the peripheral region PREG, a third conductive loop passing through the lower left corner region and the upper left corner region of the peripheral region PREG, and a fourth conductive loop passing through the lower right corner region and the upper right corner region of the peripheral region PREG. A shielding loop (S100) for at least partially shielding electrical interference between the first conductive loop to the fourth conductive loop is also provided.

[0098] According to this method, a test input signal can be applied to the input end node of the defect detection structure (S200). Then, the first test output signal to the fourth test output signal are received from the first output end node to the fourth output end node of the first conductive loop to the fourth conductive loop (S300). Then, based on the test input signal and the first test output signal to the fourth test output signal, it is determined that there is at least one defect and the position of any defect in the semiconductor die (S400).

[0099] Fig.15 is a block diagram showing a test system according to an exemplary embodiment. Referring to Fig.15 , the test system may include a tester 50 and a semiconductor device 100. The semiconductor device 100 may include: a defect detection structure including the first conductive loop to the fourth conductive loop LP1 to LP4 as described above. The first conductive loop LP1 may be an open-loop loop passing through or in the lower left corner region CLB, and the second conductive loop LP2 may be an open-loop loop passing through the lower right corner region CRB. The third conductive loop LP3 may be an open-loop loop passing through or in the lower left corner region CLB and the upper left corner region CLU, and / or the fourth conductive loop LP4 may be an open-loop loop passing through or in the lower right corner region CRB and the upper right corner region CRU.

[0100] The input end nodes ENI and the first output end nodes to the fourth output end nodes ENO1 to ENO4 of the first conductive loop to the fourth conductive loop LP1 to LP4 may be connected to a test input pad PTI and a test output pad PTO, and the test input pad PTI and the test output pad PTO are formed on the surface of the semiconductor device 100. The first conductive loop to the fourth conductive loop LP1 to LP4 may be electrically connected to an external tester 50 through the test input pad PTI and the test output pad PTO.

[0101] The tester 50 may include a crack detector CDET 510. The crack detector 510 may apply a test input signal TSI to the test input pad PTI, and then receive a test output signal TSO through the test output pad PTO, where the test output signal TSO corresponds to the test input signal TSI after passing through the first conductive loop to the fourth conductive loop LP1 to LP4. The crack detector 510 may determine the presence or occurrence of a defect and the position of the defect in the semiconductor die by comparing the test input signal TSI and the test output signal TSO.

[0102] Fig.16 is a circuit diagram showing an input / output circuit included in a semiconductor die according to an exemplary embodiment, and Fig.17 is showing Fig.16Timing diagram of the test signal of the input / output circuit. Refer to Fig.16 , the input / output circuit 201 may include an input buffer 211, an output buffer 212, a selection circuit 213, a test input pad PTI, and a test output pad PTO. In some example embodiments, the input buffer 211 and / or the output buffer 212 may be omitted. The test input pad PTI may be electrically connected to the input terminal node ENI to apply a test input signal TSI to the input terminal node ENI.

[0103] The selection circuit 213 may sequentially connect the test output pad PTO to the first output terminal node ENO1 of the first conductive loop LP1, the second output terminal node ENO2 of the second conductive loop LP2, the third output terminal node ENO3 of the third conductive loop LP3, and the fourth output terminal node ENO4 of the fourth conductive loop LP4. Thus, as Fig. 20 shown, the test output signal TSO from the selection circuit 213 may sequentially include a first test output signal to a fourth test output signal TSO1 to TSO4 respectively corresponding to the test input signals STI passing through the first conductive loop to the fourth conductive loop LP1 to LP4.

[0104] Refer to Fig.17 , Fig.15 The crack detector 510 in

[0105] may compare the phase of the test input signal TSI with the phases of the first test output signal to the fourth test output signal TSO1 to TSO4 to measure the phase difference or the delay times td1 to td4. The presence and location of the defect may be determined based on the delay times td1 to td4. Such a crack detector 510 may generate the test input signal TSI and sequentially receive the first test output signal to the fourth test output signal TSO1 to TSO4 from the defect detection structure. The test input signal TSI is activated in the form of pulses at time points T1 to T4 to apply the test input signal TSI to the defect detection structure. If any one of the first test output signal to the fourth test output signal TSO1 to TSO4 does not include a pulse, it may be determined that the corresponding conductive loop is completely cut off.

[0106] Fig.18 is a circuit diagram showing an input / output circuit included in a semiconductor die according to an example embodiment. Fig.19is a timing diagram showing Fig.18 the test signal of the input / output circuit. Refer to Fig.18 , the input / output circuit 202 may include: an input buffer 211; output buffers 221, 222, 223, and 224; a test input pad PTI; and a first test output pad to a fourth test output pad PTO1 to PTO4. In some example embodiments, the input buffer 211 and / or the output buffers 221, 222, 223, and 224 may be omitted.

[0107] The test input pad PTI may be electrically connected to the input terminal node ENI to apply a test input signal TSI to the input terminal node ENI. The first test output pad to the fourth test output pad PTO1 to PTO4 may be electrically connected to the first output terminal node to the fourth output terminal node ENO1 to ENO4, respectively. Thus, as Fig. 22 shown, the first test output signal to the fourth test output signal TSO1 to TSO4 corresponding to the test input signals STI passing through the first conductive loop to the fourth conductive loop LP1 to LP4 may be provided in parallel.

[0108] Refer to Fig.19 , Fig.15 the crack detector 510 in Fig.18 may compare the phase of the test input signal TSI with the phases of the first test output signal to the fourth test output signal TSO1 to TSO4 to measure the phase difference or the delay times td1 to td4. The presence and location of the defect may be determined based on the delay times td1 to td4. Fig.18 shows a case of four test output pads PTO1 to PTO4, but the example embodiments are not limited thereto. In some example embodiments, using a selection circuit similar to the Fig.16 selection circuit in

[0109] two of the first signal to the fourth signal TSO1 to TSO4 may be provided in parallel through two test output pads, and then the other two of the first signal to the fourth signal TSO1 to TSO4 may be provided in parallel.

[0110] The crack detector 510 may generate the test input signal TSI and receive the first test output signal to the fourth test output signal TSO1 to TSO4 from the defect detection structure in parallel. The test input signal TSI is activated in the form of a pulse at the time point T1 to apply the test input signal TSI to the defect detection structure. If any one of the first test output signal to the fourth test output signal TSO1 to TSO4 does not include a pulse, it may be determined that the corresponding conductive loop is completely cut off.

[0110] The first test output signal to the fourth test output signal TSO1 to TSO4 may have a first delay time to a fourth delay time td1 to td4 with respect to the test input signal TSI, respectively. Defects such as cracks can be detected by comparing the first delay time to the fourth delay time td1 to td4 with a reference value or by comparing the first delay time to the fourth delay time td1 to td4 with each other.

[0111] Fig. 20 and Fig.21 is a diagram for describing defect detection in a semiconductor device according to an exemplary embodiment. Refer to Fig. 20 , for example, during the process of dicing a wafer, cracks can be caused at various positions. The first crack CR1 represents a defect near the lower left corner region CLB, the second crack CR2 represents a defect near the lower right corner region CRB, the third crack CR3 represents a defect near the upper left corner region CLU, and the fourth crack CR4 represents a defect near the upper right corner region CRU. Using a plurality of conductive loops LP1 to LP4 passing through different combinations of corner regions, in addition to the presence of defects, the defect detection structure according to the exemplary embodiment can also efficiently detect the position of defects such as cracks.

[0112] Fig.21 shows the delays of the first conductive loop to the fourth conductive loop LP1 to LP4 according to the position or location of the cracks CR1 to CR4. In Fig.21 , DEL represents that the delay time exceeds a reference value for indicating the occurrence of a defect in the corresponding conductive loop, and NOR represents that the delay time is shorter than a reference value for indicating that the corresponding conductive loop does not include a defect. Therefore, the measurement results of the first conductive loop to the fourth conductive loop LP1 to LP4 can have different combinations according to the position of the crack, and thus the position of the crack can be determined.

[0113] In the defect detection structure as described in reference Figures 1 to 13B , the first conductive loop LP1 and the second conductive loop LP2 are bilaterally symmetric, and the third conductive loop LP3 and the fourth conductive loop LP4 are bilaterally symmetric. In such a symmetric structure, the first conductive loop LP1 and the second conductive loop LP2 can have substantially the same delay time, and the third conductive loop LP3 and the fourth conductive loop LP4 can also have substantially the same delay time. The position of the defect can be determined by comparing the mutual delay of the first test output signal TSO1 and the second test output signal TSO2, and by comparing the mutual delay of the third test output signal TSO3 and the fourth test output signal TSO4, regardless of the test input signal TSI.

[0114] Fig. 22 is a diagram showing a semiconductor device according to an exemplary embodiment. Except for the end nodes, Fig. 22 The semiconductor device 103 and Fig.11 the semiconductor device 102 are substantially the same, and duplicate descriptions are omitted. The semiconductor device 103 may not include a shielding circuit as described with reference to Fig.23 or may include a shielding circuit as described with reference to Fig.24 .

[0115] Reference Fig. 22 , the end nodes of the first conductive loop to the fourth conductive loop LP1 to LP4, that is, the first input end node ENI1, the second input end node ENI2, the first output end node ENO1, the second output end node ENO2, the third output end node ENO3, and the fourth output end node ENO4 may be located in the end node region ENR. In Fig.11 the semiconductor device 102, the first conductive loop to the fourth conductive loop LP1 to LP4 have a common input end node ENI. In contrast, in Fig. 22 the semiconductor device 103, the first conductive loop LP1 and the second conductive loop LP2 have a common first input end node ENI1, and the third conductive loop LP3 and the fourth conductive loop LP4 have a common second input end node ENI2.

[0116] The first input end node ENI1 may be disconnected from the second input end node ENI2, and a first input signal and a second test input signal may be applied to the first input end node ENI1 and the second input end node ENI2, respectively. In this case, even if a crack appears in one of the first conductive loop LP1 and the third conductive loop LP3, noise caused by electrical interference can be reduced because an independent test input signal is input to the other of the first conductive loop LP1 and the third conductive loop LP3. Although not shown in the drawings, the first conductive loop to the fourth conductive loop LP1 to LP4 may be disconnected from each other, and four independent test input signals may be applied to the four corresponding input end nodes of the first conductive loop to the fourth conductive loop LP1 to LP4.

[0117] Fig.23 and Fig.24 are perspective views showing a defect detection structure according to an exemplary embodiment. Fig.23 The defect detection structure 14 and Fig.24 the defect detection structure 15 are similar to the defect detection structure 13 described with reference to Fig.12 , Fig.13A and Fig. 13B , and duplicate descriptions are omitted.

[0118] Reference Fig.23, in the defect detection structure 14, the first conductive loop LP1 and the second conductive loop LP2 have a common first input terminal node ENI1, and the third conductive loop LP3 and the fourth conductive loop LP4 have a common second input terminal node ENI2. A first test input signal and a second test input signal independent of each other can be applied to the first input terminal node ENI1 and the second input terminal node ENI2 respectively. In this case, the noise caused by the electrical interference between the first conductive loop LP1 and the third conductive loop LP3 and the electrical interference between the second conductive loop LP2 and the fourth conductive loop LP4 can be reduced by applying independent test input signals. In this case, as Fig.23 shown, the shielding loop SLP of Fig.12 can be omitted.

[0119] Except for the first input terminal node ENI1 and the second input terminal node ENI2, Fig.24 the defect detection structure 15 of Fig.12 is the same as the defect detection structure 13 of

[0120] Fig.25 is a block diagram showing a memory cell array included in a NAND flash memory device, where the NAND flash memory device can be integrated in a semiconductor device. Fig.26 is a circuit diagram showing an equivalent circuit of a memory block in the memory cell array of Fig.25 . Referring to Fig.25 , the memory cell array 400 of the NAND flash memory device may include a plurality of memory blocks BLK1 to BLKz. In an exemplary embodiment, the memory blocks BLK1 to BLKz can be selected by an address decoder in the NAND flash memory device. For example, the address decoder can select a specific memory block corresponding to the block address from the memory blocks BLK1 to BLKz.

[0121] In Fig.25 and Fig.26 , the first direction D1 indicates a vertical direction perpendicular to the upper surface of the semiconductor substrate, and the second direction D2 and the third direction D3 indicate two orthogonal directions parallel to the upper surface of the semiconductor substrate. The memory block BLKi of Fig.26 can be formed on the semiconductor substrate in a three-dimensional structure (or vertical structure). For example, a plurality of NAND strings or cell strings included in the memory block BLKi can extend along the first direction D1.

[0122] Referring to Fig.26, the memory block BLKi may include NAND strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1 to MC8, and a ground select transistor GST. In Fig.26 , each of the NAND strings NS11 to NS33 is shown as including eight memory cells MC1 to MC8. However, the exemplary embodiments are not limited thereto. In some exemplary embodiments, each of the NAND strings NS11 to NS33 may include any number of memory cells.

[0123] Each string select transistor SST may be connected to a corresponding string select line (one of SSL1 to SSL3). The plurality of memory cells MC1 to MC8 may be respectively connected to corresponding gate lines GTL1 to GTL8. The gate lines GTL1 to GTL8 may be word lines, and some of the gate lines GTL1 to GTL8 may be dummy word lines. Each ground select transistor GST may be connected to a corresponding ground select line (one of GSL1 to GSL3). Each string select transistor SST may be connected to a corresponding bit line (e.g., one of BL1, BL2, and BL3), and each ground select transistor GST may be connected to the common source line CSL.

[0124] Word lines having the same height (e.g., WL1) may be commonly connected, and the ground select lines GSL1 to GSL3 and the string select lines SSL1 to SSL3 may be separated. In Fig.26 , the memory block BLK is shown as being coupled to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3. However, the exemplary embodiments are not limited thereto. Each memory block in the memory cell array 400 may be coupled to any number of word lines and any number of bit lines.

[0125] Fig.25 and Fig.26 illustrates a non-limiting exemplary embodiment in which a semiconductor device according to an exemplary embodiment corresponds to a vertical NAND flash memory device, and the defect detection structure may be applied to any semiconductor device manufactured using semiconductor dies.

[0126] Fig. 27 is a block diagram illustrating a mobile system according to an exemplary embodiment. Referring to Fig. 27 , the mobile system 3000 includes an application processor 3100, a communication unit 3200, a volatile storage device VM 3300, a non-volatile storage device NVM 3400, a user interface 3500, and a power supply 3600 connected via a bus.

[0127] The application processor 3100 may execute applications such as a web browser, a game application, a video player, etc. The communication unit 3200 may perform wired or wireless communication with an external device. The volatile memory device 3300 may store data processed by the application processor 3100 or may operate as a working memory. For example, the volatile memory device 3300 may be a DRAM, for example, a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power DDR (LPDDR) SDRAM, a graphics DDR (GDDR) SDRAM, a Rambus DRAM (RDRAM), etc. The non-volatile memory device 3400 may store a boot image for booting the mobile system 3000 and other data. The user interface 3500 may include at least one input device (e.g., a keypad, a touch screen, etc.) and at least one output device (e.g., a speaker, a display device, etc.). The power supply 3600 may supply a power voltage to the mobile system 3000. In an exemplary embodiment of the inventive concept, the mobile system 3000 may further include: a camera image processor (CIP); and / or a storage device, for example, a memory card, a solid state drive (SSD), a hard disk drive (HDD), a compact disc read only memory (CD-ROM), etc.

[0128] The volatile memory device 3300 and / or the non-volatile memory device 3400 may be implemented as a semiconductor device including a defect detection structure as described above. The defect detection structure includes a first conductive loop, a second conductive loop, a third conductive loop, a fourth conductive loop, and a shielding loop. The first conductive loop passes through the lower left corner region CLB of the peripheral region PREG. The second conductive loop passes through the lower right corner region CRB of the peripheral region PREG. The third conductive loop passes through the lower left corner region CLB and the upper left corner region CLU of the peripheral region PREG. The fourth conductive loop passes through the lower right corner region CRB and the upper right corner region CRU of the peripheral region PREG. The shielding loop shields the electrical interference between the first conductive loop to the fourth conductive loop.

[0129] As described above, the defect detection structure, semiconductor device, and associated method according to the exemplary embodiment may accurately detect various types of crack intrusions using a plurality of conductive loops and a shielding loop formed in the peripheral region, where the peripheral region surrounds a central region in which a semiconductor integrated circuit is formed. The defect detection structure, semiconductor device, and associated method according to the exemplary embodiment may prevent the production of defective products by utilizing enhanced crack detection capabilities.

[0130] The inventive concept can be applied to any electronic devices and systems formed using semiconductor dies. For example, the defect detection structure according to an exemplary embodiment can be applied to various systems such as memory cards, solid state drives (SSDs), embedded multimedia cards (eMMCs), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, video recorders, personal computers (PCs), servo computers, workstations, laptop computers, digital TVs, set top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0131] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting thereof. Although some exemplary embodiments have been described, those skilled in the art will readily appreciate that various modifications of the exemplary embodiments may exist that do not depart in essence from the inventive concept.

Claims

1. A semiconductor device, comprising: A semiconductor die, including a central region and a peripheral region surrounding at least a part of the central region, a semiconductor integrated circuit being formed in the central region, and the peripheral region including a lower left corner region, an upper left corner region, an upper right corner region, and a lower right corner region; And A defect detection structure, formed in the peripheral region, the defect detection structure including a first conductive loop passing through the lower left corner region, a second conductive loop passing through the lower right corner region, a third conductive loop passing through the lower left corner region and the upper left corner region, and a fourth conductive loop passing through the lower right corner region and the upper right corner region; Wherein, the defect detection structure further includes: a shielding loop, configured to at least partially shield the first conductive loop to the fourth conductive loop from electrical interference between the first conductive loop to the fourth conductive loop, Wherein, the shielding loop is annular and extends along the peripheral region by passing through the lower left corner region, the upper left corner region, the upper right corner region, and the lower right corner region, Wherein, during a test operation for detecting a defect of the semiconductor device, a constant bias voltage is applied to at least one bias node on the shielding loop, Wherein, the number and position of the at least one bias node are determined according to the resistive voltage drop of the shielding loop and the expected crack position.

2. The semiconductor device according to claim 1, wherein, A first part of the shielding loop is disposed at a position for at least partially shielding electrical interference between a horizontal line of the first conductive loop and a horizontal line of the third conductive loop; and wherein, a second part of the shielding loop is disposed at a position for at least partially shielding electrical interference between a horizontal line of the second conductive loop and a horizontal line of the fourth conductive loop.

3. The semiconductor device according to claim 1, wherein At least a part of the shielding loop is disposed at a position for at least partially shielding electrical interference between two horizontal lines respectively included in the first conductive loop to the fourth conductive loop.

4. The semiconductor device according to claim 1, wherein, The defect detection structure is formed in multiple conductive layers and is a three-dimensional annular structure at least partially surrounding the central region.

5. The semiconductor device according to claim 1, wherein, The horizontal lines of the first conductive loop and the second conductive loop are formed in a first conductive layer and a second conductive layer; wherein, the horizontal lines of the shielding loop are formed in a third conductive layer; and wherein, the third conductive loop and the fourth conductive loop are formed in the first conductive layer and a fourth conductive layer.

6. The semiconductor device according to claim 1, wherein, The defect detection structure includes: A first horizontal line, formed in the first conductive layer, the annular first horizontal line extends along the peripheral region by passing through the lower left corner region, the upper left corner region, the upper right corner region, and the lower right corner region, and the first horizontal line is cut off in a third edge region located between the upper left corner region and the upper right corner region; A second horizontal line, formed in the second conductive layer, the second horizontal line extends from an end node region located between the lower left corner region and the lower right corner region to a first edge region located between the lower left corner region and the upper left corner region and passes through the lower left corner region; A third horizontal line is formed in the second conductive layer. The third horizontal line extends from the end node region between the lower left corner region and the lower right corner region to the second edge region between the lower right corner region and the upper right corner region and passes through the lower right corner region; A fourth horizontal line is formed in the fourth conductive layer. The fourth horizontal line extends from the end node region between the lower left corner region and the lower right corner region to the third edge region by passing through the lower left corner region and the upper left corner region; A fifth horizontal line is formed in the fourth conductive layer. The fifth horizontal line extends from the end node region between the lower left corner region and the lower right corner region to the third edge region by passing through the lower right corner region and the upper right corner region; A sixth horizontal line is formed in the third conductive layer. The annular sixth horizontal line serves as the shielding loop, and the sixth horizontal line is cut off in the third edge region; A first vertical line electrically connects the first horizontal line and the second horizontal line in the first edge region; A second vertical line electrically connects the first horizontal line and the third horizontal line in the second edge region; A third vertical line electrically connects the first horizontal line and the fourth horizontal line in the third edge region; and A fourth vertical line electrically connects the first horizontal line and the fifth horizontal line in the third edge region.

7. The semiconductor device according to claim 1, wherein, The horizontal lines of the first conductive loop and the second conductive loop are formed in the first conductive layer and the second conductive layer, the horizontal line of the shielding loop is formed in the third conductive layer, and the horizontal lines of the third conductive loop and the fourth conductive loop are formed in the fourth conductive layer and the fifth conductive layer.

8. The semiconductor device according to claim 1, wherein, The defect detection structure includes: A first horizontal line is formed in the first conductive layer. The first horizontal line extends from the first edge region between the lower left corner region and the upper left corner region to the second edge region between the lower right corner region and the upper right corner region by passing through the lower left corner region and the lower right corner region; A second horizontal line is formed in the second conductive layer. The second horizontal line extends from the end node region between the lower left corner region and the lower right corner region to the first edge region by passing through the lower left corner region; A third horizontal line is formed in the second conductive layer. The third horizontal line extends from the end node region between the lower left corner region and the lower right corner region to the second edge region by passing through the lower right corner region; A fourth horizontal line is formed in the fourth conductive layer. The annular fourth horizontal line extends along the peripheral region by passing through the lower left corner region, the upper left corner region, the upper right corner region and the lower right corner region. The fourth horizontal line is cut off in the third edge region between the upper left corner region and the upper right corner region; The fifth horizontal line is formed in the fifth conductive layer. The fifth horizontal line extends from the end node region located between the lower left corner region and the lower right corner region to the third edge region by passing through the lower left corner region and the upper left corner region; The sixth horizontal line is formed in the fifth conductive layer. The sixth horizontal line extends from the end node region located between the lower left corner region and the lower right corner region to the third edge region by passing through the lower right corner region and the upper right corner region; The seventh horizontal line is formed in the third conductive layer. The annular seventh horizontal line serves as the shielding loop; The first vertical line electrically connects the first horizontal line and the second horizontal line in the first edge region; The second vertical line electrically connects the first horizontal line and the third horizontal line in the second edge region; The third vertical line electrically connects the fourth horizontal line and the fifth horizontal line in the third edge region; The fourth vertical line electrically connects the fourth horizontal line and the sixth horizontal line in the third edge region; and The fifth vertical line electrically connects the first horizontal line and the fourth horizontal line in the end node region.

9. The semiconductor device according to claim 1, wherein, The shielding loop includes: a plurality of conductive loops respectively formed in a plurality of conductive layers, and the plurality of conductive loops are electrically connected.

10. The semiconductor device according to claim 1, wherein, All end nodes of the first conductive loop to the fourth conductive loop are located in the end node region between the lower left corner region and the lower right corner region.

11. The semiconductor device according to claim 1, wherein, The first conductive loop to the fourth conductive loop have a common input end node.

12. The semiconductor device according to claim 1, wherein, The first conductive loop and the second conductive loop have a common first input end node, and the third conductive loop and the fourth conductive loop have a common second input end node.

13. The semiconductor device according to claim 1 further comprises: An input / output circuit is electrically connected to the corresponding end nodes of the first conductive loop, the second conductive loop, the third conductive loop, and the fourth conductive loop. The input / output circuit includes an output pad; and a selection circuit configured to sequentially electrically connect the output pad to the first output end node of the first conductive loop, the second output end node of the second conductive loop, the third output end node of the third conductive loop, and the fourth output end node of the fourth conductive loop.

14. A defect detection structure in a peripheral region of a semiconductor die, the peripheral region at least partially surrounding a central region of the semiconductor die, a semiconductor integrated circuit being formed in the central region. The defect detection structure includes: The first conductive loop passes through the lower left corner region of the peripheral region; The second conductive loop passes through the lower right corner region of the peripheral region; The third conductive loop passes through the lower left corner region and the upper left corner region of the peripheral region; The fourth conductive loop passes through the lower right corner region and the upper right corner region of the peripheral region; And A shielding loop for at least partially shielding electrical interference between the first conductive loop to the fourth conductive loop Wherein, the shielding loop is annular and extends along the peripheral region by passing through the lower left corner region, the upper left corner region, the upper right corner region, and the lower right corner region. Wherein, during a test operation for detecting a defect, a constant bias voltage is applied to at least one bias node on the shielding loop. Wherein, the number and position of the at least one bias node are determined according to the resistive voltage drop of the shielding loop and the predicted crack position.

15. A method for detecting defects in a semiconductor die, the semiconductor die comprising: (i) A central region formed with a semiconductor integrated circuit, (ii) a peripheral region surrounding the central region, the peripheral region including a lower left corner region, an upper left corner region, an upper right corner region, and a lower right corner region, and (iii) a defect detection structure. In the peripheral region, the defect detection structure includes a first conductive loop passing through the lower left corner region, a second conductive loop passing through the lower right corner region, a third conductive loop passing through the lower left corner region and the upper left corner region, a fourth conductive loop passing through the lower right corner region and the upper right corner region, and a shielding loop for at least partially shielding the electrical interference between the first conductive loop to the fourth conductive loop. Wherein, the shielding loop is annular and extends along the peripheral region by passing through the lower left corner region, the upper left corner region, the upper right corner region, and the lower right corner region. The method includes: Applying a test input signal to an input terminal node of the defect detection structure; Receiving a first test output signal to a fourth test output signal from a first output terminal node to a fourth output terminal node of the first conductive loop to the fourth conductive loop; and Identifying the position of a defect in the semiconductor die based on the test input signal and the first test output signal to the fourth test output signal. Wherein, the method further includes: during detecting a defect in the semiconductor die, applying a constant bias voltage to at least one bias node on the shielding loop, wherein, the number and position of the at least one bias node are determined according to the resistive voltage drop of the shielding loop and the predicted crack position.

16. The method according to claim 15, wherein, The first test output signal to the fourth test output signal are sequentially provided through output pads on the semiconductor die.

17. The method according to claim 15, wherein At least two of the first test output signal to the fourth test output signal are provided in parallel through at least two output pads on the semiconductor die.

18. The method according to claim 15, wherein, Determining the position of the defect by comparing the delay time of the first test output signal and the delay time of the second test output signal; and wherein, determining the position of the defect by comparing the delay time of the third test output signal and the delay time of the fourth test output signal.

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