Method for forming semiconductor device

Abstract

A method for forming a semiconductor device includes: providing a substrate, the substrate including a contact area and a non-contact area; forming a transition layer on the substrate; modifying the transition layer on the contact area so that the material density of the transition layer on the contact area is less than that of the transition layer on the non-contact area; after the modification, forming an interlayer dielectric layer on the transition layer, the interlayer dielectric layer having an opening, the opening exposing the transition layer on the contact area; and etching away the transition layer at the bottom of the opening using a wet etching process. The above scheme is easy to quickly remove the transition layer on the contact area, and the etching loss of the side wall of the transition layer in the non-contact area exposed by the opening is small, thereby avoiding the undercut effect of the etching process and improving the performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular to a method for forming a semiconductor device. Background Art

[0002] Integrated circuits are manufactured layer by layer using the so-called planar process. The process of logic devices includes the front-end process and the back-end process.

[0003] Among them, the front-end process is to realize N-type and P-type field effect transistors on the semiconductor substrate, which specifically includes: dividing the active area of ​​the transistor on the semiconductor substrate; performing well ion implantation to realize the N-type area and the P-type area; forming the gate structure, and then performing ion implantation again to form the source and drain of each transistor. The back-end of line (BEOL) process corresponds to the front-end process. The so-called back-end process is actually to establish several layers of conductive metal wires, and the metal wires of different layers are connected by pillar metals.

[0004] In the back-end of line (BEOL) of advanced manufacturing processes, the transition layer oxide connecting the upper and lower metal layers has the problem of large etching consumption, which affects the performance of semiconductor devices. Summary of the invention

[0005] The problem solved by the present invention is how to improve the performance of semiconductor devices.

[0006] In order to solve the above problems, the present invention provides a method for forming a semiconductor device, the method comprising:

[0007] providing a substrate, the substrate comprising a contact region and a non-contact region;

[0008] forming a transition layer on the substrate;

[0009] Modifying the transition layer on the contact area so that the material density of the transition layer on the contact area is less than the material density of the transition layer on the non-contact area;

[0010] After the modification treatment, an interlayer dielectric layer is formed on the transition layer, wherein the interlayer dielectric layer has an opening, and the opening exposes the transition layer on the contact area;

[0011] The transition layer at the bottom of the opening is removed by etching using a wet etching process.

[0012] Optionally, the modification treatment includes a plasma treatment process.

[0013] Optionally, the processing gas used in the plasma treatment process includes any one or a combination of C4F8, CF4, CH4, N2, He and Ar.

[0014] Optionally, the chemical solution used in the wet etching process is hydrofluoric acid, phosphoric acid or nitric acid.

[0015] Optionally, in the wet etching process, an etching selectivity ratio between the transition layer on the contact area and the transition layer on the non-contact area is greater than or equal to 3:1.

[0016] Optionally, the base comprises a substrate and an underlying dielectric layer located on the substrate, wherein the underlying dielectric layer has a metal layer;

[0017] After the transition layer is formed, the transition layer is located on the metal layer and the underlying dielectric layer; the opening is located on a portion of the metal layer;

[0018] The transition layer at the bottom of the opening is removed by etching using a wet etching process until the surface of the metal layer is exposed.

[0019] Optionally, the material of the metal layer includes copper.

[0020] Optionally, the wet etching process has an etching selectivity ratio of the transition layer to the metal layer greater than or equal to 5:1.

[0021] Optionally, the material of the transition layer includes SiO, SiOC, SiC, TiO2, AlO, SiN, HfO2 or polysilicon.

[0022] Optionally, the interlayer dielectric layer is made of a low-K dielectric constant material.

[0023] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0024] In the above scheme, the transition layer at the bottom of the opening is etched and removed by a wet etching process, thus avoiding a large etching loss of the material at the bottom of the transition layer. Before wet etching the transition layer at the bottom of the opening, the transition layer on the contact area is modified so that the material density of the transition layer on the contact area is less than that of the transition layer on the non-contact area. Therefore, in the process of etching the transition layer at the bottom of the opening, the etching rate of the transition layer on the contact area is greater than the etching rate of the transition layer on the non-contact area, making it easy to quickly remove the transition layer on the contact area, and the etching loss of the side wall of the transition layer in the non-contact area exposed by the opening is small, thereby avoiding the undercut effect of the etching process and improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 3A schematic diagram of a method for forming a semiconductor device;

[0026] Figure 4 is a schematic flow chart of a method for forming a semiconductor device in an embodiment of the present invention;

[0027] Figures 5 to 12 It is a schematic cross-sectional diagram of an intermediate structure of a semiconductor device corresponding to a method for forming a semiconductor device in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] As can be seen from the background art, the performance of semiconductor devices formed by the methods for forming semiconductor devices in the prior art needs to be improved.

[0029] A method for forming a semiconductor device, comprising:

[0030] See also Figure 1 , providing a substrate (not shown), on which a bottom dielectric layer (not shown) and a bottom metal layer 110 , a transition layer 120 located on the bottom metal layer 110 , and an interlayer dielectric material layer 130 located on the transition layer 120 are formed.

[0031] See also Figure 2 A hard mask transition material layer 140 and a patterned hard mask layer 150 are formed on the interlayer dielectric material layer 130, and the hard mask transition material layer 140 and the interlayer dielectric material layer 130 are sequentially etched using the patterned hard mask layer 150 as a mask until the top surface of the bottom metal layer 110 is exposed, thereby forming a hard mask transition material layer 141 and an interlayer dielectric layer 131, wherein the interlayer dielectric layer 131 has an opening 135.

[0032] See also Figure 3 , the transition layer 120 at the bottom of the opening 135 is etched using a wet etching process until the top surface of the bottom metal layer 110 is exposed.

[0033] In the process of etching the transition layer 120 by wet etching, due to the isotropic characteristics of the wet etching process, the transition layer 120 at the bottom of the interlayer dielectric material layer 130 causes an undercut effect, which reduces the performance of the semiconductor device.

[0034] To solve the above problems, a method for forming a semiconductor device in an embodiment of the present invention includes: providing a substrate, the substrate including a contact area and a non-contact area; forming a transition layer on the substrate; performing a modification treatment on the transition layer on the contact area so that the material density of the transition layer on the contact area is less than the material density of the transition layer on the non-contact area; after the modification treatment, forming an interlayer dielectric layer on the transition layer, the interlayer dielectric layer having an opening, the opening exposing the transition layer on the contact area; and etching away the transition layer at the bottom of the opening using a wet etching process.

[0035] In the method for forming a semiconductor device provided by an embodiment of the present invention, a wet etching process is used to etch and remove the transition layer at the bottom of the opening, thereby avoiding a large etching loss of the material at the bottom of the transition layer. Before wet etching the transition layer at the bottom of the opening, the transition layer on the contact area is modified so that the material density of the transition layer on the contact area is less than that of the transition layer on the non-contact area. Therefore, in the process of etching the transition layer at the bottom of the opening, the etching rate of the transition layer on the contact area is greater than the etching rate of the transition layer on the non-contact area, so that the transition layer on the contact area can be easily removed, and the etching loss of the side wall of the transition layer in the non-contact area exposed by the opening is small, thereby avoiding the undercut effect of the etching process and improving the performance of the semiconductor device.

[0036] Figure 4 A schematic diagram of a method for forming a semiconductor device in an embodiment of the present invention is shown. Figure 4 A method for forming a semiconductor device in an embodiment of the present invention may specifically include:

[0037] Step S401: providing a substrate, wherein the substrate comprises a contact area and a non-contact area;

[0038] Step S402: forming a transition layer on the substrate;

[0039] Step S403: modifying the transition layer on the contact area so that the material density of the transition layer on the contact area is less than the material density of the transition layer on the non-contact area;

[0040] Step S404: after the modification treatment, an interlayer dielectric layer is formed on the transition layer, wherein the interlayer dielectric layer has an opening, and the opening exposes the transition layer on the contact area;

[0041] Step S405: using a wet etching process to etch away the transition layer at the bottom of the opening.

[0042] The following will be combined Figures 5 to 10 The method for forming a semiconductor device in an embodiment of the present invention is described in further detail.

[0043] See also Figure 5 , providing a substrate (not shown), wherein the substrate includes a contact area I and a non-contact area II.

[0044] The base includes a substrate and a bottom dielectric layer (not shown) located on the substrate, and the bottom dielectric layer has a metal layer 510 therein.

[0045] In a specific implementation, the substrate may be a silicon substrate or a germanium substrate, etc. In addition, other devices may be formed on the substrate, such as PMOS and NMOS transistors; an isolation structure may be formed in the substrate, and the isolation structure may be a shallow trench isolation (STI) structure or a local oxide of silicon (LOCOS) isolation structure; CMOS devices may be formed in the substrate, such as NMOS transistors and / or PMO transistors, etc. Similarly, a conductive member may be formed in the substrate, and the conductive member may be a gate, source or drain of a transistor, or a metal interconnect structure electrically connected to the transistor, etc.

[0046] The substrate comprises a contact region I and a non-contact region II, wherein the contact region I is used as a contact between a subsequently formed metal layer and an upper metal layer.

[0047] The metal layer 510 may be a bottom metal layer M1 or an intermediate metal layer Mn (n is an integer greater than 1) in a semiconductor device, and may be made of metal materials such as copper or tungsten.

[0048] Continue to see Figure 5 , forming a transition layer 520 on the substrate.

[0049] Specifically, the transition layer is located on the metal layer 510 and the underlying dielectric layer.

[0050] The transition layer 520 is used to improve the adhesion between the metal layer 510 and the subsequently formed interlayer dielectric layer.

[0051] In this embodiment, the material of the transition layer 520 is aluminum oxide (AlO). In other embodiments, the material of the transition layer 520 can also be SiO, SiOC, SiC, TiO2, SiN, HfO2 or polysilicon.

[0052] See also Figure 6 , forming a patterned first mask layer 530 on the transition layer 520 .

[0053] The first mask layer 530 is used as a mask for subsequent modification of the transition layer 520 .

[0054] In the embodiment of the present invention, the material of the first mask layer 530 is photoresist.

[0055] The first mask layer 530 covers the transition layer 520 on the non-contact region II and exposes the transition layer 520 on the contact region I.

[0056] See also Figure 7 , using the patterned first mask layer 530 as a mask, a modification treatment is performed on the transition layer 520 on the contact area I, so that the density of the transition layer 520 on the contact area I is less than the density of the transition layer 520 on the non-contact area II.

[0057] In this embodiment, a plasma treatment process is used to perform a modification treatment on the transition layer 520 .

[0058] The transition layer 520 is subjected to a plasma treatment process using the patterned first mask layer 530 as a mask. Since the plasma treatment process will destroy the atomic bonds in the metal oxide serving as the transition layer 520, the density of the area in the transition layer 520 that has undergone the plasma treatment process is lower than that of the area that has not undergone the plasma treatment process, and the material is looser, which is conducive to rapid removal in the subsequent wet etching process.

[0059] In the embodiment of the present invention, the processing gas used in the plasma treatment process includes any one or a combination of C4F8, CF4, CH4, N2, He and Ar.

[0060] See also Figure 8 After performing a modification process on the transition layer 520 , the patterned first mask layer 530 is removed.

[0061] In a specific implementation, the first patterned mask layer 530 may be removed by using an ashing process or the like.

[0062] See also Fig. 9 After removing the patterned first mask layer 530 , an interlayer dielectric material layer 540 is formed on the transition layer 520 , and a hard mask transition material layer 550 is formed on the interlayer dielectric material layer 540 .

[0063] In the embodiment of the present invention, the interlayer dielectric material layer 540 is made of a low dielectric constant material, such as silicon dioxide (SiO 2 ).

[0064] The interlayer dielectric material layer 540 may be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition.

[0065] The hard mask transition material layer 550 is used to improve the adhesion between the subsequently formed hard mask layer and the interlayer dielectric material layer 540 .

[0066] The hard mask transition material layer 550 may be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition.

[0067] See also Fig.10 , forming a patterned hard mask layer 560 on the hard mask transition material layer 550 .

[0068] In a specific implementation, the patterned hard mask layer 560 is used as an etching mask for etching the hard mask transition material layer 550 and the interlayer dielectric material layer 540 .

[0069] The pattern of the patterned hard mask layer 560 is the same as the pattern of the first mask layer, so that after the hard mask transition material layer 550 and the interlayer dielectric material layer 540 are subsequently etched using the patterned hard mask layer 560 as a mask, the transition layer 520 above the contact area I is exposed.

[0070] See also Fig.11 , using the patterned hard mask layer 560 as a mask, the hard mask transition material layer 550 and the interlayer dielectric material layer 540 are etched until the top surface of the transition layer 520 above the contact area I is exposed, thereby forming the hard mask transition layer 551 and the interlayer dielectric layer 541, wherein the interlayer dielectric layer 541 has an opening 545, and the opening 545 exposes the top surface of the transition layer 520 above the contact area I.

[0071] In this embodiment, the process of etching the hard mask transition material layer 550 and the interlayer dielectric material layer 540 is a dry etching process. The dry etching process is an anisotropic dry etching process, which can better control the morphology of the sidewall profile of the hard mask transition layer 550 and the interlayer dielectric layer 541 after etching.

[0072] See also Fig.12 , a wet etching process is used to etch away the transition layer 520 at the bottom of the opening 545 until the top surface of the metal layer 510 is exposed.

[0073] In a specific implementation, when the transition layer 520 is etched by a wet etching process, the etching selectivity ratio of the plasma-treated area to the non-plasma-treated area in the transition layer 520 is greater than or equal to 3:1, so that the plasma-treated area in the transition layer 520 can be quickly etched and removed, shortening the processing time of the wet etching process, facilitating the rapid removal of the transition layer 520 on the contact area I, and causing less etching loss on the sidewall of the transition layer in the non-contact area II exposed by the opening 545, thereby avoiding the undercut effect of the etching process and improving the performance of the formed semiconductor device. In this embodiment, the etching selectivity ratio of the wet etching process for the transition layer to the metal layer is greater than or equal to 5:1.

[0074] In the embodiment of the present invention, the chemical solution used in the wet etching process includes hydrofluoric acid (HF), phosphoric acid (H3PO4) or nitric acid (HNO3) or the like.

[0075] In the above scheme of the embodiment of the present invention, the transition layer at the bottom of the opening is etched and removed by a wet etching process, so as to avoid causing a large etching loss to the material at the bottom of the transition layer. Before wet etching the transition layer at the bottom of the opening, the transition layer on the contact area is modified so that the material density of the transition layer on the contact area is less than that of the transition layer on the non-contact area. Therefore, in the process of etching the transition layer at the bottom of the opening, the etching rate of the transition layer on the contact area is greater than the etching rate of the transition layer on the non-contact area, so that the transition layer on the contact area is easily and quickly removed, and the etching loss of the side wall of the transition layer in the non-contact area exposed by the opening is small, thereby avoiding the undercut effect of the etching process and improving the performance of the semiconductor device.

[0076] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a contact area and a non-contact area, and the substrate comprising a substrate and an underlying dielectric layer located on the substrate, the underlying dielectric layer having a metal layer, and the material of the metal layer comprising copper; Forming a transition layer on the substrate, the transition layer being located on the metal layer and the underlying dielectric layer; modifying the transition layer on the contact area so that the material density of the transition layer on the contact area is less than the material density of the transition layer on the non-contact area; After the modification treatment, an interlayer dielectric layer is formed on the transition layer, wherein the interlayer dielectric layer has an opening, and the opening exposes the transition layer on the contact area; Using a wet etching process to etch and remove the transition layer at the bottom of the opening; The modification treatment includes a plasma treatment process, and the treatment gas used in the plasma treatment process includes any one or a combination of C4F8, CF4, CH4, N2, He and Ar; in the wet etching process, the etching selectivity ratio of the transition layer on the contact area to the transition layer on the non-contact area is greater than or equal to 3:1; A wet etching process is used to etch away the transition layer at the bottom of the opening until the surface of the metal layer is exposed. The wet etching process has an etching selectivity rate ratio of the transition layer to the metal layer greater than or equal to 5:

1. The chemical solution used in the wet etching process is hydrofluoric acid, phosphoric acid or nitric acid.

2. The method for forming a semiconductor device according to claim 1, wherein: The material of the transition layer includes SiO, SiOC, SiC, TiO2, AlO, SiN, HfO2 or polysilicon.

3. The method for forming a semiconductor device according to claim 1, wherein: The interlayer dielectric layer is made of a low dielectric constant material.

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