Semiconductor device including gate spacers

Abstract

A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region at a location in the first active region adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0042140 entitled "Semiconductor Devices Including Gate Spacer", filed on April 7, 2020, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to semiconductor devices including gate spacers and methods for forming the same. Background Technology

[0004] With the trend towards high integration in semiconductor devices, technologies using gate spacers and alternative gate electrodes have been developed. The shape of the gate spacer has a significant impact on the process of forming the alternative gate electrode. Summary of the Invention

[0005] An exemplary embodiment of the present disclosure may include a first active region defined on a substrate. A first gate electrode may be disposed across the first active region. A first drain region may be disposed in the first active region adjacent to the first gate electrode. An undercut region may be disposed between the first active region and the first gate electrode. A first gate spacer may be disposed on a side surface of the first gate electrode and may extend into the undercut region.

[0006] An exemplary embodiment of the present disclosure may include: a first active region defined in a first region on a substrate. A first gate electrode may be disposed across the first active region in the first active region. A first drain region may be disposed in the first active region at a location adjacent to the first gate electrode. A first gate spacer may be disposed on a side surface of the first gate electrode. A second active region may be defined in a second region on the substrate. A second gate electrode may be disposed across the second active region in the second active region and may have a horizontal width different from the horizontal width of the first gate electrode. A second drain region may be disposed in the second active region at a location adjacent to the second gate electrode. A lower gate dielectric layer may be disposed between the second active region and the second gate electrode and may have a width smaller than the width of the second gate electrode. The second gate spacer may be disposed on a side surface of the second gate electrode and may extend in an undercut region between the second active region and the second gate electrode. The second gate spacer may contact a side surface of the lower gate dielectric layer.

[0007] An exemplary embodiment of the present disclosure may include: a first active region defined in a first region on a substrate. A first gate electrode may be disposed across the first active region on the first active region. A first gate dielectric layer may be disposed between the first active region and the first gate electrode. A pair of first drain regions may be disposed in the first active region at positions adjacent to opposite sides of the first gate electrode and may be spaced apart from each other. An undercut region may be disposed between the first active region and the first gate electrode. A first gate spacer may be disposed on a side surface of the first gate electrode and may extend into the undercut region. A second active region may be defined in a second region on the substrate. A second gate electrode may be disposed across the second active region on the second active region and may have a horizontal width greater than the horizontal width of the first gate electrode. A second gate dielectric layer may be disposed between the second active region and the second gate electrode. A pair of second drain regions may be disposed in the second active region at positions adjacent to opposite sides of the second gate electrode and may be spaced apart from each other. A lower gate dielectric layer may be disposed between the second active region and the second gate dielectric layer and may have a horizontal width greater than the horizontal width of the second gate electrode. A second gate spacer may be disposed on the side surface of the second gate electrode. The first active region may include multiple channel regions. Each of the multiple channel regions may contact the pair of first drain regions. The first gate electrode may surround the top, side, and bottom surfaces of at least one of the multiple channel regions. The second gate electrode may be disposed on the top and side surfaces of the second active region. The lower end of the second gate electrode may be disposed at a lower level than the upper end of the second active region.

[0008] A method of forming a semiconductor device according to an exemplary embodiment of the present disclosure may include: defining a first active region and a second active region on a substrate. A first gate electrode may be formed on the first active region across the first active region, and a second gate electrode may be formed on the second active region across the second active region. A first drain region may be formed in the first active region at a location adjacent to the first gate electrode, and a second drain region may be formed in the second active region at a location adjacent to the second gate electrode. A first gate spacer may be formed on a side surface of the first gate electrode. A lower gate dielectric layer is formed between the second active region and the second gate electrode. A second gate spacer may be formed on a side surface of the second gate electrode. The first gate spacer may extend in an undercut region between the first active region and the first gate electrode. Attached Figure Description

[0009] The features will become clear to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 This is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0011] Figure 2This illustrates the layout of a semiconductor device according to exemplary embodiments of the present disclosure.

[0012] Figures 3 to 5 yes Figure 1 An enlarged view of the portion shown.

[0013] Figures 6 to 13 This is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0014] Figures 14 to 57 This is a cross-sectional view of a stage in a method for forming a semiconductor device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0015] Figure 1 This shows a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure, and Figure 2 This illustrates the layout of a semiconductor device according to exemplary embodiments of the present disclosure. Figures 3 to 5 yes Figure 1 An enlarged view of the portion shown. Figure 1 It shows along Figure 2 The cross-sectional views are taken from lines 1-1', 2-2', 3-3', 4-4', and 5-5'. A semiconductor device according to exemplary embodiments of this disclosure may include... FinFET or a combination thereof.

[0016] Reference Figure 1 The semiconductor device according to exemplary embodiments of the present disclosure may include a substrate 20, a first active region 21, a second active region 22, a device isolation layer 25, a lower gate dielectric layer 28, a first gate spacer 41, a second gate spacer 42, a plurality of first drain regions 47, a plurality of second drain regions 48, an interlayer insulating layer 49, a first gate dielectric layer 53, a second gate dielectric layer 54, a plurality of first gate electrodes 55, and a plurality of second gate electrodes 56.

[0017] The first active region 21 may include multiple channel regions 21A, 21B, 21C, and 21D. The multiple channel regions 21A, 21B, 21C, and 21D may include a first channel region 21A, a second channel region 21B, a third channel region 21C, and a fourth channel region 21D. The first gate spacer 41 may include a first inner spacer 41A and a first outer spacer 41B. The second gate spacer 42 may include a second inner spacer 42A and a second outer spacer 42B. Each of the multiple first drain regions 47 may include a first layer 47A and a second layer 47B. Each of the multiple second drain regions 48 may include a third layer 48A and a fourth layer 48B.

[0018] Reference Figure 2The substrate 20 may be configured to have a first region 11 and a second region 12 adjacent to the first region 11. A first active region 21 may be disposed in the first region 11 on the substrate 20. A second active region 22 may be disposed in the second region 12 on the substrate 20. A plurality of first gate electrodes 55 may be disposed across the first active region 21 in the first region 11. A plurality of second gate electrodes 56 may be disposed across the second active region 22 in the second region 12.

[0019] Each of the plurality of second gate electrodes 56 may have a horizontal width different from that of each of the plurality of first gate electrodes 55. Each of the plurality of second gate electrodes 56 may have a horizontal width greater than that of each of the plurality of first gate electrodes 55. Each of the plurality of first gate electrodes 55 may have a first width W1. Each of the plurality of second gate electrodes 56 may have a second width W2. The second width W2 may be greater than the first width W1.

[0020] The reference shows the line 1-1′. Figure 1 The amplified portion Figure 3 A first gate dielectric layer 53 may be disposed between the first gate electrode 55 and the plurality of channel regions 21A, 21B, 21C, and 21D. The first gate dielectric layer 53 may extend between the first gate electrode 55 and the first gate spacer 41. An interface dielectric layer 51 may be disposed between the first gate dielectric layer 53 and the plurality of channel regions 21A, 21B, 21C, and 21D. The interface dielectric layer 51 may include silicon oxide formed by a thermal oxidation process or a cleaning process. The interface dielectric layer 51 may be omitted. In an exemplary embodiment, the first gate dielectric layer 53 may be located between the first gate electrode 55 and the interface dielectric layer 51.

[0021] A pair of first drain regions 47 may be disposed in the first active region 21 at a position adjacent to the opposite side of the first gate electrode 55. The pair of first drain regions 47 may be spaced apart from each other. Each of the plurality of channel regions 21A, 21B, 21C and 21D may contact the pair of first drain regions 47.

[0022] The first undercut region UC1 can be located between the first active region 21 and the first gate electrode 55. For example, as Figure 3 As shown, the bottom of the first gate electrode 55 may have a stepped profile at its bottom corner. For example, the central portion of the bottom of the first gate electrode 55 may extend deeper than the edge portion of the bottom of the first gate electrode 55 to define the stepped profile, so that the undercut region UC1 may be defined below the edge portion of the bottom of the first gate electrode 55.

[0023] The first gate spacer 41 may include a first inner spacer 41A and a first outer spacer 41B. The first inner spacer 41A may include an upper portion 411 disposed on a side surface of the first gate electrode 55; and a lower portion 412 extending from the lower end of the first upper portion 411 (e.g., continuously) into the first undercut region UC1. The lower portion 412 may extend between the first active region 21 and the first gate electrode 55, for example, between the edge portion of the first active region 21 and the bottom of the first gate electrode 55. A straight line (e.g., an imaginary line) extending along the outermost surface of the first gate electrode 55 and perpendicular to the surface of the substrate 20 may intersect the lower portion 412. The height of the upper portion 411 may be greater than the horizontal width of the upper portion 411. The horizontal width of the lower part 412 may be greater than the height of the lower part 412. For example, the upper part 411 and the lower part 412 may have an inverted "T" combined cross section that extends along the outermost surface of the first gate electrode 55 and protrudes into the first undercut region UC1 to partially overlap with the edge portion of the bottom of the first gate electrode 55.

[0024] The first gate dielectric layer 53 may be located between the first gate electrode 55 and the upper portion 411, and between the first gate electrode 55 and the lower portion 412. The first gate dielectric layer 53 may contact the side surface and top surface of the lower portion 412. The first gate dielectric layer 53 may contact the side surface of the upper portion 411; for example, the first gate dielectric layer 53 may be conformal to the outer surface of the first gate electrode 55.

[0025] The reference shows the line 2-2′. Figure 1 The amplified portion Figure 4 The interface dielectric layer 51 can cover the top and side surfaces of the first channel region 21A. The interface dielectric layer 51 can surround the top, bottom, and side surfaces of the second channel region 21B, the third channel region 21C, and the fourth channel region 21D. The first gate electrode 55 can surround the top, bottom, and side surfaces of the second channel region 21B, the third channel region 21C, and the fourth channel region 21D. The first gate electrode 55 can cover the top and side surfaces of the first channel region 21A. The first gate dielectric layer 53 can be disposed between the first gate electrode 55 and the interface dielectric layer 51. The interface dielectric layer 51 can be omitted.

[0026] The reference shows the line 4-4'. Figure 1 The amplified portion Figure 5A pair of second drain regions 48 may be disposed in the second active region 22 at a position adjacent to the second gate electrode 56. The pair of second drain regions 48 may be spaced apart from each other. A second gate dielectric layer 54 may be disposed between the second gate electrode 56 and the second active region 22. A lower gate dielectric layer 28 may be disposed between the second gate dielectric layer 54 and the second active region 22. A second gate spacer 42 may be disposed on the side surface of the second gate electrode 56. The second gate dielectric layer 54 may extend between the second gate electrode 56 and the second gate spacer 42.

[0027] The lower gate dielectric layer 28 may have a horizontal width greater than the horizontal width of the second gate electrode 56. The lower gate dielectric layer 28 may (e.g., in the horizontal direction) protrude beyond the second gate electrode 56. The second gate spacer 42 may contact the top and side surfaces of the lower gate dielectric layer 28. The second gate spacer 42 may include a second inner spacer 42A and a second outer spacer 42B. The second inner spacer 42A may contact the top and side surfaces of the lower gate dielectric layer 28. In an exemplary embodiment, the second gate dielectric layer 54 may be disposed on the lower gate dielectric layer 28.

[0028] Refer again Figures 1 to 5 A first active region 21 and a second active region 22 may be defined on the substrate 20. A first gate electrode 55 may be disposed across the first active region 21. A first drain region 47 may be disposed in the first active region 21 at a position adjacent to the first gate electrode 55. A first undercut region UC1 may be disposed between the first active region 21 and the first gate electrode 55. A first gate spacer 41 may be disposed on a side surface of the first gate electrode 55 and may extend into the first undercut region UC1. The first gate spacer 41 may have, for example, an inverted T-shape or an L-shape.

[0029] The second gate electrode 56 may be disposed across the second active region 22. The second drain region 48 may be disposed in the second active region 22 at a position adjacent to the second gate electrode 56. The lower gate dielectric layer 28 may be disposed between the second active region 22 and the second gate electrode 56. The second gate spacer 42 may be disposed on the side surface of the second gate electrode 56. The second gate electrode 56 may be disposed on the top surface and side surface of the second active region 22. The lower end of the second gate electrode 56 may be disposed at a level lower than the upper end of the second active region 22. The second gate electrode 56 may have a horizontal width greater than the horizontal width of the first gate electrode 55. In an exemplary embodiment, the lower portion 412 of the first inner spacer 41A may (e.g., in the vertical direction) have a thickness substantially the same as the lower gate dielectric layer 28.

[0030] Figures 6 to 13 This is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the present disclosure. Figures 6 to 13 It is along Figure 2The cross-sectional views taken from lines 1-1', 2-2', 3-3', 4-4', and 5-5'.

[0031] Reference Figure 6 The first active region 21 may include a first notch 21N, which is disposed adjacent to the top surface of the device isolation layer 25. The second active region 22 may include a second notch 22N, which is disposed adjacent to the top surface of the device isolation layer 25.

[0032] Reference Figure 7 The second active region 22 may include multiple semiconductor layers 22A, 23A, 22B, 23B, 22C, 23C, and 22D. The multiple semiconductor layers 22A, 23A, 22B, 23B, 22C, 23C, and 22D may include a first semiconductor layer 22A, a second semiconductor layer 23A, a third semiconductor layer 22B, a fourth semiconductor layer 23B, a fifth semiconductor layer 22C, a sixth semiconductor layer 23C, and a seventh semiconductor layer 22D stacked sequentially. The first semiconductor layer 22A may be confined within the second active region 22. The first semiconductor layer 22A may include a semiconductor layer such as a single-crystal silicon layer.

[0033] Each of the second semiconductor layer 23A, the third semiconductor layer 22B, the fourth semiconductor layer 23B, the fifth semiconductor layer 22C, the sixth semiconductor layer 23C, and the seventh semiconductor layer 22D may include a single-crystal semiconductor layer formed by epitaxial growth. In an exemplary embodiment, each of the third semiconductor layer 22B, the fifth semiconductor layer 22C, and the seventh semiconductor layer 22D may include a single-crystal silicon layer. Each of the second semiconductor layer 23A, the fourth semiconductor layer 23B, and the sixth semiconductor layer 23C may include a single-crystal SiGe layer.

[0034] Reference Figure 8 Multiple blocking patterns 59 may be disposed between multiple first drain regions 47 and multiple first gate electrodes 55. The multiple blocking patterns 59 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In an exemplary embodiment, the multiple blocking patterns 59 may include silicon nitride. The multiple blocking patterns 59 may be disposed between multiple channel regions 21A, 21B, 21C, and 21D. The multiple blocking patterns 59 may be located between the first layer 47A and the first gate dielectric layer 53.

[0035] Reference Figure 9The intermediate gate dielectric layer 128 may be disposed on the lower gate dielectric layer 28. The second gate dielectric layer 54 may be disposed on the intermediate gate dielectric layer 128. The intermediate gate dielectric layer 128 may include a material with etch selectivity relative to the lower gate dielectric layer 28. The intermediate gate dielectric layer 128 may include a material different from the lower gate dielectric layer 28. The intermediate gate dielectric layer 128 may have a horizontal width greater than the horizontal width of the second gate electrode 56. The intermediate gate dielectric layer 128 may protrude beyond the second gate electrode 56. The second inner spacer 42A may contact the top surface of the intermediate gate dielectric layer 128.

[0036] Reference Figure 10 The first gate spacer 41 can have various thicknesses and shapes. In an exemplary embodiment, the portion of the first gate spacer 41 located between the first gate electrode 55 and the first active region 21 can be thicker than the lower gate dielectric layer 28. The outermost part of the lower gate dielectric layer 28 can be aligned between the second gate spacer 42 and the second gate electrode 56.

[0037] Reference Figure 11 The portion of the first gate spacer 41 located between the first gate electrode 55 and the first active region 21 may have substantially the same thickness as the lower gate dielectric layer 28. The outermost part of the lower gate dielectric layer 28 may be aligned between the second gate spacer 42 and the second gate electrode 56.

[0038] Reference Figure 12 The lower gate dielectric layer 28 may have a horizontal width smaller than that of the second gate electrode 56. The second gate spacer 42 may extend within the second undercut region UC2 between the second active region 22 and the second gate electrode 56. The second gate spacer 42 may have an L-shape. In an exemplary embodiment, the second inner spacer 42A may extend within the second undercut region UC2. The second inner spacer 42A may have an L-shape. The second inner spacer 42A may contact the side surface of the lower gate dielectric layer 28.

[0039] Reference Figure 13 The first gate spacer 41 can be disposed on the side surface of the first gate electrode 55. The first gate dielectric layer 53 can be disposed between the first gate electrode 55 and the first active region 21, and also between the first gate electrode 55 and the first gate spacer 41. The first undercut region can be omitted. Figure 3 UC1 in the middle.

[0040] The lower gate dielectric layer 28 may have a smaller horizontal width than the horizontal width of the second gate electrode 56. The second gate spacer 42 may extend within the second undercut region UC2 between the second active region 22 and the second gate electrode 56. The second gate spacer 42 may have an L-shape. The second gate spacer 42 may contact the side surface of the lower gate dielectric layer 28.

[0041] Figures 14 to 27 This is a cross-sectional view of a stage in a method for forming a semiconductor device according to an exemplary embodiment of the present disclosure. Figures 14 to 27 It is along Figure 2 Cross-sectional views of lines 1-1', 2-2', 3-3', 4-4', and 5-5'.

[0042] Reference Figure 2 and Figure 14 A device isolation layer 25 can be formed on the substrate 20 to define a first active region 21 and a second active region 22. The first active region 21 can be formed in a first region 11 on the substrate 20. The second active region 22 can be formed in a second region 12 on the substrate 20. The first active region 21 may include a plurality of channel regions 21A, 21B, 21C, and 21D. A plurality of sacrificial layers 23 can be formed between the plurality of channel regions 21A, 21B, 21C, and 21D. The plurality of channel regions 21A, 21B, 21C, and 21D and the plurality of sacrificial layers 23 can be stacked alternately and repeatedly. The plurality of channel regions 21A, 21B, 21C, and 21D may include a first channel region 21A, a second channel region 21B, a third channel region 21C, and a fourth channel region 21D.

[0043] Substrate 20 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The height of each of the first active region 21 and the second active region 22 may (e.g., vertically) be greater than its horizontal width. Forming a plurality of channel regions 21A, 21B, 21C, and 21D, and a plurality of sacrificial layers 23 may include an epitaxial growth process. In an exemplary embodiment, the plurality of sacrificial layers 23 may include SiGe layers formed by epitaxial growth. Each of the second channel region 21B, the third channel region 21C, and the fourth channel region 21D may include a silicon layer formed by epitaxial growth. The first channel region 21A may be defined in substrate 20. The first channel region 21A may include a single-crystal silicon layer. The second active region 22 may be defined in substrate 20. The second active region 22 may include a single-crystal silicon layer.

[0044] The device isolation layer 25 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof. The top surface of the device isolation layer 25 may be formed at a lower level than the top surfaces of the first active region 21 and the second active region 22. The upper ends of the first active region 21 and the second active region 22 may protrude to a higher level than the top surface of the device isolation layer 25. The upper corners of the first active region 21 and the second active region 22 may be rounded.

[0045] Reference Figure 2 and Figure 15A buffer layer 27 and a lower gate dielectric layer 28 can be formed on the substrate 20. In an exemplary embodiment, the buffer layer 27 and the lower gate dielectric layer 28 can be formed simultaneously. The buffer layer 27 and the lower gate dielectric layer 28 can have substantially the same thickness. The buffer layer 27 and the lower gate dielectric layer 28 can include an insulating material, such as silicon oxide. The buffer layer 27 can cover the first active region 21. The lower gate dielectric layer 28 can cover the second active region 22.

[0046] Reference Figure 2 and Figure 16 A first mask pattern 29 can be formed to cover the buffer layer 27 and expose the lower gate dielectric layer 28. Nitrogen can be implanted into the lower gate dielectric layer 28. In an exemplary embodiment, implanting nitrogen into the lower gate dielectric layer 28 may include a decoupled plasma nitriding (DPN) process, a post-nitriding annealing (PNA) process, or a combination thereof. The first mask pattern 29 can be used to prevent nitrogen from being implanted into the buffer layer 27 during the process of implanting nitrogen into the lower gate dielectric layer 28.

[0047] Reference Figure 2 and Figure 17 The buffer layer 27 can be exposed by removing the first mask pattern 29. A plurality of first temporary gate electrodes 31 can be formed on the buffer layer 27 across the first active region 21. A second mask pattern 33 can be formed on the plurality of first temporary gate electrodes 31. A plurality of second temporary gate electrodes 32 can be formed on the lower gate dielectric layer 28 across the second active region 22. A third mask pattern 34 can be formed on the plurality of second temporary gate electrodes 32.

[0048] In an exemplary embodiment, the plurality of first temporary gate electrodes 31 and the plurality of second temporary gate electrodes 32 may include a polysilicon layer. The second mask pattern 33 and the third mask pattern 34 may include silicon nitride. Forming the plurality of first temporary gate electrodes 31 and the plurality of second temporary gate electrodes 32 may include an anisotropic etching process using the second mask pattern 33 and the third mask pattern 34 as etching masks. The buffer layer 27 between the plurality of first temporary gate electrodes 31 may be partially etched, and the thickness of the buffer layer 27 between the plurality of first temporary gate electrodes 31 may be reduced. The lower gate dielectric layer 28 between the plurality of second temporary gate electrodes 32 may be partially etched, and the thickness of the lower gate dielectric layer 28 between the plurality of second temporary gate electrodes 32 may be reduced.

[0049] Reference Figure 2 and Figure 18 A spacer layer 36L can be formed on the top and side surfaces of the buffer layer 27, the lower gate dielectric layer 28, the plurality of first temporary gate electrodes 31, the plurality of second temporary gate electrodes 32, the second mask pattern 33, and the third mask pattern 34. A fourth mask pattern 35 can be formed on the spacer layer 36L to cover the first region 11 and expose the second region 12.

[0050] Sacrificial spacers 36 can be formed on the sidewalls of a plurality of second temporary gate electrodes 32 and a third mask pattern 34 by anisotropically etching the spacer layer 36L. The sacrificial spacers 36 may comprise silicon nitride. A second active region 22 may be exposed to the exterior of the sacrificial spacer 36. The bottom of the sacrificial spacer 36 may contact the top surface of the lower gate dielectric layer 28. The sacrificial spacer 36 may contact the side surfaces of the plurality of second temporary gate electrodes 32 and the third mask pattern 34.

[0051] Reference Figure 2 and Figure 19 The spacer layer 36L can be exposed by removing the fourth mask pattern 35. A fifth mask pattern 38 can be formed to cover the second region 12 and expose the first region 11. The spacer layer 36L can be removed.

[0052] Reference Figure 2 and Figure 20 This can remove the fifth mask pattern 38.

[0053] Reference Figure 2 and Figure 21 By partially removing the buffer layer 27, the first active region 21 can be exposed between the plurality of first temporary gate electrodes 31. The buffer layer 27 can remain between the plurality of first temporary gate electrodes 31 and the first active region 21. The horizontal width of the buffer layer 27 can be smaller than the horizontal width of each of the plurality of first temporary gate electrodes 31. A first undercut region UC1 can be formed below the plurality of first temporary gate electrodes 31. In an exemplary embodiment, the first undercut region UC1 can be formed between the plurality of first temporary gate electrodes 31 and the first active region 21.

[0054] The sidewalls of the plurality of second temporary gate electrodes 32 and the third mask pattern 34 can be exposed by removing the sacrificial spacer 36. The horizontal width of the lower gate dielectric layer 28 can be greater than the horizontal width of a corresponding one of the plurality of second temporary gate electrodes 32. The lower gate dielectric layer 28 can protrude beyond a corresponding one of the plurality of second temporary gate electrodes 32.

[0055] Reference Figure 2 and Figure 22 A first gate spacer 41 can be formed on the sidewalls of a plurality of first temporary gate electrodes 31 and a second mask pattern 33. A second gate spacer 42 can be formed on the sidewalls of a plurality of second temporary gate electrodes 32 and a third mask pattern 34. The first gate spacer 41 may include a first inner spacer 41A and a first outer spacer 41B. The second gate spacer 42 may include a second inner spacer 42A and a second outer spacer 42B. In an exemplary embodiment, the first inner spacer 41A and the second inner spacer 42A may include silicon nitride. The first outer spacer 41B and the second outer spacer 42B may include silicon oxide or silicon oxynitride.

[0056] A first inner spacer 41A can be formed on the sidewalls of the plurality of first temporary gate electrodes 31 and the second mask pattern 33. The first inner spacer 41A can extend in the first undercut region UC1. The first inner spacer 41A can contact the bottom surface of the plurality of first temporary gate electrodes 31 and the first active region 21. The first inner spacer 41A can contact the side surface of the buffer layer 27. A first outer spacer 41B can be formed on the outer surface of the first inner spacer 41A.

[0057] A second inner spacer 42A may be formed on the sidewalls of the plurality of second temporary gate electrodes 32 and the third mask pattern 34. The second inner spacer 42A may contact the side surface and top surface of the lower gate dielectric layer 28. A second outer spacer 42B may be formed on the outer surface of the second inner spacer 42A.

[0058] Reference Figure 2 and Figure 23 Multiple first trenches 43 can be formed in the first active region 21 between multiple first temporary gate electrodes 31. Multiple second trenches 44 can be formed in the second active region 22 between multiple second temporary gate electrodes 32.

[0059] Reference Figure 2 and Figure 24 A plurality of first drain regions 47 can be formed in a plurality of first trenches 43, and a plurality of second drain regions 48 can be formed in a plurality of second trenches 44. Each of the plurality of first drain regions 47 may include a first layer 47A and a second layer 47B disposed on the first layer 47A. Each of the plurality of second drain regions 48 may include a third layer 48A and a fourth layer 48B disposed on the third layer 48A. The upper ends of the plurality of first drain regions 47 may protrude to a level higher than the upper end of the first active region 21. The upper ends of the plurality of second drain regions 48 may protrude to a level higher than the upper end of the second active region 22.

[0060] Each of a plurality of first drain regions 47 and a plurality of second drain regions can be formed using selective epitaxial growth (SEG). Each of the plurality of first drain regions 47 and the plurality of second drain regions 48 may comprise SiGe, Si, SiC, or a combination thereof. In an exemplary embodiment, each of the first layer 47A and the third layer 48A may comprise a Si layer, and each of the second layer 47B and the fourth layer 48B may comprise a SiGe layer. In an exemplary embodiment, the first layer 47A may comprise a SiGe layer having a lower Ge density than the second layer 47B. The third layer 48A may comprise a SiGe layer having a lower Ge density than the fourth layer 48B.

[0061] Reference Figure 2 and Figure 25An interlayer insulating layer 49 may be formed on a plurality of first drain regions 47 and a plurality of second drain regions 48. The interlayer insulating layer 49 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof. In an exemplary embodiment, the interlayer insulating layer 49 may include silicon oxide.

[0062] By removing the second mask pattern 33 and the third mask pattern 34 using a planarization process, the top surfaces of a plurality of first temporary gate electrodes 31 and a plurality of second temporary gate electrodes 32 can be exposed. The planarization process may include a chemical mechanical polishing (CMP) process.

[0063] Reference Figure 2 and Figure 26 The first gate trench 31T can be formed by removing multiple first temporary gate electrodes 31 and buffer layer 27. The second gate trench 32T can be formed by removing multiple second temporary gate electrodes 32.

[0064] Reference Figure 2 and Figure 27 Multiple gap regions 21G can be formed by removing multiple sacrificial layers 23. The multiple gap regions 21G can communicate with the first gate trench 31T. Multiple first drain regions 47 can be exposed within the multiple gap regions 21G.

[0065] The first inner spacer 41A can be used to prevent damage to the multiple first drain regions 47 during the process of removing the multiple sacrificial layers 23. The second inner spacer 42A and the lower gate dielectric layer 28 can be used to prevent damage to the multiple second drain regions 48 and the second active region 22 during the process of removing the multiple sacrificial layers 23.

[0066] Refer again Figure 1 and Figure 2 A first gate dielectric layer 53 can be formed on the inner walls of the first gate trench 31T and the plurality of gap regions 21G. A second gate dielectric layer 54 can be formed on the inner wall of the second gate trench 32T. A first gate electrode 55 can be formed on the first gate dielectric layer 53 to fill the first gate trench 31T. A second gate electrode 56 can be formed on the second gate dielectric layer 54 to fill the second gate trench 32T.

[0067] Each of the first gate dielectric layer 53 and the second gate dielectric layer 54 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof. In an exemplary embodiment, each of the first gate dielectric layer 53 and the second gate dielectric layer 54 may include a high-k dielectric, for example, a metal oxide. Each of the first gate electrode 55 and the second gate electrode 56 may include, for example, a metal, a metal silicide, a metal nitride, a metal oxide, polysilicon, conductive carbon, or a combination thereof. In an exemplary embodiment, each of the first gate electrode 55 and the second gate electrode 56 may include, for example, a work function metal.

[0068] Figures 28 to 30 This is a cross-sectional view showing a stage in a method of forming a semiconductor device according to an exemplary embodiment of the present disclosure. Figures 28 to 30 It is along Figure 2 Cross-sectional views of lines 1-1', 2-2', 3-3', 4-4', and 5-5' are shown below. The differences will be described only briefly in the following text.

[0069] Reference Figure 2 and Figure 28 This can form a fifth mask pattern 38 to cover the second region 12 and expose the first region 11.

[0070] Reference Figure 2 and Figure 29 A first undercut region UC1 can be formed below a plurality of first temporary gate electrodes 31 by partially removing the buffer layer 27.

[0071] Reference Figure 2 and Figure 30 This allows the removal of the fifth mask pattern 38. Subsequently, it can be compared with a reference... Figures 22 to 27 Semiconductor devices are formed in a similar manner to those described above.

[0072] Figure 31 and Figure 32 This is a cross-sectional view showing a stage in a method of forming a semiconductor device according to an exemplary embodiment of the present disclosure. Figure 31 and Figure 32 It is along Figure 2 Cross-sectional views of lines 1-1', 2-2', 3-3', 4-4', and 5-5'.

[0073] Reference Figure 2 and Figure 31 A temporary buffer layer 27A and a lower gate dielectric layer 28 can be formed. In an exemplary embodiment, the temporary buffer layer 27A can be formed simultaneously with the lower gate dielectric layer 28 using the same process as the lower gate dielectric layer 28, and the temporary buffer layer 27A may include substantially the same material as the lower gate dielectric layer 28. The temporary buffer layer 27A and the lower gate dielectric layer 28 may include, for example, silicon oxynitride or silicon nitride.

[0074] Reference Figure 2 and Figure 32A fifth mask pattern 38 can be formed to cover the lower gate dielectric layer 28 and expose the temporary buffer layer 27A. The buffer layer 27 can be formed by removing nitrogen from the temporary buffer layer 27A using a surface modification process (e.g., a deslagging process). The nitrogen concentration in the buffer layer 27 can be lower than the nitrogen concentration in the lower gate dielectric layer 28. The buffer layer 27 can have etch selectivity relative to the lower gate dielectric layer 28. The buffer layer 27 can have a higher etch rate than the lower gate dielectric layer 28. The fifth mask pattern 38 can be removed. Subsequently, it can be compared with a reference... Figures 17 to 29 Semiconductor devices are formed in a similar manner to those described above.

[0075] Figures 33 to 37 This is a cross-sectional view showing a stage in a method of forming a semiconductor device according to an exemplary embodiment of the present disclosure. Figures 33 to 37 It is along Figure 2 Cross-sectional views of lines 1-1', 2-2', 3-3', 4-4', and 5-5'.

[0076] Reference Figure 2 and Figure 33 A sacrificial buffer layer 127 can be formed on the buffer layer 27. An intermediate gate dielectric layer 128 can be formed on the lower gate dielectric layer 28. The buffer layer 27 can be formed simultaneously with the lower gate dielectric layer 28 using the same process as the lower gate dielectric layer 28, and the buffer layer 27 can comprise substantially the same material as the lower gate dielectric layer 28. Similarly, the sacrificial buffer layer 127 can be formed simultaneously with the intermediate gate dielectric layer 128 using the same process as the intermediate gate dielectric layer 128, and the sacrificial buffer layer 127 can comprise substantially the same material as the intermediate gate dielectric layer 128.

[0077] In an exemplary embodiment, each of the buffer layer 27 and the lower gate dielectric layer 28 may include, for example, silicon oxide or silicon oxynitride. The sacrificial buffer layer 127 and the intermediate gate dielectric layer 128 may include materials different from those of the buffer layer 27 and the lower gate dielectric layer 28. The sacrificial buffer layer 127 and the intermediate gate dielectric layer 128 may include silicon oxynitride or silicon nitride.

[0078] refer to Figure 2 and Figure 34 A sixth mask pattern 138 can be formed to cover the intermediate gate dielectric layer 128. The sacrificial buffer layer 127 can be removed by an isotropic etching process to expose the buffer layer 27. The sixth mask pattern 138 can then be removed.

[0079] Reference Figure 2 and Figure 35 Multiple first temporary gate electrodes 31, multiple second temporary gate electrodes 32, a second mask pattern 33, and a third mask pattern 34 can be formed.

[0080] Reference Figure 2 and Figure 36 By partially removing the buffer layer 27, the first active region 21 can be exposed between the plurality of first temporary gate electrodes 31. The buffer layer 27 can remain between the plurality of first temporary gate electrodes 31 and the first active region 21. The horizontal width of the buffer layer 27 can be smaller than the horizontal width of each of the plurality of first temporary gate electrodes 31. A first undercut region UC1 can be formed below the plurality of first temporary gate electrodes 31. In an exemplary embodiment, the first undercut region UC1 can be formed between the plurality of first temporary gate electrodes 31 and the first active region 21. The intermediate gate dielectric layer 128 can be used to prevent etch damage to the lower gate dielectric layer 28 during the formation of the first undercut region UC1.

[0081] Reference Figure 2 and Figure 37 A first gate spacer 41 can be formed on the sidewalls of a plurality of first temporary gate electrodes 31 and a second mask pattern 33. A second gate spacer 42 can be formed on the sidewalls of a plurality of second temporary gate electrodes 32 and a third mask pattern 34. The first gate spacer 41 may include a first inner spacer 41A and a first outer spacer 41B. The second gate spacer 42 may include a second inner spacer 42A and a second outer spacer 42B.

[0082] The first inner spacer 41A can extend within the first undercut region UC1. The second inner spacer 42A can be formed on the sidewalls of the plurality of second temporary gate electrodes 32 and the third mask pattern 34. The lower end of the second inner spacer 42A can contact the top surface of the intermediate gate dielectric layer 128.

[0083] Refer again Figure 2 and Figure 9 The intermediate gate dielectric layer 128 may be retained on the lower gate dielectric layer 28. The second gate dielectric layer 54 may be formed on the intermediate gate dielectric layer 128. The horizontal width of the intermediate gate dielectric layer 128 may be greater than the horizontal width of the second gate electrode 56. The intermediate gate dielectric layer 128 may protrude beyond the second gate electrode 56.

[0084] Figures 38 to 42 This is a cross-sectional view showing a stage in a method of forming a semiconductor device according to an exemplary embodiment of the present disclosure. Figures 38 to 42 It is along Figure 2 Cross-sectional views of lines 1-1', 2-2', 3-3', 4-4', and 5-5'.

[0085] Reference Figure 2 and Figure 38A temporary buffer layer 27A and a temporary lower gate dielectric layer 28A can be formed. The temporary buffer layer 27A may be thicker than the temporary lower gate dielectric layer 28A. In an exemplary embodiment, the temporary buffer layer 27A and the temporary lower gate dielectric layer 28A may comprise the same material. The temporary buffer layer 27A and the temporary lower gate dielectric layer 28A may comprise silicon oxide.

[0086] Reference Figure 2 and Figure 39 The buffer layer 27 and the lower gate dielectric layer 28 can be formed by injecting nitrogen into the temporary buffer layer 27A and the temporary lower gate dielectric layer 28A. In an exemplary embodiment, injecting nitrogen into the temporary buffer layer 27A and the temporary lower gate dielectric layer 28A may include a decoupled plasma nitriding (DPN) process, a post-nitriding annealing (PNA) process, or a combination thereof.

[0087] Reference Figure 2 and Figure 40 Multiple first temporary gate electrodes 31, multiple second temporary gate electrodes 32, a second mask pattern 33, and a third mask pattern 34 can be formed.

[0088] Reference Figure 2 and Figure 41 By partially removing the buffer layer 27, the first active region 21 can be exposed between the plurality of first temporary gate electrodes 31. The buffer layer 27 can remain between the plurality of first temporary gate electrodes 31 and the first active region 21. A first undercut region UC1 can be formed below the plurality of first temporary gate electrodes 31.

[0089] During the formation of the first undercut region UC1, the lower gate dielectric layer 28 can be partially removed. The lower gate dielectric layer 28 can remain between the plurality of second temporary gate electrodes 32 and the second active region 22. Since the lower gate dielectric layer 28 is thinner than the buffer layer 27, the etching rate of the lower gate dielectric layer 28 between the plurality of second temporary gate electrodes 32 and the second active region 22 can be reduced during the formation of the first undercut region UC1. In an exemplary embodiment, the horizontal width of the lower gate dielectric layer 28 can be substantially the same as, or greater than, the horizontal width of an adjacent second temporary gate electrode among the plurality of second temporary gate electrodes 32.

[0090] Reference Figure 2 and Figure 42A first gate spacer 41 can be formed on the sidewalls of the plurality of first temporary gate electrodes 31 and the second mask pattern 33. A second gate spacer 42 can be formed on the sidewalls of the plurality of second temporary gate electrodes 32 and the third mask pattern 34. The first gate spacer 41 can have various thicknesses and shapes. In an exemplary embodiment, the portion of the first gate spacer 41 located between the plurality of first temporary gate electrodes 31 and the first active region 21 can be thicker than the lower gate dielectric layer 28. The outermost portion of the lower gate dielectric layer 28 can be aligned with the side surfaces of the plurality of second temporary gate electrodes 32. In an exemplary embodiment, the side surfaces of the lower gate dielectric layer 28 and the side surfaces of the plurality of second temporary gate electrodes 32 can form substantially the same plane.

[0091] Refer again Figure 2 and Figure 10 The portion of the first gate spacer 41 located between the first gate electrode 55 and the first active region 21 may be thicker than the lower gate dielectric layer 28. The outermost part of the lower gate dielectric layer 28 may be aligned between the second gate spacer 42 and the second gate electrode 56.

[0092] Figures 43 to 46 This is a cross-sectional view showing a stage in a method for forming a semiconductor device according to an exemplary embodiment of the present disclosure. Figures 38 to 46 It is along Figure 2 Cross-sectional views of lines 1-1', 2-2', 3-3', 4-4', and 5-5'.

[0093] Reference Figure 2 and Figure 43 A sacrificial buffer layer 127 can be formed on the buffer layer 27. A lower gate dielectric layer 28 can be formed on the second active region 22. In an exemplary embodiment, the sacrificial buffer layer 127 may include a material with etch selectivity relative to the buffer layer 27. The lower gate dielectric layer 28 can be formed simultaneously with the sacrificial buffer layer 127 using the same process, and the lower gate dielectric layer 28 may include substantially the same material as the sacrificial buffer layer 127. The buffer layer 27 may include silicon oxide or silicon oxynitride. The lower gate dielectric layer 28 and the sacrificial buffer layer 127 may include silicon oxynitride or silicon nitride.

[0094] Reference Figure 2 and Figure 44 Multiple first temporary gate electrodes 31, multiple second temporary gate electrodes 32, a second mask pattern 33, and a third mask pattern 34 can be formed.

[0095] Reference Figure 2 and Figure 45The first active region 21 can be exposed by partially removing the sacrificial buffer layer 127 and the buffer layer 27. The sacrificial buffer layer 127 can remain beneath the plurality of first temporary gate electrodes 31. The sacrificial buffer layer 127 can have a horizontal width substantially the same as that of adjacent first temporary gate electrodes 31 among the plurality of first temporary gate electrodes 31. A first undercut region UC1 can be formed beneath the sacrificial buffer layer 127. During the removal of the sacrificial buffer layer 127, the lower gate dielectric layer 28 can be partially removed to expose the second active region 22. The lower gate dielectric layer 28 can have a horizontal width substantially the same as that of adjacent second temporary gate electrodes 32 among the plurality of second temporary gate electrodes 32.

[0096] Reference Figure 2 and Figure 46 A first gate spacer 41 can be formed on the sidewalls of a plurality of first temporary gate electrodes 31 and a second mask pattern 33. A second gate spacer 42 can be formed on the sidewalls of a plurality of second temporary gate electrodes 32 and a third mask pattern 34.

[0097] Refer again Figure 2 and Figure 11 The outermost part of the lower gate dielectric layer 28 can be aligned between the second gate spacer 42 and the second gate electrode 56.

[0098] Figures 47 to 51 This is a cross-sectional view showing a stage in a method for forming a semiconductor device according to an exemplary embodiment of the present disclosure. Figures 47 to 51 It is along Figure 2 Cross-sectional views of lines 1-1', 2-2', 3-3', 4-4', and 5-5'.

[0099] Reference Figure 2 and Figure 47 Buffer layer 27 and sacrificial buffer layer 127 may be sequentially stacked on the first region 11 and the second region 12. Buffer layer 27 and sacrificial buffer layer 127 may cover the first active region 21 and the second active region 22. In an exemplary embodiment, sacrificial buffer layer 127 may include a material having etch selectivity relative to buffer layer 27. Buffer layer 27 may include silicon oxide or silicon oxynitride. Sacrificial buffer layer 127 may include silicon oxynitride or silicon nitride. A first mask pattern 29 may be formed to cover the first region 11 and expose the second region 12.

[0100] Reference Figure 2 and Figure 48 The buffer layer 27 can be exposed by removing the sacrificial buffer layer 127 in the second region 12.

[0101] Reference Figure 2 and Figure 49The sacrificial buffer layer 127 in the first region 11 can be exposed by removing the first mask pattern 29. The second active region 22 can be exposed by removing the buffer layer 27 in the second region 12.

[0102] Reference Figure 2 and Figure 50 The buffer layer 27 can be exposed by removing the sacrificial buffer layer 127 in the first region 11. The buffer layer 27 can cover the first active region 21.

[0103] Reference Figure 2 and Figure 51 An upper buffer layer 227 can be formed on the buffer layer 27 in the first region 11. A lower gate dielectric layer 28 can be formed on the second active region 22. The lower gate dielectric layer 28 can be formed simultaneously with the upper buffer layer 227 using the same process as the upper buffer layer 227, and the lower gate dielectric layer 28 can include substantially the same material as the upper buffer layer 227.

[0104] Subsequently, it can be used as a reference. Figures 38 to 46 Semiconductor devices are formed in a similar manner to those described above.

[0105] Figures 52 to 54 This is a cross-sectional view showing a stage in a method for forming a semiconductor device according to an exemplary embodiment of the present disclosure. Figures 52 to 54 It is along Figure 2 Cross-sectional views of lines 1-1', 2-2', 3-3', 4-4', and 5-5'.

[0106] Reference Figure 2 and Figure 52 The following structures can be formed: a buffer layer 27, a lower gate dielectric layer 28, a plurality of first temporary gate electrodes 31, a plurality of second temporary gate electrodes 32, a second mask pattern 33, and a third mask pattern 34. The lower gate dielectric layer 28 can be formed simultaneously with the buffer layer 27 using the same process as the buffer layer 27, and the lower gate dielectric layer 28 may include substantially the same material as the buffer layer 27.

[0107] Reference Figure 2 and Figure 53 By partially removing the buffer layer 27, a first active region 21 can be exposed between the plurality of first temporary gate electrodes 31. The horizontal width of the buffer layer 27 can be smaller than the horizontal width of each of the plurality of first temporary gate electrodes 31. A first undercut region UC1 can be formed below the plurality of first temporary gate electrodes 31.

[0108] By partially removing the lower gate dielectric layer 28, a second active region 22 can be exposed between the plurality of second temporary gate electrodes 32. The lower gate dielectric layer 28 can remain between the plurality of second temporary gate electrodes 32 and the second active region 22. The horizontal width of the lower gate dielectric layer 28 can be smaller than the horizontal width of each of the plurality of second temporary gate electrodes 32. A second undercut region UC2 can be formed below the plurality of second temporary gate electrodes 32. In an exemplary embodiment, the second undercut region UC2 can be formed between the plurality of second temporary gate electrodes 32 and the second active region 22. The formation of the first undercut region UC1 and the second undercut region UC2 can be performed simultaneously using the same process.

[0109] Reference Figure 2 and Figure 54 A first gate spacer 41 can be formed on the sidewalls of a plurality of first temporary gate electrodes 31 and a second mask pattern 33. A second gate spacer 42 can be formed on the sidewalls of a plurality of second temporary gate electrodes 32 and a third mask pattern 34. The first gate spacer 41 may include a first inner spacer 41A and a first outer spacer 41B. The second gate spacer 42 may include a second inner spacer 42A and a second outer spacer 42B. In an exemplary embodiment, the second gate spacer 42 may have a shape similar to that of the first gate spacer 41.

[0110] A second inner spacer 42A may be formed on the sidewalls of the plurality of second temporary gate electrodes 32 and the third mask pattern 34. The second inner spacer 42A may extend in the second undercut region UC2. The second inner spacer 42A may contact the bottom surface of the plurality of second temporary gate electrodes 32 and the second active region 22. The second inner spacer 42A may contact the side surface of the lower gate dielectric layer 28.

[0111] Refer again Figure 2 and Figure 12 The first gate spacer 41 can extend in the first undercut region UC1 between the first active region 21 and the first gate electrode 55. The horizontal width of the lower gate dielectric layer 28 can be smaller than the horizontal width of the second gate electrode 56. The second gate spacer 42 can extend in the second undercut region UC2 between the second active region 22 and the second gate electrode 56.

[0112] Figures 55 to 57 This is a cross-sectional view showing a stage in a method of forming a semiconductor device according to an exemplary embodiment of the present disclosure. Figures 55 to 57 It is along Figure 2 Cross-sectional views of lines 1-1', 2-2', 3-3', 4-4', and 5-5'.

[0113] Reference Figure 2 and Figure 55It can form a buffer layer 27, a lower gate dielectric layer 28, multiple first temporary gate electrodes 31, multiple second temporary gate electrodes 32, a second mask pattern 33, and a third mask pattern 34.

[0114] The first active region 21 may be exposed between the plurality of first temporary gate electrodes 31. A buffer layer 27 may be retained between the plurality of first temporary gate electrodes 31 and the first active region 21. The buffer layer 27 may have a horizontal width substantially the same as that of adjacent first temporary gate electrodes 31 among the plurality of first temporary gate electrodes 31. The side surfaces of the buffer layer 27 and the side surfaces of the plurality of first temporary gate electrodes 31 may form substantially the same plane.

[0115] The second active region 22 may be exposed between the plurality of second temporary gate electrodes 32. A lower gate dielectric layer 28 may be retained between the plurality of second temporary gate electrodes 32 and the second active region 22. The lower gate dielectric layer 28 may have a substantially the same horizontal width as adjacent second temporary gate electrodes 32 among the plurality of second temporary gate electrodes 32. The side surfaces of the lower gate dielectric layer 28 and the side surfaces of the plurality of second temporary gate electrodes 32 may form substantially the same plane.

[0116] Reference Figure 2 and Figure 56 The fourth mask pattern 35 can be formed to cover the first region 11. A second undercut region UC2 can be formed below the plurality of second temporary gate electrodes 32 by partially removing the lower gate dielectric layer 28. The horizontal width of the lower gate dielectric layer 28 can be smaller than the horizontal width of each of the plurality of second temporary gate electrodes 32. In an exemplary embodiment, the second undercut region UC2 can be formed between the plurality of second temporary gate electrodes 32 and the second active region 22.

[0117] Reference Figure 2 and Figure 57 The fourth mask pattern 35 can be removed. A first gate spacer 41 can be formed on the sidewalls of the plurality of first temporary gate electrodes 31 and the second mask pattern 33. A second gate spacer 42 can be formed on the sidewalls of the plurality of second temporary gate electrodes 32 and the third mask pattern 34.

[0118] A first inner spacer 41A can be formed on the sidewalls of the plurality of first temporary gate electrodes 31 and the second mask pattern 33. The first inner spacer 41A can contact the side surface of the buffer layer 27. The first inner spacer 41A can be aligned externally to the plurality of first temporary gate electrodes 31. A second inner spacer 42A can be formed on the sidewalls of the plurality of second temporary gate electrodes 32 and the third mask pattern 34. The second inner spacer 42A can extend in the second undercut region UC2. The second inner spacer 42A can contact the bottom surface of the plurality of second temporary gate electrodes 32 and the second active region 22. The second inner spacer 42A can contact the side surface of the lower gate dielectric layer 28.

[0119] Refer again Figure 2 and Figure 13 The first gate spacer 41 may be formed on the side surface of the first gate electrode 55. The first gate dielectric layer 53 may be formed between the first gate electrode 55 and the first active region 21, and between the first gate electrode 55 and the first gate spacer 41. The horizontal width of the lower gate dielectric layer 28 may be smaller than the horizontal width of the second gate electrode 56. The second gate spacer 42 may extend in the second undercut region UC2 between the second active region 22 and the second gate electrode 56.

[0120] Through summarization and review, optimized shapes for gate spacers and alternative gate electrodes are needed. Therefore, exemplary embodiments provide semiconductor devices with optimized gate spacer shapes, thereby improving the electrical performance of the semiconductor devices and their formation methods.

[0121] In other words, according to an exemplary embodiment, the semiconductor device includes a gate spacer on the side surface of the gate electrode, such that the gate spacer extends into the undercut region between the gate electrode and the active region. Due to the gate spacer, defects during the formation of the gate electrode can be greatly reduced, thus enabling the realization of a semiconductor device with excellent electrical performance.

[0122] Example embodiments have been disclosed herein, and although specific terminology has been used, it is for descriptive purposes only and should be interpreted in a general descriptive sense, not for limiting purposes. In some instances, as will be appreciated by those skilled in the art upon which this application has been filed, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly stated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: The first active region is confined to the substrate; The first gate electrode spans the first active region; The first drain region is located in the first active region at a position adjacent to the first gate electrode; The undercut region is located between the first active region and the first gate electrode; as well as The first gate spacer is located on the side surface of the first gate electrode and extends into the undercut region. The first gate spacer includes: The upper part, on the side surface of the first gate electrode; and The lower part extends from the upper part to the undercut region, and The upper part and the lower part are integrally formed.

2. The semiconductor device according to claim 1, wherein, The first gate spacer has an L-shape or an inverted T-shape.

3. The semiconductor device according to claim 1, wherein, The lower portion extends between the first active region and the first gate electrode.

4. The semiconductor device according to claim 1, wherein, An imaginary straight line extending along the side surface of the first gate electrode and perpendicular to the surface of the substrate intersects the lower portion.

5. The semiconductor device according to claim 1, wherein, The first active region includes a plurality of channel regions, each of which contacts the first drain region, and The first gate electrode surrounds the top surface, side surface, and bottom surface of at least one of the plurality of channel regions.

6. The semiconductor device according to claim 5, further comprising: A first gate dielectric layer extends between the first gate electrode and the plurality of channel regions and between the first gate electrode and the first gate spacer, the first gate dielectric layer contacting the lower side surface and the top surface.

7. The semiconductor device according to claim 1, further comprising: The second active region is defined on the substrate; The second gate electrode spans the second active region; The second drain region is located in the second active region at a position adjacent to the second gate electrode; The lower gate dielectric layer is located between the second active region and the second gate electrode; and The second gate spacer is located on the side surface of the second gate electrode.

8. The semiconductor device according to claim 7, wherein, The second gate electrode is located on the top and side surfaces of the second active region, with the lower end of the second gate electrode at a lower level than the upper end of the second active region.

9. The semiconductor device according to claim 7, further comprising: The second gate dielectric layer extends between the lower gate dielectric layer and the second gate electrode, and between the second gate spacer and the second gate electrode.

10. The semiconductor device according to claim 7, wherein, The horizontal width of the second gate electrode is greater than the horizontal width of the first gate electrode, and the horizontal width of the lower gate dielectric layer is greater than the horizontal width of the second gate electrode.

11. The semiconductor device according to claim 7, wherein, The lower gate dielectric layer protrudes beyond the second gate electrode.

12. The semiconductor device according to claim 7, wherein, The second gate spacer is in contact with the top and side surfaces of the lower gate dielectric layer.

13. The semiconductor device according to claim 7, wherein, The horizontal width of the lower gate dielectric layer is smaller than the horizontal width of the second gate electrode, and the second gate spacer extends between the second active region and the second gate electrode.

14. The semiconductor device according to claim 13, wherein, The second gate spacer has an L-shape or an inverted T-shape.

15. A semiconductor device, comprising: The first active region is defined in a first region on the substrate; The first gate electrode spans the first active region; The first drain region is located in the first active region at a position adjacent to the first gate electrode; The first gate spacer is on the side surface of the first gate electrode; The second active region is defined in a second region on the substrate; The second gate electrode spans the second active region and has a horizontal width different from that of the first gate electrode; The second drain region is located in the second active region at a position adjacent to the second gate electrode; A lower gate dielectric layer is located between the second active region and the second gate electrode, and has a width smaller than that of the second gate electrode; as well as A second gate spacer is located on the side surface of the second gate electrode and extends into the undercut region between the second active region and the second gate electrode. The second gate spacer is in contact with the side surface of the lower gate dielectric layer. The second gate spacer includes: The upper part, on the side surface of the second gate electrode; and The lower part extends from the upper part to the undercut region, and The upper part and the lower part are integrally formed.

16. The semiconductor device according to claim 15, wherein, The first active region includes a plurality of channel regions, each of which is in contact with the first drain region. The first gate electrode surrounds the top surface, side surface, and bottom surface of at least one of the plurality of channel regions, and The second gate electrode is located on the top and side surfaces of the second active region, with the lower end of the second gate electrode at a lower level than the upper end of the second active region.

17. A semiconductor device, comprising: The first active region is defined in a first region on the substrate; The first gate electrode spans the first active region; A first gate dielectric layer is located between the first active region and the first gate electrode; A pair of first drain regions are located in the first active region at positions adjacent to the opposite side of the first gate electrode and spaced apart from each other; The undercut region is located between the first active region and the first gate electrode; The first gate spacer is on the side surface of the first gate electrode and extends into the undercut region; The second active region is defined in a second region on the substrate; The second gate electrode spans the second active region and has a horizontal width greater than that of the first gate electrode. A second gate dielectric layer is located between the second active region and the second gate electrode; A pair of second drain regions are located in the second active region at positions adjacent to the opposite side of the second gate electrode and spaced apart from each other; The lower gate dielectric layer is located between the second active region and the second gate dielectric layer, and has a horizontal width greater than that of the second gate electrode. as well as The second gate spacer is located on the side surface of the second gate electrode. The first active region includes a plurality of channel regions, each of which is in contact with the pair of first drain regions. The first gate electrode surrounds the top surface, side surface, and bottom surface of at least one of the plurality of channel regions. The second gate electrode is located on the top and side surfaces of the second active region, and the lower end of the second gate electrode is at a lower level than the upper end of the second active region. The first gate spacer includes: The upper part, on the side surface of the first gate electrode; and The lower part extends from the upper part to the undercut region, and The upper part and the lower part are integrally formed.

18. The semiconductor device according to claim 17, in, The first gate dielectric layer extends between the first gate electrode and the first gate spacer, and the first gate dielectric layer contacts the lower side surface and the top surface.

19. The semiconductor device according to claim 17, wherein, The second gate dielectric layer extends between the second gate electrode and the second gate spacer, and the second gate spacer contacts the top and side surfaces of the lower gate dielectric layer.

20. A method of forming a semiconductor device, the method comprising: A first active region and a second active region are defined on the substrate; A first gate electrode is formed across the first active region and a second gate electrode is formed across the second active region; A first drain region is formed in the first active region at a position adjacent to the first gate electrode, and a second drain region is formed in the second active region at a position adjacent to the second gate electrode; A first gate spacer is formed on the side surface of the first gate electrode; A lower gate dielectric layer is formed between the second active region and the second gate electrode; as well as A second gate spacer is formed on the side surface of the second gate electrode. The first gate spacer extends in the undercut region between the first active region and the first gate electrode. The first gate spacer includes: The upper part, on the side surface of the first gate electrode; and The lower part extends from the upper part to the undercut region, and The upper part and the lower part are integrally formed.

21. The method according to claim 20, wherein, The formation of the first gate spacer, the second gate spacer, the first gate electrode, the lower gate dielectric layer, and the second gate electrode includes: A buffer layer is formed on the first active region; The lower gate dielectric layer is formed on the second active region; A first temporary gate electrode is formed on the buffer layer, and a second temporary gate electrode is formed on the lower gate dielectric layer; The buffer layer is partially removed to form an undercut region between the first active region and the first gate electrode; The first gate spacer is formed on the side surface of the first temporary gate electrode, and the second gate spacer is formed on the side surface of the second temporary gate electrode; Remove the first temporary gate electrode and the buffer layer to form the first gate electrode; and Remove the second temporary gate electrode to form the second gate electrode.

22. The method according to claim 21, wherein, Forming the undercut region further includes forming a sacrificial spacer on the side surface of the second temporary gate electrode before partially removing the buffer layer.

23. The method according to claim 22, wherein, The sacrificial spacer is in contact with the top surface of the lower gate dielectric layer and the side surface of the second temporary gate electrode.

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