High bandwidth die-to-die interconnect with reduced package area

Abstract

A package structure with a folded die arrangement and a method of manufacturing it are described. In one embodiment, the package structure includes a first die and a vertical interposer arranged side by side. A second die is positioned face down on and electrically connected to the vertical interposer, and a partial interposer electrically connects the first die to the vertical interposer.

Description

Technical Field

[0001] The implementation schemes described herein relate to semiconductor packaging, and more specifically, to folded die packaging structures. Background Technology

[0002] Current market demands for portable and mobile electronic devices, such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming devices, and other mobile devices, require the integration of more performance and features into increasingly smaller spaces. While the form factor (e.g., thickness) and footprint (e.g., area) of semiconductor die packages are decreasing, system-on-chip (SoC) designs are becoming more complex.

[0003] Scaling features to reduce the number of technology nodes in a single die is often a way to meet both higher SoC requirements and smaller area. This, in turn, places significantly higher demands on design verification, leading to the partitioning of hardware and / or software (such as central processing unit (CPU), GPU (graphics processing unit), memory application processor (MEM / AP), voltage regulation, passive integration, etc.) of certain SoC cores (also known as IP blocks) within the chip (also known as the die).

[0004] Recently, the industry has begun to explore splitting SoC core dies into individual dies. Several advanced packaging solutions have emerged as potential candidates to accommodate SoC die splitting, such as fan-out packages with redistribution layers (RDLs), 2.5D packages with dies mounted side-by-side on an interposer, or 3D packages with stacked dies. Summary of the Invention

[0005] The implementation describes a package structure including a folded die arrangement. Specifically, such a folded die arrangement can be used to split a SoC core into individual dies. In one implementation, the folded die arrangement is implemented using a combination of vertical and local interposers to electrically connect the split dies. The vertical interposer provides vertical interconnects, while the local interposer provides lateral interconnects. Attached Figure Description

[0006] Figure 1 This is a cross-sectional side view of a stacked package structure according to one implementation scheme.

[0007] Figure 2 This is a schematic top-view layout diagram of various packaged components according to one implementation scheme.

[0008] Figure 3 This is a flowchart illustrating a sequence of forming a package structure according to one embodiment.

[0009] Figures 4A to 4FThis is a cross-sectional side view illustration of a sequence of encapsulation structures according to one implementation scheme.

[0010] Figure 5 This is a cross-sectional side view of a stacked package structure according to one implementation scheme.

[0011] Figure 6 This is a cross-sectional side view of a flip-chip ball grid array package structure according to one embodiment. Detailed Implementation

[0012] The implementation describes a package structure including a folded die arrangement. Specifically, such a folded die arrangement can be used to split a SoC core into individual dies. In one implementation, the package structure includes a first wiring layer, which includes a first side and a second side opposite to the first side. A first die and a vertical interposer may be located side-by-side on the first side of the first wiring layer. The vertical interposer includes electrical interconnects from the first side of the vertical interposer coupled to the first side of the first wiring layer to the second side of the vertical interposer opposite to the first side of the vertical interposer. A second die is located face-down on the second side of the vertical interposer and electrically connected to the vertical interposer, and a partial interposer is located on the second side of the first wiring layer and electrically connected to the first die and the vertical interposer.

[0013] In one aspect, the folded die package structure according to the implementation scheme can simultaneously achieve high-bandwidth die-to-die interconnects and reduced package footprint (area) by utilizing both vertical stacking and localized interposers. This stacking arrangement reduces footprint compared to fan-out RDL or 2.5D packaging solutions. Furthermore, this stacking arrangement offers significant cost savings compared to 3D packaging solutions, where surface-to-surface die interconnects formed using technologies such as through-silicon vias (TSVs) can be expensive.

[0014] Various embodiments are described with reference to the accompanying drawings. However, some embodiments may be implemented without one or more of these specific details or without being combined with other known methods and configurations. In the following description, numerous specific details such as particular configurations, dimensions, and processes are shown to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the embodiments. The phrase "an embodiment" as used throughout the specification means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, the repeated use of the phrase "in an embodiment" throughout the specification does not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, configuration, or characteristic may be combined in one or more embodiments in any suitable manner.

[0015] As used herein, the terms “above,” “to,” “between,” “across,” and “on” can refer to the relative position of a layer with respect to other layers. A layer being “above,” “across,” or “on” another layer, or in combination with “to” another layer, or “in contact with” another layer, can mean directly contacting another layer or may have one or more interlayers. A layer “between” multiple layers can mean directly contacting those multiple layers or may have one or more interlayers.

[0016] See now Figure 1 A cross-sectional side view of a stacked package (PoP) structure is provided according to an embodiment. As shown, the PoP structure 300 may include a lower package structure 100 having a folded die arrangement according to an embodiment, and a top package structure 200 mounted on the lower package structure 100. As shown, the lower package structure 100 may include a first package level 111 and a second package level 171 below the first package level 111. The first package level may include a first die 140 stacked on and biased against the first die 110. For example, this can be achieved by stacking the first die 140 on the second die 110 and a mechanical chiplet 120 (e.g., silicon). A vertical interposer 130 is also stacked on the second die 110 and electrically connected to the second die. A wiring layer 160 spans terminals 146 of the first die 140 and terminals 136 of the vertical interposer 130. According to an embodiment, the wiring layer 160 may fan out or fan in with the vertical interposer 130 and the first die 140. Although wiring layer 160 may form some electrical connections between vertical interposer 130 and first die 140, according to certain embodiments, wiring layer 160 does not form all electrical connections between vertical interposer 130 and first die 140. In some embodiments, wiring layer 160 does not include any electrical connections between the vertical interposer and the first die. For example... Figure 1 As shown, the local interposer 170 located within the second package level 171 can be used to complete the electrical connection between the first die 140 and the vertical interposer 130, which in turn connects to the second die 110, thereby completing the electrical path from the first die 140 to the wiring layer 160 (optional), to the local interposer 170, to the wiring layer 160 (optional), to the vertical interposer 130, and to the second die 110. Therefore, this method utilizes both the vertical stack (first die 140, second die 110, vertical interposer 130) and the local interposer 170 to achieve both high-bandwidth die-to-die interconnection and reduced package area.

[0017] According to the implementation scheme, for example, the first die 140 may be a main chip including a high-performance core (e.g., CPU, GPU) or a core manufactured using a smaller node technology, while the second die 110 may be a sub-chip including a lower-performance core (e.g., RF, memory) or a core manufactured using a larger node technology. Various potential reasons for die splitting are envisioned.

[0018] In one embodiment, the package structure includes a first wiring layer 160, which includes a first side 162 and a second side 164 opposite to the first side. A first die 140 and a vertical interposer 130 are located side-by-side (and laterally adjacent) on the first side 162 of the first wiring layer 160. The vertical interposer 130 includes electrical interconnects 130 from the first side 132 of the vertical interposer coupled to the first side 162 of the first wiring layer 160 to the second side 164 of the vertical interposer opposite to the first side of the vertical interposer. For example, the electrical interconnects 130 may be or include pillars or through-silicon vias (TSVs) through a bulk silicon die. A second die 110 is located face-down on the second side 134 of the vertical interposer 130 and is electrically connected to the second side of the vertical interposer. According to an embodiment, a partial interposer 170 is mounted on the second side 164 of the first wiring layer 160 and is electrically connected to the first die 140 and the vertical interposer 130. In one embodiment, the local interposer 170 includes a plurality of terminals 176 located on a first side 172 of the local interposer coupled to a second side 164 of the first wiring layer 160, and the local interposer 170 does not include terminals located on a second side 174 of the local interposer opposite to the first side 172 of the local interposer. Therefore, the local interposer 170 can be used for lateral wiring between the first die 140 and the vertical interposer 130, rather than for vertical wiring of the vertical interposer 130.

[0019] Still referencing Figure 1 The first molding compound 150 may encapsulate the first die 140, the vertical interposer 130, and the second die 110. Additionally, a mechanical chip 120 may be attached to the first die 140 and laterally adjacent to the second die 110. More specifically, the first die 140 may be attached to the second die 110 and the mechanical chip 120, for example, using an adhesive layer 148. A first plurality of conductive posts 104 may extend from the first wiring layer 160 and pass through the first molding compound 150.

[0020] A second molding compound 180 may encapsulate a partial interposer 170 on a second side 164 of the first wiring layer 160. Additionally, a second plurality of conductive pillars 185 may extend from the first wiring layer 160 and through the second molding compound 180. As shown, a second wiring layer 190 may be formed on the second molding compound 180 and connected to the second plurality of conductive pillars 185. In one embodiment, the second wiring layer 190 is located on a planarized surface including the second molding compound 180, the second plurality of conductive pillars 185, and the partial interposer 170. Solder bumps 199 may be placed on landing pads 196 of the second wiring layer 190. For example, solder bumps 199 may be used for mounting onto a circuit board.

[0021] exist Figure 1 In the particular PoP (Package of Package) embodiment shown, the second package 200 may be mounted on the lower package 100. For example, the second package 200 may be mounted on and electrically connected to the first plurality of conductive pillars 104. In one embodiment, the second package includes a chip 210 connected to a wiring substrate 220 and encapsulated within a molding compound 230. In one embodiment, the chip 210 is a memory chip, such as dynamic random access memory (DRAM) or NAND. The chip 210 may be connected to the wiring substrate 220 by a variety of methods, including wire bonding 212.

[0022] Figure 2 This is a schematic top-view layout illustration of various packaged components according to one embodiment. While the embodiment is not limited to the specific configuration provided, Figure 2 This should be understood as a particularly suitable implementation of the folded die structure according to the embodiment. As shown, the first die 140 can occupy the largest area within the package structure. The first die 140 is also located below the second die 110. This position facilitates close routing to the circuit board within the package structure.

[0023] As shown in the figure, the first die 140 and the vertical interposer 130 are laterally adjacent or side-by-side. The second die 110 or sub-chip can be sized as needed according to the core it contains. The relative width (W) of the components is... Figure 1The lateral overlap direction is shown. The relative depth (D) of the components is shown in a direction orthogonal to the width. In one embodiment, the second die 110 overlaps with the vertical interposer 130 and may completely overlap a region of the vertical interposer 130. The second die 110 may partially or completely overlap with the first die 140. In the illustrated embodiment, the area of ​​the second die 110 is smaller than that of the first die 140 and only partially overlaps with the first die 140. In such embodiments, the mechanical chiplet 120 may overlap with some remaining area of ​​the first die 140. This provides mechanical stability and thermal expansion matching for the package structure. The mechanical chiplet 120 may also contribute to thermal performance. As shown, the partial interposer 170 overlaps with the first die 140 and the vertical interposer 130. As shown, the relative depth (D) of the components may be only as deep as required for the lateral and vertical wiring. For example, the depth (D) of the partial interposer may be less than the depth of the first chiplet 140 and the optional vertical interposer 130. The depth of the vertical interposer 130 is less than the depth of the second die 110 and the optional partial interposer 170.

[0024] In one embodiment, the first die 140 occupies a larger area than the second die 110. The first die 140 and the second die 110 may include split logic. For example, one IP logic block (e.g., a CPU) may be in one die, while another IP logic block (GPU) is in another die. Alternatively, one IP logic block (e.g., a higher-performance block with an optional smaller processing node) may be in one die, while another IP logic block (e.g., a lower-performance block with an optional larger processing node) may be in the second die. In one embodiment, the processing node of the first transistor of the first die 140 is smaller than the processing node of the second transistor of the second die 110.

[0025] Now for reference Figure 3 and Figures 4A to 4F , Figure 3 This is a flowchart illustrating a sequence of steps for forming a package structure according to one embodiment; Figures 4A to 4F This is a cross-sectional side view illustrating a sequence of encapsulation structures according to one embodiment. For clarity and simplicity, refer to... Figures 4A to 4F The features shown are used to describe Figure 3 The flowchart below. In the following description, the processing sequence can be used to form an encapsulation structure, and specifically, to form a process related to... Figure 1 The first packaging level structure and the second packaging level structure, and Figure 5 and Figure 6 The structural variations provided in the text.

[0026] like Figure 4AAs shown, at operation 3010, a second die 110 and a mechanical chip 120 are placed on a carrier substrate 102. The second die 110 may include a first side 112 and a second side 114 opposite to the first side. Similarly, the mechanical chip 120 may include a first side 122 opposite to the second side 124. In the illustrated embodiment, the second die 110 is attached to the carrier substrate 102 with its face upwards. In one embodiment, the first side 112 of the second die 110 includes exposed terminals 116 (e.g., copper pads) and a passivation material 117. In some embodiments, the passivation material 117 may be an oxide material (e.g., silicon oxide) for hybrid bonding. The second die 110 and the mechanical chip 120 may optionally be secured to the carrier substrate 102 with adhesive layers 118, 128, respectively. In one embodiment, the mechanical chip 120 is formed of silicon for thermal expansion matching.

[0027] exist Figure 4A In the illustrated embodiment, the first plurality of conductive pillars 104 are located on the carrier substrate 102. The first plurality of conductive pillars 104 may be formed prior to the placement of the second die 110 and the mechanical chiplet 120. For example, the first plurality of conductive pillars 104 may be electroplated. Alternatively, the first plurality of conductive pillars 104 may be placed on the substrate. This may occur before or after the placement of the second die 110 and the mechanical chiplet 120. In one embodiment, the second die 110 and the mechanical chiplet 120 are placed within the periphery of or between rows of the first plurality of conductive pillars 104.

[0028] At operation 3020, the vertical interlayer 130 is joined to the second die 110, as follows. Figure 4B As shown. The vertical interposer 130 can be joined using techniques such as hybrid bonding to achieve a high-density terminal pitch (e.g., less than 15 μm), or using micro (solder) bumps to achieve a terminal pitch density of less than 40 μm. The vertical interposer 130 may include terminals 136 on a first side 132 of the vertical interposer and electrical interconnects 135 extending from terminals 136 to terminals 138 on a second side 134 of the vertical interposer opposite to the first side of the vertical interposer. Terminals 138 are bonded to terminals 116 of the second die 110. In the specific embodiment shown, terminals 138 and passivation layer 137 (e.g., oxide) on the second side 134 of the vertical interposer 130 are hybrid bonded (metal-metal and oxide-oxide) to terminals 116 and passivation layer 117 of the second die 110.

[0029] See still Figure 4BAt operation 3030, the first die 140 is placed on the second die 110 and optionally on the mechanical chiplet 120. The first die 140 may be placed face up and secured with adhesive 148. As shown, the first die 140 includes a first side 142 having terminals 146 and a second side 144 opposite to the first side 142. The second die 110 and the mechanical chiplet 120 may have approximately the same height to facilitate attachment of the first die 140.

[0030] It should be understood that variations in the processing sequence are possible. For example, the first die 140 may be placed before the vertical interposer 130 is bonded. In another variation, the vertical interposer 130 and the second die 110 are bonded before being placed on the carrier substrate 102. Furthermore, the first plurality of conductive pillars 104 may be formed or placed at different times.

[0031] See now Figure 4C At operation 3040, the second die 110, optional mechanical chiplet 120, vertical interposer 130, first die 140, and optional first plurality of conductive posts 104 are encapsulated in molding compound 150. This may be followed by additional planarization and / or etching to expose terminals 146, 136, and the first plurality of conductive posts 104, which may extend between a first side 152 and a second side 154 of molding compound 150. In an alternative processing sequence, the first plurality of conductive posts 104 are formed in molding compound 150 after the molding operation.

[0032] Then, optionally, a wiring layer 160 is formed on the first side 152 of the molding compound, the first side 142 of the first die 140, and the first side 132 of the vertical interposer 130, and the wiring layer 160 is electrically connected to the terminals 146 of the first die 140 and the terminals 136 of the vertical interposer 130, such as... Figure 4D As shown. Wiring layer 160 may also be referred to as redistribution layer (RDL). For example, wiring layer 160 may have a dielectric layer 166 deposited and patterned, as well as a metal seed deposited, patterned, and plated (e.g., copper) to form redistribution lines 164. Contact pads may also be formed as part of or as a supplement to the redistribution lines in wiring layer 160.

[0033] See now Figure 4EAt operation 3050, a partial interposer 170 is mounted on and electrically connected to the first die 140 and the vertical interposer 130. In one embodiment, the partial interposer 170 includes a single face and is mounted face down. For example, the partial interposer 170 includes a first side 172 and a second side 174 opposite the first side. The first side includes a plurality of terminals 176 that are respectively bonded to terminals 146 of the first die 140 and terminals 136 of the vertical interposer 130. In one embodiment, bonding is accomplished using solder bumps 179. As shown, the partial interposer 170 includes wiring 171 to electrically connect the vertical interposer 130 and the first die 140.

[0034] Similarly, like the first plurality of conductive pillars 104, a second plurality of conductive pillars 185 may be formed on the wiring layer 160. The second plurality of conductive pillars 185 may be formed prior to the placement of the local interposer layer 170. For example, the second plurality of conductive pillars 185 may be electroplated. Alternatively, the second plurality of conductive pillars 185 may be placed on the underlying structure. This may occur before or after the placement of the local interposer layer 170. In one embodiment, the local interposer layer 170 is placed within the periphery of the second plurality of conductive pillars 185 or between rows.

[0035] See now Figure 4F At operation 3060, a local interposer 170 and optionally a second plurality of conductive pillars 185 are encapsulated within a second molding compound 180. This may subsequently be followed by additional planarization and / or etching to expose a second side 174 of the local interposer 170 and the second plurality of conductive pillars 185, which may extend between a first side 182 and a second side 184 of the second molding compound 180. In an alternative processing sequence, the second plurality of conductive pillars 185 are formed in the molding compound 180 after the molding operation.

[0036] Then, various processing sequences can be executed according to the final package structure to be formed. Figure 4F In the exemplary embodiment shown, a second wiring layer 190, including one or more insulating layers 192 and wiring layers 194, is formed on a first side 182 of the second molding compound 180, on exposed second plurality of pillars 185, and optionally directly formed on a second side 174 of the local interposer layer 174. The second wiring layer 190 may include landing pads 196, and solder bumps 199 may be placed on the landing pads 196 for further integration, after which the carrier substrate 102 is removed.

[0037] Figure 5 This is a cross-sectional side view of a stacked package structure according to one implementation scheme. Figure 5 Basically similar Figure 1The structure provided in the previous version differs in that it uses micro (solder) bumps 139 to bond the vertical interposer 130 to the second die 110.

[0038] Figure 6 This is a cross-sectional side view of a flip-chip ball grid array (FCBGA) package structure according to one embodiment. As previously described, the package structure, including a first package level 111 and a second package level 171, can be integrated into various package configurations, including PoP and flip-chip FCBGA. Figure 6 In the illustrated embodiment, the landing pad 196 may be located on the stud 197. The package structure 100 may be bonded to the package substrate 402 using solder bumps 199. An underfill material 195 may then be applied between the package 100 and the package substrate 402. Package (solder) bumps 404 may then be applied to opposite sides of the package substrate 402 for mounting onto a circuit board, etc.

[0039] When utilizing the various aspects of the embodiments, it will be apparent to those skilled in the art that combinations or variations of the above embodiments are possible for forming a folded die package structure. Although the embodiments have been described in language specific to structural features and / or methodological behavior, it should be understood that the appended claims are not necessarily limited to the specific features or behaviors described. Rather, the specific features and behaviors disclosed should be understood as embodiments used for illustrative purposes.

Claims

1. A packaging structure, comprising: A first wiring layer, the first wiring layer including a first side and a second side opposite to the first side; A first die and a vertical interposer layer, the first die and the vertical interposer layer being located side-by-side on a first side of a first wiring layer, wherein the vertical interposer layer includes an electrical interconnect from a first side of the vertical interposer layer coupled to the first side of the first wiring layer to a second side of the vertical interposer layer opposite to the first side of the vertical interposer layer; The second die is located face down on the second side of the vertical interposer and is electrically connected to the second side of the vertical interposer. and A local interposer layer is located on the second side of the first wiring layer and is electrically connected to the first die and the vertical interposer layer, wherein the first transistor of the first die has a processing node smaller than the processing node of the second transistor of the second die.

2. The packaging structure according to claim 1, wherein the partial interposer includes a plurality of terminals on a first side of the partial interposer, the first side of the partial interposer is coupled to a second side of the first wiring layer, and the partial interposer does not include terminals on the second side of the partial interposer, the second side of the partial interposer being opposite to the first side of the partial interposer.

3. The packaging structure according to claim 1, wherein the first die occupies an area larger than that occupied by the second die.

4. The packaging structure according to claim 3, wherein the first die and the second die include split logic.

5. The packaging structure according to claim 3, wherein the second die occupies an area larger than that occupied by the vertical interposer and larger than that occupied by the partial interposer.

6. The packaging structure according to claim 2, wherein the vertical interposer is co-bonded with the second die.

7. The packaging structure according to claim 2, wherein the solder bumps electrically connect the vertical interposer to the second die.

8. The packaging structure according to claim 1 further includes a first molding compound, wherein the first molding compound encapsulates the first die, the vertical interposer, and the second die.

9. The packaging structure according to claim 1 further includes a mechanical chiplet, wherein the mechanical chiplet is attached to the first die in a laterally adjacent manner to the second die.

10. The packaging structure of claim 8, further comprising a first plurality of conductive pillars extending from the first wiring layer and through the first molding compound.

11. The packaging structure of claim 8, further comprising a second molding compound, the second molding compound encapsulating the partial interposer layer located on the second side of the first wiring layer.

12. The packaging structure of claim 11 further includes a second plurality of conductive pillars extending from the first wiring layer and through the second molding compound.

13. The packaging structure of claim 12 further includes a second wiring layer, the second wiring layer being located on the second molding compound and connected to the second plurality of conductive pillars.

14. The packaging structure of claim 13, wherein the second wiring layer is located on a planarized surface including the second molding compound, the second plurality of conductive pillars and the partial interposer layer.

15. The packaging structure according to claim 12 further includes a second package, the second package being located on the first plurality of conductive pillars and electrically connected to the first plurality of conductive pillars.

16. The packaging structure of claim 13 further includes a plurality of solder bumps, the plurality of solder bumps electrically connecting the second wiring layer to the packaging wiring substrate.

17. A method for forming an encapsulation structure, comprising: The second die and the mechanical chip are placed on the carrier substrate; The vertical interlayer is bonded to the second die; The first die is placed on the second die and the mechanical chip; The second die, the mechanical chiplet, the vertical interposer, and the first die are encapsulated in a first molding compound; A partial intermediate layer is installed on the vertical intermediate layer and the first die and electrically connected to the vertical intermediate layer and the first die; as well as The local interposer layer is encapsulated in a second molding compound, wherein the first transistor of the first die has a processing node smaller than the processing node of the second transistor of the second die.

18. The method of claim 17, wherein bonding the vertical interlayer to the second die comprises hybrid bonding.

19. The method of claim 17, wherein bonding the vertical interlayer to the second die includes forming solder bumps.

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