Source / Drain Formation with Reduced Selectivity Loss Defects

Abstract

The present disclosure relates to source / drain formation with reduced selective loss defects. A method includes: forming a first semiconductor fin and a second semiconductor fin in an n-type fin field effect transistor (FinFET) region and a p-type FinFET region, respectively; forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively; forming a first epitaxial mask to cover the second semiconductor fin and the second dielectric fin; performing a first epitaxial process to form an n-type epitaxial region based on the first semiconductor fin; removing the first epitaxial mask; forming a second epitaxial mask to cover the n-type epitaxial region and the first dielectric fin; performing a second epitaxial process to form a p-type epitaxial region based on the second semiconductor fin; and removing the second epitaxial mask. After removing the second epitaxial mask, a first portion of the second epitaxial mask remains on the first dielectric fin.

Description

Technical Field

[0001] The present disclosure relates to source / drain formation with reduced selective loss defects. Background Art

[0002] In the formation of fin field-effect transistors (FinFETs), source / drain regions are typically formed by etching silicon fins to form recesses and then performing an epitaxial process to grow epitaxial regions from the recesses. Since the source / drain regions of p-type FinFETs and n-type FinFETs are formed of different materials, the source / drain regions of p-type FinFETs and n-type FinFETs are formed in different processes. Summary of the Invention

[0003] According to an embodiment of the present disclosure, there is provided a method of forming a semiconductor device, including: forming a first semiconductor fin and a second semiconductor fin in an n-type fin field-effect transistor (FinFET) region and a p-type FinFET region, respectively; forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively; forming a first epitaxial mask to cover the second semiconductor fin and the second dielectric fin; performing a first epitaxial process to form an n-type epitaxial region based on the first semiconductor fin; removing the first epitaxial mask; forming a second epitaxial mask to cover the n-type epitaxial region and the first dielectric fin; performing a second epitaxial process to form a p-type epitaxial region based on the second semiconductor fin; and removing the second epitaxial mask, wherein, after removing the second epitaxial mask, a first portion of the second epitaxial mask remains on the first dielectric fin.

[0004] According to another embodiment of the present disclosure, there is provided a semiconductor structure, including: an n-type fin field-effect transistor (FinFET) region and a p-type FinFET region; an n-type FinFET located in the n-type FinFET region, wherein the n-type FinFET includes: a first semiconductor fin; a first gate stack located on the first semiconductor fin; and an n-type source / drain region located beside the first gate stack; a first dielectric fin located in the n-type FinFET region, wherein the first dielectric fin has a first width; a p-type FinFET located in the p-type FinFET region, wherein the p-type FinFET includes: a second semiconductor fin; a second gate stack located on the second semiconductor fin; and a p-type source / drain region located beside the second gate stack; and a second dielectric fin located in the p-type FinFET region, wherein the second dielectric fin has a second width smaller than the first width.

[0005] According to another embodiment of the present disclosure, a semiconductor structure is provided, including: a semiconductor substrate; a plurality of isolation regions extending into the semiconductor substrate; a first n-type source / drain region and a second n-type source / drain region extending above the top surfaces of the plurality of isolation regions; a first dielectric fin located between the first n-type source / drain region and the second n-type source / drain region, wherein the first dielectric fin has a first width measured at a first level above the top surfaces of the plurality of isolation regions and a second width measured at a second level below the top surfaces of the plurality of isolation regions; a first p-type source / drain region and a second p-type source / drain region extending above the top surfaces of the plurality of isolation regions; and a second dielectric fin located between the first p-type source / drain region and the second p-type source / drain region, wherein the second dielectric fin has a third width measured at the first level and a fourth width measured at the second level, and wherein the first width is greater than the third width. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figures 1 - 15 , Figure 16A , Figure 16B and Figures 17 - 20 show perspective, cross-sectional, and top views of intermediate stages in the formation of FinFETs separated by dielectric fins, according to some embodiments.

[0008] Figure 21 show a cross-section of a dielectric fin, according to some embodiments.

[0009] Figure 22 show examples of n-type and p-type source / drain regions and the dielectric fin therebetween, according to some embodiments.

[0010] Figure 23 show a process flow for forming n-type and p-type FinFETs, according to some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or above a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. Such repetition is for purposes of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] In addition, spatial relative terms (such as, "beneath", "below", "lower", "above", "upper", etc.) may be used herein to easily describe one element or feature's relationship to another (one or more) element(s) or (one or more) feature(s) shown in the figures. These spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein may likewise be interpreted accordingly.

[0013] According to some embodiments, a fin field-effect transistor (FinFET) having source / drain regions and a method of forming the same are provided. The epitaxial process for forming the source / drain regions may have a selective loss defect, which is the adverse growth of source / drain material on a dielectric material due to selective loss of certain portions. According to some embodiments, the source / drain regions of an n-type FinFET are formed before the source / drain regions of a p-type FinFET, such that the selective loss defect is n-type and the subsequently formed source / drain regions are p-type. During subsequent p-type source / drain epitaxy, it is easier to remove the n-type selective loss defect (rather than the reverse) because appropriate process gases for removing the n-type selective loss defect are available at any time during p-type source / drain epitaxy. The embodiments discussed herein will provide examples to enable the making or using of the subject matter of the present disclosure, and those of ordinary skill in the art will readily appreciate the modifications that can be made while remaining within the scope of the different embodiments. In the various views and illustrative embodiments, like reference numerals are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] Figures 1 - 20Shows a perspective view, a cross-sectional view, and a top view of an intermediate stage of forming an n-type FinFET, a p-type FinFET, and their corresponding source / drain regions according to some embodiments. The corresponding processes are also schematically reflected in Process Flow 200 as shown in Figure 23 shown.

[0015] Figure 1 Shows a perspective view of an initial structure. The initial structure includes a wafer 10, and the wafer 10 further includes a substrate 20. The substrate 20 can be a semiconductor substrate, which can be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 can be doped with p-type or n-type impurities. Isolation regions 22 such as shallow trench isolation (STI) regions can be formed to extend from the top surface of the substrate 20 into the substrate 20. The corresponding process is shown as the process 202 in Process Flow 200 as shown in Figure 23 shown. The portion of the substrate 20 between adjacent STI regions 22 is referred to as a semiconductor strip 24. According to some embodiments of the present disclosure, the semiconductor strip 24 is a portion of the original substrate 20, so the material of the semiconductor strip 24 is the same as the material of the substrate 20. According to alternative embodiments of the present disclosure, the semiconductor strip 24 is a replacement strip formed by etching the portion of the substrate 20 between the STI regions 22 to form a recess and performing an epitaxial process to regrow another semiconductor material in the recess. Therefore, the semiconductor strip 24 is formed of a semiconductor material different from the semiconductor material of the substrate 20. According to some embodiments, the semiconductor strip 24 is formed of Si, SiP, carbon-doped silicon, SiPC, SiGe, SiGeB, Ge, III-V compound semiconductors (such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs, etc.).

[0016] The STI region 22 can include a liner oxide (not shown), which can be a thermal oxide formed by thermal oxidation of the surface layer of the substrate 20. The liner oxide can also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), etc. The STI region 22 can also include a dielectric material on top of the liner oxide, where the dielectric material can be formed using flowable chemical vapor deposition (FCVD), spin coating, etc.

[0017] Figure 2 Shows the formation of a dielectric dummy strip 25. The corresponding process is shown as in Figure 23Process 204 in the process flow 200 shown. The dielectric dummy strip 25 can be formed by various methods. For example, one of the semiconductor strips 24 can be etched to form a recess, and then the recess can be filled with a dielectric material to form the dielectric dummy strip 25. Alternatively, the dielectric dummy strip 25 can be formed by forming a large STI region 22, etching a portion of the large STI region 22 to form a trench, and filling the trench with a dielectric material different from the material of the STI region 22. The material of the dielectric dummy strip 25 can be selected such that it has a high etch selectivity with respect to the material of the STI region 22 (e.g., silicon oxide) and the material of the subsequent formed dummy gate stack. For example, the dielectric material can be formed of SiOC, SiON, SiOCN, etc. The bottom surface of the dielectric dummy strip 25 can be higher than, lower than, or flush with the bottom surface of the STI region 22.

[0018] According to some embodiments, the dielectric dummy strip 25 has a seam 28 in the middle. The seam 28 can be caused by conformal deposition of the dielectric material such that the dielectric material is deposited on opposite sidewalls of the trench and grows towards each other, and finally leaves the seam 28 due to premature sealing of the remaining trench.

[0019] According to some embodiments, the dielectric dummy strip 25 separates the p-type FinFET region 100P and the n-type FinFET region 100N from each other. The p-type FinFET region 100P is used to form a p-type FinFET in a subsequent process, and the n-type FinFET region 100N is used to form an n-type FinFET in a subsequent process. More details of the p-type FinFET region 100P and the n-type FinFET region 100N are as Figures 6 to 15 shown.

[0020] Referring Figure 3 , the STI region 22 is recessed. The tops of the semiconductor strip 24 and the dielectric dummy strip 25 protrude above the top surface 22A of the remaining portion of the STI region 22 to form a protruding fin 24' and a dummy fin 25', respectively. The corresponding process is shown as process 205 in the process flow 200 as Figure 23 shown. The etching can be performed using a dry etching process, in which an etching gas such as a mixture of HF and NH3 can be used. According to an alternative embodiment of the present disclosure, the recessing of the STI region 22 is performed using a wet etching process. For example, the etching chemical can include a diluted HF solution.

[0021] In the embodiments shown above, the fins may be patterned by any suitable method. For example, one or more lithographic processes (including double or multi-patterning processes) may be used to pattern the fins. Generally, double or multi-patterning processes combine lithography and self-alignment processes, allowing patterns to be created with a pitch, for example, smaller than that which could otherwise be obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithographic process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0022] Further referring Figure 3 , dummy gate stacks 30 and gate spacers 38 are formed on the top surfaces and sidewalls of the protruding semiconductor fins 24' and dummy fins 25'. The corresponding process is shown as the process 206 in the process flow 200 as Figure 23 shown. The dummy gate stack 30 may include a dummy gate dielectric (not shown) on the top surface and sidewalls of the protruding fin 24'. The dummy gate stack 30 may further include a dummy gate electrode 34 located over the dummy gate dielectric. For example, the dummy gate electrode 34 may be formed of polysilicon or amorphous silicon, and other materials may also be used. Each dummy gate stack 30 may further include one (or more) hard mask layers 36 located over the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or a multi-layer thereof. The dummy gate stack 30 may span across a single or multiple protruding fins 24' and dummy fins 25' and / or STI regions 22. The dummy gate stack 30 has a longitudinal direction perpendicular to the longitudinal direction of the protruding fins 24' and dummy fins 25'.

[0023] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stacks 30. The corresponding process is shown as the process 206 in the process flow 200 as Figure 23 shown. According to some embodiments of the present disclosure, the gate spacers 38 are formed of dielectric materials such as silicon nitride (SiN), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxynitride (SiON), silicon oxynitride (SiOCN), etc., and may have a single-layer structure or a multi-layer structure including a substrate and multiple dielectric layers. The width of the gate spacers 38 may be in the range of about 1 nm to about 3 nm.

[0024] Figure 4 and Figure 5Schematically shows the recess of the protruding fin and the formation of source / drain regions by epitaxy. According to some embodiments of the present disclosure, an etching process (hereinafter referred to as source / drain recess) is performed to etch the portion of the protruding fin 24' that is not covered by the dummy gate stack 30 and the gate spacer 38, thereby forming a recess 40. It can be appreciated that Figure 4 and Figure 5 The processes shown in are short, and the details of performing these processes are as shown in Figures 6 to 15 Therefore, Figure 4 and Figure 5 Only show what the recess 40 and the resulting source / drain region 42 look like in a perspective view, without showing the formation order. For example, the recess of the protruding fin 24' in the p-type device region 100P and the n-type FinFET region 100N can be performed in separate etching processes, rather than in a common process as shown in Figure 4 shown.

[0025] The recess can be anisotropic, so the portion of the protruding fin 24' directly below the dummy gate stack 30 and the gate spacer 38 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 24 can be lower than the top surface 22A of the STI region 22. The space left by the etched portion of the protruding fin 24' is called the recess 40. During the etching process, the dielectric dummy fin 25' is not etched. For example, a mixture of NF3 and NH3, a mixture of HF and NH3, etc. can be used to etch the protruding fin 24'.

[0026] Epitaxial regions (source / drain regions) 42P and 42N, collectively referred to as the source / drain region 42, are formed. The epitaxial regions 42P and 42N are formed by selectively growing semiconductor material from the recess 40, thereby forming the structure in Figure 5 It can be appreciated that the source / drain regions 42 of the p-type FinFET and the n-type FinFET can have different shapes, and the details of the shapes are as shown in Figure 15 shown. In addition, the dielectric dummy fins 25' in the p-type FinFET region 100P and the dielectric dummy fins 25' in the n-type FinFET region 100N can have different thicknesses and / or different layered structures, which are also discussed in detail with reference to Figures 6 to 15 shown.

[0027] Figure 6A cross-sectional view is shown that depicts the p-type FinFET region 100P and the n-type FinFET region 100N, as well as the protruding fins 24' and dummy fins 25' in the p-type FinFET region 100P and the n-type FinFET region 100N. Additionally, one of the dummy fins 25' can be used as a partitioning feature to separate the p-type FinFET region 100P and the n-type FinFET region 100N, and is hereinafter referred to as the dummy fin 25'D. For purposes of distinction, the protruding fins 24' in the p-type FinFET region 100P and the n-type FinFET region 100N are respectively referred to as the protruding fins 24'P and 24'N, and the dummy fins 25' in the p-type FinFET region 100P and the n-type FinFET region 100N are respectively referred to as the dummy fins 25'P and 25'N. Moreover, Figure 6 The cross-sectional view shown depicts Figure 3 reference cross-section 6-6 in Figure 3 and the perspective view shown depicts Figure 6 portion 44 in Figure 6 No dummy gate stack 30 ( Figure 3 ) is shown. In Figure 6 , the widths W1 of the dielectric fins 25'P, 25'D, and 25'N are substantially equal to each other. Additionally, the widths W1', W2', and W3' can be substantially equal to each other.

[0028] Referring to Figure 7 , a first epitaxial mask 46 is formed. The corresponding process is shown as in Figure 23Process 208 in the process flow 200 shown. According to some embodiments, the epitaxial mask 46 is formed of a dielectric material, which can be formed of or include SiON, SiOCN, AlO, SiN, SiOC, SiO2, etc. The materials of the epitaxial mask 46 and the dielectric fin 25' can be the same as or different from each other. Thus, the epitaxial mask 46 and the dielectric fin 25' can be distinguishable from each other or not. According to some embodiments, the thickness T1 of the epitaxial mask 46 can be in the range of about 0.5 nm to about 2.5 nm. The epitaxial mask 46 can be formed as a conformal layer that has a horizontal thickness of the horizontal portion and a vertical thickness of the vertical portion, and the horizontal thickness and the vertical thickness are equal (or substantially equal) to each other, for example, the variation is less than about 20%. The epitaxial mask 46 can be a single layer or a composite layer including multiple sub-layers. The sub-layers can be formed of materials different from each other, and the different materials can be selected from the above materials. Alternatively, the sub-layers in the epitaxial mask 46 can include the same elements, such as Si, O, C, and N, while the atomic percentages of the sub-layers are different from each other. According to some embodiments of the present disclosure, the epitaxial mask 46 is deposited using a conformal deposition process (such as atomic layer deposition (ALD), chemical vapor deposition (CVD), etc.). At the same time, the epitaxial mask 46 is deposited on the protruding fin 24' and the dielectric fin 25', and the epitaxial mask 46 is also deposited on the top surface and sidewalls of the gate stack 30 and the gate spacer 38 as shown in Figure 3 the top surface and sidewalls of the gate stack 30 and the gate spacer 38 shown.

[0029] An etch mask 48 is also formed and deposited. The corresponding process is shown as process 210 in the process flow 200 as shown in Figure 23 According to some embodiments, the etch mask 48 is formed of or includes a photoresist. Other layers such as a bottom anti-reflection coating (BARC), a hard mask layer, etc. can or cannot be formed as part of the etch mask 48. The etch mask 48 is patterned to cover the p-type FinFET region 100P and expose the n-type FinFET region 100N. According to some embodiments, the edge of the etch mask 48 is aligned with the dielectric fin 25'D.

[0030] Referring to Figure 8 , an etching process 50 is performed to remove the portion of the epitaxial mask 46 in the n-type FinFET region 100N while protecting the portion of the epitaxial mask 46 in the p-type FinFET region 100P from being removed by the etch mask 48. The corresponding process is shown as in Figure 23Process 212 in the process flow 200 shown. The etching process is an isotropic process, which can be a dry etching process or a wet etching process. Thus, the epitaxial mask 46 can be completely removed from the n-type FinFET region 100N.

[0031] Next, the protruding fin 24'N is removed by etching, thereby forming a recess 40N, Figure 4 also shown as 40 in. The resulting structure is as Figure 9 shown. The corresponding process is shown as in Figure 23 Process 214 in the process flow 200 shown. The etching mask 48 is also removed and can be removed before or after etching the protruding fin 24'N. According to some embodiments, the etching of the protruding fin 24'N is performed until the recess 40N extends to a level below the top surface of the STI region 22.

[0032] Refer to Figure 10 , an epitaxial region 42N is formed in the first selective epitaxy process, which is also referred to as the epitaxial region 42. In the first selective epitaxy process, semiconductor material is selectively grown starting from the recess 40N. The corresponding process is shown as in Figure 23 Process 216 in the process flow 200 shown. According to some embodiments, the epitaxial region 42N is formed of or includes silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), silicon, etc. The epitaxial region 42N forms the source / drain region of the resulting n-type FinFET and is also referred to as the source / drain region 42N. According to some embodiments, for example, when the epitaxial material is silicon, an implantation process can be performed to implant n-type impurities into the epitaxial region 42N. According to alternative embodiments, for example, when the epitaxial material already includes n-type impurities (such as phosphorus), the implantation process can be skipped. Each of the epitaxial regions 42N can also include multiple sub-layers. For example, the atomic percentages of phosphorus in the multiple sub-layers are different from each other. According to some embodiments, the epitaxial region 42N has straight edges and vertical edges as well as inclined facets. The epitaxial region 42N can also include a flat top surface. The epitaxial region 42N can extend all the way to the adjacent dielectric fin 25'N or can be separated from the adjacent dielectric fin 25'N by a gap.

[0033] The epitaxy process is selective by including an etching gas such as HCl in the process gas. Selective deposition causes semiconductor material to grow on semiconductor material but not on dielectric materials such as dielectric fins 25', gate spacers 38 ( Figure 5 ) and hard mask 36, etc. It can be appreciated that due to selective loss in certain regions, defects may sometimes occur such that semiconductor material grows unfavorably on dielectric materials such as gate spacers 38, dielectric fins 25', etc. For example, Figure 10Defects 54N1 in the n-type FinFET region 100N and defects 54N2 in the p-type FinFET region 100P are schematically shown, which are unwanted semiconductor materials. Defects 54N1 and 54N2 are also referred to as selective loss defects because they are formed due to selective loss. The presence of the selective loss defect 54N1 does not significantly affect subsequent processes because it does not grow larger and can thus be removed in subsequent cleaning processes. Therefore, the selective loss defect 54N1 is not shown in subsequent figures. It has been found that it is easier to remove n-type selective loss defects (such as SiP) than p-type selective loss defects (such as SiGeB) because readily available process gases can effectively remove n-type selective loss defects, but the efficiency of removing p-type selective loss defects is lower. Therefore, in the embodiments of the present disclosure, an n-first process is adopted, which means that the n-type epitaxial region (source / drain region) is formed before the formation of the p-type epitaxial region.

[0034] Then, an etching process is performed to remove the remaining portion of the epitaxial mask 46 in the p-type FinFET region 100P. The corresponding process is shown as the process 218 in the process flow 200 as Figure 23 shown. The etching process is an isotropic process, which can be a dry etching process or a wet etching process, and the etching chemical is selected based on the materials of the epitaxial mask 46, the protruding fin 24', and the epitaxial region 42N. Thus, the protruding fin 24' and the dielectric fin 25' are re-exposed. If the selective loss defect 54N2 is formed, it is not removed during the removal of the epitaxial mask 46, and it will also unfavorably protect the underlying portion of the epitaxial mask 46 from being removed.

[0035] Referring to Figure 11 , a second epitaxial mask 56 is formed. The corresponding process is shown as Figure 23Process 220 in the process flow 200 shown. According to some embodiments, the epitaxial mask 56 is formed of a dielectric material, which can be formed of or include SiON, SiOCN, AlO, SiN, SiOC, SiO2, etc. The material of the epitaxial mask 56 can be the same as or different from the material of the dielectric fin 25', and can be the same as or different from the material of the epitaxial mask 46. The material(s) of the epitaxial mask 56 can be selected from the same set of candidate materials used to form the epitaxial mask 46. The epitaxial mask 56 and the dielectric fin 25' may or may not be distinguishable from each other. According to some embodiments, the thickness T2 of the epitaxial mask 56 can be in the range of about 0.5 nm to about 2.5 nm. The epitaxial mask 56 can be a single layer or a composite layer including multiple sub-layers, which can be formed of materials selected from the above materials. Alternatively, the sub-layers in the epitaxial mask 56 can include the same elements, such as Si, O, C, and N, but the atomic percentages of the sub-layers are different from each other. According to some embodiments of the present disclosure, the epitaxial mask 56 is deposited using a conformal deposition process (such as ALD, CVD, etc.). At the same time, the epitaxial mask 56 is deposited on the protruding fin 24' and the dielectric fin 25', and the epitaxial mask 56 is also deposited on the top surface and sidewalls of the gate stack 30 and the gate spacer 38 as shown in Figure 3 the top surface and sidewalls of the gate stack 30 and the gate spacer 38 shown.

[0036] In some embodiments, the previous process leaves the selective loss defect 54N2 and the lower layer portion of the epitaxial mask 46. According to these embodiments, the epitaxial mask 56 covers the selective loss defect 54N2 and the lower layer portion of the epitaxial mask 46.

[0037] As shown in Figure 11 According to some embodiments, some or all of the epitaxial regions 42N are spaced apart from the adjacent dielectric fins 25'N by some gaps. Therefore, the epitaxial mask 56 extends downward all the way (in and through the gaps) to the top surface of the STI region 22. Some or all of the epitaxial regions 42N may also be joined to the adjacent dielectric fins 25'N. Therefore, the corresponding epitaxial mask 56 is formed above the point where the epitaxial region 42N is joined to the corresponding dielectric fin 25'N, and does not extend into the space below the meeting point. For example, as shown in Figure 11 When the dielectric fins 25'D and / or 25'N are connected to their adjacent epitaxial regions 42N, the portion 56' of the epitaxial mask 56 will not be formed. In another example, when the dielectric fins 25'D and / or 25'N are spaced apart from their adjacent epitaxial regions 42N, the portion 56' will be formed.

[0038] Further referring to Figure 11 , a patterned etch mask 58 is formed. The corresponding process is shown as inFigure 23 Process 222 in the process flow 200 shown. The etch mask 58 can be formed of the same or a similar material as the etch mask 48 ( Figure 7 ), and can have a structure similar to that of the etch mask 48. The etch mask 58 is patterned to cover the n-type FinFET region 100N and expose the p-type FinFET region 100P. According to some embodiments, the edge of the etch mask 58 is aligned with the dielectric fin 25’D.

[0039] Refer to Figure 12 , an etch process 60 is performed to remove a portion of the epitaxial mask 56 in the p-type FinFET region 100P, while the portion of the epitaxial mask 56 in the n-type FinFET region 100N is protected by the etch mask 58 and not removed. The corresponding process is shown as process 224 in the process flow 200 as Figure 23 shown. The etch process is an isotropic process, which can be a dry etch process or a wet etch process, and an etch chemical is selected based on the materials of the epitaxial mask 56 and the protruding fin 24’P to remove the exposed portion of the epitaxial mask 56 without damaging the protruding fin 24’P exposed after removing the epitaxial mask 56. After etching, the selective loss defect 54N2 (if any) will be revealed again.

[0040] As Figure 12 shown, the etch mask 58 is removed, and the protruding fin 24’P is removed by etching. The resulting structure is as Figure 13 shown. A recess 40P is formed as a result of the etching. The corresponding process is shown as process 226 in the process flow 200 as Figure 23 shown. The etch mask 58 is also removed, and can be removed before or after etching the protruding fin 24’P. According to some embodiments, the etching of the protruding fin 24’P is performed until the recess 40P extends to a level below the top surface of the STI region 22.

[0041] Refer to Figure 14 , an epitaxial region 42P, also referred to as 42, is formed in a second selective epitaxy process in which semiconductor material is selectively grown starting from the recess 40P. The corresponding process is shown as Figure 23Process 228 in the process flow 200 shown. According to some embodiments, the epitaxial region 42P is formed of or includes silicon germanium boron (SiGeB), SiB, GeB, Si, etc., and forms the source / drain regions of the resulting p-type FinFETs and is also referred to as the p-type source / drain region 42P. According to some embodiments, for example, when the epitaxial material is silicon, an implantation process may be performed to implant p-type impurities. According to alternative embodiments, for example, when the epitaxial material already includes p-type impurities (such as boron), the implantation process may be skipped. Each of the epitaxial regions 42P may also include a plurality of sub-layers, for example, the atomic percentages of boron and / or germanium in the sub-layers are different from each other. According to some embodiments, the epitaxial region 42P has a rhombus shape. Some adjacent epitaxial regions 42P may merge with each other. Additionally, the epitaxial region 42P may extend all the way to the adjacent dielectric fin 25’P or may be spaced apart from the adjacent dielectric fin 25’P by some gap.

[0042] By including an etching gas such as HCl in the process gas, the epitaxial process is selective. However, the selectivity may be detrimentally lost and cause the epitaxial material to grow on the selectivity loss defect 54N2 ( Figure 13 ), resulting in an increase in the selectivity loss defect 54N2. Therefore, the process gas and process conditions are adjusted such that during the epitaxy for forming the epitaxial region 42P, the selectivity loss defect 54N2 is selectively etched and removed. This can be achieved, for example, by increasing the flow rate of the etching gas, adjusting the process conditions (such as reducing the partial pressures of the precursors (such as SiH4 and GeH4)), etc. The corresponding process is shown as Figure 23 Process 228 in the process flow 200 shown. With the adjusted epitaxial process, and further because the n-type epitaxial region 42N is more easily etched than the p-type epitaxial region 42P, the selectivity loss defect 54N2 can be removed during the epitaxy of the p-type epitaxial region 42P.

[0043] In embodiments of the present disclosure, when the n-type process is adopted first, the n-type selectivity loss defect (54N2) generated in the first epitaxial process can be removed during the second epitaxial process for forming the p-type epitaxial region 42P. However, if the p-type process is adopted first, p-type selectivity loss defects will be generated in the first epitaxial process and must be removed by the second epitaxial process. However, p-type selectivity loss defects (such as those formed by SiGeB) are difficult to remove because there are no good available process gases and conditions. Therefore, in the second epitaxial process, p-type selectivity loss defects are more likely to grow rather than be eliminated. Therefore, the n-type process is adopted first in embodiments of the present disclosure.

[0044] Then, an etching process is performed to remove the remaining portion of the epitaxial mask 56 in the n-type FinFET region 100N. The corresponding process is shown as process 230 in the process flow 200 as shown in Figure 23 The resulting structure is as shown in Figure 15 The etching process is an isotropic process, which can be a dry etching process or a wet etching process, and the etching chemical is selected based on the materials of the epitaxial mask 56, the protruding fin 24'P, and the epitaxial region 42P. Accordingly, the epitaxial region 42N is re-exposed. To reduce the damage to the epitaxial region 42P, the etching process is controlled to be as light as possible. Additionally, since the epitaxial region 42N has been formed, which results in a small spacing between the dielectric fin 25'N and the epitaxial region 42N, the epitaxial mask 56 is not completely removed. The remaining portion of the etching mask 56 is observed in the transmission electron microscope (TEM) image of the sample wafer.

[0045] Figure 15 The dielectric fins 25'P and 25'N after the formation of the epitaxial regions 42P and 42N are shown. Throughout the specification, the dielectric fin 25'N and the remaining epitaxial mask 56 thereabove are collectively referred to as the dielectric fin 25'NF. The materials of the dielectric fin 25'N and the epitaxial mask 56 may be the same as each other and thus may not be distinguishable from each other, or may be different from each other. The widths of the dielectric fins 25'P and 25'NF are W1 and W2, respectively. When the epitaxial regions 42P and 42N are spaced apart from the adjacent dielectric fins 25'P and 25'N, the corresponding widths W1 and W2 are measured at the intermediate height (level 1) of the dielectric fins 25'P and 25'NF. When the epitaxial regions 42P and 42N connect the adjacent dielectric fins 25'P and 25'N, the widths W1 and W2 are measured at the intermediate levels (levels 2 and 3) between the top surfaces of the dielectric fins 25'P and 25'NF and the corresponding connection points. For example, a dashed line 64 is drawn to show the sidewall of the epitaxial region 42P connecting the dielectric fin 25'P. Accordingly, the width W1 is measured at level 2, which is intermediate between the top surface level and the connection point 65.

[0046] Since the dielectric fins 25’P and 25’N have the same width W1, the width W2 of the dielectric fin 25’NF is greater than the width W1 of the dielectric fin 25’P. According to some embodiments, the width W1 is in the range of about 3 nm to about 20 nm, and the width W2 is in the range of about 4 nm to about 25 nm. The width difference (W2 - W1) can be in the range of about 1 nm to about 5 nm. The width difference between the widths W2 and W1 is an indicator for forming source / drain regions using the prior n process. According to some embodiments, the dielectric fin 25’D can have an epitaxial mask 56 on its sidewall facing the n-type FinFET region 100N, while no epitaxial mask 56 is left on the sidewall facing the p-type FinFET region 100P. The dielectric fin 25’D and the corresponding epitaxial mask 56 are collectively referred to as the dielectric fin 25’DF, and its width W3 is measured at level 1 or level 2 or level 3. There may be a relationship of W2 > W3 > W1. In addition, the width differences (W2 - W3) and (W3 - W1) can be in the range of about 0.5 nm to about 2.5 nm. According to an alternative embodiment, due to process reasons, there is a relationship of W2 > W1 > W3. On the other hand, the widths W1’, W2’, W3’ measured at a level slightly below the top surface of the STI region 22 can be equal to each other.

[0047] Some example values of the shown features are provided herein. According to some embodiments, the n-type source / drain region 42N has a straight edge 42E, where the height H1 is in the range of about 5 nm to about 50 nm. The width W4 of the single-fin source / drain region 42N can be in the range of about 20 nm to about 40 nm, and the width W5 of the double-fin source / drain region 42N can be in the range of about 33 nm to about 66 nm. The width W6 of the single-fin source / drain region 42P can be in the range of about 21 nm to about 45 nm, and the width W7 of the double-fin source / drain region 42P can be in the range of about 31 nm to about 71 nm. The height H2 of the dielectric strips 25’P and 25’N can be in the range of about 30 nm to about 130 nm, where the height H2 is measured from the top of the dielectric fin to the bottom of the corresponding underlying STI region 22.

[0048] Figure 16A and Figure 16B Perspective and cross-sectional views of the structure after forming the contact etch stop layer (CESL) 70 and the interlayer dielectric (ILD) 72 are respectively shown. The corresponding processes are shown as Figure 23Process 232 in the process flow 200 shown. The CESL 70 can be formed of silicon nitride, silicon carbonitride, etc. For example, conformal deposition methods such as ALD or CVD can be used to form the CESL 70. The ILD 72 can include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or another deposition method. The ILD 72 can also be formed of or include an oxygen-containing dielectric material, which can be silica-based, such as silica, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process such as a CMP process or a mechanical polishing process is performed to make the top surfaces of the ILD 72, the dummy gate stack 30, and the gate spacers 38 flush with each other.

[0049] Then, the dummy gate stack 30 is removed by etching, and the resulting structure is as Figure 17 shown. Trenches 74 are formed in the space left by the removed dummy gate stack 30.

[0050] Figure 18 The formation of the replacement gate stack 80 is shown, which includes replacement gate stacks 80P and 80N. The corresponding process is shown as process 234 in the process flow 200 as Figure 23 shown. The replacement gate stack 80 includes a gate dielectric 76 and a gate electrode 78. Next, an isolation region 82 is formed to cut the replacement gate stack 80 into gate stacks 80P and 80N, where the gate stack 80P is the replacement gate stack of a p-type FinFET, and the gate stack 80N is the replacement gate stack of an n-type FinFET. The isolation region 82 extends to the dielectric fin 25', such that the gate stack 80P is electrically disconnected from the corresponding gate stack 80N.

[0051] Then, the replacement gate stack 80 is etched back, thereby forming a recess between the opposing gate spacers 38. Next, as Figure 19 shown, a hard mask 84 is formed in the recess. According to some embodiments of the present disclosure, the formation of the hard mask 84 includes a deposition process of filling the recess with a dielectric material, and a planarization process of removing the excess dielectric material above the gate spacers 38 and the ILD 72. The hard mask 84 can be formed of, for example, silicon nitride or other similar dielectric materials.

[0052] Figure 19 Some features formed in subsequent processes are further shown, which can include source / drain contact plugs 86, source / drain silicide regions 88, and gate contact plugs 90. Thus, a p-type FinFET 92P and an n-type FinFET 92N are formed.

[0053] Figure 20 Shown according to some embodiments ofFigure 19 Top view of the structure shown. The P-type FinFET 92P includes a gate stack 80P and source / drain regions 42P formed based on the protruding fin 24'. The N-type FinFET 92N includes a gate stack 80N and source / drain regions 42N formed based on the protruding fin 24'.

[0054] Figure 21 Shows several possible cross-sectional shapes of the top of the dielectric fin 25'P or 25'NF( Figure 15 ). The first possible shape is square, where the angle formed between the top surface and the sidewall is substantially equal to 90 degrees. The second shape is chamfered, with a fixed angular transition at its upper vertex and a top length less than the width of the lower portion. The third shape is circular. The fourth shape is gourd-shaped.

[0055] Figure 22 Shows the shape of the features in the exemplary structure and represents Figure 15 the structure shown in, except that the p-type FinFET region 100P is shown to the right rather than the left of the n-type FinFET region 100N. It can be realized that the height H4 of the STI region 22 in the p-type FinFET region 100P can be greater than the height H5 of the STI region 22 in the n-type FinFET region 100N.

[0056] Embodiments of the present disclosure have some advantageous features. By performing an n-type epitaxial process first, it is easier to remove selective loss defects than by performing a p-type epitaxial process first. Therefore, the selective loss defects generated in the previous n-type epitaxial process can be easily removed in the subsequently performed p-type epitaxial process.

[0057] According to some embodiments of the present disclosure, a method includes: forming a first semiconductor fin and a first dielectric fin in an n-type FinFET region; forming a second semiconductor fin and a second dielectric fin in a p-type FinFET region; forming a first epitaxial mask to cover the second semiconductor fin and the second dielectric fin; performing a first epitaxial process to form an n-type epitaxial region based on the first semiconductor fin; removing the first epitaxial mask; forming a second epitaxial mask to cover the n-type epitaxial region and the first dielectric fin; performing a second epitaxial process to form a p-type epitaxial region based on the second semiconductor fin; and removing the second epitaxial mask, wherein after removing the second epitaxial mask, a first portion of the second epitaxial mask remains on the first dielectric fin. In an embodiment, after removing the first epitaxial mask, substantially no portion of the first epitaxial mask remains on the second dielectric fin. In an embodiment, each of the first epitaxial mask and the second epitaxial mask has a thickness in a range between about 0.5 nm and about 2.5 nm. In an embodiment, the method further includes forming a third dielectric fin that separates the n-type FinFET region from the p-type FinFET region, wherein at a time after removing the second epitaxial mask, a second portion of the second epitaxial mask remains on a first side of the third dielectric fin, wherein the first side faces the n-type FinFET region. In an embodiment, at the time, substantially no portion of the first epitaxial mask and the second epitaxial mask remains on a second side of the third dielectric fin, wherein the second side faces the p-type FinFET region. In an embodiment, in the first epitaxial process, a portion of the n-type semiconductor material for forming the n-type epitaxial region forms as a defect on the dielectric material in the p-type FinFET region, and during the second epitaxial process, the defect is removed. In an embodiment, the second epitaxial mask and the first dielectric fin are formed of the same dielectric material. In an embodiment, both the second epitaxial mask and the first dielectric fin include Si, O, C, and N. In an embodiment, the second epitaxial mask and the first dielectric fin are formed of different dielectric materials.

[0058] According to some embodiments of the present disclosure, a structure includes: an n-type FinFET region and a p-type FinFET region; an n-type FinFET located in the n-type FinFET region, wherein the n-type FinFET includes: a first semiconductor fin; a first gate stack located on the first semiconductor fin; and an n-type source / drain region located beside the first gate stack; a first dielectric fin located in the n-type FinFET region, wherein the first dielectric fin has a first width; a p-type FinFET located in the p-type FinFET region, wherein the p-type FinFET includes: a second semiconductor fin; a second gate stack located on the second semiconductor fin; and a p-type source / drain region located beside the second gate stack; and a second dielectric fin located in the p-type FinFET region, wherein the second dielectric fin has a second width smaller than the first width. In an embodiment, the first width is greater than the second width by a difference greater than about 1 nm. In an embodiment, the difference is in the range between about 1 nm and about 5 nm. In an embodiment, the first dielectric fin includes: an inner portion formed of a first material; and an outer portion located on the sidewalls of the inner portion, wherein the outer portion is formed of a second material different from the first material. In an embodiment, the second dielectric fin includes the first material and does not include the second material. In an embodiment, the inner portion of the first dielectric fin includes: an upper portion; a middle portion located below the upper portion, wherein the middle portion is in physical contact with the n-type source / drain region; and a lower portion located below the middle portion, wherein the lower portion does not form the outer portion on its sidewalls. In an embodiment, there is no fin between the n-type source / drain region and the first dielectric fin, and wherein there is no fin between the p-type source / drain region and the second dielectric fin.

[0059] According to some embodiments of the present disclosure, a structure includes: a semiconductor substrate; a plurality of isolation regions extending into the semiconductor substrate; a first n-type source / drain region and a second n-type source / drain region extending above a top surface of the plurality of isolation regions; a first dielectric fin located between the first n-type source / drain region and the second n-type source / drain region, wherein the first dielectric fin has a first width measured at a first level above the top surface of the plurality of isolation regions and a second width measured at a second level below the top surface of the plurality of isolation regions; a first p-type source / drain region and a second p-type source / drain region extending above the top surface of the plurality of isolation regions; and a second dielectric fin located between the first p-type source / drain region and the second p-type source / drain region, wherein the second dielectric fin has a third width measured at the first level and a fourth width measured at the second level, and wherein the first width is greater than the third width. In an embodiment, the second width is equal to the fourth width. In an embodiment, the first dielectric fin contacts the first n-type source / drain region and the second n-type source / drain region, and an upper portion of the first dielectric fin has the first width, and a lower portion of the first dielectric fin is narrower than the upper portion. In an embodiment, the first dielectric fin includes: an inner portion formed of a first material; and an outer portion located on sidewalls of the inner portion, wherein the outer portion is formed of a second material different from the first material.

[0060] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0061] Example 1 is a method of forming a semiconductor device, including: forming a first semiconductor fin and a second semiconductor fin in an n-type fin field-effect transistor (FinFET) region and a p-type FinFET region respectively; forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region respectively; forming a first epitaxial mask to cover the second semiconductor fin and the second dielectric fin; performing a first epitaxial process to form an n-type epitaxial region based on the first semiconductor fin; removing the first epitaxial mask; forming a second epitaxial mask to cover the n-type epitaxial region and the first dielectric fin; performing a second epitaxial process to form a p-type epitaxial region based on the second semiconductor fin; and removing the second epitaxial mask, wherein, after removing the second epitaxial mask, a first portion of the second epitaxial mask remains on the first dielectric fin.

[0062] Example 2 is the method according to Example 1, wherein, after removing the first epitaxial mask, substantially no portion of the first epitaxial mask remains on the second dielectric fin.

[0063] Example 3 is the method according to Example 1, wherein each of the first epitaxial mask and the second epitaxial mask has a thickness in a range between about 0.5 nm and about 2.5 nm.

[0064] Example 4 is the method according to Example 1, further including: forming a third dielectric fin that separates the n-type FinFET region from the p-type FinFET region, wherein, at a time after removing the second epitaxial mask, a second portion of the second epitaxial mask remains on a first side of the third dielectric fin, and the first side faces the n-type FinFET region.

[0065] Example 5 is the method according to Example 4, wherein, at the time, substantially no portion of the first epitaxial mask and the second epitaxial mask remains on a second side of the third dielectric fin, and the second side faces the p-type FinFET region.

[0066] Example 6 is the method according to Example 1, wherein, in the first epitaxial process, a portion of the n-type semiconductor material for forming the n-type epitaxial region is formed as a defect on the dielectric material in the p-type FinFET region, and during the second epitaxial process, the defect is removed.

[0067] Example 7 is the method according to Example 1, wherein the second epitaxial mask and the first dielectric fin are formed of the same dielectric material.

[0068] Example 8 is the method described in Example 7, wherein both the second epitaxial mask and the first dielectric fin comprise Si, O, C, and N.

[0069] Example 9 is the method described in Example 1, wherein the second epitaxial mask and the first dielectric fin are formed of different dielectric materials.

[0070] Example 10 is a semiconductor structure comprising: an n-type fin field-effect transistor (FinFET) region and a p-type FinFET region; an n-type FinFET located in the n-type FinFET region, wherein the n-type FinFET comprises: a first semiconductor fin; a first gate stack located on the first semiconductor fin; and an n-type source / drain region located beside the first gate stack; a first dielectric fin located in the n-type FinFET region, wherein the first dielectric fin has a first width; a p-type FinFET located in the p-type FinFET region, wherein the p-type FinFET comprises: a second semiconductor fin; a second gate stack located on the second semiconductor fin; and a p-type source / drain region located beside the second gate stack; and a second dielectric fin located in the p-type FinFET region, wherein the second dielectric fin has a second width smaller than the first width.

[0071] Example 11 is the structure described in Example 10, wherein the first width is greater than the second width by a difference of more than about 1 nm.

[0072] Example 12 is the structure described in Example 11, wherein the difference is in the range of about 1 nm to about 5 nm.

[0073] Example 13 is the structure described in Example 10, wherein the first dielectric fin comprises: an inner portion formed of a first material; and an outer portion located on the sidewalls of the inner portion, wherein the outer portion is formed of a second material different from the first material.

[0074] Example 14 is the structure described in Example 13, wherein the second dielectric fin comprises the first material and does not contain the second material.

[0075] Example 15 is the structure described in Example 13, wherein the inner portion of the first dielectric fin comprises: an upper portion; a middle portion located below the upper portion, wherein the middle portion is in physical contact with the n-type source / drain region; and a lower portion located below the middle portion, wherein the lower portion does not have the outer portion formed on its sidewalls.

[0076] Example 16 is the structure described in Example 10, wherein there is no fin between the n-type source / drain region and the first dielectric fin, and wherein there is no fin between the p-type source / drain region and the second dielectric fin.

[0077] Example 17 is a semiconductor structure, comprising: a semiconductor substrate; a plurality of isolation regions extending into the semiconductor substrate; a first n-type source / drain region and a second n-type source / drain region extending above a top surface of the plurality of isolation regions; a first dielectric fin located between the first n-type source / drain region and the second n-type source / drain region, wherein the first dielectric fin has a first width measured at a first level above the top surface of the plurality of isolation regions and a second width measured at a second level below the top surface of the plurality of isolation regions; a first p-type source / drain region and a second p-type source / drain region extending above the top surface of the plurality of isolation regions; and a second dielectric fin located between the first p-type source / drain region and the second p-type source / drain region, wherein the second dielectric fin has a third width measured at the first level and a fourth width measured at the second level, and wherein the first width is greater than the third width.

[0078] Example 18 is the structure described in Example 17, wherein the second width is substantially equal to the fourth width.

[0079] Example 19 is the structure described in Example 17, wherein the first dielectric fin contacts the first n-type source / drain region and the second n-type source / drain region, and an upper portion of the first dielectric fin has the first width, and a lower portion of the first dielectric fin is narrower than the upper portion.

[0080] Example 20 is the structure described in Example 17, wherein the first dielectric fin comprises: an inner portion formed of a first material; and an outer portion located on sidewalls of the inner portion, wherein the outer portion is formed of a second material different from the first material.

Claims

1. A method of forming a semiconductor device, comprising: forming a first semiconductor fin in an n-type fin field-effect transistor (FinFET) region and a second semiconductor fin in a p-type FinFET region; forming a first dielectric fin in the n-type FinFET region and a second dielectric fin in the p-type FinFET region; forming a first epitaxial mask to cover the second semiconductor fin and the second dielectric fin; performing a first epitaxial process to form an n-type epitaxial region based on the first semiconductor fin; removing the first epitaxial mask; forming a second epitaxial mask to cover the n-type epitaxial region and the first dielectric fin; performing a second epitaxial process to form a p-type epitaxial region based on the second semiconductor fin; and removing the second epitaxial mask, wherein after removing the second epitaxial mask, a first portion of the second epitaxial mask remains on the first dielectric fin.

2. The method according to claim 1, wherein After removing the first epitaxial mask, substantially no portion of the first epitaxial mask remains on the second dielectric fin.

3. The method according to claim 1, wherein Each of the first epitaxial mask and the second epitaxial mask has a thickness in the range between 0.5 nm and 2.5 nm.

4. The method according to claim 1 further comprises: forming a third dielectric fin that separates the n-type FinFET region from the p-type FinFET region, wherein at a time after removing the second epitaxial mask, a second portion of the second epitaxial mask remains on a first side of the third dielectric fin, wherein the first side faces the n-type FinFET region.

5. The method according to claim 4, wherein At the time, no portion of the first epitaxial mask and the second epitaxial mask remains on a second side of the third dielectric fin, wherein the second side faces the p-type FinFET region.

6. The method according to claim 1, wherein, In the first epitaxial process, a portion of an n-type semiconductor material for forming the n-type epitaxial region is formed as a defect on a dielectric material in the p-type FinFET region, and during the second epitaxial process, the defect is removed.

7. The method according to claim 1, wherein The second epitaxial mask and the first dielectric fin are formed of the same dielectric material.

8. The method according to claim 7, wherein Both the second epitaxial mask and the first dielectric fin include Si, O, C, and N.

9. The method according to claim 1, wherein The second epitaxial mask and the first dielectric fin are formed of different dielectric materials.

10. A semiconductor structure, comprising: an n-type fin field-effect transistor (FinFET) region and a p-type FinFET region; an n-type FinFET located in the n-type FinFET region, wherein the n-type FinFET includes: a first semiconductor fin; a first gate stack located on the first semiconductor fin; and an n-type source / drain region located beside the first gate stack; a first dielectric fin located in the n-type FinFET region, wherein the first dielectric fin has a first width; a p-type FinFET located in the p-type FinFET region, wherein the p-type FinFET includes: a second semiconductor fin; a second gate stack located on the second semiconductor fin; and A p-type source / drain region, located beside the second gate stack; and A second dielectric fin, located in the p-type FinFET region, wherein the second dielectric fin has a second width smaller than the first width.

11. The semiconductor structure according to claim 10, wherein, The first width is greater than the second width by a difference greater than 1 nm.

12. The semiconductor structure according to claim 11, wherein, The difference ranges from 1 nm to 5 nm.

13. The semiconductor structure according to claim 10, wherein, The first dielectric fin includes: An inner portion, formed of a first material; and An outer portion, located on the sidewalls of the inner portion, wherein the outer portion is formed of a second material different from the first material.

14. The semiconductor structure according to claim 13, wherein, The second dielectric fin includes the first material and does not include the second material.

15. The semiconductor structure according to claim 13, wherein, The inner portion of the first dielectric fin includes: An upper portion; A middle portion, located below the upper portion, wherein the middle portion is in physical contact with the n-type source / drain region; and A lower portion, located below the middle portion, wherein the lower portion does not form the outer portion on its sidewalls.

16. The semiconductor structure according to claim 10, wherein, There is no fin between the n-type source / drain region and the first dielectric fin, and there is no fin between the p-type source / drain region and the second dielectric fin.

17. A semiconductor structure, comprising: A semiconductor substrate; A plurality of isolation regions, extending into the semiconductor substrate; A first n-type source / drain region and a second n-type source / drain region, extending above the top surface of the plurality of isolation regions; A first dielectric fin, located between the first n-type source / drain region and the second n-type source / drain region, wherein the first dielectric fin has a first width measured at a first level above the top surface of the plurality of isolation regions and a second width measured at a second level below the top surface of the plurality of isolation regions; A first p-type source / drain region and a second p-type source / drain region, extending above the top surface of the plurality of isolation regions; and A second dielectric fin, located between the first p-type source / drain region and the second p-type source / drain region, wherein the second dielectric fin has a third width measured at the first level and a fourth width measured at the second level, and wherein the first width is greater than the third width.

18. The semiconductor structure according to claim 17, wherein, The second width is equal to the fourth width.

19. The semiconductor structure according to claim 17, wherein, The first dielectric fin contacts the first n-type source / drain region and the second n-type source / drain region, and the upper portion of the first dielectric fin has the first width, and the lower portion of the first dielectric fin is narrower than the upper portion.

20. The semiconductor structure according to claim 17, wherein, The first dielectric fin includes: An inner portion, formed of a first material; and An outer portion, located on the sidewalls of the inner portion, wherein the outer portion is formed of a second material different from the first material.

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