Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor packaging device and a manufacturing method thereof. By designing the semiconductor packaging device to include a redistribution layer, an isolation layer disposed on the redistribution layer, the water absorption of the isolation layer being less than that of the redistribution layer, a filling layer disposed on the isolation layer, and two functional chips disposed on the filling layer and electrically connected to the redistribution layer through the filling layer and the isolation layer, the two functional chips have a gap cavity therebetween, the gap cavity passes through the filling layer and abuts against the isolation layer, so that the isolation layer can block the diffusion of water vapor from the redistribution layer to the filling layer in a thermal cycle process, thereby avoiding stress caused by the accumulation of water vapor in the filling layer. In addition, since the two functional chips have the gap cavity passing through the filling layer, the filling layer can be prevented from being broken due to the extrusion between the two functional chips and the filling layer in the thermal cycle process.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] Currently, semiconductor packaging requires integrating different materials into the same semiconductor packaging device. Since different materials have different coefficients of thermal expansion (CTE), it is necessary to consider the various problems that may be caused by the deformation of different materials when the temperature changes.

[0003] Underfill (UF) is usually placed between two adjacent chips and in the bottom gap of each chip. Through simulation and testing, it has been found that because the coefficient of thermal expansion of the underfill is much greater than that of the chip, when heated at high temperature, it will cause the two chips to push against each other, which can easily cause the underfill to crack. Summary of the Invention

[0004] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0005] Rewire layer;

[0006] An isolation layer is disposed on the redistribution layer, and the water absorption of the isolation layer is less than that of the redistribution layer;

[0007] A filling layer is disposed on the isolation layer;

[0008] Two functional chips are disposed on the filling layer, pass through the filling layer and the isolation layer, and are electrically connected to the redistribution layer. There is a gap cavity between the two functional chips, and the gap cavity passes through the filling layer and abuts against the isolation layer.

[0009] In some optional embodiments, the upper surface of the redistribution layer is provided with a bump under metal, and the functional chip is provided with a metal bump below it. The metal bump of the functional chip is electrically connected to the bump under metal of the redistribution layer.

[0010] In some alternative implementations, the isolation layer has an opening corresponding to the upper surface of the metal under the bump.

[0011] In some alternative implementations, the thickness of the isolation layer at the edge corresponding to the opening is greater than the thickness of the portion of the under-bump metal exposed from the plane containing the upper surface of the redistribution layer.

[0012] In some alternative implementations, the water absorption of the insulating layer is less than 0.85%.

[0013] In some alternative implementations, the insulating layer comprises silicon dioxide.

[0014] In some alternative implementations, the isolation layer comprises a dry film photoresist.

[0015] In some alternative embodiments, the apparatus further includes:

[0016] A first encapsulation material is disposed on the redistribution layer and forms a receiving cavity with the upper surface of the redistribution layer. The two functional chips are disposed in the receiving cavity. The upper surfaces of the two functional chips are substantially coplanar with the upper surface of the first encapsulation material. The filling layer fills the gaps in the receiving cavity except for the void cavity.

[0017] In some alternative embodiments, the apparatus further includes:

[0018] A second encapsulating material is disposed within the cavity and matches the receiving cavity.

[0019] In some alternative embodiments, the apparatus further includes:

[0020] A thermally conductive layer is disposed on the two functional chips, covering the upper surface of the two functional chips and the upper surface of the first encapsulation material.

[0021] In some alternative embodiments, the surface of the isolation layer that contacts the void cavity has a recess.

[0022] In some alternative embodiments, the surface of the filling layer that contacts the void cavity has a recess.

[0023] In some alternative embodiments, the apparatus further includes:

[0024] A substrate, wherein the upper surface of the substrate is electrically connected to the lower surface of the redistribution layer.

[0025] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging device, comprising:

[0026] A redistribution layer is provided, wherein a bump under metal is provided on the upper surface of the redistribution layer;

[0027] An isolation layer is provided on the upper surface of the redistribution layer, excluding the upper surface of the metal under the bump, and the water absorption of the isolation layer is less than that of the redistribution layer.

[0028] Two functional chips are provided, and metal bumps are provided below the functional chips;

[0029] The two functional chips are bonded to the redistribution layer respectively, so that the metal bumps of each functional chip are electrically connected to the under-bump metal of the redistribution layer;

[0030] A bottom filler is filled between the two functional chips and the redistribution layer to form a filler layer;

[0031] The first package material is molded to form a first package material, which surrounds the redistribution layer and forms a receiving cavity with the upper surface of the redistribution layer, and the two functional chips are disposed in the receiving cavity.

[0032] The upper surface of the first packaging material is ground so that the upper surfaces of the two functional chips are substantially coplanar with the upper surface of the first packaging material;

[0033] A gap cavity is formed between the two functional chips, the gap cavity passing through the filling layer and abutting the isolation layer.

[0034] In the prior art, a redistribution layer is set under the chip, and the chip and the redistribution layer are fixed and bonded together by an underfiller. Since the thermal expansion coefficients of the underfiller and the functional chip are different, the underfiller may be squeezed and cracked. In addition, the dielectric layer in the redistribution layer usually has high water absorption. During thermal cycling, the underfiller in contact with the redistribution layer can easily receive moisture from the redistribution layer, which may also cause the underfiller to crack. Therefore, the semiconductor packaging apparatus and manufacturing method disclosed herein provide an isolation layer on the redistribution layer, the isolation layer having lower water absorption than the redistribution layer, a filling layer on the isolation layer, and two functional chips disposed on the filling layer. The two functional chips are electrically connected to the redistribution layer through the filling layer and the isolation layer. A gap cavity exists between the two functional chips, the gap cavity passing through the filling layer and abutting against the isolation layer. This allows the isolation layer to prevent moisture from the redistribution layer from diffusing into the filling layer during the thermal cycling process, avoiding stress caused by moisture accumulation in the filling layer. Furthermore, since the two functional chips have a gap cavity passing through the filling layer, compression between the two functional chips and the filling layer can be avoided during the thermal cycling process, thereby reducing the risk of the filling layer cracking due to compression and stress accumulation. Attached Figure Description

[0035] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0036] Figure 1 This is a longitudinal cross-sectional structural schematic diagram of one embodiment of a semiconductor packaging apparatus according to the present disclosure;

[0037] Figures 2A to 2E This is a longitudinal cross-sectional structural schematic diagram of a semiconductor packaging apparatus according to different embodiments of the present disclosure;

[0038] Figure 2F and 2G This is a partially enlarged longitudinal cross-sectional view according to an embodiment of the present disclosure;

[0039] Figures 3A to 3F This is a longitudinal cross-sectional view of a semiconductor packaging device manufactured at various stages according to an embodiment of the present disclosure;

[0040] Figures 4A to 4C This is a longitudinal cross-sectional schematic diagram of a semiconductor packaging device manufactured at various stages according to yet another embodiment of the present disclosure.

[0041] Symbol explanation:

[0042] 11-Redistribution layer; 111-Under-bump metal; 12-Isolation layer; 121-Opening; 13-Filling layer; 131-Vacuum cavity; 14-Functional chip; 141-Metal bump; 15-Thermal conductive layer; 161-First packaging material; 162-Second packaging material; 17-Substrate; 18-Carrier plate; 19-Photoresist. Detailed Implementation

[0043] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0044] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0045] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0046] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified.

[0047] refer to Figure 1 , Figure 1 This is a longitudinal cross-sectional structural diagram of one embodiment of the semiconductor packaging structure disclosed herein.

[0048] like Figure 1 As shown, the semiconductor packaging device 100 may include: a redistribution layer 11, an isolation layer 12, a fill layer 13, and two functional chips 14. Wherein:

[0049] The redistribution layer 11 can be a redistribution layer composed of conductive and dielectric materials. It should be noted that the fabrication process can employ currently known or future-developed redistribution layer formation technologies; this application does not specifically limit this. For example, redistribution layer 11 can be formed using methods including, but not limited to, photolithography, electroplating, and electroless plating. Here, the dielectric material can include organic and / or inorganic materials. Organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0050] An isolation layer 12 is disposed on the redistribution layer 11, and the water absorption of the isolation layer 12 is less than that of the redistribution layer 11.

[0051] Water absorption refers to the property of a material to absorb water. In this disclosure, the water absorption of a material is characterized by the percentage increase in weight of the material after it has fully absorbed water, relative to the weight of the material itself.

[0052] Since the water absorption of the isolation layer 12 is less than that of the redistribution layer 11, the isolation layer 12 can isolate moisture from the redistribution layer 11 to prevent moisture from the redistribution layer 11 from being conducted upwards during the thermal cycling process, which could cause the filling layer 13 on the isolation layer 12 to crack. Here, the isolation layer 12 can also increase the overall structural stress resistance of the semiconductor packaging device.

[0053] Optionally, the isolation layer 12 can be silicon dioxide (water absorption less than 0.1%), dry film photoresist (DF), or a spin-on dielectric (SOD) coating. DF has stronger hydrophilicity than the dielectric material of the redistribution layer 11, thus saving the surface treatment of the redistribution layer 11 before setting the filler layer 13.

[0054] A filler layer 13 is disposed on the isolation layer 12. Here, the filler layer 13 includes an underfill.

[0055] The water absorption of the isolation layer 12 can be less than 0.85%. It is understood that the water absorption of the bottom filler is typically about 0.85%. Because the water absorption of the isolation layer 12 is less than that of the filler layer 13, it can provide a better moisture barrier function than the filler layer 13.

[0056] Two functional chips 14 are disposed on the fill layer 13. The functional chips 14 are electrically connected to the redistribution layer 11 through the fill layer 13 and the isolation layer 12. A gap cavity 131 is provided between the two functional chips 14, which passes through the fill layer 13 and abuts against the isolation layer 12.

[0057] Functional chip 14 may include a die, an ASIC (Application Specific Integrated Circuit) chip, or an HBM (High Bandwidth Memory) chip, etc. Here, the two functional chips 14 can be the same chip or different chips, and technicians can select the functional chip 14 according to the actual chip packaging design.

[0058] Optionally, the void cavity 131 can be obtained by etching, and the etching method may include laser etching or plasma etching.

[0059] The technical effects that the semiconductor packaging apparatus 100 of the above embodiments provided in this disclosure can achieve include, but are not limited to:

[0060] First, by providing an isolation layer 12 between the redistribution layer 11 and the filling layer 13, since the water absorption of the isolation layer 12 is less than that of the redistribution layer 11, the moisture of the redistribution layer 11 can be prevented from diffusing into the filling layer 13 during thermal cycling, thereby avoiding delamination or cracking of the filling layer 13.

[0061] Secondly, by providing a cavity 131 between the two functional chips 14, during thermal cycling, if the filling layer 13 deforms, causing the two functional chips 14 to deform as well, the cavity 131 can accommodate the deformation of the two functional chips 14. Conversely, if the two functional chips 14 are also filled with a filling layer 13 without providing a cavity 131, the filling layer 13 may delaminate or crack due to compression and stress accumulation during deformation.

[0062] refer to Figures 2A to 2E , Figures 2A to 2E This is a longitudinal cross-sectional structural diagram of different embodiments of the semiconductor packaging device disclosed herein. Figures 2A to 2E The semiconductor packaging devices 200A, 200B, 200C, 200D, and 200E shown are similar to Figure 1 The semiconductor packaging device 100 shown differs in that:

[0063] like Figures 2A to 2E As shown, in some optional embodiments, a bump under-metal 111 is provided on the upper surface of the redistribution layer 11, and a metal bump 141 is provided below the functional chip 14. The metal bump 141 of the functional chip 14 is electrically connected to the bump under-metal 111 of the redistribution layer 11. It is understood that the metal bump 141 has a conductive function and is electrically connected to the active surface of the functional chip 14.

[0064] An opening 121 is provided on the upper surface of the metal 111 under the corresponding bump in the isolation layer 12.

[0065] In some alternative embodiments, the surface of the filling layer 13 that contacts the void cavity 131, and / or the surface of the insulating layer 12 that contacts the void cavity 131, may have a depression. Here, the depression is formed due to the etching process that forms the void cavity 131.

[0066] Figure 2F and Figure 2G for Figure 2AIn the partially enlarged schematic diagram within the dashed lines of the disclosed semiconductor packaging device 200A, in some optional embodiments, the thickness of the isolation layer 12 at the edge corresponding to the opening 121 may be greater than the thickness of the portion of the under-bump metal 111 exposed from the plane containing the upper surface of the redistribution layer 11. That is, the isolation layer 12 can horizontally shield the portion of the under-bump metal 111 exposed from the plane containing the upper surface of the redistribution layer 11, thereby protecting the under-bump metal 111 during the manufacturing process and preventing damage to the under-bump metal 111 during etching.

[0067] It is understandable that the local thickness of the isolation layer 12 is higher than that of the rest, and the local isolation layer 12 of this thickness can be formed by applying multiple layers of coating to the local area of ​​the isolation layer 12.

[0068] In some alternative implementations, such as Figures 2A to 2E As shown, semiconductor packages 200A, 200B, 200C, 200D, and 200E may also include:

[0069] The first encapsulation material 161 surrounds the redistribution layer 11 and forms a receiving cavity with the upper surface of the redistribution layer 11. Two functional chips 14 are disposed in the receiving cavity. The upper surfaces of the two functional chips 14 are substantially coplanar with the upper surface of the first encapsulation material 161. The filling layer 13 fills the gaps in the receiving cavity except for the void cavity 131.

[0070] The first package material 161 is located around the two functional chips 14, thereby providing protection for the two functional chips 14.

[0071] Here, the two surfaces being essentially coplanar can be considered as follows: the height difference between the two surfaces is no greater than 5 micrometers (μm), no greater than 2 micrometers (μm), no greater than 1 micrometer (μm), or no greater than 0.5 micrometers (μm).

[0072] In some alternative implementations, such as Figure 2B and 2D As shown, semiconductor packaging devices 200B and 200D may further include:

[0073] The second encapsulation material 162 is disposed within the cavity 131 and is matched with the receiving cavity 131.

[0074] The first encapsulation material 161 and the second encapsulation material 162 can be formed from various molding compounds. For example, molding compounds may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc. The coefficient of thermal expansion of the molding compound is much smaller than that of the filler layer 13, and it has high strength and is not easily broken.

[0075] The second encapsulation material 162 is located between the two functional chips 14 and is disposed within the cavity 131, matching the receiving cavity 131. During the thermal cycling process, the two functional chips 14 directly compress the second encapsulation material 162. The second encapsulation material 162 can support the two functional chips 14 to reduce stress accumulation, reduce the deformation amplitude of the compression between the two functional chips 14, and further reduce the risk of the filling layer 13 cracking.

[0076] In some alternative implementations, such as Figure 2A , 2C As shown in Figures 2 and 2E, semiconductor packaging devices 200A, 200C, and 200E also include:

[0077] A thermally conductive layer 15 is disposed on the two functional chips 14, covering the upper surfaces of the two functional chips 14 and the upper surface of the first encapsulation material.

[0078] The thermally conductive layer 15 may include metal or non-metal, and this disclosure does not specifically limit the material of the thermally conductive layer 15. For example, the thermally conductive layer 15 may be a photomask used in the etching process to form the void cavity 131.

[0079] The thermal conductive layer 15 has a thermal conductivity function and can conduct heat to the upper surface of the functional chip 14, thereby improving the heat dissipation effect of the semi-functional chip 14.

[0080] The following is for reference. Figure 2E , Figure 2E This is a longitudinal cross-sectional schematic diagram of an embodiment 200E of the semiconductor packaging apparatus according to the present disclosure. Figure 2E The semiconductor packaging device 200E shown is similar to Figure 2C The semiconductor packaging device 200C shown is different in that the semiconductor packaging device 200E further includes a substrate 17, the upper surface of which is electrically connected to the lower surface of the redistribution layer 11.

[0081] The substrate 17 can be of various types, and this disclosure does not specifically limit it. The substrate 17 may include organic and / or inorganic materials, wherein the organic materials may be, for example, polyamide fiber (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg, also known as semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while the inorganic materials may be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0082] The substrate 17 can also be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate.

[0083] The substrate 17 may also include interconnect structures, such as conductive traces and conductive vias. Here, the conductive vias may be through-holes, buried vias, or blind vias, and the through-holes, buried vias, or blind vias may be filled with conductive materials such as metals or metal alloys. Here, the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0084] The upper surface of substrate 17 and the lower surface of redistribution layer 11 can be electrically connected via an electrical connector. For example, the electrical connector can be a solder ball, solder bump, conductive pillar, solder pad, etc. In this way, the semiconductor package device 300F can achieve electrical connection with the outside world through substrate 17.

[0085] The following is for reference. Figures 3A to 3F , Figures 3A to 3F This is a longitudinal cross-sectional structural schematic diagram of semiconductor packaging devices 300A, 300B, 300C, 300D, 300E and 300F manufactured at various stages according to an embodiment of the present disclosure.

[0086] refer to Figure 3AA redistribution layer 11 is provided, and an isolation layer 12 is provided on the upper surface of the redistribution layer 11 other than the upper surface of the under-bump metal 111, wherein the water absorption of the isolation layer 12 is less than that of the redistribution layer 11.

[0087] The upper surface of the redistribution layer 11 is provided with a bump under metal 111.

[0088] Here, techniques such as printing, lamination, potting, coating, or similar methods can be used to deposit the isolation layer 12 onto the upper surface of the redistribution layer 11.

[0089] refer to Figure 3B First, two functional chips 14 are provided, and metal bumps 141 are provided below the functional chips 14.

[0090] The two functional chips 14 are then bonded to the redistribution layer 11, so that the metal bumps 141 of each functional chip 14 are electrically connected to the under-bump metal 111 of the redistribution layer 11.

[0091] Here, flip-chip bonding (FCB), thermal compression bonding (TCB), or similar techniques can be used to bond the functional chip 14 to the redistribution layer 11.

[0092] Finally, an underfill is filled between the two functional chips 14 and the redistribution layer 11 to form a fill layer 13.

[0093] refer to Figure 3C First, the first package 161 is formed by molding. The first package 161 surrounds the redistribution layer 11 and forms a receiving cavity with the upper surface of the redistribution layer 11. Two functional chips 14 are disposed in the receiving cavity.

[0094] The molding process can be selected from at least one of the following: transfer molding, injection molding, compression molding, liquid molding, and spray molding. The upper surface of the first package material 161 is then ground so that the upper surfaces of the two functional chips 14 are substantially coplanar with the upper surface of the first package material 161.

[0095] refer to Figure 3D First, after flipping the semiconductor packaging device 300C, remove the carrier plate 18.

[0096] Next, electrical connectors are placed on the surface of the redistribution layer 11. The specific implementation can be achieved using appropriate techniques depending on the type of electrical connector. For example, solder bumps can be placed on the bottom of the redistribution layer 11 using the controlled-collapsed chip connection (C4 method).

[0097] refer to Figure 3E The upper surface of the substrate 17 is electrically connected to the lower surface of the redistribution layer 11.

[0098] In electrical connection processes, techniques such as flip chip bonding (FCB), thermal compression bonding (TCB), or similar technologies can be used.

[0099] An underfill can also be filled between the substrate 17 and the redistribution layer 11 after electrical connection.

[0100] refer to Figure 3F A photomask is placed above the semiconductor packaging device 300E to form a thermally conductive layer 15, and then etched to form a gap cavity 131 between two functional chips 14. The gap cavity 131 passes through the filling layer 13 and abuts against the isolation layer 12 to form the semiconductor packaging device 300F.

[0101] The following is for reference. Figures 4A to 4C , Figures 4A to 4C This is a longitudinal cross-sectional structural diagram of semiconductor packaging devices 400A, 400B and 400C manufactured at various stages according to an embodiment of the present disclosure.

[0102] refer to Figure 4A First of all, in Figure 3C The provided semiconductor packaging device 300C has photoresist 19 on its top surface, which is etched to form a void cavity 131.

[0103] Then, it is molded to form the second encapsulation material 162.

[0104] refer to Figure 4B First, the photoresist 19 is removed after grinding, and the upper surfaces of the two functional chips 14 are made substantially coplanar with the upper surfaces of the first package material 161 and the second package material 162.

[0105] Then, the semiconductor packaging device 400A is flipped over and the carrier plate 18 is removed.

[0106] Finally, electrical connectors are placed on the surface of the redistribution layer 11.

[0107] Referring to 4C, the upper surface of the substrate 17 is electrically connected to the lower surface of the redistribution layer 11 to form a semiconductor packaging device 400C.

[0108] In electrical connection processes, techniques such as flip chip bonding (FCB), thermal compression bonding (TCB), or similar technologies can be used.

[0109] An underfill can also be filled between the substrate 17 and the redistribution layer 11 after electrical connection.

[0110] The method for manufacturing semiconductor structures disclosed herein can achieve similar technical effects to the aforementioned semiconductor structures, and will not be described in detail here.

[0111] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent components can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: a redistribution layer, an upper surface of the redistribution layer being provided with an under bump metal; an isolation layer, provided on the redistribution layer, the isolation layer having a water absorption less than the redistribution layer, the isolation layer being provided with an opening corresponding to an upper surface of the under bump metal, the opening of the isolation layer exposing the under bump metal, the isolation layer having a thickness at an edge of the opening higher than a thickness of a portion of the under bump metal exposed from a plane of the upper surface of the redistribution layer; a filling layer, provided on the isolation layer; two functional chips, provided on the filling layer, electrically connected to the redistribution layer, the two functional chips having a gap cavity therebetween, the gap cavity passing through the filling layer and abutting the isolation layer, the functional chips being provided with metal bumps thereunder.

2. The apparatus of claim 1, wherein, the metal bumps of the functional chips are electrically connected to the under bump metal of the redistribution layer.

3. The apparatus of claim 1, wherein, The device further comprises: a first encapsulant, surrounding the redistribution layer, forming a receiving cavity with the upper surface of the redistribution layer, the two functional chips being provided in the receiving cavity, upper surfaces of the two functional chips being substantially coplanar with an upper surface of the first encapsulant, the filling layer filling a gap of the receiving cavity except the gap cavity.

4. The apparatus of claim 3, wherein, The device further comprises: a second encapsulant, provided in the gap cavity, matching the receiving cavity.

5. The apparatus of claim 3, wherein, The device further comprises: a heat conduction layer, provided on the two functional chips, covering the upper surfaces of the two functional chips and the upper surface of the first encapsulant.

6. The apparatus of claim 1, wherein, a surface of the isolation layer in contact with the gap cavity has a recess.

7. The apparatus of claim 1, wherein, a surface of the filling layer in contact with the gap cavity has a recess.

8. The apparatus of claim 1, wherein, The device further comprises: a substrate, an upper surface of the substrate being electrically connected to a lower surface of the redistribution layer. 9.A method for manufacturing a semiconductor packaging device, comprising: providing a redistribution layer, an upper surface of the redistribution layer being provided with an under bump metal; providing an isolation layer on the upper surface of the redistribution layer except the upper surface of the under bump metal, the isolation layer having a water absorption less than the redistribution layer, the isolation layer having a thickness at an edge of the opening higher than a thickness of a portion of the under bump metal exposed from a plane of the upper surface of the redistribution layer; providing two functional chips, the functional chips being provided with metal bumps thereunder; bonding the two functional chips to the redistribution layer respectively, so that the metal bumps of each of the functional chips are electrically connected to the under bump metal of the redistribution layer; filling a bottom filler between the two functional chips and the redistribution layer to form a filling layer; molding to form a first encapsulant, the first encapsulant surrounding the redistribution layer, forming a receiving cavity with the upper surface of the redistribution layer, the two functional chips being provided in the receiving cavity; polishing an upper surface of the first encapsulant so that upper surfaces of the two functional chips are substantially coplanar with an upper surface of the first encapsulant; forming a gap cavity between the two functional chips, the gap cavity passing through the filling layer and abutting the isolation layer, wherein the filling layer fills a gap of the receiving cavity except the gap cavity.

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