Method for turning off a power semiconductor switch of a bridge circuit, bridge circuit and inverter comprising a bridge circuit

Abstract

The invention relates to a method for switching off power semiconductor switches of a bridge circuit (1), in which a first DC voltage connection (2) is connected to a first intermediate point (3) by means of a first power semiconductor switch (T1), the first intermediate point (3) is connected to an AC current connection (4) by means of a second power semiconductor switch (T2), the AC current connection (4) is connected to a second intermediate point (5) by means of a third power semiconductor switch (T3), and the second intermediate point (5) is connected to a second DC voltage connection (6) by means of a fourth power semiconductor switch (T4), and in which a neutral connection (7) is connected to the first intermediate point (3) by means of a fifth power semiconductor switch (T5) and to the second intermediate point (5) by means of a sixth power semiconductor switch (T6). The method comprises a switching-off process in which a configuration (K-O) is produced in which all power semiconductor switches (T1-T6) of the bridge circuit (1) are in the switched-off state. In the course of the switching-off process, configurations (K-3, K-5, K-9) are produced in which the fifth power semiconductor switch (T5) and the sixth power semiconductor switch (T6) are simultaneously in the switched-on state, while the first power semiconductor switch (T1) and the fourth power semiconductor switch (T4) are in the switched-off state. Furthermore, a bridge circuit (1) is disclosed, which has a control unit (8) which is designed to carry out such a method. In addition, an inverter (9) is disclosed, which comprises at least one such bridge circuit (1).

Description

TECHNICAL FIELD

[0001] The invention relates to a method for switching off power semiconductor switches of a bridge circuit. Furthermore, the invention relates to a bridge circuit having a control unit which is designed to implement such a method, and to an inverter comprising such a bridge circuit. BACKGROUND

[0002] Bridge circuits are used in power electronic converter circuits for converting one current form into another current form, for example in the case of an inverter for converting a direct current into an alternating current. Bridge circuits are usually composed of an arrangement of a plurality of series-connected and / or parallel-connected power semiconductor switches, wherein the connection points between the power semiconductor switches form the connection terminals of the bridge circuit. By means of different arrangements of different numbers of power semiconductor switches, a plurality of different, for the person skilled in the art known, bridge circuit topologies are obtained.

[0003] In order to convert one current form into another current form, the power semiconductor switches of the bridge circuit are switched on and off in operation in accordance with a defined switching pattern. In particular in the event of a fault, for example in the event of an overcurrent or an overvoltage, but also in the event of a conventional stoppage of the converter circuit, it is necessary to bring all the power semiconductor switches of the bridge circuit into the switched-off state, in the event of a fault even as quickly as possible. In this case, it is conceivable and is generally the case according to the prior art to place the control signals of all the power semiconductor switches of the bridge circuit directly and simultaneously into a signal state which brings the power semiconductor switches of the bridge circuit into the switched-off state.

[0004] However, due to component tolerances, in particular when power semiconductor switches of different technologies, for example field effect transistors and bipolar transistors, are used within the bridge circuit, it can happen that, after being controlled to be brought into the switched-off state, individual power semiconductor switches of the bridge circuit are brought into the switched-off state more quickly than the other power semiconductor switches.

[0005] In the case of a bridge circuit of a multi-stage topology, by principle, the levels coupled with the different electrical potentials on the input connection terminals of the bridge circuit are applied to the output connection terminals of the bridge circuit. Thereby, when all power semiconductor switches of the bridge circuit are simultaneously operated, it can occur that, due to the aforementioned different speeds of the transition of the different power semiconductor switches into the switched-off state, in combination with the then occurring currents due to the additionally present freewheeling diodes in the bridge circuit, higher voltages are applied to the individual power semiconductor switches of the bridge circuit for a short time compared to during the regular operation of the converter circuit. These higher voltages can be able to cause a damage of the individual power semiconductor switches of the bridge circuit.

[0006] A bridge circuit of a three-point topology is known, for example, from document EP 2 779 345 A1, in which a first DC voltage connection is connected with a second DC voltage connection by means of a series circuit of four power semiconductor switches, and in which the connection point between the second and third power semiconductor switches of the series circuit forms an AC current connection. The connection points between the first and second power semiconductor switches of the series circuit and between the third and fourth power semiconductor switches of the series circuit are each connected with a neutral connection by means of a further power semiconductor switch, which neutral connection thus also forms a connection point of the two further power semiconductor switches. This bridge topology is also referred to as an ANPC bridge circuit (Active-Neutral-Point-Clamped-Brückenschaltung).

[0007] In the case of an ANPC bridge circuit, a split DC voltage intermediate circuit is usually connected with the DC voltage connection terminals of the bridge circuit, wherein the midpoint of the split DC voltage intermediate circuit is connected with the neutral connection of the bridge circuit. Then, in the regular operation of the ANPC bridge circuit, half of the intermediate circuit voltage is applied to each power semiconductor switch at most. In contrast, when all power semiconductor switches are simultaneously operated in order to be transitioned into the switched-off state, it can occur that the complete intermediate circuit voltage is applied to the individual power semiconductor switches, i.e. a value of twice the voltage occurring in operation.

[0008] Therefore, different forms of a shut-down process are described in the aforementioned document EP 2 779 345 A1, in which the power semiconductor switches of the ANPC bridge circuit are operated in order to be transitioned into the switched-off state in a defined sequence, but not simultaneously. If the first or fourth power semiconductor switch of the series circuit is in the switched-on state at the beginning of the shut-down process here, these power semiconductor switches are always transitioned into the switched-off state before all other power semiconductor switches, i.e. first, in the course of the shut-down process described in the aforementioned document EP 2 779 345 A1.

[0009] In the context of making a safe state as quickly as possible in the event of a fault, it can be advantageous when using different topologies of power semiconductor switches within a bridge circuit, to first operate the second or third power semiconductor switch of the series circuit into a turned-off state before all other power semiconductor switches, rather than first operating the first or fourth power semiconductor switch of the series circuit into a turned-off state as in the aforementioned document EP 2 779 345 A1.

[0010] In the turn-off process described in the aforementioned document EP 2 779 345 A1, it is not considered, inter alia, that the potential at the connection points between the first and second power semiconductor switches of the series circuit and between the third and fourth power semiconductor switches of the series circuit can float and, as a result, a voltage greater than half the intermediate circuit voltage can be applied across the respective power semiconductor switches in the course of the turn-off process. SUMMARY

[0011] It is therefore the task of the present invention to provide a method for turning off power semiconductor switches of a bridge circuit or a corresponding bridge circuit, in which it is possible to achieve a configuration in which all power semiconductor switches of the bridge circuit are in a turned-off state, without, in the course of the turn-off process, a higher voltage occurring across the respective power semiconductor switches than in the normal operation of the bridge circuit.

[0012] According to the invention, this task is solved by the method according to the independent claim 1, by the bridge circuit according to the independent claim 15 and by the inverter comprising such a bridge circuit according to the independent claim 18. Advantageous embodiments of the invention are described in the dependent claims.

[0013] The method according to the application for switching off power semiconductor switches of a bridge circuit, in which a first DC voltage connection of the bridge circuit is connected via a first power semiconductor switch to a first intermediate point, which is connected via a second power semiconductor switch to an AC current connection of the bridge circuit, which is connected via a third power semiconductor switch to a second intermediate point, and which is connected via a fourth power semiconductor switch to a second DC voltage connection of the bridge circuit, and in which a neutral connection of the bridge circuit is connected via a fifth power semiconductor switch to the first intermediate point and via a sixth power semiconductor switch to the second intermediate point, comprises a switching-off process in which the following configuration is produced: in which configuration all power semiconductor switches of the bridge circuit are in the switched-off state. Here, the following configuration is produced deliberately in the course of the switching-off process: in which configuration the fifth power semiconductor switch and the sixth power semiconductor switch are simultaneously in the switched-on state, while the first power semiconductor switch and the fourth power semiconductor switch are in the switched-off state.

[0014] Since the fifth power semiconductor switch and the sixth power semiconductor switch are simultaneously in the switched-on state, it is brought about in this configuration that not only the potential on the first intermediate point between the first power semiconductor switch and the second power semiconductor switch, but also the potential on the second intermediate point between the third power semiconductor switch and the fourth power semiconductor switch, is fixedly clamped to the potential present on the neutral connection of the bridge circuit and thus can no longer float. As a result, the voltage applied to each power semiconductor switch of the bridge circuit can at most be the voltage applied between the first DC voltage connection and the neutral connection or between the second DC voltage connection and the neutral connection. Here, the switched-off state of the first power semiconductor switch and the switched-off state of the fourth power semiconductor switch prevent a short circuit between the first DC voltage connection and the neutral connection and between the second DC voltage connection and the neutral connection.

[0015] In the normal operation of the bridge circuit, for example, the following configuration occurs: in which configuration the first power semiconductor switch, the sixth power semiconductor switch and either the second power semiconductor switch or the third power semiconductor switch are in the switched-on state and all other power semiconductor switches are in the switched-off state. Then, in one embodiment of the method according to the application, it is possible to proceed from this configuration at the start of the switching-off process, to switch the fifth power semiconductor switch into the switched-on state in the course of the switching-off process after the first power semiconductor switch has been switched into the switched-off state in the course of the switching-off process.

[0016] Here, it is possible to turn the first power semiconductor switch into the turned-off state in the course of the turn-off process after the second power semiconductor switch or the third power semiconductor switch has already been turned into the turned-off state in the course of the turn-off process.

[0017] However, it is also possible to turn the second power semiconductor switch or the third power semiconductor switch into the turned-off state in the course of the turn-off process after the first power semiconductor switch has already been turned into the turned-off state in the course of the turn-off process.

[0018] Alternatively, it is also possible to simultaneously operate the second power semiconductor switch or the third power semiconductor switch and the first power semiconductor switch in order to be turned into the turned-off state in the course of the turn-off process. The time relationship of the turning into the turned-off state is then derived from the respective switching speed of the power semiconductor switches.

[0019] In another embodiment of the method according to the application, it is possible to turn the second power semiconductor switch or the third power semiconductor switch into the turned-off state in the course of the turn-off process after the fifth power semiconductor switch has already been turned into the turned-on state in the course of the turn-off process. In combination with the condition that the fifth power semiconductor switch is turned into the turned-on state in the course of the turn-off process after the first power semiconductor switch has already been turned into the turned-off state in the course of the turn-off process, it is also implicitly in this embodiment that the second power semiconductor switch or the third power semiconductor switch is turned into the turned-off state in the course of the turn-off process after the first power semiconductor switch has already been turned into the turned-off state in the course of the turn-off process.

[0020] In the normal operation of the bridge circuit, for example, the following configuration also occurs: in which the fourth power semiconductor switch, the fifth power semiconductor switch and either the second power semiconductor switch or the third power semiconductor switch are in the turned-on state and all other power semiconductor switches are in the turned-off state. Then, in another embodiment of the method according to the application, it is possible to start from this configuration at the beginning of the turn-off process, to turn the sixth power semiconductor switch into the turned-on state in the course of the turn-off process after the fourth power semiconductor switch has already been turned into the turned-off state in the course of the turn-off process.

[0021] Here, it is possible to turn the fourth power semiconductor switch into the turned-off state in the course of the turn-off process after the second power semiconductor switch or the third power semiconductor switch has already been turned into the turned-off state in the course of the turn-off process.

[0022] However, it is also possible to transition the second power semiconductor switch or the third power semiconductor switch into the switched-off state during the course of the switching-off process after the fourth power semiconductor switch has already been transitioned into the switched-off state during the course of the switching-off process.

[0023] Alternatively, it is also possible to simultaneously operate the second power semiconductor switch or the third power semiconductor switch and the fourth power semiconductor switch to be transitioned into the switched-off state during the course of the switching-off process. The time relationship of the transition into the switched-off state is then derived from the respective switching speed of the power semiconductor switches.

[0024] In another embodiment of the method according to the application, the second power semiconductor switch or the third power semiconductor switch is transitioned into the switched-off state during the course of the switching-off process after the sixth power semiconductor switch has already been transitioned into the switched-on state during the course of the switching-off process. In conjunction with the condition that the sixth power semiconductor switch is transitioned into the switched-on state during the course of the switching-off process after the fourth power semiconductor switch has already been transitioned into the switched-on state during the course of the switching-off process, it is also implicitly provided in this embodiment that the second power semiconductor switch or the third power semiconductor switch is transitioned into the switched-off state during the course of the switching-off process after the fourth power semiconductor switch has already been transitioned into the switched-off state during the course of the switching-off process.

[0025] In one configuration of the method according to the application, the fifth power semiconductor switch and the sixth power semiconductor switch are transitioned into the switched-off state during the course of the switching-off process after the following configuration has been produced during the course of the switching-off process, in which the fifth power semiconductor switch and the sixth power semiconductor switch are in the switched-on state and all other power semiconductor switches are in the switched-off state.

[0026] In this case, in the course of the switching-off process, starting from a configuration in which the fifth power semiconductor switch and the sixth power semiconductor switch are in the on state and all other power semiconductor switches are in the off state, the third power semiconductor switch is first brought into the on state when a positive current is present on the AC current connection, and the second power semiconductor switch is brought into the on state when a negative current is present on the AC current connection. Then, after the fifth power semiconductor switch and the sixth power semiconductor switch have previously been brought into the off state in the course of the switching-off process, the third power semiconductor switch or the second power semiconductor switch is brought into the off state again. The direction of the current as positive current or negative current is derived here from the fact that a positive potential is applied on the first DC voltage connection relative to the potential on the neutral connection and a negative potential is applied on the second DC voltage connection relative to the potential on the neutral connection, a current flow from the positive potential to the negative potential or to the potential on the neutral connection being referred to as positive current, or vice versa, a current flow from the negative potential to the positive potential or to the potential on the neutral connection being referred to as negative current.

[0027] In the previously described embodiments, it is possible, in the course of the switching-off process, to bring the third power semiconductor switch or the second power semiconductor switch into the off state after a time which can be predefined and / or after a zero crossing (Nulldurchgang) of the current which has occurred on the AC current connection, starting from the point in time at which the fifth power semiconductor switch and the sixth power semiconductor switch have already been brought into the off state.

[0028] The bridge circuit according to the application has a first power semiconductor switch, a second power semiconductor switch, a third power semiconductor switch, a fourth power semiconductor switch, a fifth power semiconductor switch and a sixth power semiconductor switch, wherein a first DC voltage connection of the bridge circuit is connected to a first intermediate point by means of the first power semiconductor switch, the first intermediate point is connected to an AC current connection of the bridge circuit by means of the second power semiconductor switch, the AC current connection is connected to a second intermediate point by means of the third power semiconductor switch, and the second intermediate point is connected to a second DC voltage connection of the bridge circuit by means of the fourth power semiconductor switch, and, in addition, a neutral connection of the bridge circuit is connected to the first intermediate point by means of the fifth power semiconductor switch and to the second intermediate point by means of the sixth power semiconductor switch. Furthermore, the bridge circuit according to the application has a control unit for actuating the power semiconductor switches of the bridge circuit in order to bring them from the off state into the on state and vice versa, and is characterized in that the control unit is designed to carry out the method according to the application.

[0029] In an embodiment of the bridge circuit according to the application, the power semiconductor switches are oriented in such a way that the first power semiconductor switch can realize a current flow from the first DC voltage connection to the first intermediate point in the on state, the second power semiconductor switch can realize a current flow from the first intermediate point to the AC current connection in the on state, the third power semiconductor switch can realize a current flow from the AC current connection to the second intermediate point in the on state, the fourth power semiconductor switch can realize a current flow from the second intermediate point to the second DC voltage connection in the on state, the fifth power semiconductor switch can realize a current flow from the first intermediate point to the neutral connection in the on state, and the sixth power semiconductor switch can realize a current flow from the neutral connection to the second intermediate point in the on state. For each power semiconductor switch, a diode in anti-parallel is arranged here, which is oriented in such a way that it can realize a current flow in the opposite direction to the current flow direction that the respective power semiconductor switch can realize in the on state.

[0030] In another embodiment of the bridge circuit according to the application, the second power semiconductor switch and the third power semiconductor switch are embodied as field effect transistors, in particular SiC-MOSFETs, and the other power semiconductor switches are embodied as bipolar transistors, in particular IGBTs in Si technology.

[0031] The arrangement of power semiconductor switches like in the bridge circuit according to the application occurs, for example, in a so-called ANPC bridge circuit, which applies three levels as a three-point topology to the AC voltage connections of the bridge circuit. However, the arrangement can also be part of a multi-level topology with more than three levels. In this case, further power semiconductor switches are connected in series with the first to fourth power semiconductor switches at the first DC voltage connection and the second DC voltage connection, the connection points of which form further intermediate points, which can in turn be connected to the neutral connection of the bridge circuit or to a further neutral connection of the bridge circuit by means of diodes or further power semiconductor switches. In this case, the teaching for operating the further power semiconductor switches is also easily derived from the teaching of the application, according to which the configuration is made purposefully in the course of the switching-off process in which the power semiconductor switches connected to one of the possible multiple neutral connections are simultaneously in the on state.

[0032] The inverter according to the application comprises at least one bridge circuit according to the application. Such an inverter according to the application can for example be a single-phase inverter in which two bridge circuits according to the application are clocked for example also in a staggered manner, but can also be a three-phase inverter in which at least three bridge circuits according to the application are clocked in a staggered manner.

[0033] In the present description of the method according to the application, the time relationships mentioned for the transition into the on or off state always refer to the end of the transition into the on or off state, that is to say the course of the transition into the on or off state can also completely overlap in time, as long as the end of the course meets the mentioned relationship. However, it is also possible to carry out the actuation to transition one power semiconductor switch into the on or off state only when the previously required transition of the other power semiconductor switch into the on or off state is complete. BRIEF DESCRIPTION OF DRAWINGS

[0034] In the following, the application is explained in more detail on the basis of the drawings. Herein, the drawings serve to illustrate embodiments of the application, but do not limit the application to the features shown.

[0035] Figure 1 A bridge circuit according to the application is shown;

[0036] Figure 2 A table showing the configuration of the states of the power semiconductor switches in the case of the method according to the application is shown;

[0037] Figure 3 A table showing the configuration of the states of the power semiconductor switches in the case of another embodiment of the method according to the application is shown;

[0038] Figure 4 A table showing the configuration of the states of the power semiconductor switches in the case of another embodiment of the method according to the application is shown;

[0039] Figure 5 A table showing the configuration of the states of the power semiconductor switches in the case of another embodiment of the method according to the application is shown;

[0040] Figure 6 A table showing the configuration of the states of the power semiconductor switches in the case of another embodiment of the method according to the application is shown;

[0041] Figure 7 A table showing the configuration of the states of the power semiconductor switches in the case of another embodiment of the method according to the application is shown;

[0042] Figure 8 Table showing the configuration of the states with the power semiconductor switches in the case of another embodiment of the method according to the application;

[0043] Figure 9 Table showing the configuration of the states with the power semiconductor switches in the case of another embodiment of the method according to the application;

[0044] Figure 10 Table showing the configuration of the states with the power semiconductor switches in the case of another embodiment of the method according to the application;

[0045] Figure 11 Table showing the configuration of the states with the power semiconductor switches in the case of another embodiment of the method according to the application; and

[0046] Figure 12 Inverter according to the application is shown. DETAILED DESCRIPTION

[0047] Figure 1 A bridge circuit 1 according to the application is shown, in which a first direct voltage connection 2 of the bridge circuit 1 is connected with a second direct voltage connection 6 of the bridge circuit 1 via a series circuit of a first power semiconductor switch T1, a second power semiconductor switch T2, a third power semiconductor switch T3 and a fourth power semiconductor switch T4. A connection point between the first power semiconductor switch T1 and the second power semiconductor switch T2 forms a first intermediate point 3, and a connection point between the third power semiconductor switch T3 and the fourth power semiconductor switch T4 forms a second intermediate point 5. An alternating current connection 4 of the bridge circuit 1 is formed via the connection point between the second power semiconductor switch T2 and the third power semiconductor switch T3.

[0048] The power semiconductor switches T1 to T4 are oriented such that the first power semiconductor switch T1 enables a current flow from the first direct voltage connection 2 to the first intermediate point 3 in the switched-on state, the second power semiconductor switch T2 enables a current flow from the first intermediate point 3 to the alternating current connection 4 in the switched-on state, the third power semiconductor switch T3 enables a current flow from the alternating current connection 4 to the second intermediate point 5 in the switched-on state, and the fourth power semiconductor switch T4 enables a current flow from the second intermediate point 5 to the second direct voltage connection 6 in the switched-on state. For each of the power semiconductor switches T1 to T4, a diode D1 to D4 is arranged in anti-parallel, which enables a current flow in the opposite direction to the possible current flow direction of the respective power semiconductor switch T1 to T4 in the switched-on state.

[0049] A series circuit of a fifth power semiconductor switch T5 and a sixth power semiconductor switch T6 is arranged between the first intermediate point 3 and the second intermediate point 5, the connection point of the fifth power semiconductor switch and the sixth power semiconductor switch forming a neutral connection 7 of the bridge circuit 1. The power semiconductor switches T5 and T6 are oriented such that the fifth power semiconductor switch T5 can realize a current flow from the first intermediate point 3 to the neutral connection 7 in the switched-on state, and the sixth power semiconductor switch T6 can realize a current flow from the neutral connection 7 to the second intermediate point 5 in the switched-on state. For each of the power semiconductor switches T5 and T6, a diode D5 or D6 connected in antiparallel is arranged such that, by means of the diode D5 or D6, a current flow in the opposite direction to the current flow that can be realized in the switched-on state of the respective power semiconductor switch T5 or T6 can be realized.

[0050] The bridge circuit 1 according to the application has a control unit 8 which provides the power semiconductor switches T1 to T6 with actuating signals G1 to G6 via control inputs, by means of which the power semiconductor switches T1 to T6 are actuated in order to be switched from the switched-off state into the switched-on state or vice versa. The control unit 8 is designed to switch the power semiconductor switches T1 to T6 on and off in the normal mode of operation by using an actuation method. For this purpose, different actuation methods are known to the person skilled in the art. In particular, however, the control unit 8 is designed to implement the method according to the application in order to produce, in the event of an application of a shut-off process, a configuration in which the power semiconductor switches T1 to T6 are all in the switched-off state.

[0051] In the embodiment in Figure 1 In the embodiment in

[0052] In another method of operation, the first and third power semiconductor switches T1 and T3, or the fourth and second power semiconductor switches T4 and T2, are switched on and off, depending on the sign of the voltage to be output on the AC voltage connection 4, complementarily to one another in the case of a PWM signal of high frequency, while the respective other power semiconductor switches of the power semiconductor switches T1 to T6 are switched on and off at the frequency of the AC current present on the AC voltage connection 4, in the case of the application of the other method of operation, completely independently of the method of operation used, but it is also possible for the other power semiconductor switches of the power semiconductor switches T1 to T6, for example the power semiconductor switches T1 and T4 or the power semiconductor switches T1 to T4, to be embodied as field-effect transistors and for the respective other power semiconductor switches to be embodied as bipolar transistors. It is also possible for all of the power semiconductor switches T1 to T6 to be embodied as field-effect transistors or for all of the power semiconductor switches T1 to T6 to be embodied as bipolar transistors.

[0053] In Figure 2 A possible embodiment of the switching-off process according to the method according to the application is shown in tabular form in Table 1, in which, in the configuration K-A present at the start of the switching-off process, the first, second and sixth power semiconductor switches T1, T2 and T6 are in the switched-on state and the third, fourth and fifth power semiconductor switches T3, T4 and T5 are in the switched-off state. Starting from this configuration present at the start of the switching-off process, the following configuration K-O is produced in which all of the power semiconductor switches T1 to T6 are in the switched-off state. To this end, the following configuration K-1 is first produced in which the second power semiconductor switch T2 has been transferred to the switched-off state. In the next step, the power semiconductor switch T1 is transferred to the switched-off state, as a result of which the configuration K-2 is obtained. In the third step, the fifth power semiconductor switch T5 is transferred to the switched-on state. As a result of this, the configuration K-3 is obtained in which, as is characteristic of the method according to the application, the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 are simultaneously in the switched-on state, while the first power semiconductor switch T1 and the fourth power semiconductor switch T4 are in the switched-off state. Subsequently, the fifth and sixth power semiconductor switches T5 and T6 are transferred to the switched-off state in order to produce the configuration K-O. Here, as is shown in the present example, the power semiconductor switches T5 and T6 can be simultaneously operated in order to be transferred to the switched-off state, but they can also be operated in succession in any order in order to be transferred to the switched-off state.

[0054] In Figure 3A further possibility of the configuration in the course of the switching-off process in the case of one embodiment of the method according to the application is shown in tabular form. Here, in the configuration K-B present at the start of the switching-off process, the first, third and sixth power semiconductor switches T1, T3 and T6 are in the on state and the second, fourth and fifth power semiconductor switches T2, T4 and T5 are in the off state, from this configuration present at the start of the switching-off process the configuration K-O is produced in such a way that first the following configuration K-4 is produced: in this configuration the first power semiconductor switch T1 has been transferred into the off state. By subsequently transferring the third power semiconductor switch T3 into the off state, the configuration K-2 is reached, from which configuration the configuration K-3 is produced by transferring the fifth power semiconductor switch T5 into the on state. Subsequently, in order to produce the configuration K-O, the fifth and sixth power semiconductor switches T5 and T6 are transferred into the off state by simultaneous actuation. Alternatively, the power semiconductor switches T5 and T6 can also be actuated in such a way that they are transferred into the off state one after the other in arbitrary order.

[0055] Figure 4 A further embodiment of the configuration with the states of the power semiconductor switches in the case of the method according to the application is shown. Here, from the configuration K-A present at the start of the switching-off process the configuration K-O is produced in such a way that, in the first step for producing the configuration K-2, the first and second power semiconductor switches T1 and T2 are not transferred into the off state one after the other as in the previous embodiment, but they are actuated simultaneously to be transferred into the off state. Then, from this, the configuration K-3 is produced by transferring the fifth power semiconductor switch T5 into the on state. Then, in this embodiment, the configuration K-O is not reached by simultaneous actuation of the fifth and sixth power semiconductor switches T5 and T6 to be transferred into the off state as in the previous embodiment, but the configuration K-O is reached in such a way that here first the configuration K-2 is produced by transferring the fifth power semiconductor switch T5 into the off state, and then in a further step the configuration K-O is produced by transferring the sixth power semiconductor switch T6 to be transferred into the off state. Of course, it is also possible that first the sixth power semiconductor switch T6 and then the fifth power semiconductor switch T5 are transferred into the off state in order to produce the configuration K-O.

[0056] In Figure 5In the embodiment of the configuration shown in Fig. 6 in the course of the commutation process in the case of the method according to the application, the configuration K-O is produced from the configuration K-B present at the start of the commutation process in the following way: First, the configuration K-4 is produced by turning the first power semiconductor switch Tl into the off state. Then, in the next step, the configuration K-5 is produced by turning the fifth power semiconductor switch T5 into the on state, and in another step, the configuration K-3 is produced by turning the third power semiconductor switch T3 into the off state. That is, in this embodiment, after the fifth power semiconductor switch T5 has been turned into the on state in the course of the commutation process, the third power semiconductor switch T3 is turned into the off state. In this embodiment, two configurations are thus obtained in the form of the configurations K-5 and K-3 in which, as characterised for the method according to the application, the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 are simultaneously in the on state, while the first power semiconductor switch Tl and the fourth power semiconductor switch T4 are in the off state. Finally, the configuration K-O is produced by turning the fifth and sixth power semiconductor switches T5 and T6 into the off state, in the present case, for example, by simultaneous actuation.

[0057] Figure 6 The embodiment in Fig. 6 shows in tabular form the commutation process according to the method according to the application in which, in the configuration K-C present at the start of the commutation process, the third, fourth and fifth power semiconductor switches T3, T4 and T5 are in the on state and the first, second and sixth power semiconductor switches Tl, T2 and T6 are in the off state, the configuration K-O is produced from this configuration. To this end, first, the configuration K-6 is produced by turning the third power semiconductor switch T3 into the off state, and in the next step, the configuration K-7 is produced, in which the fourth power semiconductor switch T4 has been turned into the off state. Then, the configuration K-3 is obtained by turning the sixth power semiconductor switch T6 into the on state, from which configuration the configuration K-O is produced by turning the fifth and sixth power semiconductor switches T5 and T6 into the off state, here, for example, by simultaneous actuation.

[0058] In the case of the method according to the application, the configuration K-O is produced from the configuration K-B present at the start of the commutation process in the following way: First, the configuration K-4 is produced by turning the first power semiconductor switch Tl into the off state. Then, in the next step, the configuration K-5 is produced by turning the fifth power semiconductor switch T5 into the on state, and in another step, the configuration K-3 is produced by turning the third power semiconductor switch T3 into the off state. That is, in this embodiment, after the fifth power semiconductor switch T5 has been turned into the on state in the course of the commutation process, the third power semiconductor switch T3 is turned into the off state. In this embodiment, two configurations are thus obtained in the form of the configurations K-5 and K-3 in which, as characterised for the method according to the application, the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 are simultaneously in the on state, while the first power semiconductor switch Tl and the fourth power semiconductor switch T4 are in the off state. Finally, the configuration K-O is produced by turning the fifth and sixth power semiconductor switches T5 and T6 into the off state, in the present case, for example, by simultaneous actuation. Figure 7In the embodiment in Fig. 6, from the configuration K-D present at the start of the switching-off process, the configuration K-O is produced in such a way that first the configuration K-8 is produced in which the fourth power semiconductor switch T4 has been transferred into the switched-off state, then the configuration K-7 is produced by transferring the second power semiconductor switch T2 into the switched-off state, the configuration K-3 is produced by transferring the sixth power semiconductor switch T6 into the switched-on state, and finally the configuration K-O is produced by transferring the fifth and sixth power semiconductor switches T5 and T6 into the switched-off state, in this embodiment by simultaneous actuation of T5 and T6.

[0059] In the embodiment in Fig. 6, from the configuration K-D present at the start of the switching-off process, the configuration K-O is produced in such a way that first the configuration K-8 is produced in which the fourth power semiconductor switch T4 has been transferred into the switched-off state, then the configuration K-7 is produced by transferring the second power semiconductor switch T2 into the switched-off state, the configuration K-3 is produced by transferring the sixth power semiconductor switch T6 into the switched-on state, and finally the configuration K-O is produced by transferring the fifth and sixth power semiconductor switches T5 and T6 into the switched-off state, in this embodiment by simultaneous actuation of T5 and T6. Figure 8 Another embodiment of the configurations with the states of the power semiconductor switches in the case of the method according to the application is shown in tabular form in Fig. 7. Here, from the configuration K-C present at the start of the switching-off process, the configuration K-O is produced in such a way that in a first step the third and fourth power semiconductor switches T3 and T4 are simultaneously actuated to be transferred into the switched-off state, which then leads to the configuration K-7 being produced. From this, the configuration K-3 is then produced by transferring the sixth power semiconductor switch T6 into the switched-on state. Then, the configuration K-O is reached in such a way that first the configuration K-2 is produced by transferring the fifth power semiconductor switch T5 into the switched-off state, and then in another step the configuration K-O is produced by transferring the sixth power semiconductor switch T6 into the switched-off state. Alternatively, it is of course also possible for the sixth power semiconductor switch T6 to be transferred into the switched-off state first, then the fifth power semiconductor switch T5, in order to produce the configuration K-O, or alternatively the two power semiconductor switches T5 and T6 are simultaneously actuated to be transferred into the switched-off state, for example in the embodiment in Figs. 5, 6 and 7. Figure 2 , 3 , 5, 6 and 7.

[0060] Figure 9The embodiment illustrates the configuration during the cut-off process according to the method of the invention, in which configuration KO is manufactured starting from configuration KD present at the beginning of the cut-off process, in the following manner: first, configuration K-8 is manufactured by switching the fourth power semiconductor switch T4 to the off state. Then, in the next step, configuration K-9 is manufactured by switching the sixth power semiconductor switch T6 to the on state, and in another step, configuration K-3 is manufactured by switching the second power semiconductor switch T2 to the off state. That is, in the process of this exemplary cut-off process, the second power semiconductor switch T2 is switched to the off state after the sixth power semiconductor switch T6 has been switched to the on state. In this embodiment, two configurations are thus obtained in the form of configurations K-9 and K-3, in which, as characterized for the method of the invention, the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 are simultaneously in the on state, while the first power semiconductor switch T1 and the fourth power semiconductor switch T4 are in the off state. Finally, the configuration KO is manufactured by switching the fifth and sixth power semiconductor switches T5 and T6 to the off state, for example, by simultaneous operation in the current situation.

[0061] exist Figure 10 Another embodiment of the method according to the invention is shown, in which, for example, starting from configuration KA present at the beginning of the cutting process, configuration K-3 is generated during the cutting process via configurations K-1 and K-2. Then, starting from this, based on the positive current I on the AC current connection terminal 4 of the bridge circuit 1... ac The configuration K-5 is manufactured by switching the third power semiconductor switch T3 to the ON state. Then, configuration K-10 is manufactured by switching the fifth and sixth power semiconductor switches T5 and T6 to the OFF state (in the current case, this is done simultaneously). Finally, after a predetermined duration T1 following the manufacture of configuration K-10, the third power semiconductor switch T3 is switched back to the OFF state, thereby manufacturing configuration K-10. Alternatively, or in addition to the predetermined duration T1, the current I on the AC current connection terminal 4 of the bridge circuit 1 after the manufacture of configuration K-10 can also be... ac Zero crossings are used as a standard for the transition from configuration K-10 to configuration KO.

[0062] In the method according to the invention Figure 11 In one embodiment, firstly, starting from configuration KC present at the beginning of the cutting process, configuration K-3 is created during the cutting process via configurations K-6 and K-7. Then, based on the negative current I at the AC current connection terminal 4 of the bridge circuit 1... acthe presence of the zero crossing of the current I ac the zero crossing of the current I ac In addition to the zero crossing of the current I

[0063] In addition to the embodiment shown in Figures 2 to 11 a number of other variants of the switching-off process can be derived, by means of which, in the case of the method according to the application, starting from the configuration K-A, K-B, K-C or K-D present at the start of the switching-off process, and depending on the method of actuation used in the normal operation of the bridge circuit 1 according to the application, starting also from other configurations present at the start of the switching-off process, the configuration K-O is produced, wherein these switching-off processes include at least one of the configurations K-3, K-5 or K-9 in which, as characterised for the method according to the application, the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 are simultaneously in the on state, while the first power semiconductor switch T1 and the fourth power semiconductor switch T4 are in the off state.

[0064] In the method according to the application, it is advantageous to wait after each transition from one configuration to the next until the transient processes in the current and the potential within the bridge circuit 1 have ended, and then to actuate the power semiconductor switches T1 to T6 to transition to the next configuration, respectively. This is advantageous in particular in the case of the configurations K-3, K-5 and K-9 in order to ensure defined values of the potential at the intermediate points 3 and 5.

[0065] In Figure 12An inverter 9 according to the application is shown in Fig. 1. This inverter first of all has a bridge circuit 1 according to the application. Between a first direct voltage connection 2 of the bridge circuit 1, which is connected to a first input connection 10 of the inverter 9, and a second direct voltage connection 6 of the bridge circuit 1, which is connected to a second input connection 11 of the inverter 9, a separate direct voltage intermediate circuit 12 is arranged. A neutral connection 7 of the bridge circuit 1 is connected to a midpoint 13 of the separate direct voltage intermediate circuit 12. An alternating current connection 4 of the bridge circuit 1 is connected via a thyristor 14 to a first output connection 16 of the inverter 9. Between the first output connection 16 of the inverter 9 and a second output connection 17, which is connected to the neutral connection 7 of the bridge circuit 1, a capacitor 15 is arranged. The capacitor 15 and the thyristor 14 together form a line filter 18 of the inverter 9.

[0066] In Figure 12 In the inverter 9 shown in Fig. 1, there is a so-called neutral potential N on the neutral connection 7 of the bridge circuit 1, in contrast to which there is a positive potential DC+ on the first direct voltage connection 2 of the bridge circuit 1 and a negative potential DC- on the second direct voltage connection 6 of the bridge circuit 1.

[0067] Figure 12 The inverter 9 in Fig. 1 is embodied in the present example as a single-phase inverter, which comprises a bridge circuit 1 according to the application. However, an inverter according to the application as a single-phase inverter can also have two bridge circuits 1 according to the application, which are operated in a staggered manner and whose first direct voltage connections 2 and second direct voltage connections 6 are connected. An inverter according to the application can also be embodied as a three-phase inverter, which then has at least three bridge circuits 1 according to the application, which are operated in a staggered manner and whose first direct voltage connections 2 and second direct voltage connections 6 are connected.

[0068] The application is not limited to the explicitly shown embodiments, but can be varied in a plurality of ways, in particular in combination with other shown or known embodiments to the person skilled in the art.

[0069] List of reference signs

[0070] 1 bridge circuit

[0071] 2 direct voltage connection

[0072] 3 midpoint

[0073] 4 alternating current connection

[0074] 5 midpoint

[0075] 6 DC voltage connection

[0076] 7 neutral connection

[0077] 8 control unit

[0078] 9 inverter

[0079] 10 input connection

[0080] 11 input connection

[0081] 12 DC voltage intermediate circuit

[0082] 13 midpoint

[0083] 14 throttle valve

[0084] 15 capacitor

[0085] 16 output connection

[0086] 17 output connection

[0087] 18 line filter

[0088] T1 power semiconductor switch

[0089] T2 power semiconductor switch

[0090] T3 power semiconductor switch

[0091] T4 power semiconductor switch

[0092] T5 power semiconductor switch

[0093] T6 power semiconductor switch

[0094] D1 diode

[0095] D2 diode

[0096] D3 diode

[0097] D4 diode

[0098] D5 diode

[0099] D6 diode

[0100] G1 control signal

[0101] G2 control signal

[0102] G3 control signal

[0103] G4 control signal

[0104] G5 steering signal

[0105] G6 steering signal

[0106] K-A configuration

[0107] K-B configuration

[0108] K-C configuration

[0109] K-D configuration

[0110] K-1 configuration

[0111] K-2 configuration

[0112] K-3 configuration

[0113] K-4 configuration

[0114] K-5 configuration

[0115] K-6 configuration

[0116] K-7 configuration

[0117] K-8 configuration

[0118] K-9 configuration

[0119] K-10 configuration

[0120] K-11 configuration

[0121] K-O configuration

[0122] DC+ potential

[0123] DC- potential

[0124] N potential

Claims

1. A method for turning off a power semiconductor switch of a bridge circuit (1), in which bridge circuit a first DC voltage connection (2) of the bridge circuit (1) is connected to a first intermediate point (3) by means of a first power semiconductor switch Tl, the first intermediate point (3) is connected to an AC current connection (4) of the bridge circuit (1) by means of a second power semiconductor switch T2, the AC current connection (4) is connected to a second intermediate point (5) by means of a third power semiconductor switch T3, and the second intermediate point (5) is connected to a second DC voltage connection (6) of the bridge circuit (1) by means of a fourth power semiconductor switch T4, in which bridge circuit a neutral connection (7) of the bridge circuit (1) is connected to the first intermediate point (3) by means of a fifth power semiconductor switch T5 and to the second intermediate point (5) by means of a sixth power semiconductor switch T6, characterized in that The method comprises a switching-off process in which the following final configuration K-O is produced: in the final configuration K-O all power semiconductor switches T1-T6 of the bridge circuit (1) are in the switched-off state, wherein the following configurations K-3, K-5, K-9 are produced purposefully in the course of the switching-off process: in the configurations K-3, K-5, K-9 the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 are simultaneously in the switched-on state, while the first power semiconductor switch T1 and the fourth power semiconductor switch T4 are in the switched-off state, wherein in the configurations K-A, K-B present at the beginning of the switching-off process the first power semiconductor switch T1, the sixth power semiconductor switch T6 and the second power semiconductor switch T2 are in the switched-on state, or the first power semiconductor switch, the sixth power semiconductor switch and the third power semiconductor switch T3 are in the switched-on state, and all other power semiconductor switches T2, T3, T4, T5 are in the switched-off state, from the configurations K-A, K-B present at the beginning of the switching-off process the fifth power semiconductor switch T5 is brought into the switched-on state in the course of the switching-off process after the first power semiconductor switch T1 has been brought into the switched-off state in the course of the switching-off process, wherein the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 are brought into the switched-off state in the course of the switching-off process after the following configuration has been produced in the course of the switching-off process: in the configuration the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 are in the switched-on state, and all other power semiconductor switches T1, T2, T3, T4 are in the switched-off state, wherein a positive potential relative to the potential on the neutral connection (7) is applied on the first direct-voltage connection (2) and a negative potential relative to the potential on the neutral connection (7) is applied on the second direct-voltage connection (6), wherein a positive potential relative to the potential on the neutral connection (7) is applied on the first direct-voltage connection (2) and a negative potential relative to the potential on the neutral connection (7) is applied on the second direct-voltage connection (6), In the course of the switching-off process, after the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 have been brought into the conducting state, the third power semiconductor switch T3 is brought into the conducting state when a positive current is present at the AC current connection (4), and the second power semiconductor switch T2 is brought into the conducting state when a negative current is present at the AC current connection (4).

2. The method of claim 1, wherein, After the second power semiconductor switch T2 or the third power semiconductor switch T3 has been brought into the non-conducting state in the course of the switching-off process, the first power semiconductor switch T1 is brought into the non-conducting state in the course of the switching-off process.

3. The method of claim 1, wherein, After the first power semiconductor switch T1 has been brought into the non-conducting state in the course of the switching-off process, the second power semiconductor switch T2 or the third power semiconductor switch T3 is brought into the non-conducting state in the course of the switching-off process.

4. The method of claim 1, wherein, In the course of the switching-off process, the second power semiconductor switch T2 and the first power semiconductor switch T1 are simultaneously brought into the non-conducting state, or the third power semiconductor switch T3 and the first power semiconductor switch T1 are simultaneously brought into the non-conducting state.

5. The method of claim 1, wherein, After the fifth power semiconductor switch T5 has been brought into the conducting state in the course of the switching-off process, the second power semiconductor switch T2 or the third power semiconductor switch T3 is brought into the non-conducting state in the course of the switching-off process.

6. A method for turning off a power semiconductor switch of a bridge circuit (1), in which bridge circuit a first DC voltage connection (2) of the bridge circuit (1) is connected to a first intermediate point (3) by means of a first power semiconductor switch Tl, the first intermediate point (3) is connected to an AC current connection (4) of the bridge circuit (1) by means of a second power semiconductor switch T2, the AC current connection (4) is connected to a second intermediate point (5) by means of a third power semiconductor switch T3, and the second intermediate point (5) is connected to a second DC voltage connection (6) of the bridge circuit (1) by means of a fourth power semiconductor switch T4, in which bridge circuit a neutral connection (7) of the bridge circuit (1) is connected to the first intermediate point (3) by means of a fifth power semiconductor switch T5 and to the second intermediate point (5) by means of a sixth power semiconductor switch T6, wherein The method comprises a switching-off process in which the following final configuration K-O is produced: in the final configuration K-O all power semiconductor switches T1-T6 of the bridge circuit (1) are in the switched-off state, characterized in that the following configurations K-3, K-5, K-9 are produced purposefully in the course of the switching-off process: in the configurations K-3, K-5, K-9 the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 are simultaneously in the switched-on state, while the first power semiconductor switch T1 and the fourth power semiconductor switch T4 are in the switched-off state, wherein in the configurations K-C, K-D present at the beginning of the switching-off process the fourth power semiconductor switch T4, the fifth power semiconductor switch T5 and the second power semiconductor switch T2 are in the switched-on state, or the fourth power semiconductor switch T4, the fifth power semiconductor switch T5 and the third power semiconductor switch T3 are in the switched-on state, and all other power semiconductor switches T1, T2, T3, T6 are in the switched-off state, from the configuration present at the beginning of the switching-off process the sixth power semiconductor switch T6 is brought into the switched-on state in the course of the switching-off process after the fourth power semiconductor switch T4 has been brought into the switched-off state in the course of the switching-off process, wherein the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 are brought into the switched-off state in the course of the switching-off process after the following configuration has been produced in the course of the switching-off process: in the configuration the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 are in the switched-on state, and all other power semiconductor switches T1, T2, T3, T4 are in the switched-off state, wherein a positive potential relative to the potential on the neutral connection (7) is applied on the first direct-voltage connection (2) and a negative potential relative to the potential on the neutral connection (7) is applied on the second direct-voltage connection (6), wherein a positive potential relative to the potential on the neutral connection (7) is applied on the first direct-voltage connection (2) and a negative potential relative to the potential on the neutral connection (7) is applied on the second direct-voltage connection (6), wherein, in the course of the switching-off process, after the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 have been brought into the on state and all other power semiconductor switches T1, T2, T3, T4 have been brought into the off state, the third power semiconductor switch T3 is brought into the on state when a positive current is present at the AC current connection (4) and the second power semiconductor switch T2 is brought into the on state when a negative current is present at the AC current connection (4), starting from the configuration.

7. The method of claim 6, wherein, After the second power semiconductor switch T2 or the third power semiconductor switch T3 has been brought into the off state in the course of the switching-off process, the fourth power semiconductor switch T4 is brought into the off state in the course of the switching-off process.

8. The method of claim 6, wherein, After the fourth power semiconductor switch T4 has been brought into the off state in the course of the switching-off process, the second power semiconductor switch T2 or the third power semiconductor switch T3 is brought into the off state in the course of the switching-off process.

9. The method of claim 6, wherein, In the course of the switching-off process, the second power semiconductor switch T2 and the fourth power semiconductor switch T4 are simultaneously brought into the off state, or the third power semiconductor switch T3 and the fourth power semiconductor switch T4 are simultaneously brought into the off state.

10. The method of claim 6, wherein, After the sixth power semiconductor switch T6 has been brought into the on state in the course of the switching-off process, the second power semiconductor switch T2 or the third power semiconductor switch T3 is brought into the off state in the course of the switching-off process.

11. The method of any one of claims 1 to 10, wherein, In the course of the switching-off process, the third power semiconductor switch T3 or the second power semiconductor switch T2 is brought into the off state after a time which can be predetermined and / or after a zero crossing of the current at the AC current connection (4) has occurred, starting from the time at which the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 have been brought into the off state. In the course of the switching-off process, the third power semiconductor switch T3 or the second power semiconductor switch T2 is brought into the off state after a time which can be predetermined and / or after a zero crossing of the current at the AC current connection (4) has occurred, starting from the time at which the fifth power semiconductor switch T5 and the sixth power semiconductor switch T6 have been brought into the off state.

12. A bridge circuit (1) having a first power semiconductor switch T1, a second power semiconductor switch T2, a third power semiconductor switch T3, a fourth power semiconductor switch T4, a fifth power semiconductor switch T5 and a sixth power semiconductor switch T6, wherein A first DC voltage connection (2) of the bridge circuit (1) is connected via the first power semiconductor switch T1 to a first intermediate point (3), which is connected via the second power semiconductor switch T2 to an AC current connection (4) of the bridge circuit (1), which is connected via the third power semiconductor switch T3 to a second intermediate point (5), and which is connected via the fourth power semiconductor switch T4 to a second DC voltage connection (6) of the bridge circuit (1), and furthermore a neutral connection (7) of the bridge circuit is connected via the fifth power semiconductor switch T5 to the first intermediate point (3) and via the sixth power semiconductor switch T6 to the second intermediate point (5), the bridge circuit furthermore having a control unit (8) for actuating the power semiconductor switches T1-T6 of the bridge circuit (1) in order to change from an off state into an on state or from an on state into an off state, characterized in that the control unit (8) is designed to carry out the method according to any one of claims 1 to 11.

13. The bridge circuit (1) according to claim 12, wherein The power semiconductor switches T1-T6 are oriented in such a way that the first power semiconductor switch T1 can realize a current flow from the first DC voltage connection (2) to the first intermediate point (3) in the on state, the second power semiconductor switch T2 can realize a current flow from the first intermediate point (3) to the AC current connection (4) in the on state, the third power semiconductor switch T3 can realize a current flow from the AC current connection (4) to the second intermediate point (5) in the on state, the fourth power semiconductor switch T4 can realize a current flow from the second intermediate point (5) to the second DC voltage connection (6) in the on state, the fifth power semiconductor switch T5 can realize a current flow from the first intermediate point (3) to the neutral connection (7) in the on state, and the sixth power semiconductor switch T6 can realize a current flow from the neutral connection (7) to the second intermediate point (5) in the on state, wherein for each power semiconductor switch T1-T6 there is arranged a diode D1-D6 in anti-parallel, which is oriented in such a way that it can realize a current flow in the opposite direction to the current flow which can be realized in the on state of the respective power semiconductor switch T1-T6.

14. The bridge circuit (1) according to claim 12 or 13, wherein The second power semiconductor switch T2 and the third power semiconductor switch T3 are embodied as field-effect transistors, and the other power semiconductor switches T1, T4, T5, T6 are embodied as bipolar transistors.

15. An inverter (9) comprising at least one bridge circuit (1) according to any one of claims 12 to 14.

Images