Chip computing device and computing system

Abstract

The application discloses a chip computing device and a computing system, relates to the technical field of integrated chips, and can increase the bandwidth of storage access and reduce the power consumption generated by storage access. The chip computing device comprises a storage array chip, an operation array chip and a programmable array chip. The storage array chip comprises a storage array used for storing data. The operation array chip comprises an operation array comprising at least one fixed operation unit used for realizing a fixed operation function. The programmable array chip comprises a programmable array used for dynamically scheduling the execution flow of the at least one fixed operation unit to obtain a target operation function. Any two of the storage array chip, the programmable array chip and the operation array chip are connected through a three-dimensional heterogeneous integration layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated chip, in particular to a chip computing device and a computing system. BACKGROUND

[0002] In order to adapt the hardware to the rapidly developing and changing computing network structure, reconfiguring computing power through programmable method has become an important development direction in the field.

[0003] However, as the operation scale of machine learning grows, the storage access capacity and bandwidth of the existing reconfigurable computing power unit increase sharply, the bandwidth of storage access is narrow, and the power consumption overhead generated by storage access is large, which is easy to form a memory wall. SUMMARY

[0004] Embodiments of the present application provide a chip computing device and a computing system, which can increase the bandwidth of storage access and reduce the power consumption generated by storage access.

[0005] In a first aspect, the present application provides a chip computing device, comprising:

[0006] a storage array chip comprising a storage array, the storage array being configured to store data;

[0007] an operation array chip comprising an operation array, the operation array comprising at least one fixed operation unit, the fixed operation unit being configured to implement a fixed operation function;

[0008] a programmable array chip comprising a programmable array, the programmable array being configured to dynamically schedule an execution flow of the at least one fixed operation unit to obtain a target operation function;

[0009] Any two of the storage array chip, the programmable array chip and the operation array chip are connected through a three-dimensional heterogeneous integration layer.

[0010] In some embodiments, the number of target operation functions is at least one.

[0011] In some embodiments, one of the storage array chip, the programmable array chip and the operation array chip comprises an external global storage access interface controller and an external global access bus, the external global storage access interface controller being connected with the external global access bus.

[0012] The storage array chip, the programmable array chip or the operation array chip comprises an internal global access bus, the internal global access bus being configured to connect functional arrays inside the chip.

[0013] The three-dimensional interconnection interface is arranged between adjacent chips of the storage array chip, the programmable array chip and the operation array chip.

[0014] The storage array chip, the programmable array chip and the operation array chip each include an internal local storage access line connected with the three-dimensional interconnection interface and the functional array.

[0015] In some embodiments, the storage array chip, the programmable array chip and the operation array chip each include an external storage access line connected with the three-dimensional interconnection interface and the functional array.

[0016] In some embodiments, the operation array chip includes a calculation interconnection line connected with the three-dimensional interconnection interface and the operation array.

[0017] In some embodiments, the storage array chip, the programmable array chip and the operation array chip each include an active layer and an internal metal layer.

[0018] The active layer includes the functional array, and / or the external global storage access interface controller.

[0019] The internal metal layer includes the external global access bus, and / or the internal local storage access line, and / or the internal global access bus, and / or the external storage access line, and / or the calculation interconnection line.

[0020] In some embodiments, adjacent chips of the storage array chip, the programmable array chip and the operation array chip are connected through a three-dimensional heterogeneous connection structure.

[0021] The three-dimensional heterogeneous connection structure includes the three-dimensional interconnection interface.

[0022] In some embodiments, a normal projection of the storage array on the programmable array chip covers the programmable array.

[0023] In some embodiments, the programmable array chip includes a controller, and the programmable array is connected with the controller.

[0024] The controller is configured to control the programmable array to dynamically schedule an execution flow of at least one fixed operation unit to obtain the target operation function; and / or,

[0025] The controller is configured to control the programmable array to execute a current target operation function based on result data obtained by executing a previous target operation function.

[0026] In some embodiments, the number of chip layers of the storage array chip is at least two; and / or,

[0027] the number of chip layers of the programmable array chip is at least two; and / or

[0028] the number of chip layers of the operation array chip is at least two.

[0029] In some embodiments, any two of the storage array, the programmable array and the operation array are disposed on the same layer of chip.

[0030] In some embodiments, at least one of the storage array chip, the programmable array chip and the operation array chip comprises a level conversion circuit.

[0031] In some embodiments, the storage array comprises one or a combination of at least two of a static random access memory, a dynamic random access memory, a Flash memory, a ferroelectric memory, a phase change memory, a magnetic memory and a variable resistance memory.

[0032] In some embodiments, the storage array chip comprises at least one of a storage array die and a storage array wafer; and / or,

[0033] the operation array chip comprises at least one of an operation array die and an operation array wafer; and / or,

[0034] the programmable array chip comprises at least one of a programmable array die and a programmable array wafer.

[0035] In a second aspect, the embodiments of the present application provide a computing system, comprising: a host system and the chip computing device according to the first aspect;

[0036] the chip computing device is provided with an external global storage access interface controller on chip is provided with an external leading-out interface;

[0037] the chip computing device is connected with the host system through the external leading-out interface.

[0038] The chip computing device and the computing system provided by the embodiments of the present application can use the programmable array to dynamically schedule the execution flow of at least one fixed operation unit to obtain a target operation function. The execution flow of the conventional fixed operation unit can be dynamically scheduled to obtain a plurality of different target operation functions, so that the operation function of the chip computing device can be reconfigured. Any two of the memory array chip, the programmable array chip and the operation array chip are connected through a three-dimensional heterogeneous integration layer, and the three-dimensional heterogeneous integration connection can form an ultra-large local bus bandwidth advantage between adjacent chips and across chips, so as to increase the bandwidth of the memory access and reduce the power consumption of the memory access. Unlike the conventional I / O interface, the I / O interface is an input / output interface. The programmable array and the operation array are connected to the memory array through the three-dimensional heterogeneous integration layer, so that the memory access can be completed in the chip computing device, the high bandwidth and low power consumption can be realized, the operation burden of the upper system can be transferred to the chip computing device, the computing power of the upper system can be unloaded, the memory access efficiency can be improved, and the power consumption can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 A structural schematic diagram of a chip computing device provided by the embodiments of the present application is provided.

[0040] Figure 2 A local cross-sectional structural schematic diagram of a chip computing device provided by the embodiments of the present application is provided.

[0041] Figure 3 A schematic structural block diagram of a computing system provided by the embodiments of the present application is provided. DETAILED DESCRIPTION

[0042] In order to better understand the technical solutions provided by the embodiments of the present application, the technical solutions of the embodiments of the present application will be described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific features in the embodiments of the present application and the embodiments are detailed descriptions of the technical solutions of the embodiments of the present application, and are not limitations of the technical solutions of the present application. In the case of no conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other.

[0043] In this article, relational terms such as first and second are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements limited by the statement "comprise one..." do not exclude the presence of other identical elements in the process, method, article or equipment comprising the elements. The term "more than two" includes two or more than two situations.

[0044] To adapt hardware to the rapidly evolving computing network architecture, programmable reconfiguration of computing power has become a key development direction in this field. However, as the computational scale of machine learning grows, the storage access capacity and bandwidth of existing reconfigurable computing units have increased dramatically. However, the bandwidth of storage access is relatively narrow, and the power consumption overhead of storage access is high, which can easily lead to the formation of a memory wall.

[0045] In view of this, embodiments of the present application provide a chip computing device and a computing system that can increase the bandwidth of storage access and reduce the power consumption generated by storage access.

[0046] In a first aspect of an embodiment of the present application, a chip computing device is provided. Figure 1 This is a schematic diagram of the structure of a chip computing device provided in an embodiment of the present application. Figure 1 As shown, the chip computing device provided by the embodiment of the present application includes: a storage array chip 100, a programmable array chip 200, and an operation array chip 300. The storage array chip 100 includes a storage array 110, which is used to store data; the operation array chip 300 includes an operation array 310, which includes at least one fixed operation unit, which is used to implement a fixed operation function; the programmable array chip 200 includes a programmable array 210, which is used to dynamically schedule the execution process of at least one fixed operation unit to obtain a target operation function; any two of the storage array chip 100, the programmable array chip 200, and the operation array chip 300 are connected by three-dimensional heterogeneous integration stacking.

[0047] The fixed operation function of the fixed operation unit includes, but is not limited to, any combination of a multiplier-adder, a multiplier, a ripple processor, a hash calculation, an encoder / decoder, a digital signal processor, and a machine learning special-purpose computing circuit. The operation array 310 can also include a hard-core IP, which can be understood as an existing solidified effective operation unit (hardware device) to increase the computing density, and the application does not make specific limitations, so that the effective operation density can be adaptively increased, that is, the density of the computing device is increased, and the types and quantities of operation functions are further increased. At least one hard-core IP can constitute a fixed operation unit, and the application does not make specific limitations. The fixed operation unit is generally a hard-core IP with relatively small granularity, so as to be combined with the programmable array 210 on the programmable array chip 200 to form a reconfigurable operation array with a certain versatility.

[0048] The programmable array 210 can adopt an FPGA (field programmable gate array) or an eFPGA (embedded field programmable gate array), and the programmable nature thereof can be used to dynamically schedule the execution flow of the fixed operation unit, and the application does not make specific limitations. The programmable array 210 can also include other hard-core IPs for increasing the operation function of the programmable array 210, and the application does not make specific limitations. The programmable array 210 obtains a target operation function by dynamically scheduling the execution flow of at least one fixed operation unit, the target operation function can be a combination of one or more fixed operation functions executed in a specific order, and the target operation function can implement a more complex operation combined data processing process. For example, a target operation function can implement an operation function of addition→multiplication→hash operation→encryption→decryption. The programmable array 210 obtains a target operation function by dynamically scheduling the fixed operation unit, which means that the programmable array 210 schedules the types and orders of multiple fixed operation units and the data input to the fixed operation unit based on programmable adjustment, and implements a reconfigurable operation that meets the target operation function. The programmable array 210 and the operation array 310 are connected through an interconnection interface to realize three-dimensional heterogeneous integrated stacking connection across chips, to realize dynamic scheduling of the programmable array 210 to the operation array 310, and to form a programmable operation storage array.

[0049] For example, the programmable array 210 can dynamically schedule the execution flow of the fixed operation unit based on an instruction sequence or a configuration file, the instruction sequence and the configuration file can be pre-stored in the programmable array 210 or pre-stored in the storage array 110, which can avoid external storage access, thereby avoiding power consumption caused by increased external storage access. The instruction sequence and the configuration file can also be sent to the programmable array 210 by the upper system, which can flexibly adjust the types of target operation functions obtained by the programmable array 210, and the application does not make specific limitations.

[0050] Exemplarily, the data stored in the storage array 110 can include target instructions issued by the upper system, and the target instructions can include instruction sequences; the data stored in the storage array 110 can include to-be-processed data issued by the upper system and result data obtained after the to-be-processed data is processed by the programmable array 210 and the operation array 310, and the result data can also be input data of other target operation functions; the upper system can read the result data from the storage array 110, and the application does not make specific limitation.

[0051] The chip computing device provided by the embodiment of the application can be used for dynamically scheduling the execution flow of at least one fixed operation unit to obtain a target operation function, and can obtain a plurality of different target operation functions by dynamically scheduling the execution flow of a conventional fixed operation unit, so that the operation function of the chip computing device can be reconfigured. Any two of the storage array chip 100, the programmable array chip 200 and the operation array chip 300 are connected through a three-dimensional heterogeneous integration layer, and the three-dimensional heterogeneous integration connection can form an ultra-large bandwidth advantage between adjacent chips and across chips, can increase the bandwidth of storage access, and reduce the power consumption of storage access. Unlike a conventional I / O interface, the I / O interface is an input and output interface, the programmable array 210 and the operation array 310 are directly connected with the storage array 110 through three-dimensional heterogeneous integration to establish a signal layer connection, complete storage access in the chip computing device, realize high bandwidth and low power consumption, transfer the operation burden of the upper system to the chip computing device, play a role of unloading the computing power of the upper system, avoid the computing unit accessing operation data through a storage wall, improve the storage access efficiency, and reduce the power consumption.

[0052] In some embodiments, the number of target operation functions is at least one. The target operation function is obtained by dynamically scheduling the execution flow of at least one fixed operation unit by the programmable array 210, the more the number of target operation functions, the more the computing steps, the higher the operation and storage access efficiency of the chip computing device, the more the chip computing device shares the computing power of the upper system, can improve the storage access efficiency, and reduce the power consumption.

[0053] In some embodiments, one of the storage array chip, the programmable array chip and the operation array chip comprises an external global storage access interface controller and an external global access bus, the external global storage access interface controller is connected with the external global access bus; the storage array chip, the programmable array chip or the operation array chip comprises an internal global access bus, the internal global access bus is used to connect the functional arrays inside the chip; a three-dimensional interconnection interface is arranged between the adjacent chips of the storage array chip, the programmable array chip and the operation array chip; the storage array chip, the programmable array chip and the operation array chip all comprise an internal local storage access line, the internal local storage access line is connected with the three-dimensional interconnection interface and the functional array respectively. The functional array can be the storage array 110, the programmable array 210 or the operation array 310. The chip serving as the chip communicating with the external device among the storage array chip 100, the programmable array chip 200 and the operation array chip 300 can be arranged at the top layer position of the chip computing device, the chip at the top layer can be arranged with the external global storage access interface controller and the external global access bus. The external global storage access interface controller is used to control the connection between the external global access bus and the external device, so as to realize the data interaction between the chip computing device and the external device, the external device can be a host system or other devices, which are not limited in the present application. The internal global access bus is used to connect the functional arrays inside the chip, the internal local storage access line is connected with the three-dimensional interconnection interface and the functional array respectively, the external global access bus in the chip at the top layer can realize the cross-chip data interaction through the three-dimensional interconnection interface and the internal local storage access line, and the internal global access bus can realize the data interaction between the functional arrays inside the chip.

[0054] For example, when the chip computing device and the external device perform storage access, the external global storage access interface controller controls the external global access bus to perform data transmission; when the internal chips of the chip computing device perform storage access, the external global storage access interface controller controls the external global access bus, the internal local storage access line and the internal global access bus, the internal local storage access line is used to connect the functional arrays across the chips, the internal global access bus is used to connect the functional arrays inside the same layer chip, and then the connection between the external global access bus and the functional arrays across the chips is realized, so as to realize the data transmission between the adjacent chips or across the chips in the chip computing device, and realize the time division multiplexing of the external global access bus and the internal global access bus.

[0055] In some embodiments, the storage array chip, the programmable array chip and the operation array chip each include an external storage access line connected with the three-dimensional interconnection interface and the functional array respectively. The external storage access line can realize the connection of the functional arrays between different chips through the three-dimensional interconnection interface. The external storage access line can be time-multiplexed. For example, when the external data access across chips is performed, the external storage access line is used to realize the external storage access across chips through the external storage access bus. When the internal data access across chips is performed, the external storage access line can be used alone to realize the data exchange across chips within the chip computing device. It should be noted that the internal global access behavior and the behavior of the external global storage access interface controller correspond to the internal calculation of the chip computing device and the data loading / reading of the chip computing device by the upper system respectively. The two behaviors do not occur at the same time, that is, the external global access bus and the external storage access line can be connected to realize the cross-array data exchange of the operation array 310 and / or the programmable array 210 at the time other than the data loading / reading of the chip computing device by the upper system.

[0056] For example, when the storage access between the chip computing device and the external device occurs, the external global storage access interface controller controls the data transmission through the external global access bus. When the storage access between the internal chips of the chip computing device occurs, the external global storage access interface controller releases the control of the external global access bus through the internal circuit such as the multiplexer, and time-multiplexes the external storage access line and the external global access bus released by the external global storage access interface controller, or time-multiplexes the internal local storage access line and the external global access bus released by the external global storage access interface controller, to realize the cross-array data exchange of the operation array 310 and / or the programmable array 210, that is, the internal global access.

[0057] In some embodiments, the operation array chip includes a calculation interconnection line connected with the three-dimensional interconnection interface and the operation array respectively. The programmable array chip can also include a calculation interconnection line, which can realize the connection between the operation arrays, or realize the connection between the programmable array and the fixed operation array through the three-dimensional interconnection interface.

[0058] For example, the storage array chip 100 can be arranged as the chip communicating with the outside on the top layer of the chip computing device, and the chip computing device with the structure of the storage array chip 100→the programmable array chip 200→the operation array chip 300 can meet most of the storage access requirements, and the resources of the internal global access bus and the external global access bus can be reconfigurably time-multiplexed. The operation array chip 300 can be arranged as the chip communicating with the outside on the top layer of the chip computing device, and the chip computing device with the structure of the operation array chip 300→the programmable array chip 200→the storage array chip 100 can also meet most of the storage access requirements.

[0059] For applications that are frequently dynamically reconfigured and sensitive to dynamic reconfiguration time, the programmable array chip 200 can be arranged as the chip communicating with the outside on the top layer of the chip computing device, and the programmable array chip 200 has an advantage in I / O density on the external device, such as the programmable array chip 200→the operation array chip 300→the storage array chip 100 and the programmable array chip 200→the storage array chip 100→the operation array chip 300.

[0060] For applications that are once loaded, have little input / output during running, and can directly realize external input / output from the operation array chip 300, such as database retrieval, the operation array chip 300 can be arranged as the chip communicating with the outside on the top layer of the chip computing device, such as the operation array chip 300→the storage array chip 100→the programmable array chip 200.

[0061] For applications in which the storage access behavior of the operation array chip 300 to the storage array chip 100 is fixed, especially the point-to-point storage access across the array region is fixed, the operation array chip 300 is designed to be adjacent to the storage array chip 100, and the density advantage of the storage access interconnection can be obtained, such as the storage array chip 100→the programmable array chip 200→the operation array chip 300.

[0062] For example, the storage array 110 can include one of an SRAM (static random access memory), a DRAM (dynamic random access memory), a Flash memory, an FRAM (ferroelectric memory), a PRAM (phase change memory), an MRAM (magnetic memory), and an RRA (variable resistance memory), or a combination of at least two of them. According to the type of the memory, the storage array 110 can be provided with a corresponding storage controller, and the present application is not limited in this regard.

[0063] For example, the memory array chip 100 can also include any external global memory access interface controller corresponding to the memory, such as an SRAM interface controller, a JEDEC-DRAM interface controller, a Flash interface controller, an AXI (Advanced eXtensible Interface, a bus protocol) interface control or other custom interface protocol controller, etc., for global memory access of the memory array 110 by external devices, which can be a host system or other devices, without limitation. The memory array chip 100 can also include an external global memory access bus of the external global memory access interface controller to all memory arrays 110 of the memory array chip 100 for external global memory access, which can include, but is not limited to, a NOC AXI AHB, etc. The interconnection width of the external global memory access bus of the external global memory access interface controller to all memory arrays of the memory array chip 100 does not need to be close to the sum of the internal local memory access widths of the chip computing device (usually tens of thousands to hundreds of thousands of widths), and can be designed according to the prior art width (tens to thousands) for implementation, because usually only the input and result data of the operation (which can be a computing process or a processing process) pass through the external global access bus, and the amount of memory access is relatively small in the total amount of memory access occurring in several operation steps. The use of three-dimensional heterogeneous integrated layer-by-layer connection can make the cross-chip connection of the memory array chip 100 not pass through the I / O circuit, because the driving, external level boosting (when output), external level reduction (when input), tri-state controller, ESD protection and surge protection circuit, etc. provided by the I / O circuit in the prior art can all be cancelled for the three-dimensional heterogeneous integrated interconnection within the same package at a close distance and with a small load.

[0064] The operation array 310 and / or the programmable array 210 and the storage array 110 are connected through a three-dimensional interconnection interface to form a programmable operation storage array. Cross-area storage access between the programmable operation storage arrays can be realized through an internal global access bus and / or a time-multiplexed internal global access interface. The form of the internal global access bus includes but is not limited to NOCA, AHB, etc., which is not limited in the present application. The bus width of the internal global access bus is designed with reference to the width of the internal local storage access interface, but does not need to reach the sum of all internal local storage access interface widths, because the operation steps corresponding to the general target operation function will try to avoid cross-programmable operation storage array storage access, i.e., the probability of cross-area storage access is relatively low compared to intra-area storage access. The internal global access bus and / or the time-multiplexed internal global access interface provide a data channel for cross-programmable operation storage array storage access with different starting points and destinations. In combination with the practical application characteristics that the probability of cross-area storage access is relatively low compared to intra-area storage access, the dynamic partial reconfiguration characteristics of the programmable routing network within the programmable array 210 and between the arrays can be used to establish a point-to-point internal global access bus additional channel (e.g., increase the bus bit width) on the basis of the internal global access bus, and the programmable resources are dynamically recycled after the cross-area storage access is completed: i.e., through the combination of the internal global access bus and the reconfigurable point-to-point interconnection channel designed by the hard core IP, a variable-bit-width internal global access bus is realized according to the operation step requirements.

[0065] Exemplarily, a variable-width internal global access bus is composed of an internal global access bus designed using hard-core IP and reconfigurable point-to-point interconnect channels, or it can be composed entirely of reconfigurable point-to-point interconnect channels. Application and architectural features can be combined to achieve dynamic reconfiguration and time-sharing of the external global access bus and the internal global access bus to reduce global interconnection overhead. These application and architectural features include: the external global access bus and the internal global access bus can be transferred across chips to their programmable array chip 200, utilizing the dynamic partial reconfiguration characteristics of the programmable routing network within and between programmable arrays 210 to perform dynamic functional reorganization; the external global access bus and the internal global access bus are both data channels for interconnecting all programmable computing storage arrays, and their physical layouts are similar; based on typical computing application requirements, the external global access bus and the internal global access bus have different high-load occupancy time segments: the former is intensive before and after the start of a computation, while the latter is used during the computation process. Part or all of the external global access bus and the internal global access bus are interconnected through the programmable routing network settings within the programmable array 210 and between arrays; combined with the dynamic reconstruction feature of the programmable routing network, resource management is performed on the merged reconfigurable global bus: when the external global access bus bandwidth is needed, part or all of the reconfigurable global bus resources are switched to the external global access bus interconnection through dynamic reconstruction; when the internal global access bus bandwidth is needed, part or all of the reconfigurable global bus resources are switched to the internal global access bus interconnection through dynamic reconstruction.

[0066] The chip computing device provided in the present application can be set in the top chip of the chip computing device as a chip for communicating with the outside. The top chip needs to be equipped with an external global storage access interface controller and an external global access bus, which can realize time-sharing multiplexing of the external global access bus and the internal global access bus, and can reduce the global interconnection overhead of the chip computing device.

[0067] In some embodiments, the memory array chip, the programmable array chip, and the computing array chip all include an active layer and an internal metal layer; the active layer includes a functional array, and / or an external global memory access interface controller; the internal metal layer includes an external global access bus, and / or an internal local memory access line, and / or an internal global access bus, and / or an external memory access line, and / or a computing interconnect line.

[0068] Adjacent chips among the storage array chip, the programmable array chip and the operation array chip are connected via a three-dimensional heterogeneous connection structure; the three-dimensional heterogeneous connection structure includes a three-dimensional interconnection interface.

[0069] For example, Figure 2A chip computing device partial cross-section structure schematic diagram is provided for the embodiments of the present application. As an example, the active layer can be a first active layer 150, a second active layer 250, or a third active layer 340; the internal metal layer can be a first internal metal layer 160, a second internal metal layer 260, or a third internal metal layer 350; the top metal layer can be a first top metal layer 170, a second top metal layer 270, or a third top metal layer 360. The three-dimensional heterogeneous connection structure can be a first three-dimensional heterogeneous connection structure 130 or a second three-dimensional heterogeneous connection structure 230. The memory array chip 100 includes a first substrate layer 140, a first active layer 150, a first internal metal layer 160, and a first top metal layer 170 arranged in sequence; the programmable array chip 200 can include a second substrate layer 240, a second active layer 250, a second internal metal layer 260, and a second top metal layer 270 arranged in sequence; the operation array chip 300 can include a third substrate layer 330, a third active layer 340, a third internal metal layer 350, and a third top metal layer 360 arranged in sequence. In combination Figure 1 and Figure 2 , the first three-dimensional heterogeneous connection structure 130 is arranged between the memory array chip 100 and the programmable array chip 200, and the second three-dimensional heterogeneous connection structure 230 is arranged between the programmable array chip 200 and the operation array chip 300. The first top metal layer 170 of the memory array chip 100 is arranged opposite to the second top metal layer 270 of the programmable array chip 200, corresponding to the face-to-face arrangement of the memory array chip 100 and the programmable array chip 200; the third top metal layer 360 of the operation array chip 300 is arranged opposite to the second substrate layer 240 of the programmable array chip 200, corresponding to the back-to-face arrangement of the programmable array chip 200 and the operation array chip 300, which is not specifically limited in the present application.

[0070] It should be noted that, Figure 1 As shown in the figure, the memory array chip 100 further includes a first structure 120, the programmable array chip 200 includes a second structure 220, and the operation array chip 300 includes a third structure 320. The first structure 120 and the second structure 220 correspond to the first three-dimensional heterogeneous connection structure 130 respectively, and the second structure 220 and the third structure 320 correspond to the second three-dimensional heterogeneous connection structure 230 respectively.

[0071] Figure 2The shown chip computing device stores the array chip 100 as the top layer chip, and the outermost interface layer 400 can be arranged on the side of the memory array chip 100 away from the programmable array chip 200, which can protect the chip computing device and lead out the external interface (PAD / BUMP) of the chip computing device. The first active layer 150 includes a memory array 110 and an external global memory access interface controller 151. The first internal metal layer 160 includes a plurality of metal connection lines, and the metal connection lines in the first internal metal layer 160 can include an external global access bus A, a first internal local memory access line B1, a second internal local memory access line B2, and an external memory access line C; the first top metal layer 170 includes a plurality of first connection lines 171; the first three-dimensional heterogeneous connection structure 130 includes a three-dimensional interconnection interface E, the first internal local memory access line B1 is connected to the first connection line 171, the first connection line 171 is connected to the three-dimensional interconnection interface E, and the connection of the memory array 110 and the programmable array 210 can be realized through the first internal local memory access line B1 and the three-dimensional interconnection interface E. The three-dimensional interconnection interface E and the first internal local memory access line B1 can realize the connection of the functional array across the chip. The second internal local memory access line B2 can connect the devices in the functional chip. The external memory access line C can be connected to the memory array 110 and the global access bus A respectively, and the external memory access line C is also connected to the three-dimensional interconnection interface E, so that the time division multiplexing of the external memory access line C can be used to realize the time division of internal memory access and external memory access in combination with the external global access bus A. The second top metal layer 270 can include a plurality of second connection lines 271; the second internal metal layer 260 can include a plurality of metal connection lines, and the metal connection lines in the second internal metal layer 260 can include an internal global access bus D, a first internal local memory access line B1, a second internal local memory access line B2, an external memory access line C, and a first computing interconnection line G1. The metal connection lines in the first internal metal layer 160 can also include an internal global access bus, and the metal connection lines in the third internal metal layer 350 can also include an internal global access bus. The second active layer 250 includes a programmable array 210, and the internal global access bus D can realize the interconnection between the programmable arrays 210. The chip computing device can also include a plurality of vias 500, which can pass through the substrate layer and the active layer, such as Figure 2As shown, the via 500 can pass through the first substrate layer 140 and the first active layer 150, and also pass through the second substrate layer 240 and the second active layer 250. The via 500 is used to connect the metal lines at both ends of the via 500. The third top metal layer 360 includes a plurality of third connection lines 361; the second three-dimensional heterogeneous connection structure 230 includes a three-dimensional interconnection port E, the third active layer 340 includes an operation array 310, and the three-dimensional interconnection port E is used to connect the operation array and the programmable array 210. The third internal metal layer 350 includes a first calculation interconnection line G1 and a second calculation interconnection line G2, the first calculation interconnection line G1 is used to connect the three-dimensional interconnection port E and the operation array 310 to realize cross-chip interconnection, and the second calculation interconnection line G2 is used to connect devices or lines within the operation array 310.

[0072] For example, the external global access bus A in the first internal metal layer 160 and the external storage access line C are interconnected, and then pass through the three-dimensional interconnection port E and the external storage access line C in the second internal metal layer 260 connected with the three-dimensional interconnection port E, so that the external global access bus A can be connected to the programmable array 210 across the chip. The external global access bus A is connected with the first internal local storage access line B1 in the first internal metal layer 160 through the storage array 110, and then passes through the first internal local storage access line B1 in the second internal metal layer 260 connected with the three-dimensional interconnection port E, so that the external global access bus A can be connected to the programmable array 210 across the chip, and then passes through the internal global access bus D to realize the connection between different programmable arrays 210, and finally realize the external storage access or internal storage access of the chip computing device. The first calculation interconnection line G1 in the second internal metal layer 260 is used to connect the programmable array 210 and the three-dimensional interconnection port E, and through the first calculation interconnection line G1 in the second internal metal layer 260, the three-dimensional interconnection port E and the first calculation interconnection line G1 in the third internal metal layer 350, the programmable array 210 can be connected with the operation array 310 across the chip, and finally realize the internal storage access of the chip computing device. The third connection line 361 can be used to connect the three-dimensional interconnection port E and the first calculation interconnection line G1.

[0073] It should be noted that the connection between the storage array 110 and the programmable array 210 can be one-to-one connection, many-to-one connection or one-to-many connection, which is not limited in the present application. Figure 2 The structure of the chip computing device shown is only illustrative, and is not a specific limitation of the present application.

[0074] The chip computing device provided by the embodiment of the present application can be arranged at the top layer position of the chip computing device as a chip for external communication, and the chip at the top layer is provided with an external global storage access interface controller 151 and an external global access bus chip computing device.

[0075] In some embodiments, the storage array is orthogonally projected onto the programmable array chip. It should be noted that the projection herein can be full or partial, and the present application does not make specific limitations.

[0076] For example, the programmable arrays 210 are distributed at the vertical projections of the physical locations of the corresponding storage arrays 110, and high-bandwidth interconnections, i.e., internal local storage access lines B, are established by three-dimensional heterogeneous integration. The bit width of the internal local storage access lines B of each group is usually several thousand to tens of thousands, and the total bit width is tens of thousands to hundreds of thousands, forming a programmable operation storage array with a distributed storage access structure.

[0077] The chip computing device provided by the embodiments of the present application has one-to-one correspondence between the programmable arrays 210 and the storage arrays 110, and one programmable array 210 and one storage array 110 can form a storage array, which can increase the bit width of the internal local storage access interface, realize high-bandwidth interconnection, and reduce the storage access power consumption.

[0078] In some embodiments, the programmable array chip includes a controller, such as a CPU / MCU, which is not specifically limited by the present application, and the programmable array is connected to the controller. The controller is configured to control the programmable array to dynamically schedule the execution flow of at least one fixed operation unit to obtain the target operation function; and / or, the controller is configured to control the programmable array to execute the current target operation function based on the result data obtained by executing the previous target operation function. It should be noted that the programmable array can execute the current target operation function based on the result data obtained by executing the previous target operation function, the initial operation data, or the result data obtained by executing other target operation functions, and the present application does not make specific limitations.

[0079] For example, one controller is provided for each programmable array 210 or a plurality of programmable arrays 210. The programming result of the programmable array 210 can be saved in the CRAM (config ram) in the programmable array 210. The power-off disappearance of the CRAM requires the controller to load the programming file from the programmable array 210. The controller can also be responsible for the boundary scan, online data observation and loading, and other functions of the programmable array 210. The controller can support dynamic partial reconfiguration function to switch the function of part of the programmable array 210 during the execution of the operation: for example, after the execution of a target operation function is completed, the corresponding programmable array 210 is dynamically reconfigured to the next target operation function, and the result data (partially or entirely stored in the corresponding storage array 110) obtained by executing the previous target operation function is inherited to implement the current target operation function. The controller can be implemented by using a processor such as a CPU, and the present application does not make specific limitations.

[0080] The chip computing device provided by the embodiments of the present application can control the reconfiguration of the programmable array 210 for the target operation function and the execution of the target operation function by setting the controller.

[0081] In some embodiments, the number of chip layers of the storage array chip is at least two; and / or,

[0082] The number of chip layers of the programmable array chip is at least two; and / or

[0083] The number of chip layers of the operation array chip is at least two.

[0084] The two layers of storage array chips can be connected through a three-dimensional heterogeneous connection structure, the two layers of programmable array chips can be connected through a three-dimensional heterogeneous connection structure, and the two layers of operation array chips can be connected through a three-dimensional heterogeneous connection structure.

[0085] The chip computing device provided by the embodiments of the present application can be set to a multi-layer chip structure according to the budget demand or the storage demand, so as to meet more operation and storage access demands. Specifically, for a large demand for storage access capacity, the number of layers of the storage chip can be set to at least two; for a large demand for operation amount, the number of layers of the operation chip can be set to at least two; and for a large demand for types of target operation functions, the number of layers of the programmable chip can be set to at least two.

[0086] In some embodiments, any two of the storage array, the programmable array and the operation array are arranged on the same layer of chip.

[0087] The chip computing device provided by the embodiments of the present application can combine any two kinds of chips into one layer of chip, which can specifically meet the case where the computing density demand is small.

[0088] In some embodiments, at least one of the storage array chip, the programmable array chip and the operation array chip comprises a level conversion circuit.

[0089] For example, when the storage array chip 100 has the same core voltage as the programmable array chip 200 and the operation array chip 300, the metal interconnection for three-dimensional heterogeneous integration is directly performed; when the storage array chip 100 has different core voltage from the programmable array chip 200 and the operation array chip 300, a level conversion circuit needs to be designed, which can be designed on the storage array chip 100, usually on or near the bonding area of three-dimensional heterogeneous integration, which is not limited in the present application.

[0090] Exemplarily, when the core voltage of the storage array chip 100 is different from that of the programmable array chip 200, a level conversion circuit is arranged on the storage array chip 100, which can also be transferred to the programmable array chip 200 in combination with the three-dimensional heterogeneous integration, usually on or near the three-dimensional heterogeneous integration bonding area; when the core voltage of the programmable array chip 200 is the same as that of the operation array chip 300, the metal interconnection of the three-dimensional heterogeneous integration is directly performed; when the core voltage of the programmable array chip 200 is different from that of the operation array chip 300, a level conversion circuit needs to be arranged on the programmable array chip 200, usually on or near the three-dimensional heterogeneous integration bonding area.

[0091] The chip computing device provided by the embodiment of the present application can realize the storage access across chips in the case that the core voltages of different chips are different, by arranging the level conversion circuit.

[0092] In some embodiments, the storage array chip can include at least one of a storage array die and a storage array wafer; and / or,

[0093] The operation array chip can include at least one of an operation array die and an operation array wafer; and / or,

[0094] The programmable array chip can include at least one of a programmable array die and a programmable array wafer.

[0095] It should be noted that the chip can be at least one of a die or a chip, a wafer, but is not limited thereto, and can be any alternative as conceived by those skilled in the art. The wafer refers to a silicon wafer used for manufacturing a silicon semiconductor circuit, and the chip or die refers to a silicon wafer obtained by dividing the wafer on which the semiconductor circuit is manufactured. The chip is taken as an example for introduction in the specific embodiments of the present application.

[0096] In a second aspect, the embodiment of the present application provides a computing system, including: a host system and the chip computing device as described in the first aspect; the chip computing device is provided with an external global storage access interface controller, and the chip is provided with an external leading-out interface; the chip computing device is connected with the host system through the external leading-out interface.

[0097] Exemplarily, Figure 3 A schematic structural block diagram of a computing system provided by the embodiment of the present application is shown in FIG. 2. As shown in FIG. 2, the computing system provided by the embodiment of the present application includes: a host system 2000 and a chip computing device 1000 as described in the first aspect; and the chip computing device 1000 is connected with the host system 2000 through an external leading-out interface. Figure 3 Figure 2 ​The chip computing device 1000 is provided with an external global storage access interface controller 151, and the on-chip is provided with an external leading-out interface F; the chip computing device 1000 is connected with the upper system 2000 through the external leading-out interface F. As shown in Figure 2 the external leading-out interface F is connected with the connection line of the upper system through the through silicon via 500, and the external leading-out interface F is connected with the external global storage access interface controller 151.

[0098] The computing system provided by the embodiment of the present application can program the array to dynamically schedule the execution flow of at least one fixed operation unit to obtain a target operation function. The execution flow of the conventional fixed operation unit can be dynamically scheduled to obtain a plurality of different target operation functions, so that the operation function of the chip computing device can be reconfigured. Any two of the storage array chip, the programmable array chip and the operation array chip are connected through a three-dimensional heterogeneous integration layer, and the three-dimensional heterogeneous integration connection can form an ultra-large local bus bandwidth advantage between adjacent chips and across chips, so as to increase the bandwidth of storage access and reduce the power consumption of storage access. Unlike the conventional I / O interface, the I / O interface is an input and output interface, and the programmable array and the operation array are connected with the storage array through the three-dimensional heterogeneous integration layer, so that the storage access can be completed in the chip computing device, high bandwidth and low power consumption can be achieved, the operation burden of the upper system can be transferred to the chip computing device, the operation of the upper system is offloaded, the operation and storage access efficiency is improved, and the power consumption is reduced.

[0099] Although the preferred embodiments of the present specification have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present specification.

[0100] Obviously, those skilled in the art can make various modifications and variations to the present specification without departing from the spirit and scope of the present specification. Thus, if these modifications and variations of the present specification fall within the scope of the claims of the present specification and their equivalent technologies, the present specification also intends to include these modifications and variations.

Claims

1. A chip computing device, comprising: The application relates to a chip stack, which comprises a storage array chip, an operation array chip and a programmable array chip. The storage array chip comprises a storage array for storing data, wherein the data stored by the storage array comprises to-be-processed data issued by a host system and result data obtained after the to-be-processed data is processed by a programmable array and an operation array. The operation array chip comprises an operation array, wherein the operation array comprises at least one fixed operation unit for realizing a fixed operation function. The programmable array chip comprises a programmable array for dynamically scheduling an execution flow of the at least one fixed operation unit to obtain a target operation function. Any two of the storage array chip, the programmable array chip and the operation array chip are connected through a three-dimensional heterogeneous connection structure, wherein the three-dimensional heterogeneous connection structure is provided with a three-dimensional mutual connection interface. The number of the target operation functions is at least one. One of the storage array chip, the programmable array chip and the operation array chip comprises an external global storage access interface controller and an external global access bus, wherein the external global storage access interface controller is connected with the external global access bus. The storage array chip, the programmable array chip or the operation array chip comprises an internal global access bus for connecting a functional array in the chip. The three-dimensional mutual connection interfaces are arranged between adjacent chips of the storage array chip, the programmable array chip and the operation array chip. The storage array chip, the programmable array chip and the operation array chip all comprise internal local storage access lines, which are respectively connected with the three-dimensional mutual connection interfaces and the functional arrays. The storage array chip, the programmable array chip and the operation array chip are connected with the functional arrays of other chips through the internal local storage access lines and the three-dimensional mutual connection interfaces.

2. The chip computer device of claim 1, wherein, The storage array chip, the programmable array chip and the operation array chip all comprise external storage access lines, which are respectively connected with the three-dimensional mutual connection interfaces and the functional arrays.

3. The chip computer device of claim 2, wherein, The operation array chip comprises a calculation interconnection line, which is respectively connected with the three-dimensional mutual connection interface and the operation array.

4. The chip computer device of claim 3, wherein, The storage array chip, the programmable array chip and the operation array chip all comprise an active layer and an internal metal layer. The active layer comprises the functional array. The internal metal layer comprises the internal local storage access lines.

5. The chip computer device of claim 1, wherein, The storage array on the programmable array chip is in a normal projection relationship with the programmable array.

6. The chip computer device of claim 1, wherein, The programmable array chip comprises a controller, and the programmable array is connected with the controller. The controller is used for controlling the programmable array to dynamically schedule the execution flow of the at least one fixed operation unit to obtain the target operation function; and / or The controller is used for controlling the programmable array to execute a current target operation function based on result data obtained after a previous target operation function is executed.

7. The chip computer device of claim 1, wherein, The number of chip layers of the storage array chip is at least two; and / or The programmable array chip comprises a controller, and the programmable array is connected with the controller. The controller is used for controlling the programmable array to dynamically schedule the execution flow of the at least one fixed operation unit to obtain the target operation function; and / or The controller is used for controlling the programmable array to execute a current target operation function based on result data obtained after a previous target operation function is executed. The number of chip layers of the storage array chip is at least two; and / or The programmable array chip comprises a controller, and the programmable array is connected with the controller. The controller is used for controlling the programmable array to dynamically schedule the execution flow of the at least one fixed operation unit to obtain the target operation function; and / or The controller is used for controlling the programmable array to execute a current target operation function based on result data obtained after a previous target operation function is executed. The number of chip layers of the storage array chip is at least two; and / or The programmable array chip has at least two chip layers; and / or The operation array chip has at least two chip layers.

8. The chip computer device of claim 1, wherein, Any two of the storage array chip, the programmable array chip and the operation array chip are arranged on the same layer of chip.

9. The chip computer device of claim 1, wherein, At least one of the storage array chip, the programmable array chip and the operation array chip comprises a level conversion circuit.

10. The chip computer device of claim 1, wherein, The storage array comprises one of static random access memory, dynamic random access memory, Flash memory, ferroelectric memory, phase change memory, magnetic memory and variable resistance memory, or a combination of at least two of them.

11. The chip computer device according to any one of claims 1-10, wherein, The storage array chip comprises at least one of a storage array die and a storage array wafer; and / or, The operation array chip comprises at least one of an operation array die and an operation array wafer; and / or, The programmable array chip comprises at least one of a programmable array die and a programmable array wafer.

12. A computing system, comprising: Comprise: The chip computing device and the upper system as claimed in any one of claims 1-11; The chip on which the external global storage access interface controller is arranged is provided with an external leading-out interface; The chip computing device is connected with the upper system through the external leading-out interface.

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