Cost-balanced gate-level circuit diagram partitioning method and computer storage medium

Abstract

The present invention discloses a cost-balanced gate-level circuit diagram segmentation method and a computer storage medium. The cost-balanced gate-level circuit diagram segmentation method includes obtaining the symmetric adjacency matrix of the undirected graph corresponding to the gate-level circuit, the cost matrix of the vertices, the number of sub-graph blocks to be segmented, and the allowed deviation ratio; calculating the average cost of the sub-graph and the deviation threshold range; randomly selecting a deviation threshold from the deviation threshold range, combining the average cost, and obtaining the current cost range of the sub-graph; using iterative operations to segment the undirected graph multiple times, selecting a round of segmentation results with the least number of isolated vertices, and recording the segmentation results; segmenting the isolated vertices into the sub-graphs adjacent to them according to preset rules, so that the number of sub-graph blocks after segmentation is consistent with the number of sub-graph blocks to be segmented. The present invention realizes the reasonable segmentation of the gate-level circuit diagram, there are no isolated vertices or vertex groups, and the sub-graph costs are balanced, which improves the simulation efficiency.

Description

Technical Field

[0001] The invention relates to a gate-level circuit diagram segmentation method and a search method, in particular to a gate-level circuit diagram segmentation method for segmenting according to the time cost required to consume when simulating devices represented by vertices. Background Art

[0002] In order to improve the processing efficiency of gate-level circuits, there are many methods for segmenting gate-level circuits in the prior art. Currently, the relevant methods for segmenting gate-level circuit diagrams include geometric methods, KL partitioning and FM partitioning based on group migration, and multi-layer partitioning methods.

[0003] The geometric method must have vertex coordinates, but does not consider the degree of association between vertices, time cost, and segmentation cost. Therefore, the graph segmentation cost may be relatively large and the segmentation quality is not ideal. The KL partitioning and FM partitioning methods based on group migration are prone to fall into local optimality. The multi-layer partitioning method is based on the edge cost between vertices, which is not applicable to the case where the vertex cost is used as the partitioning criterion.

[0004] Therefore, how to provide a cost-balanced gate-level circuit segmentation method is a technical problem that needs to be solved urgently in the industry. Summary of the invention

[0005] In order to solve the technical problem of uneven cost after gate-level circuit segmentation in the prior art, the present invention provides a cost-balanced gate-level circuit segmentation method and a computer storage medium.

[0006] The present invention proposes a cost-balanced gate-level circuit diagram segmentation method, comprising:

[0007] Step 1, obtaining the symmetric adjacency matrix of the undirected graph corresponding to the gate-level circuit, the cost matrix of the vertices in the undirected graph, the number of sub-graph blocks to be divided, and the allowed deviation ratio;

[0008] Step 2, calculating the average cost of each sub-graph after the gate-level circuit is divided and the deviation threshold range according to the cost matrix, the number of sub-graph blocks and the allowed deviation ratio;

[0009] Step 3, randomly selecting a deviation threshold from the deviation threshold range, combining it with the average cost, to obtain the current cost range of each subgraph;

[0010] Step 4, traversing the vertices of the undirected graph according to a preset algorithm, segmenting the undirected graph so that each subgraph obtained by segmentation conforms to the current cost range, and counting isolated vertices around each subgraph that cannot be segmented into a subgraph due to the current cost range;

[0011] Step 5, repeating steps 3 to 4 for a preset number of times, comparing the number of isolated vertices after each round of segmentation, selecting the segmentation result with the least number of isolated vertices, and recording each subgraph corresponding to the segmentation result and the current cost range;

[0012] Step 6: segment the isolated vertices into adjacent subgraphs according to preset rules, so that the number of subgraph blocks after segmentation is consistent with the number of subgraph blocks planned to be segmented.

[0013] Further, the step 6 specifically includes:

[0014] Step 6.1: Determine whether the sum of the costs of all vertices in the subgraph where the vertices adjacent to the isolated vertex are located is less than the maximum value of the current cost range recorded. If so, move the isolated vertex to the corresponding subgraph until all isolated vertices are split nearby;

[0015] Step 6.2, determine whether the sum of the costs of all vertices of each current subgraph is greater than the maximum value of the recorded cost range. If so, split the subgraph.

[0016] The method of the present invention further comprises:

[0017] Step 7, calculating the gains of all vertices of the segmentation result finally obtained in step 6;

[0018] Step 8: When trying to move the vertex with the maximum current gain to other subgraphs, determine whether the costs of all vertices in other subgraphs after the move meet the corresponding cost range. If so, move the vertex to other subgraphs and recalculate the gains of all adjacent vertices to the vertex.

[0019] Step 9, selecting the subgraph whose inter-subgraph segmentation cost is reduced the most or increased the least after the vertex is moved to the subgraph from the movement record of the vertex with the largest current gain, and moving the vertex to the subgraph as the final moving destination of the vertex;

[0020] Step 10, recalculate the gains of all vertices, determine the vertex with the current maximum gain, and return to step 8 until all vertices have been moved or the gains of all vertices are negative.

[0021] Furthermore, in step 10, when the vertex with the largest gain calculated is moved, the vertex with the largest gain among the vertices that have not been moved is selected in descending order of gain as the current vertex with the largest gain.

[0022] Furthermore, in step 4, a column of serial numbers is added to the symmetric adjacency matrix, where the serial numbers are the serial numbers of the vertices corresponding to each row, to form the latest adjacency matrix, and traversal begins from the vertices corresponding to the first row of the latest adjacency matrix.

[0023] Furthermore, the symmetric adjacency matrix is ​​obtained by converting the adjacency matrix of the directed graph of the gate-to-gate circuit.

[0024] Furthermore, the preset algorithm is a breadth-first search algorithm.

[0025] Furthermore, the minimum value of the cost range in step 3 is the average cost minus the deviation threshold, and the maximum value is the average cost plus the deviation threshold.

[0026] The computer storage medium proposed in the present invention is used to store a computer program, and when the computer program is executed, the cost-balanced gate-level circuit diagram segmentation method described in the above technical solution is implemented.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] 1. The present invention can effectively solve the problem in the prior art that isolated vertices or vertex groups that are not divided into subgraphs will appear when dividing a circuit diagram. The method of the present invention can obtain the division result with the least isolated vertices or vertex groups during division.

[0029] 2. The present invention assigns isolated vertices or vertex groups to their neighboring subgraphs within the acceptable range of the cost range, thereby avoiding the problem that isolated vertices or vertex groups need to occupy simulation lines separately during simulation and reducing the consumption of simulation resources.

[0030] 3. The method of the present invention can be used to obtain similar costs for each sub-graph after segmentation, thereby obtaining a gate-level circuit graph segmentation result with balanced costs.

[0031] 4. The method of the present invention can greatly reduce the connection cost between subgraphs while achieving cost balance among subgraphs, thereby improving simulation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The present invention is described in detail below with reference to the embodiments and accompanying drawings, wherein:

[0033] Figure 1 It is a schematic flow chart of the present invention.

[0034] Figure 2 It is a detailed flow chart of the present invention. DETAILED DESCRIPTION

[0035] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0036] Thus, a feature indicated in this specification will be used to illustrate one of the features of an embodiment of the present invention, rather than implying that each embodiment of the present invention must have the described feature. In addition, it should be noted that this specification describes many features. Although some features can be combined together to illustrate possible system designs, these features can also be used in other combinations that are not explicitly described. Thus, unless otherwise stated, the described combinations are not intended to be limiting.

[0037] like Figure 1 , Figure 2 As shown, the principle of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments.

[0038] Before segmenting the gate-level circuit, the present invention first finds the segmentation standard and segments the gate-level circuit according to the segmentation standard.

[0039] The present invention needs to first obtain the symmetric adjacency matrix of the undirected graph corresponding to the gate-level circuit as the basis for segmentation. At the same time, it is also necessary to obtain the cost matrix G1 of the vertices in the undirected graph, the number of sub-blocks planned to be segmented, the allowable deviation ratio and other data. In the present invention, the order of obtaining these data is not limited.

[0040] In one embodiment, the symmetric adjacency matrix of the undirected graph of the present invention is obtained by reading the adjacency matrix G4 of the directed graph of the gate-level circuit and then converting the adjacency matrix G4 of the directed graph to obtain the symmetric adjacency matrix of the undirected graph.

[0041] The cost matrix refers to the cost of each gate (i.e., the vertex in the directed or undirected graph) during simulation, such as the gate simulation time and / or simulation complexity. The cost matrix is ​​assigned values ​​based on the cost of each gate during the simulation process, and then the undirected graph is split into multiple subgraphs with equivalent costs, so that when processing gate-level circuits in parallel, each parallel branch can be completed in roughly the same time.

[0042] The number of sub-blocks to be divided is set by those skilled in the art according to needs, for example, based on hardware conditions.

[0043] The allowable deviation ratio is also set by those skilled in the art as needed. For example, in one embodiment, when the deviation ratio is set to 10%, it means that the time difference between multiple parallel branches is within 10%.

[0044] Calculate the cost sum(G1) of all vertices in the undirected graph. The average cost z expected for each subgraph is sum(G1) / K, where G1 is the cost matrix and K is the number of subgraph blocks to be split. If the z obtained in this process has a decimal part, round it to the integer.

[0045] Then, the deviation threshold range is calculated according to the deviation ratio. The minimum value of the deviation threshold range is the average cost * (1-deviation ratio), and the maximum value of the deviation threshold range is the average cost * (1+deviation ratio).

[0046] Afterwards, an iterative operation is performed. Specifically, an iteration number may be set. The setting of the iteration number may be performed by a person skilled in the art according to the complexity of the gate-level circuit.

[0047] In each round of iteration, a deviation threshold is randomly selected from the deviation threshold range and combined with the average cost to obtain the current cost range of each subgraph. The maximum value of the current cost range is the average cost plus the deviation threshold, and the minimum value of the current cost range is the average cost minus the deviation threshold.

[0048] According to the preset algorithm, the vertices of the undirected graph are traversed, and the undirected graph is divided so that each subgraph obtained by the division conforms to the current cost range, and the isolated vertices around each subgraph that cannot be divided into the subgraph due to the current cost range are counted. In a specific embodiment, the symmetric adjacency matrix of the gate-level circuit is G, and a column is added to the symmetric adjacency matrix to form the latest adjacency matrix G3, the added column is a column number, and the number added to each row is the number of the vertex corresponding to each row, thereby forming the latest adjacency matrix G3, and starting from the vertex corresponding to the first row of the latest adjacency matrix, a breadth-first search algorithm (BFS) is used to traverse the vertices in the undirected graph. Taking the vertex corresponding to the first row as an example, find the corresponding vertex in the first row of the latest adjacency matrix G3 and the vertices directly connected to it, put the vertex and its connected vertices into the currently divided vertex set b, add the cost of the vertices in the vertex set b, and compare them with the current cost range. If it is less than the minimum value qx of the cost range, perform the second-level traversal, that is, find the second vertex in the vertex set b in order, traverse the vertices directly connected to it, and add the traversed vertices to the vertex set b. Similarly, compare it with the cost range. If it is less than the minimum value qx of the cost range, find the third vertex in the vertex set b, traverse the vertex, and continue traversing according to this rule, adding the cost of the vertices and comparing them with the minimum value of the cost range until it is greater than the minimum value of the cost range, then the traversal of the currently divided vertex set is ended.

[0049] Next, the sum of the costs of the vertex set obtained in the previous step is judged. If it is less than the maximum value qd of the cost range, the costs of the vertices in vertex set b are continued to be added. If the cost of the next vertex is added, the sum of its costs will exceed the maximum value qd of the cost range, and it will not be divided into vertex set b, and the vertices that meet the cost range traversed in vertex set b are divided into one piece. If the cost of the next vertex is exactly equal to the maximum value qd of the cost range, it is directly divided into vertex set b.

[0050] If the sum of the costs of all vertices in the region where the vertex is located is less than the minimum value qx of the cost range, the region is divided into separate blocks. If the region where the vertex or multiple vertices are located has been divided multiple times, and due to the constraints of the cost range, these vertices cannot be divided into a subgraph, then the subgraph numbers of these vertices are directly set to 0, that is, these vertices are isolated vertices.

[0051] If the total cost of the remaining untraversed vertices in the latest adjacency matrix G3 is less than the minimum value qx of the cost range, a round of partitioning ends. The partitioning results are recorded by the matrix Q. The numbers in each row of the matrix Q represent the subgraph number cc to which the vertex corresponding to the row belongs. After each subgraph partition, cc is incremented by 1, and the partitioned vertices are deleted from the latest adjacency matrix G3.

[0052] Repeat the above iterative process to the preset number of times, compare the number of isolated vertices after each round of segmentation, select the segmentation result with the least number of isolated vertices, and record the subgraphs and current cost range corresponding to the segmentation result. For example, if it is expected to be segmented into 6 blocks, it is possible to get 6 subgraphs and some isolated vertices, or it is possible to get 5 subgraphs and some isolated vertices.

[0053] According to the preset rules, the isolated vertices are divided into adjacent subgraphs, so that the number of subgraph blocks after division is consistent with the number of subgraph blocks planned to be divided. This step needs to process the subgraphs and isolated vertices obtained in the previous step, so that all isolated vertices can be incorporated into the corresponding subgraphs. The specific process is as follows:

[0054] Determine whether the sum of the costs of all vertices in the subgraph where the vertices adjacent to the isolated vertex are located is less than the maximum value of the current cost range recorded. If so, move the isolated vertex to the corresponding subgraph until all isolated vertices are split nearby; determine whether the sum of the costs of all vertices in the current subgraphs is greater than the maximum value of the recorded cost range. If so, split the subgraph.

[0055] Through the above steps, a partitioning result of each subgraph with balanced cost without isolated vertices can be obtained. In a preferred embodiment, the present invention further optimizes the partitioning result.

[0056] Calculate the gains of all vertices in the final cost-balanced segmentation result obtained in the previous step. Assume that vertex i is in the child Figure 1 In the case where vertex i is not a sub Figure 1 minus the degree of vertex i in the sub Figure 1 The value of the degree in is gain(i), and gain(i) is the gain of vertex i.

[0057] Then, we need to iterate to try to move vertices with larger gains to other subgraphs to make the dependencies between subgraphs as low as possible. In the initial iteration, sort the gains of all vertices obtained in the previous step and find the vertex with the largest current gain as the vertex with the largest current gain in the initial iteration.

[0058] In each round of iteration, when trying to move the vertex with the current maximum gain to other subgraphs, determine whether the costs of all vertices in other subgraphs after the move are in line with the corresponding cost range. If so, move the vertex to other subgraphs and recalculate the gains of all vertices adjacent to the vertex. The corresponding cost range referred to here refers to the cost range corresponding to the final partition result with the least isolated vertices recorded.

[0059] In the movement record of the vertex with the largest current gain, the subgraph whose inter-subgraph segmentation cost is reduced the most or increased the least after the vertex is moved to the subgraph is selected, and the vertex is moved to the subgraph as the final moving destination of the vertex.

[0060] Recalculate the gains of all vertices, determine the vertex with the current maximum gain, and start a new round of iteration until all vertices have been moved or the gains of all vertices are negative. When calculating the gains of all new vertices in non-initial iterations, if the vertex with the maximum gain has not been moved, the vertex with the maximum gain that may not have been moved will be used as the vertex with the current maximum gain for the next round of iteration. If the vertex with the maximum gain has been moved, the vertex with the maximum gain among the vertices that have not been moved will be selected in descending order of gain as the vertex with the current maximum gain for the next round of iteration. Each movement of the vertex with the current maximum gain can be divided into three processes: calculating the initial gain, selecting the vertex with the current maximum gain, and updating the gains of all adjacent vertices. When each vertex has been moved once or the gains of all vertices are negative, the iteration ends. At this time, the dependencies between the subgraphs obtained are very weak, which improves the efficiency of subsequent parallel simulation. When all vertices have been moved once, or the gains of all vertices are negative, if the technician feels that the segmentation effect is not good enough at this time, he can perform one or more rounds of iterations based on the previously moved subgraphs to move the vertices again until the segmentation cost of the final segmentation result (also called the moving result) has no obvious change, and then stop the iteration.

[0061] By adopting the technical solution of the present invention, the gate-level circuit can be divided into several subsystems (i.e., into multiple subgraphs). Except for the input of the initial subsystem, the inputs of other subsystems are randomly given by humans. By independently simulating these subsystems in parallel, the simulation time can be significantly reduced. Because the input randomly given by humans does not necessarily correspond to the output result of the previous subsystem, if the simulation of the previous subsystem is completed, and the output result is different from the input of the next subsystem given by humans, it is necessary to re-simulate the next subsystem. In the prior art, the rollback rate is used to measure the number of times all subsystems are re-simulated, and the smaller the connection between subsystems, the smaller the rollback rate. By adopting the above-mentioned technical solution of the present invention, the connection between subsystems (subgraphs) can be effectively reduced to a very low level, making the division between subsystems very reasonable and feasible, and further improving the simulation efficiency.

[0062] The present invention also protects a corresponding computer storage medium for storing a computer program, which, when executed, implements the cost-balanced gate-level circuit diagram segmentation method described in the above technical solution of the present invention.

[0063] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A cost-balanced gate-level circuit diagram segmentation method, characterized in that: include: Step 1, obtaining the symmetric adjacency matrix of the undirected graph corresponding to the gate-level circuit, the cost matrix of the vertices in the undirected graph, the number of sub-graph blocks to be divided, and the allowed deviation ratio; Step 2, calculating the average cost of each sub-graph after the gate-level circuit is divided and the deviation threshold range according to the cost matrix, the number of sub-graph blocks and the allowed deviation ratio; the element value of the cost matrix is ​​the cost required for each gate when simulating; Step 3, randomly selecting a deviation threshold from the deviation threshold range, combining it with the average cost, to obtain the current cost range of each subgraph; Step 4, traversing the vertices of the undirected graph according to a preset algorithm, segmenting the undirected graph so that each subgraph obtained by segmentation conforms to the current cost range, and counting isolated vertices around each subgraph that cannot be segmented into a subgraph due to the current cost range; the preset algorithm is a breadth-first search algorithm; Step 5, repeating steps 3 to 4 for a preset number of times, comparing the number of isolated vertices after each round of segmentation, selecting the segmentation result with the least number of isolated vertices, and recording each subgraph corresponding to the segmentation result and the current cost range; Step 6: segment the isolated vertices into adjacent subgraphs according to preset rules, so that the number of subgraph blocks after segmentation is consistent with the number of subgraph blocks planned to be segmented.

2. The cost-balanced gate-level circuit diagram segmentation method according to claim 1, characterized in that: The step 6 specifically includes: Step 6.1: Determine whether the sum of the costs of all vertices in the subgraph where the vertices adjacent to the isolated vertex are located is less than the maximum value of the current cost range recorded. If so, move the isolated vertex to the corresponding subgraph until all isolated vertices are split nearby; Step 6.2, determine whether the sum of the costs of all vertices of each current subgraph is greater than the maximum value of the recorded cost range. If so, split the subgraph.

3. The cost-balanced gate-level circuit diagram segmentation method according to claim 1, characterized in that: Also includes: Step 7, calculating the gains of all vertices of the segmentation result finally obtained in step 6; Step 8: When trying to move the vertex with the maximum current gain to other subgraphs, determine whether the costs of all vertices in other subgraphs after the move meet the corresponding cost range. If so, move the vertex to other subgraphs and recalculate the gains of all vertices adjacent to the vertex. Step 9, selecting the subgraph whose inter-subgraph segmentation cost is reduced the most or increased the least after the vertex is moved to the subgraph from the movement record of the vertex with the largest current gain, and moving the vertex to the subgraph as the final moving destination of the vertex; Step 10, recalculate the gains of all vertices, determine the vertex with the current maximum gain, and return to step 8 until all vertices have been moved or the gains of all vertices are negative.

4. The cost-balanced gate-level circuit diagram segmentation method according to claim 3, characterized in that: In step 10, when the vertex with the largest calculated gain has been moved, the vertex with the largest gain among the vertices that have not been moved is selected in descending order of gain as the current vertex with the largest gain.

5. The cost-balanced gate-level circuit diagram segmentation method according to claim 3, characterized in that: When all vertices have been moved, or the gains of all vertices are negative, steps 7 to 10 are repeated until the segmentation cost of the segmentation result has no significant change.

6. The cost-balanced gate-level circuit diagram segmentation method according to claim 1, characterized in that: In step 4, a column of serial numbers is added to the symmetric adjacency matrix, where the serial numbers are the serial numbers of the vertices corresponding to each row, to form the latest adjacency matrix, and traversal begins from the vertices corresponding to the first row of the latest adjacency matrix.

7. The cost-balanced gate-level circuit diagram segmentation method according to claim 1, characterized in that: The symmetric adjacency matrix is ​​obtained by transforming the adjacency matrix of the directed graph of the gate-level circuit.

8. The cost-balanced gate-level circuit diagram segmentation method according to claim 1, characterized in that: The minimum value of the cost range in step 3 is the average cost minus the deviation threshold, and the maximum value is the average cost plus the deviation threshold.

9. A computer storage medium for storing a computer program, characterized in that: When the computer program is executed, the method for partitioning a gate-level circuit diagram with cost balance as claimed in any one of claims 1 to 8 is implemented.

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