Semiconductor device and method for forming the same

Abstract

The device includes a device layer, the device layer including a first transistor, a first interconnect structure on the front side of the device layer, and a second interconnect structure on the back side of the device layer. The second interconnect structure includes a first dielectric material on the back side of the device layer, a contact extending through the first dielectric material to a first source / drain region of the first transistor, and a first conductive layer including a first conductive line electrically connected to the first source / drain region through the contact. Embodiments of the present application also relate to semiconductor devices and methods for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and other elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, so that more components can be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be solved. Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor device, comprising: a device layer, comprising a first transistor; a first interconnect structure, on the front side of the device layer; and a second interconnect structure, on the back side of the device layer, the second interconnect structure comprising: a first dielectric material, on the back side of the device layer; a contact, extending through the first dielectric material to a first source / drain region of the first transistor, a first width of the contact being greater than a second width of the first source / drain region, the first width of the contact being measured at the level of the first dielectric material, the second width of the first source / drain region being measured from a first nanostructure to a second nanostructure of the first transistor; and a first conductive layer, comprising a first conductive line electrically connected to the first source / drain region through the contact.

[0005] Other embodiments of the present application provide a semiconductor device, including: a first transistor, in a device layer, the first transistor including a first source / drain region and a second source / drain region; a first dielectric material, on the back side of the device layer; a first conductive contact, extending through the first dielectric material to the first source / drain region; and an insulating plug, extending through the first dielectric material to the second source / drain region, wherein a first width of the first conductive contact is greater than a second width of the insulating plug, and both the first width and the second width are measured at the level of the first dielectric material.

[0006] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first transistor on a semiconductor substrate, the first transistor comprising a first source / drain region; planarizing the semiconductor substrate to expose a dummy semiconductor region; removing the dummy semiconductor region to define a first opening exposing the back side of the first source / drain region; widening the first opening, wherein widening the first opening comprises etching the semiconductor substrate; after widening the first opening, forming a contact in the first opening, the contact being electrically coupled to the first source / drain region; and after forming the contact in the first opening, removing the remaining portion of the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, it is clear that the size of the various components can be increased or reduced at will.

[0008] Figure 1 An example of a nanostructured field effect transistor (nanoFET) according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Figure 8C , Fig. 9A , Fig. 9B , Fig. 9C , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig.12F , Figure 12G , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig. 15C, Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig. 17C , Fig.18A , Fig.18B , Fig. 18C , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B , Fig. 20C , Fig.21A , Fig.21B , Fig. 21C , Fig.22A , Fig. 22B , Fig. 22C , Fig.23A , Fig. 23B , Fig.23C , Fig.24A , Fig. 24B , Fig.24C , Fig.25A , Fig.25B , Fig.25C , Fig.26A , Fig.26B , Fig.26C , Fig.27A , Fig.27B , Fig.27C , Fig.28A , Fig.28B , Fig.28C , Fig.29A , Fig.29B , Fig.29C , Fig. 30A , Fig. 30B , Fig. 30C , Fig.31A , Fig.31B , Fig.31C , Fig.32A , Fig.32B , Fig.32C , Fig.33A , Fig.33B , Fig.33C , Fig.34A , Fig.34B , Fig.34C , Fig.34D , Fig.34E , Fig.34F , Fig.35A , Fig.35B , Fig.35C , Fig.35D and Fig.35E is a cross-sectional view of an intermediate stage in a nanoFET fabrication process according to some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0012] Various embodiments provide methods for forming a nanoFET in a semiconductor device and a semiconductor device including a nanoFET. By forming a backside via before removing the substrate, the size of the backside via can be enlarged. Subsequent liner deposition and etching processes can be applied to the outer surface of the backside via that has been formed so that the liner formation and subsequent etching do not reduce the width of the backside via. Larger backside vias can be used for silicide formation and larger contact area to obtain better contact resistance and produce better device performance.

[0013] Some embodiments discussed herein are described in the context of dies containing nanoFETs. However, various embodiments may be applied to dies containing other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, etc.) instead of or in combination with nanoFETs.

[0014] Figure 1An example of a nanoFET (e.g., a nanowire FET, a nanosheet FET, etc.) according to some embodiments is shown in a three-dimensional view. The nanoFET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, etc.) above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 is used as a channel region of the nanoFET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. A shallow trench isolation (STI) region 68 is disposed between adjacent fins 66, and the fins 66 may protrude from above and between adjacent STI regions 68. Although the STI region 68 is described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may refer to the semiconductor substrate itself or a combination of a semiconductor substrate and a shallow trench isolation region. In addition, although the bottom of the fin 66 is shown as being a single, continuous material with the substrate 50, the bottom of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this case, the fin 66 refers to the portion extending between adjacent STI regions 68.

[0015] The gate dielectric layer 100 is located over the top surface of the fin 66 and along the top surface, sidewalls and bottom surface of the nanostructure 55. The gate electrode 102 is located over the gate dielectric layer 100. The epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102.

[0016] Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is in a plane along the longitudinal axis of the gate electrode 102 and is oriented, for example, perpendicular to the direction of current flow between the epitaxial source / drain regions 92 of the nanoFET. Cross section BB' is in an arbitrary plane parallel to cross section AA' and extends through the epitaxial source / drain regions 92 of multiple nanoFETs. Cross section CC' is in a plane perpendicular to cross section AA' and parallel to the longitudinal axis of the fin 66 of the nanoFET and in the direction of current flow, for example, between the epitaxial source / drain regions 92 of the nanoFET. For clarity, subsequent figures refer to these reference cross sections.

[0017] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments consider aspects used in planar devices, such as planar FETs or fin field effect transistors (FinFETs).

[0018] Figures 2 to 34F is a cross-sectional view of an intermediate stage in fabricating a nanoFET according to some embodiments. Figures 2 to 5 , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A , Fig.28A , Fig.29A , Fig. 30A , Fig.31A , Fig.32A , Fig.33A , Fig.34A and Fig.35A Shows Figure 1 Reference section AA' is shown. Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig.12D , Fig.12F , Figure 12G , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B , Fig.28B , Fig.29B , Fig. 30B , Fig.31B , Fig.32B , Fig.33B , Fig.34B , Fig.34E , Fig.34F , Fig.35B , Fig.35D and Fig.35E Shows Figure 1 Reference section BB' shown in . Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig.11D, Fig. 12C , Fig.12E , Fig. 13C , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig. 18C , Fig.19C , Fig. 20C , Fig. 21C , Fig. 22C , Fig.23C , Fig.24C , Fig.25C , Fig.26C , Fig.27C , Fig.28C , Fig.29C , Fig. 30C , Fig.31C , Fig.32C , Fig.33C , Fig.34C , Fig.34D and Fig.35C Shows Figure 1 Reference section CC' shown in .

[0019] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer substrates or gradient substrates may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0020] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor (e.g., an n-type nano FET), and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor (e.g., a p-type nano FET). The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator 20), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0021] Further, in Figure 2 In the embodiment of the present invention, a multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For illustration purposes and as discussed in more detail below, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form a channel region of the nanoFET in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanoFET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nanoFET in the n-type region 50N, and the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nanoFET in both the n-type region 50N and the p-type region 50P.

[0022] For illustration, the multilayer stack 64 is shown as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nanoFET, such as silicon germanium, etc., and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nanoFET, such as silicon, silicon carbon, etc. For illustration, the multilayer stack 64 is illustrated as having a bottommost semiconductor layer suitable for a p-type nanoFET. In some embodiments, the multilayer stack 64 may be formed so that the bottommost layer is a semiconductor layer suitable for an n-type nanoFET.

[0023] The first semiconductor material and the second semiconductor material can be materials with high etching selectivity to each other. In this way, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nanoFET. Similarly, in an embodiment where the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the nanoFET.

[0024] Reference now Figure 3 According to some embodiments, the fin 66 is formed in the substrate 50, and the nanostructure 55 is formed in the multilayer stack 64. In some embodiments, the nanostructure 55 and the fin 66 can be formed in the multilayer stack 64 and the substrate 50, respectively, by etching grooves in the multilayer stack 64 and the substrate 50. The etching can be any feasible etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic. By etching the multilayer stack 64 to form the nanostructure 55, the first nanostructure 52A-52C (collectively referred to as the first nanostructure 52) can be further defined from the first semiconductor layer 51, and the second nanostructure 54A-54C (collectively referred to as the second nanostructure 54) can be defined from the second semiconductor layer 53. The first nanostructure 52 and the second nanostructure 54 can be collectively referred to as the nanostructure 55.

[0025] The fins 66 and nanostructures 55 can be patterned by any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the formation of patterns with, for example, a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a mask is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned mask using a self-alignment process. The mask is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0026] To illustrate, Figure 3The fins 66 in the n-type region 50N and the p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater than or less than the width of the fins 66 in the p-type region 50P. In addition, although each of the fins 66 and the nanostructures 55 are shown to have a uniform width, in other embodiments, the fins 66 and / or the nanostructures 55 may have a tapered sidewall such that the width of each of the fins 66 and / or the nanostructures 55 increases continuously in a direction toward the substrate 50. In such an embodiment, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0027] exist Figure 4 In the embodiment shown in the figure, a shallow trench isolation (STI) region 68 is formed near the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66 and the nanostructure 55 and between adjacent fins 66. The insulating material can be a dielectric material such as an oxide (e.g., silicon oxide, nitride, etc.) or a combination thereof, and can be formed by high-density PECVD (HDP-CVD) and flowable CVD (FCVD). Other insulating materials formed by any feasible process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed so that an excess of the insulating material covers the nanostructure 55. Although the insulating material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can be first formed along the surface of the substrate 50, the fin 66 and the nanostructure 55. Then, a filling material such as described above can be formed on the liner.

[0028] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructures 55. In some embodiments, a planarization process may be utilized, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The planarization process exposes the nanostructures 55 so that after the planarization process is completed, the top surfaces of the nanostructures 55 and the insulating material are flush.

[0029] The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. In addition, the top surface of the STI region 68 may have a flat surface, a convex surface, a concave surface (e.g., a depression), or a combination thereof as shown. By appropriate etching, the top surface of the STI region 68 may be formed to be flat, convex, and / or concave. A feasible etching process may be used to recess the STI region 68, such as an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than etching the material of the fin 66 and the nanostructure 55). For example, dilute hydrofluoric acid (dHF), for example, may be used to remove oxides.

[0030] Refer to above Figures 2 to 4 The process described is merely one example of how to form the fin 66 and the nanostructure 55. In some embodiments, the fin 66 and / or the nanostructure 55 may be formed using a mask and an epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fin 66 and / or the nanostructure 55. The epitaxial structure may include alternating semiconductor materials such as a first semiconductor material and a second semiconductor material as described above. In some embodiments where the epitaxial structure is epitaxially grown, the epitaxially grown material may be in-situ doped during growth, which may avoid prior and / or subsequent implantation, although in-situ doping and implantation doping may be used together.

[0031] In addition, for the sake of explanation, in the illustration and discussion, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) include the same material only in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials, or formed in a different order in the p-type region 50P and the n-type region 50N.

[0032] In addition, Figure 4In the embodiment with different types of wells, different implantation steps of the n-type region 50N and the p-type region 50P can be implemented using a photoresist or other mask (not shown separately). For example, a photoresist can be formed over the fins 66 and the shallow trench isolation region 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed by using a spin coating technique and can be patterned using feasible photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., which are implanted in this region, and its concentration ranges from about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 After implantation, the photoresist is removed, for example, by a feasible ashing process.

[0033] After or before implanting the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using a feasible photolithography technique. Once the photoresist is patterned, a p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., implanted into the region, and its concentration is about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 After implantation, the photoresist may be removed, for example, by a feasible ashing process.

[0034] After implanting n-type region 50N and p-type region 50P, annealing may be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may avoid implantation, although in-situ doping and implantation doping may be used together.

[0035] exist Figure 5In the embodiment of the present invention, a pseudo dielectric layer 70 is formed on the fin 66 and / or the nanostructure 55. The pseudo dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to feasible techniques. A pseudo gate layer 72 is formed above the pseudo dielectric layer 70, and a mask layer 74 is formed above the pseudo gate layer 72. The pseudo gate layer 72 may be deposited above the pseudo dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 may be deposited on the pseudo gate layer 72. The pseudo gate layer 72 may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium, metal nitride, metal silicide, metal oxide, and metal. The pseudo gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The pseudo gate layer 72 may be made of other materials having high etching selectivity to the etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. Note that for illustration purposes only, the dummy dielectric layer 70 is shown as covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0036] 6A to 18C Various additional steps in the fabrication of example devices are shown. 6A to 18C Components in the n-type region 50N or the p-type region 50P are shown. FIG. 6A to FIG. 6C In the embodiment, the mask layer 74 (see Figure 5 ) can be patterned using feasible photolithography and etching techniques to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the fin 66. The pattern of the mask 78 can be used to physically separate each dummy gate 76 from the adjacent dummy gate 76. The longitudinal direction of the dummy gate 76 can also be substantially perpendicular to the longitudinal direction of each fin 66.

[0037] exist FIG. 7A to FIG. 7C In the embodiment, the first spacer layer 80 and the second spacer layer 82 are formed on FIG. 6A to FIG. 6C The first spacer layer 80 and the second spacer layer 82 will then be patterned to serve as spacers for forming self-aligned source / drain regions. FIG. 7A to FIG. 7CIn the embodiment, the first spacer 80 is formed on: the top surface of the STI region 68; the top surface and sidewalls of the fin 66, the nanostructure 55 and the mask 78; and the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. The second spacer 82 is deposited over the first spacer 80. The first spacer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. using techniques such as thermal oxidation or by CVD, ALD, etc. The second spacer 82 can be formed of a material having a different etching rate from the material of the first spacer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited by CVD, ALD, etc.

[0038] After forming the first spacer layer 80 and before forming the second spacer layer 82, an implantation for a lightly doped source / drain (LDD) region (not shown separately) may be performed. In embodiments with different device types, similar to the above, Figure 4 As discussed in the implantation, a mask, such as a photoresist, may be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type of impurity (e.g., p-type) may be implanted into the fins 66 and nanostructures 55 exposed in the p-type region 50P. The mask may then be removed. Subsequently, a mask (e.g., a photoresist) may be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type of impurity (e.g., n-type) may be implanted into the fins 66 and nanostructures 55 exposed in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The impurity concentration of the lightly doped source / drain region may be about 1×10 15 atoms / cm 3 About 1×10 19 atoms / cm 3 Annealing can be used to repair implant damage and activate implanted impurities.

[0039] exist FIG. 8A to FIG. 8C, the first spacer 80 and the second spacer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used to self-align the subsequently formed source and drain regions, and to protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processing. The first spacer 80 and the second spacer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. In some embodiments, the material of the second spacer 82 has a different etching rate than the material of the first spacer 80, so that the first spacer 80 can be used as an etch stop layer when patterning the second spacer 82, and so that the second spacer 82 can be used as a mask when patterning the first spacer 80. For example, the second spacer 82 can be etched using an anisotropic etching process, wherein the first spacer 80 is used as an etch stop layer, and wherein the remaining portion of the second spacer 82 forms the second spacer 83, such as Figure 8B Thereafter, the second spacer 83 is used as a mask while etching the exposed portion of the first spacer layer 80, thereby forming the first spacer 81, as shown in FIG. Figure 8B and Figure 8C shown.

[0040] like Figure 8B As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8C As shown, in some embodiments, the second spacer 82 can be removed from above the first spacer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 60. In other embodiments, a portion of the second spacer 82 can remain above the first spacer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0041] Note that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may also be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacer 81 may be patterned before depositing the second spacer layer 82), additional spacers may be formed and removed, and the like. Furthermore, different structures and steps may be used to form n-type and p-type devices.

[0042] exist 9A to 9CIn some embodiments, first recesses 86 and second recesses 87 are formed in fin 66, nanostructure 55, and substrate 50. Epitaxial source / drain regions will subsequently be formed in first recesses 86 and second recesses 87. First recesses 86 and second recesses 87 may extend through first nanostructure 52 and second nanostructure 54 and into substrate 50. Fig. 9B As shown, the fin 66 can be etched so that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68. In other embodiments, the top surface of the STI region 68 can be flush with the bottom surface of the first recess 86 or higher than the bottom surface of the first recess 86. The bottom surface of the second recess 87 can be disposed below the bottom surface of the first recess 86 and the top surface of the STI region 68. The first recess 86 and the second recess 87 can be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process (e.g., RIE, NBE, etc.). During the etching process for forming the first recess 86 and the second recess 87, the first spacer 81, the second spacer 83, and the mask 78 mask the fin 66, the nanostructure 55, and the portion of the substrate 50. Each layer of the nanostructure 55 and / or the fin 66 can be etched using a single etching process or multiple etching processes. After the first recess 86 and the second recess 87 reach the desired depth, a timed etching process can be used to stop etching. The second recess 87 may be etched by the same process as etching the first recess 86 and an additional etching process before or after etching the first recess 86. In some embodiments, while the additional etching process for the second recess 87 is performed, a region corresponding to the first recess 86 may be masked.

[0043] exist FIG. 10A to FIG. 10C In the embodiment, the sidewall portions of the layers of the multilayer stack 64 formed of the first semiconductor material (e.g., the first nanostructure 52) exposed by the first recess 86 and the second recess 87 are etched to form the sidewall recess 88. Although the sidewalls of the first nanostructure 52 adjacent to the sidewall recess 88 are Fig. 10C The sidewalls are shown as straight, but the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process, such as wet etching, etc. In an embodiment where the first nanostructure 52 includes, for example, SiGe and the second nanostructure 54 includes, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 The sidewall of the first nanostructure 52 is etched by a dry etching process such as OH.

[0044] exist FIG. 11A to FIG. 11D In the embodiment, the internal spacer 90 is formed in the side wall groove 88. The internal spacer 90 can be formed by FIG. 10A to FIG. 10CThe inner spacer layer (not shown separately) is deposited above the structure shown to form. The inner spacer 90 serves as an isolation member between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions and the epitaxial material will be formed in the first recess 86 and the second recess 87, and the first nanostructure 52 will be replaced with a corresponding gate structure.

[0045] The inner spacer layer may be deposited by a conformal deposition process such as CVD, ALD, etc. The inner spacer layer may include a material such as silicon nitride (SiN) or silicon oxynitride (SiO x N y ), although any suitable material may be used, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. For example, the inner spacer layer may include SiN, SiO x N y , SiOCN, ZrN, TaCN, SiCN, SiO, SiOC, AlO, AlON, ZrO, HfO, TiO, ZrAlO, ZrO, ZnO, TaO, LaO, YO, etc., or a combination thereof. The inner spacer layer can then be anisotropically etched to form an inner spacer 90. Although the outer sidewalls of the inner spacer 90 are shown to be flush with the sidewalls of the second nanostructure 54, the outer sidewalls of the inner spacer 90 may extend beyond the sidewalls of the second nanostructure 54 or be recessed from the sidewalls of the second nanostructure 54. In some embodiments, the inner spacer 90 has a width in the range of about 1 nm to about 10 nm, which is useful for subsequently formed source / drain regions and / or subsequently formed backside vias (see below, Figure 29A-29C ) may be advantageous for insulating the gate structure from a subsequently formed gate structure. Internal spacers 90 having a thickness of less than about 1 nm may be disadvantageous because they may allow shorting between the subsequent gate structure and the source / drain regions and / or the backside vias. Internal spacers 90 having a thickness of greater than about 10 nm may be disadvantageous because they may reduce the width of the gate structure and / or the source / drain regions, thereby reducing device performance.

[0046] Furthermore, although the outer side wall of the inner partition 90 is Fig. 11C 90 is shown as straight, but the outer sidewall of the inner spacer 90 can be concave or convex. As an example, Fig.11D An embodiment is shown in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the inner spacer 90 are concave, and the inner spacer 90 is recessed from the sidewalls of the second nanostructure 54. The inner spacer layer can be etched by an anisotropic etching process, such as RIE, NBE, etc. The inner spacer 90 can be used to prevent a subsequent etching process (such as an etching process for forming a gate structure) from etch-cutting the subsequently formed source / drain region (such as an epitaxial source / drain region 92, referred to below). FIG. 12A to FIG. 12E for discussion) damage.

[0047] exist FIG. 12A to FIG. 12D In the embodiment, the first epitaxial material 91 is formed in the second recess 87, the second epitaxial material 89 is formed in the first recess 86 and above the first epitaxial material 91 in the second recess 87, and the epitaxial source / drain region 92 is formed in the first recess 86 and in the second recess 87 above the second epitaxial material 89. The first epitaxial material 91 and the second epitaxial material 89 formed in the second recess 87 may also be referred to as a dummy semiconductor region 95. In some embodiments, the dummy semiconductor region 95 (e.g., including the first epitaxial material 89 and the second epitaxial material 91) may be a sacrificial material that is subsequently removed to form a backside via (e.g., backside via 130, referred to below). FIG. 30A to FIG. 30C Discussion). FIG. 12B to FIG. 12C As shown, the top surface of the first epitaxial material 91 may be flush with the bottom surface of the first recess 86 . However, in some embodiments, the top surface of the first epitaxial material 91 may be disposed above or below the bottom surface of the first recess 86 .

[0048] The first epitaxial material 91 may be epitaxially grown in the second recess 87 using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. The first epitaxial material 91 may include any feasible material, such as silicon germanium, etc. The first epitaxial material 91 may be formed of a material having a high etch selectivity to the material of the epitaxial source / drain region 92, the substrate 50, and the dielectric layer (e.g., the STI region 68). Thus, the first epitaxial material 91 may be removed and replaced with a backside via without significantly removing the epitaxial source / drain region 92 and the dielectric layer. In some embodiments, when the first epitaxial material 91 is grown in the second recess 87, the first recess 86 may be masked so that the first epitaxial material 91 is not formed in the first recess 86. This may be useful for subsequently filling the first recess with a second epitaxial material 89 (see below), which may be different from the first epitaxial material 91. After forming the first epitaxial material 91, the mask in the first recess 87 may then be removed.

[0049] Then, the second epitaxial material 89 is formed in the first groove 86 and the second groove 87 above the first epitaxial material 91. FIG. 12B to FIG. 12CAs shown, the top surface of the second epitaxial material 89 can be flush with the top surface of the STI region 68. However, in some embodiments, the top surface of the second epitaxial material 89 can be set below or above the top surface of the STI region 68. The second epitaxial material 89 can be epitaxially grown in the first recess 86 and the second recess 87 using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. The second epitaxial material 89 can include any feasible material, such as silicon germanium, etc. In some embodiments, the second epitaxial material 89 can be a material substantially the same as the first epitaxial material 91. In other embodiments, the second epitaxial material 89 can be different from the first epitaxial material 91. For example, the second epitaxial material 89 and the first epitaxial material 91 can each include silicon germanium; however, the germanium concentration of the second epitaxial material 89 can be different from the germanium concentration of the first epitaxial material 91. The first epitaxial material 91, which is different from the second epitaxial material 89, can be used as a dummy material for subsequently forming the fifth recess 128 (see below, Figure 24A-Figure 24C ). The second epitaxial material 89 may be formed of a material having a high etch selectivity to the material of the epitaxial source / drain regions 92, the substrate 50, and the dielectric layer (e.g., the STI regions 68). In this way, the second epitaxial material 89 may be removed and replaced with a backside via without significantly removing the epitaxial source / drain regions 92 and the dielectric layer.

[0050] Then, epitaxial source / drain regions 92 are formed over the second epitaxial material 89 in the first recess 86 and the second recess 87. In some embodiments, the epitaxial source / drain regions 92 may exert stress on the second nanostructure 54, thereby improving performance. Fig. 12C As shown, epitaxial source / drain regions 92 are formed in first recess 86 and second recess 87 such that each dummy gate 76 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate epitaxial source / drain regions 92 from dummy gates 76, and internal spacers 90 are used to separate epitaxial source / drain regions 92 from nanostructures 55 by an appropriate lateral distance so that epitaxial source / drain regions 92 are not short-circuited with the gate of a subsequently formed resulting nanoFET.

[0051] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by masking the p-type region 50P (e.g., PMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 and the second recess 87 of the n-type region 50N. The epitaxial source / drain region 92 may include any feasible material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may include a material that applies tensile strain on the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 may have a surface protruding from the corresponding upper surface of the nanostructure 55, and may have a small facet.

[0052] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 and the second recess 87 in the p-type region 50P. The epitaxial source / drain region 92 may include any feasible material suitable for a p-type nano FET. For example, if the first nanostructure 52 is silicon germanium, the epitaxial source / drain region 92 may include a material that applies compressive strain on the first nanostructure 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 92 may also have a surface that protrudes from the corresponding surface of the multilayer stack 56 and may have a small facet.

[0053] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 may be implanted with dopants to form the source / drain region by a process similar to the previously discussed process for forming the lightly doped source / drain region, followed by annealing. The source / drain region may have a dopant density of approximately 1×10 19 atoms / cm 3 About 1×10 21 atoms / cm 3 The n-type impurities and / or p-type impurities of the source / drain regions may be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 92 may be in-situ doped during growth.

[0054] Due to the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surface of epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of nanostructures 55. Fig. 12B As shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated. Fig.12D As shown, these facets result in the merging of adjacent epitaxial source / drain regions 92 of the same nanoFET. Fig. 12B and Fig.12D In the illustrated embodiment, the first spacer 81 can be formed on the top surface of the STI region 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 can cover a portion of the sidewalls of the nanostructure 55, further blocking epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 can be adjusted to remove the spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 68.

[0055] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. The epitaxial source / drain region 92 may use any number of semiconductor material layers. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and may be doped to a different dopant concentration. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In an embodiment where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited above the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited above the second semiconductor material layer 92B.

[0056] Fig.12E An embodiment is shown in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the inner spacer 90 are concave, and the inner spacer 90 is recessed from the sidewalls of the second nanostructure 54. Fig.12E As shown, epitaxial source / drain regions 92 may be formed in contact with the inner spacers 90 and may extend beyond the sidewalls of the second nanostructure 54 .

[0057] Fig.12F and Figure 12G It shows that Fig. 12B A detailed view of the area 85 is shown. Fig. 12B and Fig.12F In some embodiments, the widths of the first epitaxial material 91 and the second epitaxial material 89 are substantially the same, and the first epitaxial material 91 has substantially straight sidewalls. Figure 12GIn other embodiments, the first epitaxial material 91 has rounded sidewalls. The first epitaxial material 91 may have a maximum width measured between opposing rounded sidewalls that is greater than a width measured between opposing sidewalls of the second epitaxial material 89. The rounded sidewalls of the first epitaxial material 91 may result from, for example, over-etching the second recess 87 into the material of the STI region 68. For ease of illustration, based on Fig.12F The following figures are described and discussed with reference to the embodiments of the present invention, but it should be understood that the following processing can also be applied to Figure 12G Embodiment of the invention.

[0058] exist FIG. 13A to FIG. 13C In the embodiment, a first interlayer dielectric (ILD) 96 is deposited on FIG. 12A to FIG. 12C . The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any feasible process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 78, and the first spacer 81. The CESL 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has a different etching rate than the material of the first ILD 96 above.

[0059] exist FIG. 14A to FIG. 14C In the process, a planarization process such as CMP may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within process variations. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0060] exist FIG. 15A to FIG. 15CIn the embodiment of the present invention, the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps to form a third groove 98. A portion of the dummy gate dielectric 60 in the third groove 98 is also removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 60 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 76 at a faster rate than etching the first ILD 96 or the first spacer 81. Each third groove 98 exposes and / or covers a portion of the nanostructure 55, which is used as a channel region in a subsequently completed nanoFET. The portion of the nanostructure 55 used as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, when etching the dummy gate 76, the dummy gate dielectric 60 may be used as an etch stop layer. After removing the dummy gate 76, the dummy gate dielectric 60 may be removed.

[0061] exist FIG. 16A to FIG. 16C In the embodiment, the first nanostructure 52 is removed to extend the third recess 98. The first nanostructure 52 can be removed by performing an isotropic etching process (e.g., wet etching, etc.) using an etchant that is selective to the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In an embodiment where the first nanostructure 52 includes, for example, SiGe and the second nanostructures 54A-54C include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH) etc. to remove the first nanostructure 52.

[0062] exist FIG. 17A to FIG. 17C , a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the third recess 98. The gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50, and the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 may also be deposited on the top surfaces of the first ILD 96, the CESL 94, the first spacer 81, and the STI region 68, and on the sidewalls of the first spacer 81 and the inner spacer 90.

[0063] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or a combination thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the k value of the gate dielectric layer 100 may be greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. In the n-type region 50N and the p-type region 50P, the structure of the gate dielectric layer 100 may be the same or different. The formation method of the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0064] The gate electrode 102 is deposited over the gate dielectric layer 100 and fills the remaining portion of the third recess 98. The gate electrode 102 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Fig.17A and Fig. 17C , a single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler materials. Any combination of layers constituting the gate electrode 102 may be deposited in the n-type region 50N between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50, and may be deposited in the p-type region 50P between adjacent first nanostructures 52.

[0065] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by different processes, such that the gate dielectric layer 100 may be a different material and / or have a different number of layers, and / or the gate electrode 102 in each region may be formed by different processes, such that the gate electrode 102 may be a different material and / or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0066] After filling the third recess 98, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 100 and the material of the gate electrode 102, which are above the top surface of the first ILD 96. The gate electrode 102 and the remaining portions of the material of the gate dielectric layer 100 thus form a replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure".

[0067] exist 18A to 18C In the embodiment, the gate structure (including the gate dielectric layer 100 and the corresponding upper gate electrode 102) is recessed so that a groove is formed directly above the gate structure and between the opposite portions of the first spacer layer 81. A gate mask 104 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the groove, and a planarization process is then performed to remove excess portions of the dielectric material extending above the first ILD 96. The gate contact (e.g., as described below) is subsequently formed. FIG. 20A to FIG. 20C The gate contact 114 discussed penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102 .

[0068] like 18A to 18C As further shown, the second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material, such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, PECVD, etc.

[0069] exist FIG. 19A to FIG. 19C , the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a fourth recess 108 exposing the surface of the epitaxial source / drain region 92 and / or the gate structure. The fourth recess 108 may be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, the fourth recess 108 may be etched through the second ILD 106 and the first ILD 96 using a first etching process; the gate mask 104 may be etched using a second etching process; and then the CESL 94 may be etched using a third etching process. A mask (e.g., photoresist) may be formed over the second ILD 106 and patterned to mask portions of the second ILD 106 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, so that the fourth recess 108 extends into the epitaxial source / drain region 92 and / or the gate structure, and the bottom of the fourth recess 108 may be flush with the epitaxial source / drain region 92 and / or the gate structure (e.g., on the same level, or at the same distance from the substrate 50), or lower than the epitaxial source / drain region 92 and / or the gate structure (e.g., closer to the substrate 50). Fig.19C The fourth recess 108 is shown as exposing the epitaxial source / drain regions 92 and the gate structure in the same cross section, but in various embodiments, the epitaxial source / drain regions 92 and the gate structure may be exposed in different cross sections, thereby reducing the risk of shorting subsequently formed contacts.

[0070] After forming the fourth recess 108, a first silicide region 110, also referred to as first silicide 110, is formed over the epitaxial source / drain region 92. In some embodiments, the first silicide region 110 is formed by first depositing a metal (not shown separately) that can react with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof) on the exposed portion of the epitaxial source / drain region 92, and then performing a thermal annealing process to form the first silicide region 110. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although the first silicide region 110 is referred to as a silicide region, the first silicide region 110 may also be a germanide region or a silicon germanide region (e.g., a region including silicide and germanide). In some embodiments, the first silicide region 110 includes TiSi and has a thickness in a range from about 2 nm to about 10 nm.

[0071] exist FIG. 20A to FIG. 20C , source / drain contacts 112 and gate contacts 114 (also referred to as contact plugs) are formed in the fourth recess 108. The source / drain contacts 112 and the gate contacts 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the source / drain contacts 112 and the gate contacts 114 each include a barrier layer and a conductive material, and each is electrically coupled to the underlying conductive component (e.g., the gate electrode 102 and / or the first electrode silicide region 110). The gate contact 114 is electrically coupled to the gate electrode 102, and the source / drain contact 112 is electrically coupled to the first silicide region 110. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106. The epitaxial source / drain region 92, the second nanostructure 54 and the gate structure (including the gate dielectric layer 100 and the gate electrode 102) may be collectively referred to as a transistor structure 109. The transistor structure 109 may be formed in a device layer, wherein a first interconnect structure (e.g., as described below in conjunction with the transistor structure 109) is formed above the front side thereof. FIG. 21A to FIG. 21C The front interconnect structure 120 discussed above) and a second interconnect structure formed on the back side thereof (eg, as described below in conjunction with FIG. 28A to FIG. 28C Although the device layer is described as having nanoFETs, other embodiments may include device layers having different types of transistors (eg, planar FETs, finFETs, thin film transistors (TFTs), etc.).

[0072] although FIG. 20A to FIG. 20CSource / drain contacts 112 are shown extending to each epitaxial source / drain region 92, but source / drain contacts 112 may be omitted from some of the epitaxial source / drain regions 92. For example, as explained in more detail below, conductive features (e.g., backside vias or power rails) may be subsequently attached through the backside of one or more epitaxial source / drain regions 92. For these particular epitaxial source / drain regions 92, source / drain contacts 112 may be omitted or may be not electrically connected to any overlying conductive lines (e.g., first conductive features 122, described below in conjunction with the first conductive features 122). FIG. 21A to FIG. 21C discussed).

[0073] FIG. 21A to FIG. 29C An intermediate step of forming a front-side interconnect structure and a back-side interconnect structure on transistor structure 109 is shown. The front-side interconnect structure and the back-side interconnect structure may each include conductive features electrically connected to nano-FETs formed on substrate 50. Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A , Fig.28A and Fig.29A Shows Figure 1 Reference section AA' is shown. Fig. 21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B , Fig.28B and Fig.29B Shows Figure 1 Reference section BB' is shown. Fig. 21C , Fig. 22C , Fig.23C , Fig.24C , Fig.25C , Fig.26C , Fig.27C , Fig.28C and Fig.29C Shows Figure 1 Reference section CC' shown in . FIG. 21A to FIG. 29C The process steps described in can be applied to n-type region 50N and p-type region 50P. As described above, backside conductive features (e.g., backside vias or power rails) can be connected to one or more epitaxial source / drain regions 92. In this way, source / drain contacts 112 can be optionally omitted from epitaxial source / drain regions 92.

[0074] exist FIG. 21A to FIG. 21C, a front side interconnect structure 120 is formed on the second ILD 106. The front side interconnect structure 120 may be referred to as a front side interconnect structure because it is formed on the front side of the transistor structure 109 (eg, the side of the transistor structure 109 on which active devices are formed).

[0075] The front-side interconnect structure 120 may include one or more layers of first conductive features 122 formed in one or more stacked first dielectric layers 124. Each of the stacked first dielectric layers 124 may include a dielectric material such as a low-k dielectric material, an ultra-low-k (ELK) dielectric material, etc. The first dielectric layer 124 may be deposited using a suitable process such as CVD, ALD, PVD, PECVD, etc.

[0076] The first conductive features 122 may include conductive lines and conductive vias of the interconnect conductive line layers. The conductive vias may extend through the corresponding first dielectric layers in the first dielectric layers 124 to provide vertical connections between the layers of conductive lines. The first conductive features 122 may be formed by any feasible process, such as a damascene process, a dual damascene process, etc.

[0077] In some embodiments, the first conductive component 122 may be formed using a damascene process, wherein a combination of photolithography and etching techniques is used to pattern the corresponding first dielectric layer 124 to form a groove corresponding to the desired pattern of the first conductive component 122. An optional diffusion barrier layer and / or an optional adhesion layer may be deposited, and then the groove may be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, and the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, and the like. In an embodiment, the first conductive component 122 may be formed by depositing a seed layer of copper or a copper alloy and filling the groove by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from the surface of the corresponding first dielectric layer 124, and to planarize the surfaces of the first dielectric layer 124 and the first conductive component 122 for subsequent processing.

[0078] FIG. 21A to FIG. 21C Five layers of first conductive features 122 and first dielectric layers 124 are shown in the front interconnect structure 120. However, it should be understood that the front interconnect structure 120 may include any number of first conductive features 122 arranged in any number of first dielectric layers 124. The front interconnect structure 120 may be electrically connected to the gate contact 114 and the source / drain contacts 112 to form a functional circuit. In some embodiments, the functional circuit formed by the front interconnect structure 120 may include a logic circuit, a memory circuit, an image sensor circuit, etc.

[0079] exist FIG. 22A to FIG. 22CIn the embodiment, a carrier substrate 150 is bonded to the top surface of the front-side interconnect structure 120 by a first bonding layer 152A and a second bonding layer 152B (collectively referred to as bonding layers 152). The carrier substrate 150 may be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), etc. The carrier substrate 150 may provide structural support during subsequent processing steps and in the completed device.

[0080] In various embodiments, the carrier substrate 150 may be bonded to the front interconnect structure 120 by a suitable technique (e.g., dielectric-to-dielectric bonding, etc.). The dielectric-to-dielectric bonding may include depositing a first bonding layer 152A on the front interconnect structure 120. In some embodiments, the first bonding layer 152A includes silicon oxide (e.g., high density plasma (HDP) oxide, etc.) deposited by CVD, ALD, PVD, etc. The second bonding layer 152B may also be an oxide layer formed on the carrier substrate 150 prior to bonding using, for example, CVD, ALD, PVD, thermal oxidation, etc. Other suitable materials may be used for the first bonding layer 152A and the second bonding layer 152B.

[0081] The dielectric to dielectric bonding process may also include applying surface treatment to one or more of the first bonding layer 152A and the second bonding layer 152B. The surface treatment may include plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, etc.) that can be applied to one or more bonding layers 152. The carrier substrate 150 is then aligned with the front interconnect structure 120 and pressed against each other to initiate pre-bonding of the carrier substrate 150 with the front interconnect structure 120. The pre-bonding can be performed at room temperature (e.g., between about 21°C and about 25°C). After the pre-bonding, an annealing process can be applied, for example, by heating the front interconnect structure 120 and the carrier substrate 150 to a temperature of, for example, about 170°C to about 500°C.

[0082] Furthermore, in FIG. 22A to FIG. 22C In the embodiment, after bonding the carrier substrate 150 to the front-side interconnect structure 120, the device can be flipped so that the back side of the transistor structure 109 faces upward. The back side of the transistor structure 109 can refer to the side opposite to the front side of the transistor structure 109 where active devices are formed.

[0083] exist FIG. 23A to FIG. 23CIn the embodiment, a thinning process may be applied to the back side of the substrate 50. The thinning process may include a planarization process (e.g., mechanical grinding, CMP, etc.), an etch-back process, a combination thereof, etc. The thinning process may expose the surface of the first epitaxial material 91 opposite to the front interconnect structure 120. Furthermore, after the thinning process, a portion of the substrate 50 may remain above the gate structure (e.g., the gate electrode 102 and the gate dielectric layer 100) and the nanostructure 55. FIG. 23A to FIG. 23C As shown, after the thinning process, the substrate 50 , the first epitaxial material 91 , the STI regions 68 , and the back surfaces of the fins 66 may be flush with each other.

[0084] exist FIG. 24A to FIG. 24C In the embodiment, the first epitaxial material 91 and the first portion of the second epitaxial material 89 between the first epitaxial material 91 and the source / drain region 92 are removed to form the fifth recess 128. Before removing the remaining portion of the fin 66 and the substrate 50, a backside via (see below) may be subsequently formed in the fifth recess 128. Figure 29A-29C ), which is useful for achieving wider back-side vias, thereby allowing a larger contact area to obtain better contact resistance and improve device performance. The first portion of the first epitaxial material 91 and the second epitaxial material 89 can be removed by a suitable etching process, which can be an isotropic etching process, such as a wet etching process. In some embodiments, the etching process can remove a portion of the epitaxial source / drain region 92, resulting in a convex bottom of the fifth recess 128. In other embodiments, the etching process can have a high etching selectivity to the material of the first portion of the first epitaxial material 91 and the second epitaxial material 89, so that the first portion of the first epitaxial material 91 and the second epitaxial material 89 can be removed without significantly removing the material of the STI region 68 or the epitaxial source / drain region 92. The fifth recess 128 can expose the sidewalls of the STI region 68, the back side of the epitaxial source / drain region 92, the sidewalls of the first spacer 81, and the sidewalls of the internal spacer 90.

[0085] exist FIG. 25A to FIG. 25C In the embodiment of the present invention, a mask 204 is formed in the fifth groove 128. In some embodiments, the mask 204 may be formed of, for example, a dielectric, an organic material, a bottom anti-reflective coating (BARC) material, etc., and may be deposited by, for example, spin coating, PECVD, CVD, etc. After deposition, an etch-back process may be performed to remove material from the outside of the fifth groove 128 and partially expose the sidewalls of the fifth groove 128, thereby forming the mask 204. The etch-back process may cause the mask 204 to be recessed below the top surface of the substrate 50, and further recessed below the top surface of the STI region 68, so that the upper sidewalls of the fifth groove 128 are exposed. The mask 204 may be formed to have a thickness of about 20 nm to about 40 nm. The mask 204 may be used to widen the fifth groove 128 in a subsequent process, as described below with reference to FIG. 26A to FIG. 26CAs described above, the mask 204 may be deposited to a desired thickness in order to control the shape of the fifth recess 128 after the widening process. The mask 204 may further protect the underlying source / drain region 92 in a subsequent etching process.

[0086] exist FIG. 26A to FIG. 26C In the embodiment of the present invention, the fifth groove 128 is widened, and the mask 204 is removed. The widening of the fifth groove 128 can further round the sidewall of the fifth groove 128. The fifth groove 128 can be widened by a suitable etching process, such as a dry etching process. The dry etching process can use an etching gas suitable for etching silicon, such as O 2 , Cl 2 , HCl, HBr, etc., or a combination thereof. The etching process may etch the sidewalls of the substrate 50 and the STI region 68 exposed by the fifth recess 128 (eg, not covered by the mask 204). Fig.26B and Fig.26C As shown, after the etching process, the fifth groove 128 can have a gradient profile that narrows toward the front side of the device. The ratio of the maximum width RW1 of the fifth groove 128 to the minimum width RW2 of the fifth groove 128 can be in the range of about 1.1 to about 1.8. Widening the fifth groove 128 can allow for subsequent formation of larger backside vias, which advantageously reduces contact resistance and reduces the likelihood of misalignment of contacts with the backside vias. After widening the fifth groove 128, the mask 204 can then be removed using a suitable process, such as using an etch that is selective to BARC, and an ashing process, etc.

[0087] exist FIG. 27A to FIG. 27C In the embodiment, a first liner 206 (also referred to as a first dielectric liner 206) is formed on the sidewall of the fifth groove 128. The first liner 206 can be formed by FIG. 26A to FIG. 26C A first liner layer (not shown separately) is deposited over the structure shown to form. The first liner layer can be deposited by CVD, ALD, etc. The first liner layer can be formed by silicon nitride (SiN), silicon oxide (SiO), hafnium silicide (HfSi), silicon oxycarbide (SiOC), aluminum oxide (AlO), zirconium silicide (ZrSi), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), titanium oxide (TiO), zirconium aluminum oxide (ZrAlO), zinc oxide (ZnO), tantalum oxide (TaO), lanthanum oxide (LaO), yttrium oxide (YO), tantalum carbonitride (TaCN), silicon oxycarbonitride (SiOCN), silicon (Si), zirconium nitride (ZrN), silicon carbonitride (SiCN), combinations or multiple layers thereof, etc.

[0088] The first liner layer is then etched to form the first liner 206. The first liner layer may be etched using a suitable etching process, wet etching, dry etching, a combination thereof, or the like. In some embodiments, the etching process may be anisotropic. The etching process removes a lateral portion of the first liner layer and leaves the first liner 206 on the sidewalls of the fifth recess 128. In some embodiments, the etching process may further remove the first liner 206 from an upper portion of the fifth recess 128 (e.g., see Fig.34D The first line 206 may have a thickness in the range of about 1 nm to about 5 nm, which may be advantageous because it may reduce the thickness of the second silicided region 129 (see below, Figure 28A-28C ) is subsequently formed on the sidewalls of the substrate 50. A first liner 206 having a thickness less than about 1 nm may be disadvantageous because it may result in the formation of an additional second silicided region 129 on the sidewalls of the substrate 50. A first liner 206 having a thickness greater than about 5 nm may be disadvantageous because it may result in the formation of a subsequently formed backside via 130 (see below). Figure 29A-29C ) width is narrower, which may degrade device performance.

[0089] exist FIG. 28A to FIG. 28C In the embodiment of the present invention, a second silicide region 129, also referred to as second silicide 129, is formed in the fifth recess 128 on the back side of the epitaxial source / drain region 92. Forming the second silicide region 129 before removing the fin 66 and the remaining portion of the substrate 50 may be useful to improve the formation of the silicide by allowing a larger surface area for the second silicide region 129. This may reduce the contact resistance of the subsequently formed backside vias (see below, Figure 29A-29C). In some embodiments, the second silicide region 129 is formed by first depositing a metal (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof) over the exposed portion of the back side of the epitaxial source / drain region 92 that can react with the semiconductor material (e.g., silicon, silicon germanium, germanium) on the back side of the underlying epitaxial source / drain region 92 to form a silicide or germanide region, and then performing a thermal annealing process to form the second silicide region 129. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although the second silicide region 129 is referred to as a silicide region, the second silicide region 129 may also be a germanide region or a silicon germanide region (e.g., a region including silicide and germanide). In some embodiments, the second silicide region 129 in the n-type region 50N includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, Ysi, HoSi, TbSI, GdSi, LuSi, DySi, ErSi, YbSi, etc., or a combination thereof, and the second silicide region 129 in the p-type region 50P includes NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, etc., or a combination thereof.

[0090] In some embodiments, the second silicide region 129 has a thickness in the range of about 1 nm to about 10 nm, which may be advantageous for reducing contact resistance and improving device function. A second silicide region 129 having a thickness less than about 1 nm may be disadvantageous because the silicide may be too thin and increase contact resistance due to ineffective silicide thickness. A second silicide region 129 having a thickness greater than about 10 nm may be disadvantageous because it may result in higher resistance, thereby reducing device performance.

[0091] exist FIG. 29A to FIG. 29C In the embodiment of the present invention, a backside via 130 (also referred to as a contact or conductive contact 130) is formed in the fifth groove 128. Forming the backside via 130 before removing the remaining portion of the fin 66 and the substrate 50 may be useful for achieving a larger width of the backside via 130. This may result in a larger contact area with the underlying source / drain region 92, thereby reducing contact resistance and achieving better device performance. The backside via 130 may include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. The backside via 130 may be electrically coupled to the epitaxial source / drain region 92' through the second silicide region 129. The backside via 130 may include tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), nickel (Ni), combinations thereof, and the like. A planarization process such as CMP may be performed to remove excess material from the surface of the substrate 50 and the STI region 68.

[0092] In some embodiments, as described in Fig.29C As shown, the backside via 130 extends to a depth D1 measured from the level of the topmost surface of the gate electrode 102 to the bottom apex of the backside via 130, and the depth D1 may be in the range of about 0.5 nm to about 10 nm. In other embodiments, the bottom apex of the backside via 130 is flush with the topmost surface of the gate electrode 102 (not shown).

[0093] exist FIG. 30A to FIG. 30C In the embodiment of the present invention, the remaining portions of the fin 66 and the substrate 50 are removed. The fin 66 and the substrate 50 may be etched using a suitable etching process such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. The etching process may be a process that is selective to the materials of the fin 66 and the substrate 50 (e.g., etching the materials of the fin 66 and the substrate 50 at a faster rate than etching the materials of the backside via 130, the first liner 206, the STI region 68, the gate dielectric layer 100, the internal spacer 90, and the epitaxial source / drain region 92). After etching the fin 66 and the substrate 50, the surfaces of the STI region 68, the gate dielectric layer 100, the internal spacer 90, and the epitaxial source / drain region 92 may be exposed. Removing the remaining portions of the fin 66 may form a sixth recess 210 that exposes the backside of the gate dielectric layer 100 and the epitaxial source / drain region 92. In some embodiments, the etching process can remove the exposed backside portion of the epitaxial source / drain region 92, thereby producing a recessed backside surface of the epitaxial source / drain region 92. The sixth recess 210 can extend to the same depth as the fifth recess 128 discussed previously (e.g., see FIG. 24A to FIG. 24C ) and the corresponding back through hole 130 formed in the fifth groove 128 have the same or different depths.

[0094] exist FIG. 31A to FIG. 31C In the embodiment, the insulating plug 212 is filled in the sixth groove 210 and FIG. 30A to FIG. 30C1. In some embodiments, the insulating plug 212 includes a convex bottom profile that physically contacts the epitaxial source / drain region 92. In some embodiments, the insulating plug 212 includes a second liner 214 (also referred to as a second dielectric liner 214) and a second dielectric layer 125. Forming the second liner 214 and the second dielectric layer 125 on the outer sidewalls of the backside via 130 can allow the backside via 130 to be formed with a larger width, which can improve contact resistance and device performance. In some embodiments, the second liner 214 is formed over the first liner 206, the STI region 68, the gate dielectric layer 100, the epitaxial source / drain region 92, and the inner spacer 90. The second liner layer 214 may include a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO), hafnium silicide (HfSi), silicon oxycarbide (SiOC), aluminum oxide (AlO), zirconium silicide (ZrSi), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), titanium oxide (TiO), zirconium aluminum oxide (ZrAlO), zinc oxide (ZnO), tantalum oxide (TaO), lanthanum oxide (LaO), yttrium oxide (YO), tantalum carbonitride (TaCN), silicon oxycarbonitride (SiOCN), silicon (Si), zirconium nitride (ZrN), silicon carbonitride (SiCN), combinations or multilayers thereof, etc.

[0095] The second liner 214 may have a thickness in the range of about 1 nm to about 10 nm, which is advantageous for protecting the underlying epitaxial source / drain regions 92 from subsequent annealing processes performed on the second dielectric layer 125 (see below). A second liner 214 having a thickness less than about 1 nm may be disadvantageous because it may not be thick enough and therefore may not protect the underlying epitaxial source / drain regions 92 from subsequent annealing processes. A second liner 214 having a thickness greater than about 10 nm may be disadvantageous because its relatively high k value may result in undesirably high parasitic capacitance.

[0096] The second dielectric layer 125 is formed over the second liner 214. In some embodiments, the second dielectric layer 125 is a flowable film formed by FCVD or the like. In some embodiments, the second dielectric layer 125 is formed of a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like. In some embodiments, the second dielectric layer 125 includes silicon oxide (SiO), hafnium silicide (HfSi), silicon oxycarbide (SiOC), aluminum oxide (AlO), zirconium silicide (ZrSi), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), titanium oxide (TiO), zirconium aluminum oxide (ZrAlO), zinc oxide (ZnO), tantalum oxide (TaO), lanthanum oxide (LaO), yttrium oxide (YO), tantalum carbonitride (TaCN), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon (Si), zirconium nitride (ZrN), silicon carbonitride (SiCN), combinations or multilayers thereof, or the like. In some embodiments, the second dielectric layer 125 and the second liner 214 may include substantially the same material. In other embodiments, the second dielectric layer 125 may include a different material than the second liner 214. For example, the second dielectric layer 125 may have a lower k value than the second liner 214.

[0097] In some embodiments, once the second dielectric layer 125 is formed, an annealing process is performed to enhance oxidation and improve dielectric properties of the second dielectric layer 125. A CMP process or the like may be used to remove the material of the second dielectric layer 125 and the second liner 214 so that the top surfaces of the second dielectric layer 125 and the second liner 214 are flush with the top surfaces of the STI region 68 and the backside via 130.

[0098] exist FIG. 32A to FIG. 32C , conductive line 134 and third dielectric layer 132 are formed over second dielectric layer 125, STI region 68, and backside via 130. Third dielectric layer 132 may be similar to second dielectric layer 125. For example, third dielectric layer 132 may be formed of similar materials and using similar processes as second dielectric layer 125.

[0099] Conductive wire 134 is formed in third dielectric layer 132. For example, forming conductive wire 134 may include patterning grooves in third dielectric layer 132 using a combination of photolithography and etching processes. The pattern of the recess in third dielectric layer 132 may correspond to the pattern of conductive wire 134. Conductive wire 134 is then formed by depositing a conductive material in the groove. In some embodiments, conductive wire 134 includes a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, conductive wire 134 includes copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, etc. Before filling the groove with conductive material, an optional diffusion barrier layer and / or an optional adhesion layer may be deposited. Suitable materials for barrier layer / adhesion layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, etc. The material of conductive wire 134 may be formed using, for example, CVD, ALD, PVD, plating, etc. Conductive line 134 is physically and electrically coupled to epitaxial source / drain region 92 through backside via 130 and second silicide region 129. A planarization process (eg, CMP, grinding, etch-back, etc.) may be performed to remove excess portion of conductive line 134 formed over third dielectric layer 132.

[0100] In some embodiments, conductive line 134 is a power rail, which is a conductive line that electrically connects epitaxial source / drain region 92 to a reference voltage, a power supply voltage, etc. By placing the power rail on the back side of the resulting semiconductor die rather than on the front side of the semiconductor die, some advantages can be achieved. For example, the gate density of the nanoFET and / or the interconnect density of the front interconnect structure 120 can be increased. Furthermore, the back side of the semiconductor die can accommodate a wider power rail, thereby reducing resistance and improving the efficiency of power transmission to the nanoFET. For example, the width of conductive line 134 can be at least twice the width of the first level conductive line (e.g., first conductive component 122) of the front interconnect structure 120.

[0101] exist FIG. 33A to FIG. 34C 13, the remaining portion of the backside interconnect structure 136 is formed over the third dielectric layer 132 and the conductive line 134. The backside interconnect structure 136 may be referred to as a backside interconnect structure because it is formed on the backside of the transistor structure 109 (e.g., the side of the transistor structure 109 opposite to the side of the transistor structure 109 on which the active devices are formed). The backside interconnect structure 136 may include the second dielectric layer 125, the third dielectric layer 132, the backside via 130, and the conductive line 134.

[0102] The remainder of the backside interconnect structure 136 may include materials and may be formed using processes that are the same or similar to those used for the frontside interconnect structure 120, as described above with reference to FIG. FIG. 21A to FIG. 21CIn particular, the backside interconnect structure 136 may include a stack of second conductive components 140 formed in the fourth dielectric layer 138. The second conductive components 140 may include wiring (e.g., wiring between subsequently formed contact pads and external connectors). The second conductive components 140 may be further patterned to include one or more embedded passive devices, such as resistors, capacitors, inductors, etc. The embedded passive devices may be integrated with the conductive lines 134 (e.g., power rails) to provide circuits (e.g., power circuits) on the back side of the nanoFET.

[0103] exist FIG. 34A to FIG. 34C In the embodiment of the present invention, a passivation layer 144, a UBM 146, and an external connector 148 are formed over the backside interconnect structure 136. The passivation layer 144 may include a polymer such as PBO, polyimide, BCB, etc. Alternatively, the passivation layer 144 may include a non-organic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc. The passivation layer 144 may be deposited by, for example, CVD, PVD, ALD.

[0104] UBM 146 is formed to pass through passivation layer 144 to second conductive component 140 in backside interconnect structure 136, and external connector 148 is formed on UBM 146. UBM 146 may include one or more layers of copper, nickel, gold, etc. formed by a plating process, etc. External connector 148 (e.g., solder ball) is formed on UBM 146. The formation of external connector 148 may include placing solder ball on exposed portion of UBM 146 and then reflowing solder ball. In some embodiments, the formation of external connector 148 includes performing a plating step to form solder area above uppermost second conductive component 140 and then reflowing solder area. UBM 146 and external connector 148 may be used to provide input / output connection to other electronic components, such as other device die, redistribution structure, printed circuit board (PCB), motherboard, etc. UBM 146 and external connections 148 may also be referred to as backside input / output pads, which may provide signal, supply voltage, and / or ground connections to the nanoFETs described above.

[0105] FIG. 34D to FIG. 34F Shows Fig.34B and Fig.34C Detailed view of the middle area. Fig.34D According to some embodiments Fig.34C A detailed view of region 300 is shown. Backside via 130 may have a plurality of holes extending along a line between opposing sidewalls. Figure 1The cross section CC' has a minimum first width W1 measured between opposite side walls at the level of the second dielectric layer 125 above the inner spacer 90, which ranges from about 25 nm to about 50 nm. This may be advantageous because it may achieve a lower contact resistance, which may improve device performance. A first width W1 of less than about 25 nm may be disadvantageous because it may result in a higher contact resistance, which may degrade device performance. A first width W1 of greater than about 50 nm may be disadvantageous because it may increase the risk of leakage to an adjacent back side via 130. The back side via 130 may have a minimum first height H1 in the range of about 15 nm to about 50 nm measured from the top surface of the back side via 130 to the bottom vertex of the back side via 130, which may be advantageous for achieving a good connection between the device and a subsequently formed conductive line 134 (see below, Figure 32A-Figure 32C ). A first height H1 less than about 15 nm may be disadvantageous because it may result in a high risk of leakage between the device and the subsequently formed conductive line 134. A first height H1 greater than about 50 nm may be disadvantageous because it may result in a high resistance of the backside via 130.

[0106] The epitaxial source / drain regions 92 may have Figure 1 The minimum second width W2 measured between the opposite sidewalls of the second nanostructure 54 of the cross section CC' is in the range of about 15nm to about 25nm, which may be advantageous because it can reduce the source / drain resistance, thereby improving device performance. A second width W2 less than about 15nm may be disadvantageous because a narrower W2 may increase the source / drain resistance and reduce device performance. A second width W2 greater than about 25nm may be disadvantageous because it may cause device performance to degrade due to the reduction in gate length and spacer width. In some embodiments, the first width W1 is greater than the second width W2, which is useful for reducing contact resistance and improving device function.

[0107] Fig.34E and Fig.34F The following are respectively shown according to some embodiments Fig.34B A detailed view of regions 400 and 500 is shown in FIG. The backside via 130 may have a Figure 1 The minimum third width W3 measured between opposite sidewalls of the first liner 206 in the cross section BB' is in the range of about 5 nm to about 50 nm, which may be advantageous because it may reduce the resistance of the backside via 130, thereby improving device performance. A third width W3 less than about 5 nm may be disadvantageous because it may result in a higher resistance of the backside via 130, which may reduce device performance. A third width W3 greater than about 50 nm may be disadvantageous because it may increase the risk of leakage to adjacent backside vias 130. The insulating plug 212 may have a thickness along Figure 1 The minimum fourth width W4 of the cross section CC' measured between opposite sidewalls of the STI region 68 is in the range of about 10 nm to about 30 nm. In some embodiments, the third width W3 of the backside via 130 is greater than the fourth width W4 of the insulating plug 212. In some embodiments, the first width W1 of the backside via 130 is greater than the fourth width W4 of the insulating plug 212.

[0108] FIG. 35A to FIG. 35E Other embodiments are shown where epitaxial source / drain regions 92 are separated by insulating fins 280 . Fig.35A is shown along section AA' and shows Fig.34A Similar structure, but the insulating fin 280 is adjacent to the gate electrode 102 , and the gate dielectric 100 covers the insulating fin 280 . Fig.35B is shown along section BB' and shows Fig.35B Similar structure, but epitaxial source / drain regions 92 are disposed between insulating fins 280 and CESL 94 covering the insulating fins 280 . Fig.35C is shown along section CC' and shows Fig.34C The insulating fin 280 may be formed after the fin 66 is formed by etching (see Figure 4 ) and before forming the dummy gate 76 (see Figure 5 ) is formed. The insulating fin 280 can be formed by depositing a sacrificial layer (not explicitly shown) on the sidewalls of the fin 66 using a conformal deposition process (e.g., CVD, ALD, PECVD, etc.). In some embodiments, the sacrificial material is a semiconductor material (e.g., SiGe, Si, etc.) having the same material composition as the first semiconductor material 51 or the second semiconductor material 53. The sacrificial material can define a groove between the fins 66 above the sacrificial material and between the sidewalls of the sacrificial material. One or more insulating materials are deposited in the groove to form the insulating fin 280. For example, the liner 281 and the filling material 283 can be deposited in the groove by CVD, ALD, PECVD, etc. The liner 281 may include, for example, a nitride (e.g., silicon nitride), etc., and the filling material 283 may include, for example, an oxide (e.g., silicon oxide), etc. In an embodiment, a portion of the liner 281 and the filling material 283 may be partially etched, and a high-k material 285 (e.g., HfO, ZrO, etc.) may be deposited into the groove above the liner 281 and the filling material 283.

[0109] The insulating fins 280 provide insulating boundaries between adjacent epitaxial source / drain regions 92 , which may have different conductivity types. After forming the insulating fins 280 , the sacrificial material may be removed while removing the first semiconductor material 51 and / or the second semiconductor material 53 to define the nanostructures 52 .

[0110] Fig.35D and Fig.35E The following are respectively shown according to some embodiments Fig.35B The area 600 and Fig.35B Detailed view of region 700 is shown. In some embodiments, epitaxial source / drain regions 92 may contact sidewalls of insulating fins 280, and a portion of first ILD 96 may be deposited between insulating fins 280, STI regions 68, and first liner 206 or second liner 214. The portion of first ILD 96 may cause backside via 130 and insulating plug 212 to form a bottleneck profile having an upper width less than a lower width. Fig.35D A minimum one-fifth width W5 of the backside via 130 flush with the bottom surface of the STI region 68 and a one-sixth width W6 of the backside via 130 measured across the widest portion of the backside via 130 below the STI region 68 are shown. The fifth width W5 is smaller than the sixth width W6, thereby forming a bottleneck profile of the backside via 130. Fig.35E A minimum one-seventh width W7 of the insulation plug 212 flush with the bottom surface of the STI region 68 and a one-eighth width W8 of the insulation plug 212 measured at the widest portion of the insulation plug 212 below the STI region 68 are shown. The seventh width W7 is smaller than the eighth width W8, thereby forming a bottleneck profile of the backside via 130.

[0111] Embodiments may achieve several advantages. The backside vias may be widened by forming the backside vias prior to removing the remainder of the fins and substrate. The formation of the liner and subsequent etching does not reduce the width of the backside vias because they are applied to the outside of the backside vias. By forming wider backside vias prior to removal from the fins and substrate, better contact resistance, silicide formation, and resulting better device performance may be achieved.

[0112] According to some embodiments, a device includes: a device layer including a first transistor; a first interconnect structure on the front side of the device layer; and a second interconnect structure on the back side of the device layer. The second interconnect structure includes: a first dielectric material on the back side of the device layer; a contact extending through the first dielectric material to a first source / drain region of the first transistor, the first width of the contact being greater than the second width of the first source / drain region, the first width of the contact being measured at the level of the first dielectric material, the second width of the first source / drain region being measured from a first nanostructure to a second nanostructure of the first transistor; and a first conductive layer including a first conductive line electrically connected to the first source / drain region through the contact. In one embodiment, the first width is in the range of 25nm to 50nm, the second width is in the range of 15nm to 25nm, and the contact has a height in the range of 15nm to 50nm. In one embodiment, the device also includes an insulating spacer on a sidewall of the contact, the spacer separating the contact from the first dielectric material. In one embodiment, the insulating spacer extends closer to the first interconnect structure than the first dielectric material.

[0113] According to some embodiments, a device includes: a first transistor in a device layer, the first transistor including a first source / drain region and a second source / drain region; a first dielectric material on a back side of the device layer; a first conductive contact extending through the first dielectric material to the first source / drain region; and an insulating plug extending through the first dielectric material to the second source / drain region, wherein a first width of the first conductive contact is greater than a second width of the insulating plug, and the first width and the second width are both measured at the level of the first dielectric material. In one embodiment, the insulating plug includes: a dielectric liner on a sidewall of the first dielectric material; and a second dielectric material, wherein the dielectric liner separates the second dielectric material from the first dielectric material, and wherein the dielectric liner separates the second dielectric material from the second source / drain region. In one embodiment, the first dielectric material is a shallow trench isolation (STI) region. In one embodiment, the insulating plug includes a convex bottom profile that physically contacts the second source / drain region. In one embodiment, the insulating plug includes a bottleneck profile.

[0114] According to some embodiments, a method includes: forming a first transistor on a semiconductor substrate, the first transistor including a first source / drain region; planarizing the semiconductor substrate to expose a dummy semiconductor region; removing the dummy semiconductor region to define a first opening exposing a back side of the first source / drain region; widening the first opening, wherein widening the first opening includes etching the semiconductor substrate; after widening the first opening, forming a contact in the first opening, the contact electrically coupled to the first source / drain region; and after forming the contact in the first opening, removing a remaining portion of the semiconductor substrate. In one embodiment, removing the remaining portion of the semiconductor substrate defines a second opening extending through a shallow trench isolation region, wherein the method further includes forming an insulating plug in the second opening, and wherein the insulating plug extends to a second source / drain region of the first transistor. In one embodiment, forming the insulating plug includes: depositing a first dielectric liner on a sidewall and a bottom surface of the second opening; and depositing a first dielectric material in the second opening above the first dielectric liner. In one embodiment, the method further includes: depositing a second dielectric liner on a sidewall of the first opening before forming the contact in the first opening. In one embodiment, the method further comprises: forming a silicide on the back side of the first source / drain region before forming the contact in the first opening. In one embodiment, the method further comprises: depositing a mask in the first opening, the mask covering the first source / drain region while widening the first opening; and removing the mask before forming the contact in the first opening. In one embodiment, the mask comprises a bottom anti-reflective coating (BARC) material. In one embodiment, after widening the first opening, the first opening comprises a maximum width and a minimum width, and the ratio of the maximum width to the minimum width is in the range of 1.1 to 1.8. In one embodiment, etching the semiconductor substrate comprises using O 2 , Cl 2 , HCl or HBr. In one embodiment, the first width of the contact is greater than the second width of the first source / drain region, the first width of the contact is measured at the level of the shallow trench isolation region, the contact extends through the shallow trench isolation region, and the second width of the first source / drain region is measured from the first nanostructure to the second nanostructure of the first transistor. In one embodiment, the first width is in the range of 25nm to 50nm, and the second width is in the range of 15nm to 25nm.

[0115] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not deviate from the spirit and scope of the present invention, and that various changes, substitutions and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: a device layer including a first transistor including a first source / drain region and a second source / drain region; a first interconnect structure on the front side of the device layer; A second interconnect structure, on the back side of the device layer, the second interconnect structure comprising: a first dielectric material on the back side of the device layer; a contact extending through the first dielectric material to the first source / drain region of the first transistor, the first source / drain region of the first transistor being separated from the gate structure by an internal spacer, the first width of the contact being greater than the second width of the first source / drain region, a first conductive layer including a first conductive line electrically connected to the first source / drain region through the contact; and an insulating plug extending through the first dielectric material to the second source / drain region, wherein the first width of the contact is greater than a third width of the insulating plug; The first width, the second width and the third width are measured along a longitudinal axis direction parallel to the fin of the first transistor, and the first width of the contact and the third width of the insulating plug are measured between corresponding relative internal spacers at the level of the internal spacer closest to the first dielectric material, and the second width of the first source / drain region is measured from a first nanostructure of the first transistor to a second nanostructure of a transistor adjacent to the first transistor and located at the same level as the first nanostructure.

2. The semiconductor device according to claim 1, wherein The first width is in the range of 25 nm to 50 nm, the second width is in the range of 15 nm to 25 nm, and the contact has a height in the range of 15 nm to 50 nm. 3 . The semiconductor device of claim 1 , further comprising an insulating spacer on a sidewall of the contact, the insulating spacer separating the contact from the first dielectric material.

4. The semiconductor device according to claim 3, wherein: The insulating spacer extends closer to the first interconnect structure than the first dielectric material.

5. A semiconductor device comprising: a first transistor, in the device layer, the first transistor comprising a first source / drain region and a second source / drain region; a first dielectric material on the back side of the device layer; a first conductive contact extending through the first dielectric material to the first source / drain region, the first source / drain region of the first transistor being separated from the gate structure by an internal spacer; as well as an insulating plug extending through the first dielectric material to the second source / drain region, wherein a first width of the first conductive contact is greater than a second width of the insulating plug, the first width and the second width are measured along a direction parallel to a longitudinal axis of a fin of the first transistor, and the first width and the second width are both measured between corresponding opposing inner spacers at a level of an inner spacer closest to the first dielectric material.

6. The semiconductor device according to claim 5, wherein: The insulating plug comprises: a dielectric liner on a sidewall of the first dielectric material; and A second dielectric material, wherein the dielectric liner separates the second dielectric material from the first dielectric material, and wherein the dielectric liner separates the second dielectric material from the second source / drain region.

7. The semiconductor device according to claim 5, wherein: The first dielectric material is a shallow trench isolation region.

8. The semiconductor device according to claim 5, wherein: The insulating plug includes a convex bottom profile that physically contacts the second source / drain region.

9. The semiconductor device according to claim 5, wherein: The insulating plug includes a bottleneck profile.

10. A method of forming a semiconductor device, comprising: forming a first transistor on a semiconductor substrate, the first transistor comprising a first source / drain region; planarizing the semiconductor substrate to expose the dummy semiconductor region; removing the dummy semiconductor region to define a first opening exposing a back side of the first source / drain region; widening the first opening, wherein widening the first opening comprises etching the semiconductor substrate; After widening the first opening, forming a contact in the first opening, the contact being electrically coupled to the first source / drain region; and After forming the contact in the first opening, a remaining portion of the semiconductor substrate is removed.

11. The method according to claim 10, wherein: Removing a remaining portion of the semiconductor substrate defines a second opening extending through the shallow trench isolation region, wherein the method further comprises forming an insulating plug in the second opening, and wherein the insulating plug extends to a second source / drain region of the first transistor.

12. The method according to claim 11, wherein: Forming the insulating plug includes: depositing a first dielectric liner on sidewalls and a bottom surface of the second opening; and A first dielectric material is deposited in the second opening over the first dielectric liner. 13 . The method of claim 10 , further comprising depositing a second dielectric liner on sidewalls of the first opening before forming the contact in the first opening. 14 . The method of claim 10 , further comprising forming a silicide on the backside of the first source / drain region before forming the contact in the first opening.

15. The method according to claim 10, further comprising: depositing a mask in the first opening, the mask covering the first source / drain region while widening the first opening; as well as The mask is removed before forming the contact in the first opening.

16. The method according to claim 15, wherein: The mask includes a bottom anti-reflective coating (BARC) material.

17. The method according to claim 10, wherein: After widening the first opening, the first opening includes a maximum width and a minimum width, and a ratio of the maximum width to the minimum width is in a range of 1.1 to 1.

8.

18. The method according to claim 10, wherein: Etching the semiconductor substrate includes performing a dry etching process using O 2 , Cl 2 , HCl, or HBr.

19. The method according to claim 10, wherein: A shallow trench isolation region is above the back side of the first source / drain region and the contact passes through the shallow trench isolation region, the first source / drain region of the first transistor is separated from the gate structure by an internal spacer, a first width of the contact is greater than a second width of the first source / drain region, the first width and the second width are measured along a longitudinal axis direction parallel to a fin of the first transistor, and the first width of the contact is measured between relative internal spacers at the level of the internal spacer closest to the shallow trench isolation region, the contact extends through the shallow trench isolation region, and the second width of the first source / drain region is measured from a first nanostructure of the first transistor to a second nanostructure of a transistor adjacent to the first transistor that is located at the same level as the first nanostructure.

20. The method according to claim 19, wherein: The first width is in a range of 25 nm to 50 nm, and the second width is in a range of 15 nm to 25 nm.

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