Electrostatic discharge circuit and method for preventing integrated circuit from malfunctioning due to reverse connection of power supply

Abstract

The present invention discloses an electrostatic discharge circuit and a method for preventing an integrated circuit from malfunctioning due to reverse connection of a power supply. The electrostatic discharge circuit includes at least one metal oxide semiconductor field effect transistor for providing an electrostatic discharge current path, and a control circuit coupled to the at least one metal oxide semiconductor field effect transistor. When an external power supply is reversely connected, the control circuit is used to change the base potential of the at least one metal oxide semiconductor field effect transistor so as to turn off the at least one metal oxide semiconductor field effect transistor, so as to prevent the reverse connection of the external power supply from generating a current passing through the at least one metal oxide semiconductor field effect transistor and causing a malfunction of the integrated circuit.

Description

Technical Field

[0001] The present invention relates to an electrostatic discharge (ESD) circuit, and in particular to an ESD circuit and a method thereof for preventing an integrated circuit (IC) from failing due to reverse power connection. Background Art

[0002] An ESD circuit is provided inside the IC to prevent the IC from being damaged by ESD. However, the IC may also fail during the production process due to the reverse connection of the external power supply. In particular, the instantaneous large current generated by the reverse connection of the external power supply through the ESD current path will burn out the pins or wiring that couple the IC to the external power supply, causing IC failure, or further damage to the ESD circuit or the internal circuit of the IC. Therefore, how to design an ESD circuit and a method to prevent IC failure due to reverse power supply has become an important topic in the field. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides an ESD circuit, which is suitable for use in an IC and is coupled to an external power supply through a first pin and a second pin, and the reverse connection of the external power supply means that the first pin and the second pin are respectively coupled to the negative electrode and the positive electrode of the external power supply. The ESD circuit includes at least one metal oxide semiconductor field effect transistor and a control circuit, and the at least one metal oxide semiconductor field effect transistor is used to provide an ESD current path to prevent the ESD current from flowing into the internal circuit of the IC and causing damage. The control circuit is coupled to the at least one metal oxide semiconductor field effect transistor, and is used to change the base potential of the at least one metal oxide semiconductor field effect transistor when the external power supply is reversely connected, so as to turn off the at least one metal oxide semiconductor field effect transistor, so as to prevent the reverse connection of the external power supply from generating a current passing through the at least one metal oxide semiconductor field effect transistor and causing IC failure.

[0004] The embodiment of the present invention further provides a method for preventing IC from malfunctioning due to reverse connection of power supply, which is executed in the ESD circuit of the IC. The ESD circuit is coupled to an external power supply through a first pin and a second pin, and the reverse connection of the external power supply means that the first pin and the second pin are respectively coupled to the negative pole and the positive pole of the external power supply, and the method comprises the following steps. When the external power supply is reversely connected, the base potential of at least one metal oxide semiconductor field effect transistor used to provide an ESD current path is changed by a control circuit, so that the at least one metal oxide semiconductor field effect transistor is turned off to prevent the reverse connection of the external power supply from generating a current passing through the at least one metal oxide semiconductor field effect transistor and causing IC malfunction.

[0005] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and description and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 4 is a circuit diagram of an ESD circuit provided by a first embodiment of the present invention.

[0007] Figure 2 FIG. 4 is a circuit diagram of an ESD circuit provided by a second embodiment of the present invention.

[0008] Figure 3 FIG. 4 is a circuit diagram of an ESD circuit provided by a third embodiment of the present invention.

[0009] Figure 4 It is a flowchart of the steps of a method for preventing IC failure due to reverse power connection provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0010] The following is an explanation of the implementation of the present invention through specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the content provided in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following implementations will further explain the relevant technical content of the present invention in detail, but the content provided is not intended to limit the scope of protection of the present invention.

[0011] It should be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0012] It is worth mentioning that the ESD circuit provided in the embodiment of the present invention can be applicable to any IC. In short, the present invention does not limit the specific implementation method of the IC, and those skilled in the art should be able to design it according to actual needs or applications.

[0013] See also Figure 1 , Figure 11 is a circuit diagram of an ESD circuit provided in the first embodiment of the present invention. The ESD circuit 1 is coupled to an external power source 4 via a first pin P1 and a second pin P2, and in particular, the first pin P1 and the second pin P2 are usually connected to the external power source 4 by wire bonding. In this embodiment, the external power source 4 may be, for example, a battery, but the present invention is not limited thereto, and the reverse connection of the external power source 4 means that the first pin P1 and the second pin P2 are respectively coupled to the negative electrode and the positive electrode of the battery, such as Figure 1 shown.

[0014] The ESD circuit 1 includes a control circuit 10 and a metal oxide semiconductor field effect transistor 111 for providing an ESD current path to prevent the ESD current from flowing into the internal circuit 5 of the IC and causing damage. That is, the IC of this embodiment includes the internal circuit 5 and the ESD circuit 1, and the internal circuit 5 and the ESD circuit 1 are coupled in parallel between a first pin P1 receiving a power supply voltage VDD and a second pin P2 receiving a ground voltage VSS.

[0015] In addition, the control circuit 10 is coupled to the MOSFET 111, and is used to change the base potential of the MOSFET 111 when the external power source 4 (battery) is reversely connected, so as to turn off the MOSFET 111, so as to prevent the external power source 4 (battery) from reversely connecting and generating a transient large current through the MOSFET 111, thereby preventing the IC from malfunctioning. As mentioned above, the IC malfunction in this embodiment may refer to the transient large current burning out the first pin P1, the second pin P2, or the connection that couples the IC to the external power source 4 (battery).

[0016] To facilitate the following description, Figure 1 The MOSFET 111 used to provide the ESD current path may be, for example, an N-type MOSFET, but the present invention is not limited thereto, and since an N-type MOSFET is used to provide the ESD current path, the ESD circuit 1 may further include a capacitor C1 and a resistor R1. A first end of the capacitor C1 and a drain (D) of the MOSFET 111 are commonly coupled to a first pin P1 receiving a power supply voltage VDD, and a second end of the capacitor C1 is coupled to a gate (G) of the MOSFET 111.

[0017] Please note that the present invention does not limit the specific implementation of the capacitor C1. In other embodiments, the capacitor C1 may also be a polarized capacitor, and the first end and the second end of the capacitor C1 refer to the positive end and the negative end of the polarized capacitor, respectively. In addition, the first end of the resistor R1 and the second end of the capacitor C1 may be commonly coupled to the gate (G) of the MOSFET 111, and the second end of the resistor R1 is coupled to the voltage transformation node VP1.

[0018] In this way, when ESD occurs at the first pin P1, that is, the first pin P1 receives a positive electrostatic voltage, a voltage difference will be generated on the capacitor C1 due to its high voltage characteristics, and due to the existence of this voltage difference, the metal oxide semi-field effect transistor 111 will have a conduction time of about hundreds of milliseconds, so the parasitic diode will be turned on to discharge the ESD current, and the turned-on metal oxide semi-field effect transistor 111 will also provide a connected channel, that is, an ESD current path to jointly discharge the ESD current to achieve the effect of ESD protection. Since the operating principles of the metal oxide semi-field effect transistor 111, the capacitor C1 and the resistor R1 are all well known to those skilled in the art, the details thereof will not be repeated.

[0019] It should be noted that in order to change the base potential of the MOSFET 111 when the external power source 4 (battery) is reversely connected, so as to turn off the MOSFET 111, so as to prevent the external power source 4 (battery) from reversely connecting and generating a current through the MOSFET 111 and causing IC failure, Figure 1 The control circuit 10 may include an N-type MOSFET 112 and an N-type MOSFET 113. In the present embodiment, a drain (D) of the N-type MOSFET 112 is coupled to a first pin P1 receiving a power supply voltage VDD, and a gate (G) of the N-type MOSFET 112 receives a ground voltage VSS.

[0020] In addition, the source (S) of the N-type MOSFET 113 and the source (S) of the N-type MOSFET 112 are coupled to the base of the MOSFET 111 through the voltage conversion node VP1, the gate (G) of the N-type MOSFET 113 receives the power supply voltage VDD, and the drain (D) of the N-type MOSFET 113 and the source (S) of the MOSFET 111 are coupled to the second pin P2 receiving the ground voltage VSS. Since the operation principles of the N-type MOSFET 112 and the N-type MOSFET 113 are also well known to those skilled in the art, the details thereof will not be repeated.

[0021] It can be seen that, unlike the prior art, the current path may be changed when the external power source 4 (battery) is reversely connected. Figure 1The ESD circuit 1 utilizes N-type MOSFET 112 and N-type MOSFET 113 to allow the base of MOSFET 111 to receive a low voltage, such as VSSx, and because the second end of resistor R1 is coupled to voltage-changing node VP1, the second end of resistor R1 and the base of MOSFET 111 have the same potential, i.e., voltage VSSx, so the parasitic diode will not be turned on, and MOSFET 111 will not be turned on, so as to prevent the reverse connection of external power source 4 (battery) from generating a current through MOSFET 111 and causing IC failure. In addition, please refer to Figure 2 , Figure 2 is a circuit diagram of an ESD circuit provided by a second embodiment of the present invention, and Figure 2 The middle part Figure 1 The same elements are denoted by the same symbols, and thus their details will not be described again here.

[0022] like Figure 2 As shown, the internal circuit 5 and the ESD circuit 2 are also coupled in parallel between the first pin P1 and the second pin P2, and the ESD circuit 2 is coupled to the external power source 4 (battery) through the first pin P1 and the second pin P2. Figure 1 The MOSFET 111, Figure 2 The MOSFET 121 used to provide the ESD current path is, for example, a P-type MOSFET, but the present invention is not limited thereto. Since a P-type MOSFET is used to provide the ESD current path, the ESD circuit 2 may further include a resistor R2 and a capacitor C2.

[0023] The first end of the resistor R2 is coupled to the voltage transformation node VP2, and the second end of the resistor R2 is coupled to the gate (G) of the MOSFET 121. In addition, the first end of the capacitor C2 and the second end of the resistor R2 can be commonly coupled to the gate (G) of the MOSFET 121, and the second end of the capacitor C2 and the drain (D) of the P-type MOSFET 121 are commonly coupled to the second pin P2 receiving the ground voltage VSS. As mentioned above, in other embodiments, the capacitor C2 can also be a polarized capacitor, and the first end and the second end of the capacitor C2 refer to the positive end and the negative end of the polarized capacitor, respectively, but the present invention is not limited thereto.

[0024] In this way, when ESD occurs at the first pin P1, that is, the first pin P1 receives a positive electrostatic voltage, a voltage difference will be generated on the capacitor C2 due to its high voltage characteristics, and due to the existence of this voltage difference, the metal oxide semi-field effect transistor 121 will have a conduction time of about hundreds of milliseconds, so the parasitic diode will be turned on to discharge the ESD current, and the turned-on metal oxide semi-field effect transistor 121 will also provide a connected channel, that is, an ESD current path to jointly discharge the ESD current to achieve the effect of ESD protection. Since the operating principles of the metal oxide semi-field effect transistor 121, the resistor R2 and the capacitor C2 are also well known to those skilled in the art, the details thereof will not be repeated.

[0025] Similarly, in order to change the base potential of the MOSFET 121 when the external power source 4 (battery) is reversely connected, so as to turn off the MOSFET 121, so as to prevent the reverse connection of the external power source 4 (battery) from generating a current through the MOSFET 121 and causing IC failure, Figure 2 The control circuit 10 may include a P-type MOSFET 122 and a P-type MOSFET 123. In the present embodiment, the drain (D) of the P-type MOSFET 122 and the source (S) of the MOSFET 121 are commonly coupled to a first pin P1 receiving a power supply voltage VDD, and the gate (G) of the P-type MOSFET 122 receives a ground voltage VSS.

[0026] In addition, the source (S) of the P-type MOSFET 123 and the source (S) of the P-type MOSFET 122 are coupled to the base of the MOSFET 121 through the voltage conversion node VP2, the gate (G) of the P-type MOSFET 123 receives the power supply voltage VDD, and the drain (D) of the P-type MOSFET 123 is coupled to the second pin P2 receiving the ground voltage VSS. Since the operation principles of the P-type MOSFET 122 and the P-type MOSFET 123 are also well known to those skilled in the art, the details thereof will not be repeated.

[0027] It can be seen that, unlike the prior art, the current path may be changed when the external power source 4 (battery) is reversely connected. Figure 2The ESD circuit 2 utilizes a P-type MOSFET 122 and a P-type MOSFET 123 to allow the base of the MOSFET 121 to receive a low voltage, such as VDDx. Since the first end of the resistor R2 is coupled to the transformer node VP2, the first end of the resistor R2 and the base of the MOSFET 121 have the same potential, i.e., the voltage VDDx. Therefore, the parasitic diode will not be turned on, and the MOSFET 121 will not be turned on, so as to prevent the external power supply 4 (battery) from being reversely connected to generate a current through the MOSFET 121 and cause IC failure.

[0028] Finally, see Figure 3 , Figure 3 is a circuit diagram of an ESD circuit provided by a third embodiment of the present invention, and Figure 3 The middle part Figure 1 or Figure 2 The same elements are represented by the same symbols, so their details will not be described in detail here. Figure 3 As shown, the internal circuit 5 and the ESD circuit 3 are also coupled in parallel between the first pin P1 and the second pin P2, and the ESD circuit 3 is coupled to the external power source 4 (battery) through the first pin P1 and the second pin P2. Figure 1 MOSFET 111 or Figure 2 MOSFET 121, Figure 3 The MOSFETs 114 and 124 for providing the ESD current path are, for example, an N-type MOSFET and a P-type MOSFET, but the present invention is not limited thereto.

[0029] In the present embodiment, the drain (D) of the MOSFET 114 is coupled to the drain (D) of the MOSFET 124, and since an N-type MOSFET and a P-type MOSFET are used to provide an ESD current path, the ESD circuit 3 may further include a capacitor C3, a resistor R3, a resistor R4, and a capacitor C4. A first end of the capacitor C3 and a source (S) of the MOSFET 124 are commonly coupled to a first pin P1 receiving a power supply voltage VDD, and a second end of the capacitor C3 is coupled to a gate (G) of the MOSFET 114.

[0030] In addition, the first end of the resistor R3 and the second end of the capacitor C3 may be commonly coupled to the gate (G) of the MOSFET 114, and the second end of the resistor R3 is coupled to the voltage transformation node VP3. The first end of the resistor R4 is coupled to the voltage transformation node VP4, and the second end of the resistor R4 is coupled to the gate (G) of the MOSFET 124. The first end of the capacitor C4 and the second end of the resistor R4 may be commonly coupled to the gate (G) of the MOSFET 124, and the second end of the capacitor C4 and the source (S) of the MOSFET 114 are commonly coupled to the second pin P2 receiving the ground voltage VSS.

[0031] In this way, when ESD occurs at the first pin P1, that is, the first pin P1 receives a positive electrostatic voltage, a voltage difference will be generated on the capacitors C3 and C4 due to their high voltage characteristics, and due to the existence of these two voltage differences, the metal oxide semi-conductor field effect transistors 114 and 124 will have a conduction time of about hundreds of milliseconds, so the parasitic diode will be turned on to discharge the ESD current, and the turned-on metal oxide semi-conductor field effect transistors 114 and 124 will also provide a connected channel, that is, an ESD current path to jointly discharge the ESD current to achieve the effect of ESD protection. Since the operation details have been described in the above content, they will not be repeated here.

[0032] Similarly, in order to change the base potential of the MOSFETs 114 and 124 when the external power source 4 (battery) is reversely connected, so as to turn off the MOSFETs 114 and 124, so as to prevent the reverse connection of the external power source 4 (battery) from generating a current through the MOSFETs 114 and 124 and causing IC failure, Figure 3 The control circuit 10 may include N-type MOSFETs 115 ˜ 118 and P-type MOSFETs 125 ˜ 128 .

[0033] In this embodiment, the drain (D) of the N-type MOSFET 115 is coupled to the first pin P1 receiving the power supply voltage VDD, and the gate (G) of the N-type MOSFET 115 receives the ground voltage VSS. In addition, the source (S) of the N-type MOSFET 116 and the source (S) of the N-type MOSFET 115 are coupled to the base of the MOSFET 114 through the voltage conversion node VP3, the gate (G) of the N-type MOSFET 116 receives the power supply voltage VDD, and the drain (D) of the N-type MOSFET 116 is coupled to the second pin P2 receiving the ground voltage VSS.

[0034] Correspondingly, the drain (D) of the P-type MOSFET 125 is coupled to the first pin P1 receiving the power supply voltage VDD, and the gate (G) of the P-type MOSFET 125 receives the ground voltage VSS. In addition, the source (S) of the P-type MOSFET 126 and the source (S) of the P-type MOSFET 125 are coupled to the base of the MOSFET 124 through the voltage conversion node VP4, the gate (G) of the P-type MOSFET 126 receives the power supply voltage VDD, and the drain (D) of the P-type MOSFET 126 is coupled to the second pin P2 receiving the ground voltage VSS.

[0035] Furthermore, the N-type MOSFET 117 is connected in series between the first pin P1 and the N-type MOSFET 115. The drain (D) of the N-type MOSFET 117 is coupled to the first pin P1 receiving the power supply voltage VDD, the gate (G) of the N-type MOSFET 117 receives a shielding voltage VSH, and the source (S) of the N-type MOSFET 117 is coupled to the drain (D) of the N-type MOSFET 115.

[0036] The N-type MOSFET 118 is connected in series between the second pin P2 and the N-type MOSFET 116. The drain (D) of the N-type MOSFET 118 is coupled to the second pin P2 receiving the ground voltage VSS, the gate (G) of the N-type MOSFET 118 receives the shielding voltage VSH, and the source (S) of the N-type MOSFET 118 is coupled to the drain (D) of the N-type MOSFET 116.

[0037] In contrast, the P-type MOSFET 127 is connected in series between the first pin P1 and the P-type MOSFET 125. The drain (D) of the P-type MOSFET 127 is coupled to the first pin P1 receiving the power supply voltage VDD, the gate (G) of the P-type MOSFET 127 receives the shielding voltage VSH, and the source (S) of the P-type MOSFET 127 is coupled to the drain of the P-type MOSFET 125.

[0038] The P-type MOSFET 128 is connected in series between the second pin P2 and the P-type MOSFET 126. The drain (D) of the P-type MOSFET 128 is coupled to the second pin P2 receiving the ground voltage VSS, the gate (G) of the P-type MOSFET 128 receives the shielding voltage VSH, and the source (S) of the P-type MOSFET 128 is coupled to the drain of the P-type MOSFET 126. Since the operation principles of the N-type MOSFETs 115-118 and the P-type MOSFETs 125-128 are also well known to those skilled in the art, the details thereof will not be described in detail.

[0039] In practice, the shielding voltage VSH may be, for example, a voltage obtained by subtracting the ground voltage VSS from the power supply voltage VDD and then dividing it by 2, but the present invention is not limited thereto. In short, unlike the prior art, when the external power supply 4 (battery) is reversely connected, the current path may be changed. Figure 3 The ESD circuit 3 utilizes N-type MOSFETs 115-118 and P-type MOSFETs 125-128 to allow the bases of MOSFETs 114 and 124 to receive a low voltage, such as VSSx and VDDx, respectively, and makes the second end of resistor R3 and the base of MOSFET 114 have the same potential, i.e., voltage VSSx, and also makes the first end of resistor R4 and the base of MOSFET 124 have the same potential, i.e., voltage VDDx, so that the parasitic diode will not be turned on, and MOSFETs 114 and 124 will not be turned on, so as to prevent the external power supply 4 (battery) from being reversely connected to generate current through MOSFETs 114 and 124 and cause IC failure.

[0040] On the other hand, see Figure 4 , Figure 4 1 is a flowchart of the steps of the method for preventing IC from malfunctioning due to reverse connection of power supply provided by an embodiment of the present invention. It should be noted that: Figure 4 The method can be executed in Figure 1 ESD circuit 1. Figure 2 ESD circuit 2 or Figure 3 Please also refer to ESD circuit 3. Figure 1 to Figure 3 For ease of understanding, but the present invention is not limited to Figure 4 The method can only be performed in ESD circuit 1, 2 or 3.

[0041] like Figure 4 As shown, when the external power source 4 (battery) is reversely connected, in step S410, the ESD circuit 1, 2 or 3 can use the control circuit 10 to change the base potential of at least one MOSFET used to provide the ESD current path, so as to turn off the at least one MOSFET, so as to prevent the external power source 4 (battery) from reversely connecting to generate a current through the at least one MOSFET and cause IC failure. Since the details have been described in the above content, they will not be repeated here.

[0042] In summary, an embodiment of the present invention provides an ESD circuit and a method for preventing an IC from malfunctioning due to reverse power connection. The ESD circuit includes at least one metal oxide semiconductor field effect transistor for providing an ESD current path, and a control circuit coupled to the at least one metal oxide semiconductor field effect transistor. When an external power supply is reversely connected, the control circuit is used to change the base potential of the at least one metal oxide semiconductor field effect transistor so as to turn off the at least one metal oxide semiconductor field effect transistor to prevent the reverse connection of the external power supply from generating a current passing through the at least one metal oxide semiconductor field effect transistor and causing IC malfunction.

[0043] The contents disclosed above are only preferred feasible embodiments of the present invention, and are not intended to limit the scope of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention's specification and drawings are included in the scope of the present invention.

Claims

1. An electrostatic discharge circuit, suitable for use in an integrated circuit, and coupled to an external power supply through a first pin and a second pin, wherein the external power supply is reversely connected to the first pin and the second pin, respectively, to the negative pole and the positive pole of the external power supply, characterized in that: The electrostatic discharge circuit comprises: at least one metal oxide semiconductor field effect transistor, used to provide an electrostatic discharge current path to prevent the electrostatic discharge current from flowing into the internal circuit of the integrated circuit and causing damage; and a control circuit coupled to the at least one MOSFET, and configured to change the base potential of the at least one MOSFET when the external power supply is reversely connected, so as to turn off the at least one MOSFET, so as to prevent the reverse connection of the external power supply from generating a current passing through the at least one MOSFET and causing a malfunction of the integrated circuit, Wherein, the at least one metal oxide semiconductor field effect transistor is a first N-type metal oxide semiconductor field effect transistor, and the electrostatic discharge circuit further includes: a capacitor having a first end coupled to the drain of the first N-type MOSFET and connected to the first pin receiving a power supply voltage, and a second end coupled to the gate of the first N-type MOSFET; and A resistor has a first end coupled to the gate of the first N-type metal oxide semi-conductor field effect transistor together with the second end of the capacitor, and a second end coupled to a transformation node.

2. The electrostatic discharge circuit according to claim 1, characterized in that: The control circuit comprises: a second N-type MOSFET, wherein a drain of the second N-type MOSFET is coupled to the first pin receiving the power voltage, and a gate of the second N-type MOSFET receives a ground voltage; and A third N-type metal oxide semiconductor field effect transistor, wherein the source of the third N-type metal oxide semiconductor field effect transistor and the source of the second N-type metal oxide semiconductor field effect transistor are commonly coupled to the base of the first N-type metal oxide semiconductor field effect transistor through the transformer node, the gate of the third N-type metal oxide semiconductor field effect transistor receives the power supply voltage, and the drain of the third N-type metal oxide semiconductor field effect transistor and the source of the first N-type metal oxide semiconductor field effect transistor are commonly coupled to the second pin receiving the ground voltage.

3. The electrostatic discharge circuit according to claim 2, characterized in that: When the external power supply is reversed, the control circuit utilizes the second N-type MOSFET and the third N-type MOSFET to allow the base of the first N-type MOSFET to receive a low voltage, and makes the second end of the resistor and the base of the first N-type MOSFET have the same potential, resulting in the parasitic diode not being turned on and the first N-type MOSFET not being turned on, so as to prevent the reverse connection of the external power supply from generating the current passing through the first N-type MOSFET and causing the integrated circuit to malfunction.

4. An electrostatic discharge circuit, suitable for use in an integrated circuit, and coupled to an external power supply through a first pin and a second pin, wherein the external power supply is reversely connected to the negative pole and the positive pole of the external power supply, respectively, wherein: The electrostatic discharge circuit comprises: at least one metal oxide semiconductor field effect transistor, used to provide an electrostatic discharge current path to prevent the electrostatic discharge current from flowing into the internal circuit of the integrated circuit and causing damage; and a control circuit coupled to the at least one MOSFET, for changing the base potential of the at least one MOSFET when the external power supply is reversely connected, so as to turn off the at least one MOSFET, so as to prevent the reverse connection of the external power supply from generating a current passing through the at least one MOSFET and causing a malfunction of the integrated circuit, wherein the at least one MOSFET is a first P-type MOSFET, and the electrostatic discharge circuit further comprises: a resistor having a first end coupled to a transformation node and a second end coupled to the gate of the first P-type metal oxide semi-conductor field effect transistor; and A capacitor having a first end coupled to the gate of the first P-type metal oxide semiconductor field effect transistor with the second end of the resistor, and a second end coupled to the drain of the first P-type metal oxide semiconductor field effect transistor with the second pin receiving a ground voltage.

5. The electrostatic discharge circuit according to claim 4, characterized in that: The control circuit comprises: a second P-type MOSFET, wherein a drain of the second P-type MOSFET and a source of the first P-type MOSFET are commonly coupled to the first pin receiving a power supply voltage, and a gate of the second P-type MOSFET receives the ground voltage; and A third P-type metal oxide semiconductor field effect transistor, the source of the third P-type metal oxide semiconductor field effect transistor and the source of the second P-type metal oxide semiconductor field effect transistor are coupled to the base of the first P-type metal oxide semiconductor field effect transistor through the transformer node, the gate of the third P-type metal oxide semiconductor field effect transistor receives the power supply voltage, and the drain of the third P-type metal oxide semiconductor field effect transistor is coupled to the second pin receiving the ground voltage.

6. The electrostatic discharge circuit according to claim 5, characterized in that: When the external power supply is reversed, the control circuit utilizes the second P-type MOSFET and the third P-type MOSFET to allow the base of the first P-type MOSFET to receive a low voltage, and makes the first end of the resistor and the base of the first P-type MOSFET have the same potential, resulting in the parasitic diode not being turned on and the first P-type MOSFET not being turned on, so as to prevent the external power supply from being reversed to generate the current passing through the first P-type MOSFET and causing the integrated circuit to malfunction.

7. An electrostatic discharge circuit, suitable for use in an integrated circuit, and coupled to an external power supply through a first pin and a second pin, wherein the external power supply is reversely connected to the first pin and the second pin, respectively, to the negative pole and the positive pole of the external power supply, characterized in that: The electrostatic discharge circuit comprises: at least one metal oxide semiconductor field effect transistor, used to provide an electrostatic discharge current path to prevent the electrostatic discharge current from flowing into the internal circuit of the integrated circuit and causing damage; and a control circuit coupled to the at least one MOSFET, for changing the base potential of the at least one MOSFET when the external power supply is reversely connected, so as to turn off the at least one MOSFET, so as to prevent the reverse connection of the external power supply from generating a current passing through the at least one MOSFET and causing a failure of the integrated circuit, wherein the at least one MOSFET is a first N-type MOSFET and a first P-type MOSFET, the drain of the first N-type MOSFET is coupled to the drain of the first P-type MOSFET, and the electrostatic discharge circuit further comprises: a first capacitor having a first end coupled to the source of the first P-type metal oxide semiconductor field effect transistor and connected to the first pin receiving a power supply voltage, and a second end coupled to the gate of the first N-type metal oxide semiconductor field effect transistor; a first resistor having a first end coupled to the gate of the first N-type metal oxide semi-conductor field effect transistor together with the second end of the capacitor, and a second end coupled to a first voltage transformation node; a second resistor having a first end coupled to a second voltage transformation node and a second end coupled to the gate of the first P-type metal oxide semi-conductor field effect transistor; and A second capacitor has a first end coupled to the gate of the first P-type metal oxide semiconductor field effect transistor with the second end of the resistor, and a second end coupled to the source of the first N-type metal oxide semiconductor field effect transistor with the second pin receiving a ground voltage.

8. The electrostatic discharge circuit according to claim 7, characterized in that: The control circuit comprises: a second N-type metal oxide semiconductor field effect transistor, wherein a drain of the second N-type metal oxide semiconductor field effect transistor is coupled to the first pin receiving the power supply voltage, and a gate of the second N-type metal oxide semiconductor field effect transistor receives the ground voltage; a third N-type MOSFET, wherein a source of the third N-type MOSFET and a source of the second N-type MOSFET are coupled to a base of the first N-type MOSFET via the first voltage transformation node, a gate of the third N-type MOSFET receives the power supply voltage, and a drain of the third N-type MOSFET is coupled to the second pin receiving the ground voltage; a second P-type metal oxide semi-conductor field effect transistor, wherein a drain of the second P-type metal oxide semi-conductor field effect transistor is coupled to the first pin receiving the power supply voltage, and a gate of the second P-type metal oxide semi-conductor field effect transistor receives the ground voltage; and A third P-type metal oxide semiconductor field effect transistor, the source of the third P-type metal oxide semiconductor field effect transistor and the source of the second P-type metal oxide semiconductor field effect transistor are coupled to the base of the first P-type metal oxide semiconductor field effect transistor through the second transformer node, the gate of the third P-type metal oxide semiconductor field effect transistor receives the power supply voltage, and the drain of the third P-type metal oxide semiconductor field effect transistor is coupled to the second pin receiving the ground voltage.

9. The electrostatic discharge circuit according to claim 8, characterized in that: The control circuit further comprises: a fourth N-type metal oxide semiconductor field effect transistor, connected in series between the first pin and the second N-type metal oxide semiconductor field effect transistor, a drain of the fourth N-type metal oxide semiconductor field effect transistor is coupled to the first pin receiving the power supply voltage, a gate of the fourth N-type metal oxide semiconductor field effect transistor receives a shielding voltage, and a source of the fourth N-type metal oxide semiconductor field effect transistor is coupled to the drain of the second N-type metal oxide semiconductor field effect transistor; a fifth N-type MOSFET, connected in series between the second pin and the third N-type MOSFET, wherein a drain of the fifth N-type MOSFET is coupled to the second pin receiving the ground voltage, a gate of the fifth N-type MOSFET receives the shielding voltage, and a source of the fifth N-type MOSFET is coupled to the drain of the third N-type MOSFET; a fourth P-type MOSFET, connected in series between the first pin and the second P-type MOSFET, wherein a drain of the fourth P-type MOSFET is coupled to the first pin receiving the power supply voltage, a gate of the fourth P-type MOSFET receives the shielding voltage, and a source of the fourth P-type MOSFET is coupled to the drain of the second P-type MOSFET; and A fifth P-type metal oxide semiconductor field effect transistor is connected in series between the second pin and the third P-type metal oxide semiconductor field effect transistor, the drain of the fifth P-type metal oxide semiconductor field effect transistor is coupled to the second pin receiving the ground voltage, the gate of the fifth P-type metal oxide semiconductor field effect transistor receives the shielding voltage, and the source of the fifth P-type metal oxide semiconductor field effect transistor is coupled to the drain of the third P-type metal oxide semiconductor field effect transistor.

10. The electrostatic discharge circuit according to claim 9, characterized in that: The shielding voltage is a voltage obtained by subtracting the ground voltage from the power supply voltage and dividing the resultant voltage by 2.

11. The electrostatic discharge circuit according to claim 10, characterized in that: When the external power supply is reversely connected, the control circuit utilizes the second N-type MOSFET to the fifth N-type MOSFET and the second P-type MOSFET to the fifth P-type MOSFET to allow the first N-type MOSFET and the first P-type MOSFET to receive a low voltage respectively, and makes the second end of the first resistor and the base of the first N-type MOSFET have the same potential, and also makes the first end of the second resistor and the base of the first P-type MOSFET have the same potential, resulting in that the parasitic diode will not be turned on, and the first N-type MOSFET and the first P-type MOSFET will not be turned on, so as to prevent the reverse connection of the external power supply from generating the current passing through the first N-type MOSFET and the first P-type MOSFET and causing the integrated circuit to malfunction.

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