Balance adjustment method, balance adjustment device and computer readable storage medium

Abstract

The present invention relates to an equalization adjustment method, an equalization adjustment device and a computer-readable storage medium. The equalization adjustment method is implemented when a processing unit of a storage device loads and executes a program code, and includes: after detecting a symbol decoding error, repeatedly adjusting the parameters of an equalizer until the adjustment fails or the continuous waveform output by the equalizer is detected to be in an open-eye state. Through the equalization adjustment operation as described above, the storage device can actively adjust the equalizer to solve errors that occur during data reception.

Description

Technical Field

[0001] The present invention relates to a storage device, and in particular to a balance adjustment method, a balance adjustment device and a computer-readable storage medium. Background Art

[0002] Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (Host) can provide any address to access the NOR flash memory on the address pin and obtain the data stored at the address from the data pin of the NOR flash memory in a timely manner. In contrast, NAND flash memory is not random access, but serial access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processing unit needs to write serial byte values ​​to the NAND flash memory to define the type of request command (such as read, write, erase, etc.) and the address used in this command. The address can point to a page (the smallest data block for write operations in flash memory) or a block (the smallest data block for erase operations in flash memory).

[0003] When data is transmitted between the host and the device at a high speed, such as at a transmission rate higher than 6Gb / sec, data is easily affected by jitter, voltage changes on the motherboard, and inter-symbol interference (ISI), which may cause errors. Therefore, the physical layers of the host and the device may be equipped with equalizers to eliminate or suppress data errors during high-speed transmission by adjusting parameters. According to standard specifications, such as Universal Flash Storage (UFS), equalization adjustment can only be initiated by the host. The host may initiate equalization adjustment before switching the transmission mode to a high-speed file position (such as High Speed ​​Gear 4, HS-G4, or a higher speed position), or when it is found that the error rate of the data received from the device reaches or exceeds a threshold. However, in some cases, the device will find that the error rate of the received data has reached or exceeded the threshold earlier than the host, and relying solely on the host to initiate equalization adjustment will delay the timing of correcting the error. Therefore, the present invention provides a balance adjustment method that can be initiated by a device end, a balance adjustment device, and a computer-readable storage medium. Summary of the invention

[0004] In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is indeed a problem to be solved.

[0005] The present invention relates to a computer-readable storage medium for storing a computer program that can be loaded and executed by a processing unit of a storage device. When the computer program is executed by the processing unit, the following steps are implemented: after a symbol decoding error is detected, the parameters of an equalizer are repeatedly adjusted until the adjustment fails or it is detected that the continuous waveform output by the equalizer belongs to an open-eye state.

[0006] The present invention also relates to an equalization adjustment method, which is executed by a processing unit in a storage device, comprising: after detecting a symbol decoding error, repeatedly adjusting the parameters of the equalizer until the adjustment fails or the continuous waveform output by the equalizer is detected to be in an open eye state.

[0007] The present invention also relates to an equalizer adjustment device, comprising an equalizer, a symbol decoder and a processing unit. The symbol decoder is coupled to the equalizer and is used to receive host data from the equalizer. The processing unit is coupled to the equalizer and the symbol decoder, and after detecting a symbol decoding error transmitted from the symbol decoder, repeatedly adjusts the parameters of the equalizer until the adjustment fails or the continuous waveform output by the equalizer is detected to be in an open eye state.

[0008] One of the advantages of the above embodiment is that the storage device can actively adjust the equalizer to resolve errors that occur during data reception through the equalization adjustment operation described above.

[0009] Other advantages of the present invention will be explained in more detail with reference to the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0011] Figure 1 is a block diagram of a storage device according to an embodiment of the present invention.

[0012] Figure 2 FIG. 4 is a schematic diagram of an equalizer according to an embodiment of the present invention.

[0013] Figure 3 FIG. 4 is an eye diagram of an open eye state according to an embodiment of the present invention.

[0014] Figure 4 FIG. 4 is an eye diagram of an open eye state according to an embodiment of the present invention.

[0015] Figure 5 FIG. 4 is a flow chart of a balance adjustment method according to an embodiment of the present invention.

[0016] Figure 6 is a block diagram of a storage device according to an embodiment of the present invention.

[0017] Figure 7 FIG. 4 is a flow chart of a balance adjustment method according to an embodiment of the present invention.

[0018] Explanation of symbols:

[0019] 10, 60: storage device; 110, 600: physical layer; 122: equalizer; 1225: register; 123: eye diagram analyzer; 124: deserializer; 126: filler generator; 128: symbol decoder; 129, 660: multiplexer; 130: medium access control layer; 150: processing unit; 170: interrupt generator; 210: first-order continuous time linear equalizer; 230: first-order decision feedback equalizer; S510~S590, S710~S730: method steps; 620: data buffer; 640: control circuit. DETAILED DESCRIPTION

[0020] The embodiments of the present invention will be described below with reference to the accompanying drawings. In these drawings, the same reference numerals represent the same or similar components or method flows.

[0021] It must be understood that the words "comprise", "include", etc. used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, elements and / or components, but do not exclude the addition of more technical features, values, method steps, operations, elements, components, or any combination of the above.

[0022] The words "first", "second", "third", etc. used in the present invention are used to modify the components in the claims, and are not used to indicate a priority order, a prior relationship, or that one component precedes another, or a time sequence when executing method steps. They are only used to distinguish components with the same name.

[0023] It should be understood that when a component is described as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, and there may be intervening components. Conversely, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intervening components. Other words used to describe the relationship between components can also be interpreted in a similar manner, such as "between" versus "directly between", or "adjacent" versus "directly adjacent", etc.

[0024] refer to Figure 1. The storage device 10 can be set in an electronic device, such as a personal computer, a laptop computer (Laptop PC), a tablet computer, a mobile phone, a digital camera, a digital video camera, a flash drive, a memory card, a solid state disk (SSD) and other electronic products. The storage device 10 includes a physical layer (PHY) 110, a media access control layer (MAC) 130, a processing unit 150 and an interrupt generator 170. The processing unit 150 can be implemented in a variety of ways, such as using general hardware (for example, a single processor, a multi-processor with parallel processing capabilities, a graphics processor or other processors with computing capabilities), and providing specified functions when executing software and / or firmware instructions. The processing unit 150 can receive host commands from the host side through the physical layer 110 and the media access control layer 130, such as read, write, and erase commands that comply with the Universal Flash Storage (UFS) standard.

[0025] The storage device 10 includes a storage unit (not shown in FIG. Figure 1 ), providing a large amount of storage space, usually hundreds of gigabytes (Gigabytes), or even several terabytes (Terabytes), for storing a large amount of user data, such as high-resolution pictures, movies, etc. The storage unit includes a control circuit and a memory array. The storage cells in the memory array may include single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs) or any combination thereof.

[0026] The physical layer 110 is built on an 8b / 10b, 64b / 66b or 128b / 130b serializer / deserializer (SerDes) environment and includes a pair of functional circuits to compensate for the limited input / output. It provides data transmission on a differential pair so that the input and output pins and the wiring therebetween can be minimized. In detail, the host's transmitting end converts a low-speed parallel signal into a high-speed serial signal and transmits it to the receiving end of the storage device 10 through a differential pair. The physical layer 110 includes a deserializer 124 for converting a high-speed serial signal received via an equalizer 122 into a low-speed parallel signal. The signal transmitted from the host's transmitting end to the receiving end of the storage device 10 is also called host data.

[0027] In order to solve the technical problem that data is easily affected by jitter, voltage change on the motherboard, and inter-symbol interference during high-speed transmission between the host and the device, the physical layer 110 sets an equalizer 122 between the transmission channel and the deserializer 124. The equalizer 122 includes a register 1225, allowing the processing unit 150 to adjust the parameters of the equalizer 122 during operation by setting the value in the register 1225. Figure 2 For example, the equalizer 122 includes a first-order continuous time linear equalizer (CTLE) 210 and a first-tap decision feedback equalizer (DFE) 230. Figure 2 The equalizer architecture shown in the figure, but those skilled in the art may use other well-known architectures to design the equalizer 122, for example, the equalizer 122 only includes a first-stage continuous-time linear equalizer 210, the first-stage continuous-time linear equalizer 210 is replaced with other equivalent continuous-time linear equalizers, the first-order decision feedback equalizer 230 is replaced with a multi-order decision feedback equalizer or other equivalent decision feedback equalizers, and the present invention is not limited thereby.

[0028] The characteristics of CTLE can be expressed using the following transfer function:

[0029]

[0030] Among them, A DC represents DC gain, ω represents 2πf, f z represents 0, f P1 represents the first pole, f P2 Represents the second pole.

[0031] The characteristics of DFE can be expressed using the following formula:

[0032] y k =x k -V DFE_RX

[0033] y k =x k -d1sgn(y k-1 )

[0034] Among them, y k represents the output voltage signal of DFE, x k Represents the voltage signal input to DFE, V DFE_RX represents the feedback voltage signal of DFE, k represents the sampling index value of the data bit, and d1 represents the feedback coefficient of DFE.

[0035] The physical layer 110 includes an eye diagram analyzer 123. The processing unit 150 can send a signal to the eye diagram analyzer 123 to start the eye diagram analyzer 123. Traditionally, the eye diagram analyzer 123 is used in the factory to allow engineers to calibrate the equalizer 122, but is not used in the actual operation of the storage device 10 after it leaves the factory. The eye diagram analyzer 123 calculates a value representing the eye diagram and determines whether the calculated value belongs to the eye open state (e.g., Figure 3 Eye Close State, as shown Figure 4 As shown in FIG. 1 , the eye diagram is a combined graph formed by superimposing the continuous waveforms output by the equalizer 122. When the calculated value belongs to the open eye state, the signal output by the equalizer 122 is acceptable. When the calculated value belongs to the closed eye state, it means that the equalizer 122 currently has no way to eliminate interference and needs further adjustment. In order to save power consumption, under normal circumstances, the eye diagram analyzer 123 can be turned off and not run. The processing unit 150 can send a control signal to the eye diagram analyzer 123 to start the eye diagram analyzer 123 as appropriate. When the eye diagram analyzer 123 detects that the continuous waveform output by the equalizer 122 belongs to the closed eye state, the calculated value is transmitted to the processing unit 150 so that the processing unit 150 can adjust the equalizer 122 accordingly. When the eye diagram analyzer 123 detects that the continuous waveform output by the equalizer 122 belongs to the open eye state, information is transmitted to notify the processing unit 150 that the signal output by the current equalizer 122 is acceptable.

[0036] The physical layer 110 includes a symbol decoder 128, which may be an 8b / 10b converter, a 64b / 66b converter, or a 128b / 130b converter according to different SerDes environments. The symbol decoder 128 includes a mapping table for converting input data bits into codes represented by fewer bits, such as mapping input 10, 66, or 130-bit data into 8, 64, or 128-bit codes. For example, in an 8b / 10b SerDes environment, 10 bits may represent 2 10 = 1024 states, the mapping table only includes 2 8 = 256 mapping relationships. When any input data bit cannot be converted into any valid code according to the mapping table, the symbol decoder 128 determines that the input data bit is wrong and can set a register in the interrupt generator 170 to notify the processing unit 150 of the symbol decoding error.

[0037] When the content of the register in the interrupt generator 170 is changed, the interrupt generator 170 will send an interrupt signal (Interrupt, referred to as INT) to the processing unit 150 to trigger the processing unit 150 to execute the interrupt service routine. In the interrupt service routine, the processing unit 150 checks the content of the register and thereby knows the state detected by the physical layer 110, such as the occurrence of a symbol decoding error. When a symbol decoding error is detected, the processing unit 150 loads and executes appropriate firmware program code to implement the equalization adjustment method of the embodiment of the present invention.

[0038] The physical layer 110 includes a filler generator 126 for generating continuous fillers, such as K.28.1 symbols, etc. When the MAC layer 130 or the processing unit 150 detects the fillers, it knows that these symbols are not data transmitted from the host.

[0039] The physical layer 110 includes a multiplexer (MUX) 129, an input end of which is coupled to the symbol decoder 128 and the padding element generator 126, and an output end of which is coupled to the MAC layer 130. Under normal circumstances, the multiplexer 129 connects the output of the symbol decoder 128 to the input of the MAC layer 130, so as to transmit the data of the host side to the MAC layer 130 via the multiplexer 129. In addition, the multiplexer 129 can be controlled by the processing unit 150 to connect the output of the padding element generator 126 to the input of the MAC layer 130, so as to transmit the padding element generated by the padding element generator 126 to the MAC layer 130, in other words, to prevent the data of the host side from being transmitted to the MAC layer 130.

[0040] In order to enable the storage device 120 to actively adjust the equalizer 122 to resolve errors that occur during data reception, the processing unit 150 may load and execute firmware program code to complete the following steps: Figure 5 The method flow chart shown. This method flow can be limited to the host side and the storage device 10 running in a high-speed transmission environment, such as High Speed ​​Gear 4 (HS-G4) or a higher speed gear, or it can be executed at any transmission rate. The equalization adjustment method described in the embodiment of the present invention is characterized in that after a symbol decoding error is detected, the parameters of the equalizer 122 are repeatedly adjusted until the adjustment fails or the continuous waveform output by the equalizer 122 is detected to be in an open eye state. The detailed description is as follows:

[0041] Step S510: Detecting a symbol decoding error in the symbol decoder 128 through the interrupt signal INT. The symbol decoding error can be regarded as a condition for the storage device 10 to initiate equalization adjustment. Since the interrupt signal INT is the highest priority signal, the processing unit 150 will first execute the program code in response to the symbol decoding error.

[0042] Step S520: Send a control signal to the multiplexer 129 to connect the parallel output of the padding element generator 126 to the parallel input of the MAC layer 130, so that the padding elements generated by the padding element generator 126 are transmitted to the MAC layer 130 via the multiplexer 129 and avoid erroneous host data from being transmitted to the MAC layer 130.

[0043] Step S530: Send a control signal to the eye diagram analyzer 123 to start the eye diagram analyzer 123. After starting, the eye diagram analyzer 123 continuously transmits values ​​corresponding to the eye diagram to the processing unit 150. In addition, when the eye diagram is detected to be in an open state, corresponding information can be transmitted to notify the processing unit 150.

[0044] Step S540: The register 1225 may be set according to the value calculated by the eye diagram analyzer using an algorithm known to those skilled in the art to adjust the parameters of the equalizer 122 .

[0045] Step S550: Determine whether an open eye state is detected based on the data and / or information received from the eye diagram analyzer 123. If yes, proceed to step S580; otherwise, proceed to step S560.

[0046] Step S560: Determine whether the adjustment fails. If so, proceed to step S570; otherwise, proceed to step S540. In some embodiments, the processor 150 may start a timer in step S510 to count a period of time, which represents the time allowed for adjustment. When it is detected that the timer has counted beyond this period of time, it indicates that the equalization adjustment has exceeded the allowed time and cannot be adjusted further, and the adjustment has failed. In other embodiments, the processor 150 may determine whether all candidate parameter value combinations for adjusting the equalizer 122 have been tried. If so, it indicates that the equalizer 122 cannot be adjusted further, and the adjustment has failed.

[0047] Step S570: Activate other error correction mechanisms. For example, the processing unit 150 transmits information to the host through the physical layer 110 to notify the host of a symbol decoding error. The host may try to reduce the transmission speed between the host and the storage device 10 and then increase the speed, activate the feed forward equalizer (FFE) of the host transmitter, and assist in equalization adjustment by continuously transmitting training frames (such as PRBS9) to the storage device 10, or use other mechanisms to try to resolve the symbol decoding error that occurred in the storage device 10.

[0048] Step S580: Send a control signal to the multiplexer 129 to connect the parallel output of the symbol decoder 128 to the parallel input of the MAC layer 130, returning to the default connection state.

[0049] Step S590: sending a control signal to the eye diagram analyzer 123 to shut down the eye diagram analyzer 123 to save power consumption.

[0050] Steps S540 to S560 form a loop, which may be executed once every millisecond or a plurality of milliseconds.

[0051] When the eye diagram analyzer 123 detects that the continuous waveform output by the equalizer 122 is in the open eye state (the "yes" path in step S550), it means that the equalizer 122 is adjusted successfully and leaves the loop. Then, the processor 150 restores the multiplexer 129 and the eye diagram analyzer 123 to the original default state (steps S580 and S590).

[0052] When the output of the equalizer 122 cannot be adjusted to the open eye state after a default period of time or after trying all candidate parameter value combinations (the "yes" path in step S560), it means that the adjustment of the equalizer 122 has failed and the loop is exited. Then, the processor 150 activates other error correction mechanisms (step S570) and restores the multiplexer 129 and the eye diagram analyzer 123 to the original default state (steps S580 and S590).

[0053] The execution of step S530 and step S580 is used to allow the processing unit 150 to continuously output filler elements to the media access control layer 130 after detecting a symbol decoding error, so as to replace the output data of the symbol decoder 128, until the adjustment fails or the continuous waveform output by the equalizer 122 is detected to be in an open-eye state. In some cases, the MAC layer 130 may receive information about a symbol decoding error from the symbol decoder 128 of the physical layer 110 but directly trigger the error correction mechanism initiated by the host without waiting for the result of the equalization adjustment. The above steps can prevent the information about the symbol decoding error from being transmitted to the MAC layer 130, and further prevent the error correction mechanism initiated by the host from being triggered.

[0054] However, Figure 1 The physical layer 110 will lose the data transmitted from the host end during the period from when the symbol decoder 128 has a symbol decoding error to when the equalizer 122 is successfully adjusted. Figure 6 In another embodiment of the storage device 60 described, in order to retain the data transmitted from the host during this period, the physical layer 600 further includes a data cache 620 and a control circuit 640. The processing unit 150 can send a control signal to drive the control circuit 640 to start writing the data transmitted from the host into the data cache 620 in sequence. In addition, in order to allow the data in the data cache 620 to be re-input into the equalizer 122, the physical layer 600 further includes a multiplexer 660, the input end of which is coupled to the output of the receiver and the output of the control circuit 640, and the output end is coupled to the input of the equalizer 122. Under normal circumstances, the receiver of the physical layer 600 is coupled to the equalizer 122 via the multiplexer 660. The processing unit 150 can send a control signal to the multiplexer 660 to couple the output of the control circuit 640 to the equalizer 122, and send a control signal to drive the control circuit 640 to read the data in the data cache 620 in sequence and re-input the data into the equalizer 122 via the multiplexer 660. For distinction, the multiplexer 129 in the physical layer 600 may be referred to as a first multiplexer, and the multiplexer 660 in the physical layer 600 may be referred to as a second multiplexer.

[0055] according to Figure 6 The architecture shown in FIG. 1 is implemented by loading and executing another firmware program code by the processing unit 150. Figure 7 In the new process, step S710 is added after step S510, and step S730 is added after the "yes" path in step S550. The detailed description is as follows:

[0056] Step S710 : the driving control circuit 640 starts to write the data transmitted from the host end (ie, the data transmitted from the host end after a symbol decoding error is detected) into the data buffer 620 in sequence.

[0057] Step S730: Control the multiplexer 660 to couple the output of the control circuit 640 to the equalizer 122 (at this time, the equalizer 122 has been adjusted), and send a control signal to drive the control circuit 640 to sequentially read the data in the data buffer 620 and re-input the data into the equalizer 122 via the multiplexer 660. If the period from when the symbol decoding error occurs in the symbol decoder 128 to when the equalizer 122 is successfully adjusted is too long so that the data buffer 620 cannot store all the data, the processing unit 150 may abandon re-inputting the data in the data buffer 620 into the adjusted equalizer 122.

[0058] All or part of the steps in the method described in the present invention can be implemented by a computer program, such as a driver for specific hardware in a storage device, or a software program. In addition, it can also be implemented in other types of programs as shown above. A person with ordinary knowledge in the relevant technical field can write the method of the embodiment of the present invention into a computer program, which will not be described for the sake of simplicity. The computer program implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer-readable data medium, such as a DVD, CD-ROM, USB, hard disk, or can be placed on a network server that can be accessed through a network (e.g., the Internet, or other appropriate carriers).

[0059] Although Figure 1 , Figure 2 and Figure 6 The above-described components are included in the invention, but it is not excluded that more additional components may be used to achieve better technical effects without violating the spirit of the invention. Figure 5 and Figure 7 The flowchart is executed in a specified order, but without violating the spirit of the invention, a person skilled in the art can modify the order of these steps while achieving the same effect, so the present invention is not limited to the order described above. In addition, a person skilled in the art can also integrate several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention is not limited thereto.

[0060] Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, the present invention covers obvious modifications and similar arrangements that are obvious to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest way to include all obvious modifications and similar arrangements.

Claims

1. A computer-readable storage medium for storing a computer program executable by a processing unit in a storage device, characterized in that: When the computer program is executed by the processing unit, the following steps are implemented: After a symbol decoding error is detected, repeatedly adjusting the parameters of the equalizer until the adjustment fails or a continuous waveform output by the equalizer is detected to be in an open eye state; as well as After the symbol decoding error is detected, the multiplexer is controlled to connect the filler generator to the media access control layer, so that the filler generator continuously outputs fillers to the media access control layer to replace the output result of the symbol decoder to prevent the error correction mechanism initiated by the host from being triggered, until the adjustment fails or the continuous waveform output by the equalizer is detected to belong to the open eye state. The multiplexer includes an input end and an output end, the input end is coupled to the symbol decoder and the padding element generator, and the output end is coupled to the medium access control layer.

2. The computer-readable storage medium according to claim 1, wherein: When the computer program is executed by the processing unit, the following steps are implemented: After receiving the interrupt signal, the occurrence of the symbol decoding error is known by checking the content of the register in the interrupt generator.

3. The computer-readable storage medium according to claim 1, wherein: When the computer program is executed by the processing unit, the following steps are implemented: After the symbol decoding error is detected, the eye diagram analyzer is started to repeatedly adjust the parameters of the equalizer according to the values ​​corresponding to the eye diagram calculated by the eye diagram analyzer until the adjustment fails or the continuous waveform output by the equalizer is detected to belong to the open eye state.

4. The computer-readable storage medium according to claim 3, wherein: When the computer program is executed by the processing unit, the following steps are implemented: After detecting that the continuous waveform output by the equalizer belongs to the open eye state or the adjustment fails, the eye diagram analyzer is turned off.

5. The computer-readable storage medium according to claim 1, wherein: When the computer program is executed by the processing unit, the following steps are implemented: After detecting that the continuous waveform output by the equalizer belongs to the open eye state or adjustment fails, the multiplexer is controlled to connect the symbol decoder to the media access control layer, so that the symbol decoder outputs the decoding result of the symbol decoder to the media access control layer to replace the filling element.

6. The computer-readable storage medium of claim 1, wherein: If a continuous waveform output by the equalizer is not detected after a predetermined period of time after the symbol decoding error is detected, it belongs to the open eye state, indicating adjustment failure.

7. The computer-readable storage medium of claim 1, wherein: After trying all candidate parameter value combinations to adjust the equalizer, if no continuous waveform output by the equalizer is detected to belong to the open eye state, it means that the adjustment fails.

8. The computer-readable storage medium of claim 1, wherein: The symbol decoding error means that the data output from the equalizer cannot be converted into any valid code.

9. A method for equalization adjustment, implemented by a processing unit of a storage device loading and executing a computer program, characterized in that: The balance adjustment method comprises: After a symbol decoding error is detected, repeatedly adjusting the parameters of the equalizer until the adjustment fails or a continuous waveform output by the equalizer is detected to be in an open eye state; and After the symbol decoding error is detected, the multiplexer is controlled to connect the filler generator to the media access control layer, so that the filler generator continuously outputs fillers to the media access control layer to replace the output result of the symbol decoder to prevent the error correction mechanism initiated by the host from being triggered, until the adjustment fails or the continuous waveform output by the equalizer is detected to belong to the open eye state. The multiplexer includes an input end and an output end, the input end is coupled to the symbol decoder and the padding element generator, and the output end is coupled to the medium access control layer.

10. The equalization adjustment method according to claim 9, characterized in that: Also includes: After the symbol decoding error is detected, the eye diagram analyzer is started to repeatedly adjust the parameters of the equalizer according to the values ​​corresponding to the eye diagram calculated by the eye diagram analyzer until the adjustment fails or the continuous waveform output by the equalizer is detected to belong to the open eye state.

11. The equalization adjustment method according to claim 10, characterized in that: Also includes: After detecting that the continuous waveform output by the equalizer belongs to the open eye state or the adjustment fails, the eye diagram analyzer is turned off.

12. A balance adjustment device, characterized in that: include: Equalizer; a symbol decoder, coupled to the equalizer, for receiving host data from the equalizer; Populate the meta generator; Media access control layer; A multiplexer, comprising an input end and an output end, wherein the input end is coupled to the symbol decoder and the filler generator, and the output end is coupled to the medium access control layer; as well as a processing unit coupled to the equalizer, the symbol decoder and the medium access control layer, and repeatedly adjusting the parameters of the equalizer after detecting a symbol decoding error transmitted from the symbol decoder until the adjustment fails or the continuous waveform output by the equalizer is detected to be in an open eye state; And after detecting the symbol decoding error, controlling the multiplexer to connect the fill element generator to the media access control layer, so that the fill element generator continuously outputs fill elements to the media access control layer, replacing the output result of the symbol decoder to prevent triggering the error correction mechanism initiated by the host end, until the adjustment fails or it is detected that the continuous waveform output by the equalizer belongs to the open eye state.

13. The balance adjustment device according to claim 12, characterized in that: Also includes: An interrupt generator, comprising a register, coupled to the symbol decoder and the processing unit, After receiving the interrupt signal from the interrupt generator, the processing unit checks the content of the register in the interrupt generator to know that the symbol decoding error occurs.

14. The balance adjustment device according to claim 12, characterized in that: Also includes: an eye diagram analyzer coupled to the equalizer and the processing unit, After detecting the symbol decoding error, the processing unit starts the eye diagram analyzer and repeatedly adjusts the parameters of the equalizer according to the numerical values ​​corresponding to the eye diagram calculated by the eye diagram analyzer until the adjustment fails or it is detected that the continuous waveform output by the equalizer belongs to the open eye state.

15. The balance adjustment device according to claim 14, characterized in that: The processing unit turns off the eye diagram analyzer after detecting that the continuous waveform output by the equalizer belongs to the open eye state or the adjustment fails.

16. The balance adjustment device according to claim 12, characterized in that: After detecting that the continuous waveform output by the equalizer belongs to the open eye state or the adjustment fails, the processing unit controls the multiplexer to connect the symbol decoder to the media access control layer, so as to output the decoding result of the symbol decoder to the media access control layer to replace the padding element.

17. The balance adjustment device according to claim 12, characterized in that: If the processing unit has not detected that the continuous waveform output by the equalizer belongs to the open eye state after a default period of time has passed after the processing unit has detected the symbol decoding error, or if the processing unit has not detected that the continuous waveform output by the equalizer belongs to the open eye state after trying all candidate parameter value combinations to adjust the equalizer, it means that the adjustment has failed.

18. The balance adjustment device according to claim 12, characterized in that: Also includes: Data buffer; A control circuit coupled to the data buffer; as well as a multiplexer comprising an input end and an output end, wherein the input end is coupled to the control circuit and the receiver, and the output end is coupled to the equalizer, After detecting that the continuous waveform output by the equalizer belongs to the open eye state, the processing unit controls the multiplexer to connect the control circuit to the equalizer, and drives the control circuit to re-input the host data cached after the symbol decoding error is detected into the equalizer.

Images