Quantum computing devices and systems

Abstract

A quantum computing device and system are provided. The quantum computing device includes: a first qubit chip; a readout cavity structure surrounding a first end of the first qubit chip; and a storage cavity structure surrounding a second end of the first qubit chip, wherein the first qubit chip includes: a first readout antenna disposed within the readout cavity structure; a first storage antenna disposed in the storage cavity structure; and a first qubit element disposed between the first readout antenna and the first storage antenna, and wherein the first qubit element is disposed between the readout cavity structure and the storage cavity structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0046880, filed on April 17, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference for all purposes. Technical Field

[0003] The present disclosure relates to a quantum computing device and system. Background Art

[0004] A quantum computer is a computing machine that relies on or uses quantum mechanical phenomena such as quantum superposition and quantum entanglement as operating principles, for example, to perform data processing. A unit element capable of storing information (or the information itself) using the principles of quantum mechanics is called a qubit or quantum bit and can be used as the basic unit of information in a quantum computer.

[0005] The bits used in classical information storage elements have a state of either "0" or "1," but due to the phenomenon of superposition, qubits can be in both states "0" and "1" simultaneously. Furthermore, interactions between qubits can be achieved through entanglement. Due to the properties of these qubits, 2N pieces of information can be generated using N qubits. Therefore, compared to classical processing using classical information storage elements, the amount of information and processing speed can be increased exponentially as the number of qubits increases. Summary of the Invention

[0006] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0007] In one general aspect, a quantum computing device includes: a first qubit chip; a readout cavity structure surrounding a first end of the first qubit chip; and a storage cavity structure surrounding a second end of the first qubit chip, wherein the first qubit chip includes: a first readout antenna disposed within the readout cavity structure; a first storage antenna disposed in the storage cavity structure; and a first qubit element disposed between the first readout antenna and the first storage antenna, and wherein the first qubit element is disposed between the readout cavity structure and the storage cavity structure.

[0008] The first qubit chip further includes: a first through-pad facing the first qubit element; and a first through-wiring electrically connected to the first through-pad, wherein the first through-pad may be closer to the first qubit element than the first through-wiring.

[0009] The quantum computing device may further include: a bus chip, arranged between the readout cavity structure and the storage cavity structure, wherein the bus chip may include: a connection pad, configured to receive an electrical signal from outside the bus chip; a transmission pad, facing the connection pad; and a transmission wiring, electrically connected to the transmission pad, wherein the transmission wiring may be electrically connected to the first through wiring.

[0010] The transmission pad may be configured to capacitively couple with the connection pad with respect to the received electrical signal.

[0011] The first qubit chip may further include: a first readout wiring, electrically connecting the first readout antenna to the first qubit element; a first storage wiring, electrically connecting the first storage antenna to the first qubit element; and a first qubit board, arranged on the bus chip, wherein the first qubit element, the first readout antenna, the first readout wiring, the first storage antenna and the first storage wiring may be arranged on the first qubit board.

[0012] The first qubit element may include a first superconducting material pattern, a dielectric film, and a second superconducting material pattern stacked sequentially, wherein the first superconducting material pattern, the dielectric film, and the second superconducting material pattern may constitute a Josephson junction.

[0013] The first superconducting material pattern may be electrically connected to the first readout antenna through a first readout wiring, and the second superconducting material pattern may be electrically connected to the first storage antenna through a first storage wiring.

[0014] The first through pad may be configured to be capacitively coupled with the second superconducting material pattern.

[0015] The quantum computing device may also include a second quantum bit chip separated from the first quantum bit chip, wherein the second quantum bit chip may further include: a second readout antenna, arranged in the readout cavity structure; a second storage antenna, arranged in the storage cavity structure; a second quantum bit element, arranged between the second readout antenna and the second storage antenna; a second through-hole pad, facing the second quantum bit element; and a second through-hole wiring, electrically connected to the second through-hole pad, wherein the second through-hole pad is closer to the second quantum bit element than the second through-hole wiring, and wherein the second quantum bit element may be arranged between the readout cavity structure and the storage cavity structure.

[0016] The bus chip may further include a high-frequency resonator disposed between the first qubit chip and the second qubit chip, wherein both the first qubit element and the second qubit element may be coupled to the high-frequency resonator.

[0017] The transmission wiring may be electrically connected to the high-frequency resonator, wherein both ends of the high-frequency resonator may be electrically connected to the first through-wiring and the second through-wiring, respectively.

[0018] The bus chip, the first quantum bit chip, the second quantum bit chip, the readout cavity structure and the storage cavity structure can be arranged in a lower sub-quantum computing device, wherein the quantum computing device may also include: in an upper sub-quantum computing device arranged on the lower sub-quantum computing device, another bus chip having the configuration of the bus chip, another first quantum bit chip and a second quantum bit chip having corresponding configurations of the first quantum bit chip and the second quantum bit chip, another readout cavity structure having the configuration of the readout cavity structure, and another storage cavity structure having the configuration of the storage cavity structure, and wherein the lower sub-quantum computing device can be connected to the upper sub-quantum computing device via a connecting line.

[0019] Each of the lower sub-quantum computing device and the upper sub-quantum computing device may include a corresponding high-frequency resonator configured to form quantum entanglement between all quantum bits of the lower sub-quantum computing device and the upper sub-quantum computing device.

[0020] The quantum computing device may further include: a bus chip, arranged between the readout cavity structure and the storage cavity structure.

[0021] The quantum computing device may further include a bus chip, wherein the bus chip may be arranged adjacent to an outward-facing sidewall of the readout cavity structure, the first quantum bit element may be configured between an inward-facing sidewall of the readout cavity structure and an inward-facing sidewall of the storage cavity structure, and the bus chip may be spatially distant from the first quantum bit element.

[0022] The quantum computing device may also include a second quantum bit chip separated from the first quantum bit chip, wherein the second quantum bit chip may include a second quantum bit element, the second quantum bit element is arranged between the inward-facing side wall of the readout cavity structure and the inward-facing side wall of the storage cavity structure, and is spatially away from the bus chip, and wherein the second quantum bit chip may further include: a second readout antenna, arranged in the readout cavity structure; and a second storage antenna, arranged in the storage cavity structure.

[0023] The first qubit chip and the second qubit chip may include corresponding through-wiring configured to provide electrical contact from the bus chip to corresponding through-pads of the first qubit chip and the second qubit chip, and the corresponding through-pads may be configured to capacitively couple with corresponding superconducting material patterns of the first qubit element and the second qubit element.

[0024] The quantum computing device may further include a first connector coupled to the first readout antenna, wherein the first connector may be configured to be inserted into the readout cavity structure.

[0025] The first connector and the first readout antenna may face each other.

[0026] The readout cavity structure and the storage cavity structure may include superconducting material.

[0027] The first readout antenna can extend toward the first quantum bit element so that a portion of the first readout antenna is disposed between the readout cavity structure and the storage cavity structure, and the first storage antenna can extend toward the first quantum bit element so that a portion of the first storage antenna is disposed between the readout cavity structure and the storage cavity structure.

[0028] The quantum computing device may further include: a shielding film surrounding the first quantum bit chip between the readout cavity structure and the storage cavity structure, and the shielding film may include a superconducting material.

[0029] In one general aspect, a quantum computing device includes: a bus chip extending along a first direction; a storage cavity structure spaced apart from the bus chip in a second direction intersecting the first direction; a readout cavity structure disposed between the bus chip and the storage cavity structure; and a plurality of quantum bit chips sequentially arranged on the bus chip along the first direction, wherein the plurality of quantum bit chips respectively extend into the storage cavity structure along the second direction, including respectively extending through the readout cavity structure, the plurality of quantum bit chips each including: a corresponding readout antenna disposed in the readout cavity structure; a corresponding storage antenna disposed in the storage cavity structure; and a corresponding quantum bit element disposed between the corresponding readout antenna and the corresponding storage antenna, the bus chip including a plurality of high-frequency resonators respectively disposed between the plurality of quantum bit chips, and each of the corresponding quantum bit elements is coupled to a corresponding high-frequency resonator among the plurality of high-frequency resonators.

[0030] The readout cavity structure may include a plurality of readout cavities arranged along a first direction, the storage cavity structure may include a plurality of storage cavities arranged along a first direction, the corresponding readout antennas may be respectively arranged in the plurality of readout cavities, the corresponding storage antennas may be respectively arranged in the plurality of storage cavities, wherein, in each of the plurality of quantum bit chips, the corresponding readout antenna and the corresponding quantum bit element may be electrically connected to each other, and wherein, in each of the plurality of quantum bit chips, the corresponding storage antenna and the corresponding quantum bit element may be electrically connected to each other.

[0031] The quantum computing device may further include respective connectors coupled to respective readout antennas, wherein the respective connectors may each be configured to be inserted into the readout cavity structure to be inserted into a corresponding readout cavity of the plurality of readout cavities.

[0032] Each of the plurality of qubit chips may include: a through wiring coupled to a corresponding qubit element; and a connecting wiring arranged between the through wiring and a corresponding high-frequency resonator among the plurality of high-frequency resonators and configured to electrically connect the through wiring to the corresponding high-frequency resonator.

[0033] For each of the plurality of qubit chips, the connection wiring may extend from a corresponding region on the bus chip along the second direction to a corresponding region between the readout cavity structure and the storage cavity structure.

[0034] The bus chip may further include: a connecting pad; a transmission pad facing the connecting pad; and a transmission wiring arranged between the transmission pad and a high-frequency resonator among the multiple high-frequency resonators, wherein the transmission wiring can be electrically connected to the transmission pad, the high-frequency resonator and the through wiring corresponding to the quantum bit chip among the multiple quantum bit chips.

[0035] The corresponding quantum bit element can be arranged between the readout cavity structure and the storage cavity structure.

[0036] The quantum computing device may also include: an internal shielding film surrounding each of the multiple quantum bit chips between the readout cavity structure and the storage cavity structure; and an external shielding film, for each quantum bit chip in the multiple quantum bit chips, the external shielding film jointly surrounding the bus chip and each quantum bit chip in the multiple quantum bit chips, wherein the internal shielding film and the external shielding film may include superconducting materials.

[0037] In one general aspect, a quantum computing device includes a lower sub-quantum computing device, an upper sub-quantum computing device, and a connecting line, wherein the lower sub-quantum computing device includes: a first readout cavity structure and a first storage cavity structure, respectively extending along a first direction and spaced apart from each other in a second direction intersecting the first direction; and a plurality of first qubit chips, each of which is arranged in the second direction; the upper sub-quantum computing device is disposed on the lower sub-quantum computing device and includes: a second readout cavity structure and a second storage cavity structure, respectively extending along the first direction and spaced apart from each other in the second direction; and a plurality of second qubit chips, each of which is arranged in the second direction; and the connecting line is configured to connect the lower sub-quantum computing device to the upper sub-quantum computing device. The computing device is electrically connected to the upper sub-quantum computing device, wherein each of the plurality of first quantum bit chips may include: a first readout antenna, correspondingly arranged in the first readout cavity structure; a first storage antenna, correspondingly arranged in the first storage cavity structure; and a corresponding first quantum bit element, arranged between the correspondingly arranged first readout antenna and the correspondingly arranged first storage antenna, and wherein each of the plurality of second quantum bit chips may include: a second readout antenna, correspondingly arranged in the second readout cavity structure; a second storage antenna, correspondingly arranged in the second storage cavity structure; and a corresponding second quantum bit element, arranged between the correspondingly arranged second readout antenna and the correspondingly arranged second storage antenna.

[0038] The lower sub-quantum computing device may include a first bus chip extending along the first direction between the first readout cavity structure and the first storage cavity structure, and the upper sub-quantum computing device may include a second bus chip extending along the first direction between the second readout cavity structure and the second storage cavity structure, the first bus chip may include: a first connection pad; a first transmission pad facing the first connection pad; and a first transmission wiring electrically connected to the first transmission pad, the second bus chip may include: a second connection pad; a second transmission pad facing the second connection pad; and a second transmission wiring electrically connected to the second transmission pad, wherein the connection line may electrically connect the first connection pad with the second connection pad.

[0039] The lower sub-quantum computing device may include a first bus chip, which extends along the first direction and is away from the first readout cavity structure and the first storage cavity structure in the second direction. The upper sub-quantum computing device may include a second bus chip, which extends along the first direction and is away from the second readout cavity structure and the second storage cavity structure in the second direction. The first bus chip may include: a first connecting pad; a first transmission pad facing the first connecting pad; and a first transmission wiring that can be electrically connected to the first transmission pad. The second bus chip may include: a second connecting pad; a second transmission pad facing the second connecting pad; and a second transmission wiring that is electrically connected to the second transmission pad, and the connecting line can electrically connect the first connecting pad with the second connecting pad.

[0040] The connecting lines may include a conductive material.

[0041] The quantum computing device may further include an interlayer shielding film disposed between the lower sub-quantum computing device and the upper sub-quantum computing device, wherein the interlayer shielding film may include a superconducting material.

[0042] Other features and aspects will become apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and other aspects, features and advantages of some embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0044] Figure 1 is a perspective view of a quantum computing device according to one or more embodiments;

[0045] Figure 2 yes Figure 1 A plan view of a quantum computing device;

[0046] Figure 3 It is along Figure 1 A cross-sectional view of a quantum computing device taken along line II';

[0047] Figure 4 It is along Figure 1 A cross-sectional view of a quantum computing device taken along line II-II';

[0048] Figure 5 is a perspective view of a quantum computing device according to one or more embodiments;

[0049] Figure 6 yes Figure 5 A plan view of a quantum computing device;

[0050] Figure 7 It is along Figure 6A cross-sectional view of a quantum computing device taken along line III-III′;

[0051] Figure 8 is a perspective view of a quantum computing device according to one or more embodiments;

[0052] Figure 9 is a perspective view of a quantum computing device according to one or more embodiments;

[0053] Figure 10 yes Figure 9 A plan view of a quantum computing device;

[0054] Figure 11 It is along Figure 9 A cross-sectional view of a quantum computing device taken along line IV-IV′;

[0055] Figure 12 It is along Figure 9 A cross-sectional view of a quantum computing device taken along line V-V';

[0056] Figure 13 is a perspective view of a quantum computing device according to one or more embodiments;

[0057] Figure 14 yes Figure 13 A plan view of a quantum computing device;

[0058] Figure 15 It is along Figure 14 A cross-sectional view of a quantum computing device taken along line VI-VI'; and

[0059] Figure 16 is a perspective view of a quantum computing device according to one or more embodiments. DETAILED DESCRIPTION

[0060] The following detailed description is provided to help the reader gain a comprehensive understanding of the methods, devices and / or systems described herein. However, after understanding the disclosure of this application, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be apparent.

[0061] For example, the order of operations described herein is merely exemplary and is not limited to those operations set forth herein, but may be significantly changed after understanding the disclosure of this application, except for operations that must be performed in a certain order. In addition, descriptions of features understood in the art after understanding the disclosure of this application may be omitted for clarity and brevity.

[0062] Reference will now be made in detail to the embodiments, examples of which are shown in the accompanying drawings, wherein like reference numerals denote like elements throughout and the size of each component in the drawings may be exaggerated for clarity and brevity of description. In this regard, one or more embodiments may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiments are described below solely with reference to the accompanying drawings to illustrate various aspects of this specification. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of..." modify the entire list of elements when following a list of elements, rather than modifying the individual elements in the list.

[0063] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as that commonly understood by those skilled in the art after understanding the disclosure of this application. Terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as in the context of the relevant technology and the disclosure of this application, and should not be interpreted as ideal or overly formal meanings unless explicitly defined as such herein.

[0064] Throughout the description of the embodiments, when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or may be electrically connected or coupled to the other element with intervening elements interposed therebetween. The terms "include" and / or "comprising" or "having" and / or "containing" when used in this specification specify the presence of the recited elements, but do not preclude the presence or addition of one or more other elements.

[0065] The terms used herein are only used to describe various examples and are not used to limit the present disclosure. Unless the context clearly indicates otherwise, the articles "a", "an" and "the" are also intended to include plural forms. The terms "include", "comprise" and "have" indicate the presence of the described features, numbers, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements and / or combinations thereof. Hereinafter, what is described as "on" or "above" may include not only directly contacting above, but also non-contacting above, and what is described as "below" or "below" may include not only directly contacting below, but also non-contacting below.

[0066] Although terms such as "first", "second", "third" may be used herein to describe various members, components, regions, layers or parts, these members, components, regions, layers or parts should not be limited by these terms. On the contrary, these terms are only used to distinguish one member, component, region, layer or part from another member, component, region, layer or part. Therefore, without departing from the teachings of the examples, the first member, component, region, layer or part mentioned in the examples described herein may also be referred to as the second member, component, region, layer or part. In this article, it should be noted that the use of the term "may" with respect to an example or embodiment (for example, with respect to what an example or embodiment may include or implement) means that there is at least one example or embodiment in which such feature is included or implemented, and all examples and embodiments are not limited thereto.

[0067] With respect to one or more embodiments described below, various types of qubits are available, including qubits using superconductors (i.e., superconducting qubits), which can potentially be easily manufactured using semiconductor or integrated circuit technology. For example, one or more embodiments can provide a quantum computing device or system with high structural scalability.

[0068] Figure 1 is a perspective view of a quantum computing device according to one or more embodiments. Figure 2 yes Figure 1 A plan view of a quantum computing device. Figure 3 It is along Figure 1 A cross-sectional view of a quantum computing device taken along line II'. Figure 4 It is along Figure 1 Cross-sectional view of a quantum computing device taken along line II-II'.

[0069] refer to Figures 1 to 4, the quantum computing device (or system) 11 may include a bus chip 100, a qubit chip 200, a readout cavity structure 310, a storage cavity structure 410, and an internal shielding film 500. The bus chip 100 may include a bus board 110, a connection pad 120, a transmission pad 130, and a transmission wiring 140. The bus chip 100 may provide a signal received from outside the quantum computing device 11 to the qubit chip 200. For example, the signal received from the outside may be received at the connection pad 120 and provided to the qubit chip 200 through, for example, corresponding interactions between the connection pad 120 and the transmission pad 130, between the transmission pad 130 and the transmission wiring 140, and between the transmission wiring 140 and the qubit chip 200. In an example, the bus board 110 may extend along a first direction (e.g., the first direction DR1 shown), which is different from a second direction (e.g., the second direction DR2) along which the qubit chip 200 extends. The bus board 110 may include an insulating material. For example, bus plate 110 may include a silicon (Si) plate or a sapphire plate. Connection pads 120 may include a superconducting material. For example, as a non-limiting example, connection pads 120 may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0070] The transmission pad 130 may be spaced apart from the connection pad 120 in the first direction DR1, and one end or other portion of the transmission pad 130 may face one end or other portion of the connection pad 120. The transmission pad 130 may thus be configured to be capacitively coupled with the connection pad 120. For example, the end or other portion of the transmission pad 130 may have a length in the second direction DR2 that is substantially the same as the length of the end or other portion of the connection pad 120 in the second direction DR2. As a non-limiting example, the first direction DR1 and the second direction DR2 may be perpendicular to each other. In such an example, and as Figure 2 As shown, the length of the end portion or other portion of the transmission pad 130 in the second direction DR2 can be equal to the length of the end portion or other portion of the connection pad 120 in the second direction DR2, while the length of the connection pad 120 in the first direction DR1 can be substantially greater than the length of the transmission pad 130 in the first direction DR1. The transmission pad 130 may include a superconducting material. For example, as a non-limiting example, the transmission pad 130 may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0071] The transmission wiring 140 may extend from the transmission pad 130 along the first direction DR1. For example, the transmission wiring 140 may be electrically connected to the transmission pad 130. The transmission wiring 140 may directly contact the transmission pad 130. For example, the transmission wiring 140 and the transmission pad 130 may be connected to each other without an interface therebetween. The transmission wiring 140 may include a superconducting material. For example, as a non-limiting example, the transmission wiring 140 may include aluminum (Al), niobium (Nb), indium (In), and combinations thereof.

[0072] As a non-limiting example, the qubit chip 200 may have a through-pad 252, and the transmission wiring 140 may interact with the through-pad 252. The through-pad 252 may be configured to interact (e.g., capacitively couple) with the Josephson junction represented by the qubit element 240. Furthermore, in an example where the quantum computing device includes multiple qubit chips 200, each disposed relative to one bus chip 100, the one bus chip 100 may further include, for example, multiple high-frequency resonators 150, each electrically connected to or interacting with the corresponding transmission wiring 140, such that the corresponding high-frequency electromagnetic signals generated by the high-frequency resonators 150 may control the formation of quantum entanglement between the corresponding multiple qubits of the multiple qubit chips 200. In an alternative example, as a non-limiting example, the multiple high-frequency resonators 150 may be disposed on multiple corresponding bus chips 100 corresponding to the multiple qubit chips 200. Furthermore, in an example, the quantum computing device may be a quantum computing device or system comprising a plurality of quantum computing devices, wherein each quantum computing device comprises such a plurality of quantum bit chips 200. For example, the following relative to Figures 1 to 4 and further relative to Figures 5 to 16 This example of a quantum computing device or system is further explained in more detail.

[0073] Therefore, the qubit chip 200 may include a qubit board 210, a readout antenna 222, a storage antenna 224, a qubit element 240, a readout wiring 232, a storage wiring 234, a through wiring 250, and a through pad 252. Figures 1 to 4As shown, in an example, a qubit board 210 can be disposed on the bus chip 100. For example, the qubit board 210 can extend along a second direction DR2, e.g., extending beyond one or more sides of the bus chip 100 along the second direction DR2. From the perspective of a third direction DR3 that is different from the first direction DR1 and the second direction DR2, the qubit board 210 can intersect the bus chip 100. For example, when the first direction DR1 and the second direction DR2 are different directions in the same horizontal plane, as a non-limiting example, the third direction DR3 can be a vertical direction, and thus, the qubit board 210 can vertically overlap the bus chip 100. The qubit board 210 can include a first end 210A and an opposing second end 210B spaced apart from each other in the second direction DR2. From the perspective of the third direction DR3, the first end 210A and the second end 210B of the qubit board 210 can be spaced apart from each other, with the bus chip 100 disposed therebetween, e.g., with the bus chip 100 extending along an exemplary centerline of the qubit board 210 in the first direction DR1. The qubit board 210 may include an insulating material. For example, the qubit board 210 may include a silicon (Si) board or a sapphire board.

[0074] The readout antenna 222 can be disposed on the first end 210A of the qubit board 210. For example, the readout antenna 222 can extend from the first end 210A of the qubit board 210 to the second end 210B, for example, to the exemplary readout wiring 232. The readout antenna 222 can be capacitively coupled to the readout connector 320 described in more detail below. The readout antenna 222 can be configured to receive a high frequency signal provided from the readout connector 320 and to send a high frequency signal to the readout connector 320, for example, to be operated to receive a high frequency signal or to send a high frequency signal. The readout antenna 222 can include a superconducting material. For example, as a non-limiting example, the readout antenna 222 can include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0075] The storage antenna 224 can be disposed on the second end 210B of the qubit board 210. For example, the storage antenna 224 can extend from the second end 210B to the first end 210A, for example, to the exemplary storage wiring 234. The storage antenna 224 can be capacitively coupled to the storage connector 220 described below. The storage antenna 224 can be configured to receive a high-frequency signal provided from the storage connector 220 and to send a high-frequency signal to the storage connector 220, for example, to be operated to receive a high-frequency signal or to send a high-frequency signal. The storage antenna 224 can be disposed in a storage cavity 412 described in more detail below to increase the coherent state cycle duration of the qubit element 240 and to perform unified operation. The storage antenna 224 may include a superconducting material. For example, as a non-limiting example, the storage antenna 224 may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0076] As described above, the qubit element 240 can be set on the qubit board 210. The qubit element 240 can represent an element with nonlinear coupling. For example, the qubit element 240 can represent the exemplary Josephson junction described above. The Josephson junction can include a first superconducting material pattern and a second superconducting material pattern facing each other, and a non-superconducting material pattern (e.g., a dielectric film) or an air gap between the first superconducting material pattern and the second superconducting material pattern. Cooper pairs can tunnel the Josephson junction. Cooper pairs can refer to electron pairs that do not receive resistance within the superconducting material pattern. Therefore, Cooper pairs can represent the same quantum state and can be represented by the same wave function.

[0077] The readout wiring 232 can be arranged between the readout antenna 222 and the quantum bit element 240. The readout wiring 232 can extend along the second direction DR2. The readout wiring 232 can be electrically connected to the readout antenna 222. For example, the readout wiring 232 can directly contact the readout antenna 222. In the example where the quantum bit element 240 includes an exemplary Josephson junction, the readout wiring 232 can be electrically connected to the first superconducting material pattern of the Josephson junction. For example, the readout wiring 232 can directly contact the first superconducting material pattern. In one example, the readout wiring 232, the readout antenna 222, and the first superconducting material pattern can have a single structure. In other words, the readout wiring 232, the readout antenna 222, and the first superconducting material pattern can be connected to each other without an interface therebetween. The readout wiring 232 can include a superconducting material. For example, as a non-limiting example, the readout wiring 232 can include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0078] The storage wiring 234 may be disposed between the storage antenna 224 and the qubit element 240. The storage wiring 234 may extend along the second direction DR2. The storage wiring 234 may be electrically connected to the storage antenna 224. For example, the storage wiring 234 may directly contact the storage antenna 224. In an example where the qubit element 240 includes an exemplary Josephson junction, the storage wiring 234 may be electrically connected to the second superconducting material pattern of the Josephson junction. For example, the storage wiring 234 may directly contact the second superconducting material pattern. In one example, the storage wiring 234, the storage antenna 224, and the second superconducting material pattern may have a single structure. In other words, the storage wiring 234, the storage antenna 224, and the second superconducting material pattern may be connected to each other without an interface therebetween. The storage wiring 234 may include a superconducting material. For example, as a non-limiting example, the storage wiring 234 may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0079] The through wiring 250 may be disposed in the qubit board 210. The through wiring 250 may be disposed below the qubit element 240. For example, the through wiring 250 may overlap the qubit element 240 in the third direction DR3. The through wiring 250 may extend from a position having the same height as the bottom surface of the qubit board 210 along the third direction DR3 to the through pad 252. As described above, in an example, the through wiring 250 may be electrically connected to the transmission wiring 140. For example, the through wiring 250 may penetrate the bottom surface of the qubit board 210 and directly contact the transmission wiring 140. The through wiring 250 may include a superconducting material. For example, as a non-limiting example, the through wiring 250 may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0080] The through pad 252 may be provided on the through wiring 250 or at one end thereof. Thus, the through pad 252 may be electrically connected to the through wiring 250. For example, the through pad 252 may directly contact the upper end of the through wiring 250. In one example, the through pad 252 may have a single structure with the through wiring 250. In other words, the through pad 252 and the through wiring 250 may be connected to each other without an interface therebetween. In an example, as Figure 4As shown, the through-pad 252 may have a larger circumference or diameter than the through-wiring 250, for example, as compared to the respective widths along the third direction DR3. In other words, for example, the width of the through-pad 252 in the first direction DR1 or the second direction DR2 may be greater than the width of the through-wiring 250 in the respective first direction DR1 or the second direction DR2. The through-pad 252 may be proximate to or facing the qubit element 240, for example, configured relative to the qubit element 240 to capacitively couple with the qubit element 240. In examples where the qubit element 240 includes a Josephson junction, the through-pad 252 may be capacitively coupled to the underlying superconducting material pattern of the Josephson junction. The through-pad 252 may include a superconducting material. For example, as non-limiting examples, the through-pad 252 may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0081] The readout cavity structure 310 can surround at least a portion of the first end 210A of the qubit chip 200, for example, the readout cavity structure 310 can encapsulate at least a portion or all of the readout antenna 222. The readout cavity structure 310 can define a readout cavity 312 therein. By way of example only, with the configuration of the readout cavity structure 310, the readout cavity 312 can be configured as an element for reading out qubits and for increasing the duration of the coherent state cycle of the qubits, compared to other configurations without such a readout cavity structure. The readout cavity structure 310 may include a superconducting material. For example, as a non-limiting example, the readout cavity structure 310 may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0082] The readout connector 320 can be disposed in or at the readout cavity structure 310. The readout connector 320 can be configured to access, pass through, or penetrate the readout cavity structure 310, for example, in the following manner: by configuring and encapsulating a portion or all of the readout antenna 222 with the readout cavity structure 310 to maintain or provide the benefit of increasing the duration of the coherent state cycle. Therefore, the readout connector 320 can provide the ability to access the readout cavity 312. For example, the readout connector 320 can be aligned with or facing the readout antenna 222 in the second direction DR2 and can be configured to capacitively couple with the readout antenna 222. Therefore, the readout connector 320 can also be configured to receive an electrical signal from a device external to the quantum computing device 11. The readout connector 320 can be configured to convert the electrical signal into an electromagnetic wave signal having a high frequency.

[0083] The storage cavity structure 410 may be spaced apart from the readout cavity structure 310 in the second direction DR2. For example, the storage cavity structure 410 may surround at least a portion of the second end 210B of the qubit chip 200. For example, the storage cavity structure 410 may encapsulate at least a portion or all of the storage antenna 224. The storage cavity structure 410 may define a storage cavity 412 therein.

[0084] By way of example only, the configuration of storage cavity structure 410 allows storage cavity 412 to be configured as an element for performing unified operations using qubits and for increasing the duration of a coherent state cycle of the qubits, compared to other configurations without such a storage cavity structure. Storage cavity structure 410 may comprise a superconducting material. For example, as a non-limiting example, storage cavity structure 410 may comprise aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0085] The storage connector 220 can be disposed in or at the storage cavity structure 410. The storage connector 220 can be configured to access, pass through, or penetrate the storage cavity structure 410, for example, in the following manner: by configuring and encapsulating a portion or all of the storage antenna 224 with the storage cavity structure 410 to maintain or provide the benefit of increasing the duration of the coherent state period. Therefore, the storage connector 220 can provide the ability to access the storage cavity 412. For example, the storage connector 220 can be aligned with or facing the storage antenna 224 in the second direction DR2, and can be configured to capacitively couple with the storage antenna 224. Therefore, the storage connector 220 can also be configured to receive an electrical signal from a device external to the quantum computing device 11. The storage connector 220 can be configured to convert the electrical signal into an electromagnetic wave signal having a high frequency.

[0086] The internal shielding film 500 can be disposed between the readout cavity structure 310 and the storage cavity structure 410. For example, the internal shielding film 500 can cover a portion of the bus chip 100 and a portion of the qubit chip 200, such as the portion of the qubit chip 200 not covered by the readout cavity structure 310 and the storage cavity structure 410. Thus, the internal shielding film 500 can provide the benefit of shielding the bus chip 100 and the qubit chip 200 from unwanted electromagnetic waves. In one example, the internal shielding film 500 can completely surround or encapsulate the respective portions of the bus chip 100 and the qubit chip 200 between the readout cavity structure 310 and the storage cavity structure 410. For example, the inner shielding film 500 may include a lower inner shielding film 510 and an upper inner shielding film 520, and an additional example may be provided in which the upper inner shielding film 520 is further extended to cover the remaining sides of the qubit chip 200, for example, further extended between adjacent ends of the lower inner shielding film 510 and the upper inner shielding film 520 to completely surround or encapsulate the portion of the qubit chip 200 including the qubit elements 240 and the portion of the bus chip 100 overlapping with the qubit chip 200. In such a non-limiting example, the lower inner shielding film 510 may contact and support the bus chip 100 below the bus chip 100. The shielding films (e.g., the lower inner shielding film 510 and the upper inner shielding film 520) may be or include a superconducting material. For example, as non-limiting examples, the shielding films may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0087] As mentioned above about Figures 1 to 4 And the following about Figures 5 to 16 As discussed, the quantum computing device may include: a bus chip extending along a first direction at least between a readout cavity structure and a storage cavity structure; and a quantum bit chip disposed on the bus chip and extending into the readout cavity structure and into the storage cavity structure.

[0088] In one or more embodiments, such a quantum computing device may include a bus chip and a qubit chip extending in a different second direction, wherein the qubit chip includes a qubit element representing a qubit element formed by a first superconducting material pattern and a second superconducting material pattern, the first superconducting material pattern being connected to an antenna at least partially disposed in a readout cavity structure, and the second superconducting material pattern being connected to another antenna at least partially disposed in a storage cavity structure. The qubit chip may include an electrical connection to the bus chip, the electrical connection being configured to influence the formation of the qubit. For influencing the formation of the qubit, the electrical connection may include through wiring and through pads in the qubit chip, the through wiring and through pads being configured to capacitively couple with the second superconducting material pattern. The remaining portion of the qubit chip including the qubit element and between the readout cavity structure and the storage cavity structure may be encapsulated by an internal shielding film, which may also cover a portion of the bus chip that vertically overlaps with the qubit chip. A portion of the internal shielding film may also support the bus chip. A quantum computing system may include two or more qubit chips, a readout cavity, a storage cavity, and a high-frequency resonator, wherein the high-frequency resonator is used to control the formation of quantum entanglement between corresponding two or more qubits of the two or more qubit chips.

[0089] Therefore, when, for example, the number of qubit chips, readout cavities, and storage cavities is further increased, the above description of quantum computing devices or systems can be further applied to understanding the implementation of various exemplary multi-qubit structures. Other exemplary quantum computing devices or systems with such multi-qubit structures will be described in more detail below. Therefore, various embodiments of the present disclosure can provide quantum computing devices and systems with high structural scalability.

[0090] Figure 5 is a perspective view of a quantum computing device according to one or more embodiments. Figure 6 yes Figure 5 A plan view of a quantum computing device. Figure 7 It is along Figure 6 For simplicity of description, unless otherwise specified, reference is made to Figures 1 to 4 The description given applies to the same reference numerals, and therefore will not be repeated below.

[0091] refer to Figures 5 to 7The quantum computing device (or system) 12 may include a bus chip 100, a plurality of qubit chips 200, a readout cavity structure 310, a storage cavity structure 410, and a plurality of internal shielding films 500. The bus chip 100 may include a bus board 110, a first connection pad 122, a second connection pad 124, a transmission pad 130, a transmission wiring 140, and a high-frequency resonator 150.

[0092] About Figures 1 to 4 The description of the bus board 110, the connection pad 120, the transmission pad 130 and the transmission wiring 140 are respectively applicable to Figures 5 to 7 The bus board 110, the first connection pads 122, the transmission pads 130 and the transmission wiring 140 are described in detail, and therefore will not be described again below.

[0093] As a non-limiting example, the second connection pads 124 may be a bonding area configured to connect / bond to a connection line that connects the bus chip 100 of the quantum computing device 12 to a bus chip of another quantum computing device other than the quantum computing device 12. The second connection pads 124 may include a superconducting material. For example, as a non-limiting example, the second connection pads 124 may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0094] The high-frequency resonators 150 may be respectively arranged between the qubit chips 200. Each high-frequency resonator 150 may include an LC resonator for electromagnetic signals having a high frequency. The high-frequency resonator 150 may include elements and configurations for forming quantum entanglement between the corresponding qubits of the qubit chip 200. The shape, arrangement, or form of each high-frequency resonator 150 is not limited to the shape, arrangement, or form shown. Examples include various shapes, arrangements, and forms of the high-frequency resonators 150, thereby having corresponding LC resonator functions for various electromagnetic signals having a high frequency. The high-frequency resonators 150 may be arranged sequentially along the first direction DR1. The high-frequency resonators 150 may be electrically connected to each other in series. For example, directly adjacent high-frequency resonators 150 may be in direct contact with each other. Directly adjacent corresponding transmission wiring 140 and high-frequency resonators 150 may be electrically connected. For example, directly adjacent corresponding transmission wiring 140 and high-frequency resonators 150 may be in direct contact with each other.

[0095] The qubit chips 200 may be sequentially arranged along the first direction DR1 and respectively disposed between the high frequency resonators 150. In view of the discussion of various aspects of the quantum computing device 12 herein, the above reference Figures 1 to 4 The description of the qubit chip 200 provided is applicable to Figures 5 to 7Each qubit chip 200 is described in detail below, and therefore will not be described again. However, each through-wiring 250 of each qubit chip 200 may be electrically connected to a corresponding adjacent high-frequency resonator 150. For example, each through-wiring 250 may directly contact a region of the bus board 110 that is connected to directly adjacent high-frequency resonators 150.

[0096] In addition, in an example, the readout cavity structure 310 can be configured to provide a plurality of readout cavities 312, wherein corresponding readout antennas 222 are respectively disposed in corresponding readout cavities 312. Figure 5 and Figure 6 The plurality of readout cavities 312 are shown as being arranged in one readout cavity structure 310, but the embodiment is not limited thereto. For example, in other embodiments, the readout cavities 312 may be respectively arranged in a plurality of readout cavity structures.

[0097] The readout connectors 320 may be respectively disposed in or at the readout cavity structure 310. For example, each readout connector 320 may be configured to access, pass through, or penetrate the readout cavity structure 310, such as described above with respect to Figures 1 to 4 Therefore, the readout connectors 320 can each provide access to the corresponding readout cavity 312. The readout connectors 320 can each be aligned with or face the readout antenna 222 extending along the second direction DR2. The readout connectors 320 can each be configured to capacitively couple to the readout antenna 222.

[0098] The storage cavity structure 410 can be configured to provide storage cavities 412, wherein corresponding storage antennas 224 are respectively disposed in corresponding storage cavities 412. Figures 5 and 6 The plurality of storage cavities 412 are shown as being arranged in one storage cavity structure 410, but the embodiment is not limited thereto. For example, in other embodiments, the storage cavities 412 may be respectively arranged in a plurality of storage cavity structures.

[0099] The storage connectors 220 may be respectively disposed in or at the storage cavity structure 410. For example, each storage connector 220 may be configured to access, pass through, or penetrate the storage cavity structure 410, such as described above. Figures 1 to 4 Therefore, the storage connectors 220 can each provide access to the corresponding storage cavity 412. The storage connectors 220 can be respectively aligned with or facing the storage antenna 224 extending along the second direction DR2. The storage connectors 220 can be configured to be capacitively coupled to the storage antenna 224.

[0100] The internal shielding film 500 may be disposed between the readout cavity structure 310 and the storage cavity structure 410. The internal shielding film 500 may cover the qubit chips 200, respectively. The bus chip 100 may extend through the internal shielding film 500. The high frequency resonator 150 may be exposed between the internal shielding films 500. Figures 1 to 4 Further discussion of the shielding example also applies to Figures 5 to 7 Shielding example.

[0101] Quantum entanglement can occur between the quantum bits of the quantum computing device 12.

[0102] Therefore, according to Figures 1 to 7 One or more embodiments and descriptions and the following Figures 8 to 16 As described herein, a quantum computing device or system may include a plurality of qubit chips, readout cavities, and storage cavities arranged along a first direction. A plurality of qubit chips, a plurality of readout cavities, and a plurality of storage cavities are available, and it is noted that the examples are not limited to the brief descriptions herein. Examples include additional or fewer corresponding numbers of qubit chips, readout cavities, and storage cavities. Therefore, various embodiments of the present disclosure may provide quantum computing devices and systems with high structural scalability.

[0103] Figure 8 is a perspective view of a quantum computing device 13 according to one or more embodiments. For simplicity of description, unless otherwise indicated below, the following non-limiting examples are provided. Figures 1 to 7 and Figure 16 The description applies to the same and related reference numerals, and therefore will not be repeated below.

[0104] refer to Figure 8 , the quantum computing device (or system) 13 may include a first sub-quantum computing device 12a, a second sub-quantum computing device 12b, a third sub-quantum computing device 12c, a fourth sub-quantum computing device 12d, a first interlayer shielding film 1110, a second interlayer shielding film 1120, a third interlayer shielding film 1130, a first wire W1, a second wire W2, a third wire W3 and a fourth wire W4.

[0105] Each of the first sub-quantum computing device 12a, the second sub-quantum computing device 12b, the third sub-quantum computing device 12c, and the fourth sub-quantum computing device 12d can be the same as the above reference Figures 5 to 7 The quantum computing device 12 described in the embodiment is the same as or corresponds to any of the embodiments described above. For example, with respect to a multi-qubit device or system, each sub-quantum computing device can be the same as the one described above with respect to Figures 1 to 4The first sub-quantum computing device 12a, the second sub-quantum computing device 12b, the third sub-quantum computing device 12c, and the fourth sub-quantum computing device 12d can be arranged along the third direction DR3. For example, the first sub-quantum computing device 12a, the second sub-quantum computing device 12b, the third sub-quantum computing device 12c, and the fourth sub-quantum computing device 12d can be arranged in a stepped form. From the perspective of the third direction DR3, the first connection pad 122 and the second connection pad 124 of the sub-quantum computing device (e.g., the first sub-quantum computing device 12a) disposed at a lower position can be partially exposed by the step-shifting of the next sub-quantum computing device (e.g., the second sub-quantum computing device 12b) disposed at a higher position.

[0106] The first interlayer shielding film 1110, the second interlayer shielding film 1120, and the third interlayer shielding film 1130 can be disposed between the first sub-quantum computing device 12a, the second sub-quantum computing device 12b, the third sub-quantum computing device 12c, and the fourth sub-quantum computing device 12d. The first interlayer shielding film 1110, the second interlayer shielding film 1120, and the third interlayer shielding film 1130 can be configured to prevent unintended electromagnetic waves from being transmitted and received between any of the first sub-quantum computing device 12a, the second sub-quantum computing device 12b, the third sub-quantum computing device 12c, and the fourth sub-quantum computing device 12d, respectively. The first interlayer shielding film 1110, the second interlayer shielding film 1120, and the third interlayer shielding film 1130 can be or include a superconducting material. For example, as a non-limiting example, the first interlayer shielding film 1110, the second interlayer shielding film 1120, and the third interlayer shielding film 1130 can each include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0107] In this example, the first wire W1 is electrically connected to a high-frequency electrical signal generating device external to the quantum computing device (system) 13 or external to the first, second, third, and fourth quantum computing sub-devices 12a, 12b, 12c, and 12d, and is further connected to the first connection pad 122 of the first quantum computing sub-device 12a to receive the high-frequency electrical signal. The first wire W1 can apply the electrical signal generated by the high-frequency electrical signal generating device to any one of the first and second connection pads 122, 124 of the first quantum computing sub-device 12a.

[0108] The second wire W2 may electrically connect the other of the first and second connection pads 122 and 124 of the first sub-quantum computing device 12a to any one of the first and second connection pads 122 and 124 of the second sub-quantum computing device 12b.

[0109] The third wire W3 may electrically connect the other of the first connection pad 122 and the second connection pad 124 of the second sub-quantum computing device 12b to any one of the first connection pad 122 and the second connection pad 124 of the third sub-quantum computing device 12c.

[0110] The fourth wire W4 may electrically connect the other of the first connection pad 122 and the second connection pad 124 of the third sub-quantum computing device 12c to any one of the first connection pad 122 and the second connection pad 124 of the fourth sub-quantum computing device 12d.

[0111] The second wire W2, the third wire W3, and the fourth wire W4 can provide the electrical signals generated by the high-frequency electrical signal generating device to the second sub-quantum computing device 12b, the third sub-quantum computing device 12c, and the fourth sub-quantum computing device 12d, respectively. The first wire W1, the second wire W2, the third wire W3, and the fourth wire W4 can each include a superconducting material. For example, as a non-limiting example, the first wire W1, the second wire W2, the third wire W3, and the fourth wire W4 can each include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0112] Therefore, according to Figures 1 to 8 One or more embodiments and descriptions and the following Figures 9 to 16 As described herein, quantum entanglement may occur between qubits of a quantum computing device or system including a quantum computing system, which may include, for example, a plurality of quantum computing devices stacked along a third direction. Each of the plurality of quantum computing devices may include a plurality of qubit chips 200, a readout cavity 312, and a storage cavity 412 arranged along a first direction. Although a quantum computing device or system having an exemplary plurality of quantum computing devices is discussed for purposes of illustration, the embodiments are not limited thereto. The number of qubit chips in any one quantum computing device is not limited to the exemplary disclosure herein, the number of qubit chips need not be the same in different steps of the quantum computing device, and the number of steps of the quantum computing device is not limited to the disclosure herein, as there are various examples with various numbers of steps. Thus, one or more embodiments demonstrate examples of quantum computing devices or systems that may provide higher structural scalability.

[0113] Figure 9 is a perspective view of a quantum computing device according to one or more embodiments. Figure 10 yes Figure 9 A plan view of a quantum computing device. Figure 11 It is along Figure 9 Cross-sectional view of a quantum computing device taken along line IV-IV′. Figure 12 It is along Figure 9For simplicity of description, unless otherwise specified, reference is made to Figures 1 to 8 The given description applies to the same or related reference numerals, and therefore will not be repeated below.

[0114] refer to Figures 9 to 12 , the quantum computing device (or system) 21 may include a bus chip 100, a quantum bit chip 200, a readout cavity structure 310, a storage cavity structure 410, an inner shielding film 500, and an outer shielding film 600. For example, the bus chip 100 may have the same Figures 1 to 4 The bus chip 100 may be arranged along a first direction DR1, and the qubit chip 200 may be arranged along a second direction (eg, along a different second direction DR2). However, regarding Figures 9 to 12 The bus chip 100 does not overlap or is not overlapped with the quantum bit chip 200. Figures 9 to 12 In the example, after the readout cavity structure 310 is arranged along the second direction DR2, the bus chip 100 may be arranged along the second direction DR2.

[0115] The qubit chip 200 may include a qubit board 210, a readout antenna 222, a storage antenna 224, a readout wiring 232, a storage wiring 234, a through wiring 250, a through pad 252, and a lower wiring 260. The readout antenna 222, the storage antenna 224, the readout wiring 232, the storage wiring 234, the through wiring 250, and the through pad 252 may be respectively connected to a reference Figures 1 to 4 The readout antenna 222 , the storage antenna 224 , the readout wiring 232 , the storage wiring 234 , the through wiring 250 , and the through pad 252 described are substantially the same.

[0116] and Figures 1 to 4 Similar to the above discussion of the connection of the transmission wiring 140 to the through wiring 250 of the qubit chip 200, Figures 9 to 12 The lower wiring 260 is configured to connect the transmission wiring 140 of the bus chip 100 to the through wiring 250 of the qubit chip 200, for example, due to Figures 9 to 12In the example shown, the bus chip 100 and the qubit elements 240 of the qubit chip 200 are separated, so the lower wiring 260 can be used to connect the transmission wiring 140 to the through wiring 250. For example, the qubit board 210 can extend from the bus chip 100 into the storage cavity 412 in the second direction DR2, wherein one of the two ends of the qubit board 210 in the second direction DR2 can be disposed on the bus chip 100, while the other end can be disposed within the storage cavity 412. The qubit board 210 can be configured to penetrate, for example, a pair of sidewalls facing each other in the readout cavity structure 310 in the second direction DR2. As a non-limiting example, the sidewall of the readout cavity structure 310 facing the bus chip 100 can be a sidewall in which the readout connector 320 is disposed or buried. Although examples herein include, as non-limiting examples, examples of any board or chip penetrating a fully or partially formed cavity structure or shielding film, these examples also include examples in which such a cavity structure or shielding film is formed relative to any existing structure of such board or chip to allow such access or penetration. As another example, examples herein of connectors configured in or at a sidewall or cavity structure may also include connectors buried in the sidewall or cavity structure.

[0117] To connect the transmission wiring 140 to the through wiring 250 of the qubit chip 200, a lower wiring 260 can be disposed below the qubit board 210. For example, the lower wiring 260 can transition or extend along the bottom of the qubit board 210 and, in one example, can be buried within the underside of the qubit board 210, e.g., until the through wiring 250 reaches below the qubit element 240. For example, the lower wiring 260 can extend along the second direction DR2. In an example, the lower wiring 260 can directly contact the transmission wiring 140 and directly contact the through wiring 250.

[0118] The inner shielding film 500 surrounding the qubit chip 200 may be disposed between the readout cavity structure 310 and the storage cavity structure 410. The inner shielding film 500 may be disposed between the readout cavity structure 310 and the storage cavity structure 410. Figures 1 to 4 The inner shielding films 500 described are substantially the same.

[0119] An external shielding film 600 can be provided from the upper and lower sides of the readout cavity structure 310, for example, facing the bus chip 100, to cover the bus chip 100 and the qubit chip 200. The external shielding film 600 can surround the bus chip 100 and the qubit chip 200, for example, covering the corresponding upper and lower surfaces. In one example, the external shielding film 600 can also completely cover the end of the qubit chip 200, for example, thereby encapsulating the bus chip 100 and the entire portion of the qubit chip 200 that extends beyond the readout cavity structure 310. The external shielding film 600 may include a superconducting material. For example, as a non-limiting example, the external shielding film 600 may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0120] Therefore, according to Figures 1 to 12 One or more embodiments and descriptions and the following about Figures 13 to 16 As discussed above, a quantum computing device may include: a bus chip extending in a first direction; and a qubit chip disposed on the bus chip, extending in a second direction and reaching into a readout cavity structure and into a storage cavity structure. Similar to the above description regarding the arrangement of the bus chip relative to the readout cavity structure, an example includes: a bus chip arranged relative to a readout cavity structure relative to the readout cavity structure (but compared to the reference Figures 1 to 4 The present invention also includes a discussion of a quantum bit chip disposed on the other side of the readout cavity structure, and a qubit chip disposed on a bus chip and connected to the readout cavity structure and the storage cavity structure. Examples include multiple qubit chips, readout cavities, and storage cavities, thereby providing a quantum computing device or system with high structural scalability.

[0121] Figure 13 is a perspective view of a quantum computing device according to one or more embodiments. Figure 14 yes Figure 13 A plan view of a quantum computing device. Figure 15 It is along Figure 14 For simplicity of description, unless otherwise specified, reference is made to Figures 9 to 12 The description given applies to the same or related reference numerals, and thus will not be repeated below.

[0122] refer to Figures 13 to 15, the quantum computing device (or system) 22 may include a bus chip 100, a quantum bit chip 200, a readout cavity structure 310, a storage cavity structure 410, an inner shielding film 500, and an outer shielding film 600. The bus chip 100 may include a bus board 110, a first connection pad 122, a second connection pad 124, a transmission pad 130, a transmission wiring 140, and a high-frequency resonator 150. The bus board 110, the first connection pad 122, the transmission pad 130, and the transmission wiring 140 may be respectively connected to the reference Figures 9 to 12 The bus board 110, connection pads 120, transmission pads 130 and transmission wiring 140 described are substantially the same and are identical to those of FIG. Figures 5 to 8 The bus chip 100 is related, considering Figures 9 to 12 and the following disclosures, Figures 5 to 8 The description is also applicable.

[0123] As a non-limiting example, the second connection pads 124 may be a bonding area configured to connect / bond to a connection line that connects the bus chip 100 of the quantum computing device 22 to a bus chip of another quantum computing device other than the quantum computing device 22. The second connection pads 124 may include a superconducting material. For example, as a non-limiting example, the second connection pads 124 may include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0124] The high-frequency resonators 150 may be respectively arranged between the qubit chips 200. Each high-frequency resonator 150 may include an LC resonator for electromagnetic signals having a high frequency. The high-frequency resonator 150 may include elements and configurations for forming quantum entanglement between the corresponding qubits of the qubit chip 200. The shape, arrangement, or form of each high-frequency resonator 150 is not limited to the shape, arrangement, or form shown. Examples include various shapes, arrangements, and forms of the high-frequency resonators 150, thereby having corresponding LC resonator functions for various electromagnetic signals having a high frequency. The high-frequency resonators 150 may be arranged sequentially along the first direction DR1. The high-frequency resonators 150 may be electrically connected to each other in series. For example, directly adjacent high-frequency resonators 150 may be in direct contact with each other. Directly adjacent corresponding transmission wiring 140 and high-frequency resonators 150 may be electrically connected. For example, directly adjacent corresponding transmission wiring 140 and high-frequency resonators 150 may be in direct contact with each other.

[0125] The qubit chips 200 may be sequentially arranged along the first direction DR1 and respectively disposed between the high frequency resonators 150. Each qubit chip 200 may include a qubit board 210, a readout antenna 222, a storage antenna 224, a readout wiring 232, a storage wiring 234, a through wiring 250, a through pad 252, and a lower wiring 260. Each qubit chip 200 may be connected to a reference Figures 9 to 12 The qubit chip 200 described above is substantially the same. The lower wiring 260 can be electrically connected to the high-frequency resonator 150. For example, the lower wiring 260 can directly contact the area to which the high-frequency resonators 150 that are directly adjacent to each other are connected. The adjacent connections and the following discussion of the readout cavity structure, readout cavity, readout connector, storage cavity structure, storage cavity and storage connector are also the same as the above discussion of Figures 5 to 7 Description about Figures 13 to 15 The same reference numeral features in FIG. 1 also incorporate this description.

[0126] The readout cavity structure 310 may include corresponding readout cavities 312. The readout antennas 222 may be respectively disposed in the readout cavities 312. Although an example is shown in which the readout cavity 312 is disposed in one readout cavity structure 310, the example is not limited thereto. In another example, the readout cavities 312 may be respectively disposed in a plurality of readout cavity structures.

[0127] The readout connectors 320 can be respectively arranged in or at the readout cavity structure 310. For example, each readout connector 320 can be configured to access, pass through or penetrate the readout cavity structure 310, such as discussed above. Therefore, the readout connectors 320 can provide the ability to access the corresponding readout cavity 312. The readout connectors 320 can be spaced apart from the quantum bit board 210 in the third direction DR3. For example, the readout connectors 320 can be slightly misaligned with the readout antenna 222 in the third direction DR3. However, the position and spacing of the readout connectors 320 are not limited in this article. The readout connectors 320 can be capacitively coupled to the readout antenna 222 respectively.

[0128] The storage cavity structure 410 may include a storage cavity 412. The storage antennas 224 may be respectively disposed in the storage cavity 412. Although an example is shown in which the storage cavity 412 is disposed in one storage cavity structure 410, the example is not limited thereto. For example, in another embodiment, the storage cavity 412 may be respectively disposed in a plurality of storage cavity structures.

[0129] The storage connectors 220 can be respectively disposed in or at the storage cavity structure 410. For example, each storage connector 220 can be configured to access, pass through, or penetrate the storage cavity structure 410, such as discussed above. Thus, each storage connector 220 can provide access to a corresponding storage cavity 412. The storage connectors 220 can respectively face or align with the storage antenna 224 in the second direction DR2. The storage connectors 220 can respectively be capacitively coupled to the storage antenna 224.

[0130] The inner shielding film 500 may be disposed between the readout cavity structure 310 and the storage cavity structure 410. The inner shielding film 500 may cover the qubit chips 200, respectively.

[0131] The outer shielding films 600 may be provided to cover the qubit chips 200. For example, the outer shielding films 600 may completely cover the ends of the qubit chips 200. The bus chip 100 may extend through the outer shielding films 600. The high-frequency resonator 150 may be exposed between the outer shielding films 600.

[0132] Quantum entanglement can occur between the quantum bits of the quantum computing device 22.

[0133] Therefore, according to Figures 1 to 15 One or more embodiments and descriptions and the following Figure 16 As described above, a quantum computing device may include a plurality of qubit chips, a readout cavity, and a storage cavity arranged along a first direction. A plurality of qubit chips, a plurality of readout cavities, and a plurality of storage cavities may be provided, but the examples of the present disclosure are not limited thereto. In various examples, various numbers of qubit chips, readout cavities, and storage cavities are available. Therefore, various embodiments of the present disclosure may provide a quantum computing device or system with high structural scalability.

[0134] Figure 16 is a perspective view of a quantum computing device according to one or more embodiments. For simplicity of description, unless otherwise indicated, reference is made to Figures 8 to 15 The description given applies to the same or related reference numerals, and thus will not be repeated below.

[0135] refer to Figure 16 , the quantum computing device (or system) 23 may include a first sub-quantum computing device 22a, a second sub-quantum computing device 22b, a third sub-quantum computing device 22c, a fourth sub-quantum computing device 22d, a first interlayer shielding film 1110, a second interlayer shielding film 1120, a third interlayer shielding film 1130, a first wire W1, a second wire W2, a third wire W3, and a fourth wire W4. Any one or all of the first sub-quantum computing device 22a, the second sub-quantum computing device 22b, the third sub-quantum computing device 22c, and the fourth sub-quantum computing device 22d may be respectively connected to the reference Figures 13 to 15 The quantum computing device 22 described is substantially the same, wherein the tiering or stacking of the quantum computing devices and the connections between the quantum computing devices are also the same. Figure 8 In view of the following, the disclosure of Figure 8 Description.

[0136] The first sub-quantum computing device 22a, the second sub-quantum computing device 22b, the third sub-quantum computing device 22c, and the fourth sub-quantum computing device 22d can be stacked along the third direction DR3. The first sub-quantum computing device 22a, the second sub-quantum computing device 22b, the third sub-quantum computing device 22c, and the fourth sub-quantum computing device 22d can be arranged in a stepped or stacked form. From the perspective of the third direction DR3, the first connection pad 122 and the second connection pad 124 of the sub-quantum computing device (e.g., the first sub-quantum computing device 22a) disposed at a lower position can be partially exposed by the sub-quantum computing device (e.g., the second sub-quantum computing device 22b) stacked or disposed at a higher position.

[0137] The first interlayer shielding film 1110, the second interlayer shielding film 1120, and the third interlayer shielding film 1130 can be disposed between the first sub-quantum computing device 22a, the second sub-quantum computing device 22b, the third sub-quantum computing device 22c, and the fourth sub-quantum computing device 22d. The first interlayer shielding film 1110, the second interlayer shielding film 1120, and the third interlayer shielding film 1130 can be configured to prevent unintended electromagnetic waves from being transmitted and received between any of the first sub-quantum computing device 22a, the second sub-quantum computing device 22b, the third sub-quantum computing device 22c, and the fourth sub-quantum computing device 22d, respectively. The first interlayer shielding film 1110, the second interlayer shielding film 1120, and the third interlayer shielding film 1130 can be or include a superconducting material. For example, as a non-limiting example, the first interlayer shielding film 1110, the second interlayer shielding film 1120, and the third interlayer shielding film 1130 can each include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0138] In the example, the first line W1 is electrically connected to a high-frequency electric signal generating device outside the quantum computing device (system) 23 or outside the first sub-quantum computing device 22a, the second sub-quantum computing device 22b, the third sub-quantum computing device 22c, and the fourth sub-quantum computing device 22d, and is also connected to the first connection pad 122 of the first sub-quantum computing device 22a, thereby receiving a high-frequency electric signal. The first line W1 can apply the electric signal generated by the high-frequency electric signal generating device to any one of the first connection pad 122 and the second connection pad 124 of the first sub-quantum computing device 22a. Figures 1 to 7 and Figures 9 to 15 Examples of quantum computing devices and systems may similarly receive high-frequency electrical signals from high-frequency generating devices, such as those described herein. Figures 1 to 4 and Figures 9 to 12 The connection pad 120 or the Figures 5 to 7 and Figures 13 to 15 As various non-limiting examples, the first connection pad 122 of Figures 1 to 7 and Figures 9 to 15 A high frequency generation device is provided externally to any quantum computing device or system.

[0139] The second wire W2 may electrically connect the other of the first and second connection pads 122 and 124 of the first sub-quantum computing device 22 a to any one of the first and second connection pads 122 and 124 of the second sub-quantum computing device 22 b .

[0140] The third wire W3 may electrically connect the other of the first connection pad 122 and the second connection pad 124 of the second sub-quantum computing device 22 b to any one of the first connection pad 122 and the second connection pad 124 of the third sub-quantum computing device 22 c .

[0141] The fourth wire W4 may electrically connect the other of the first connection pad 122 and the second connection pad 124 of the third sub-quantum computing device 22 c to any one of the first connection pad 122 and the second connection pad 124 of the fourth sub-quantum computing device 22 d .

[0142] The second wire W2, the third wire W3, and the fourth wire W4 can provide the electrical signals generated by the high-frequency electrical signal generating device to the second sub-quantum computing device 22b, the third sub-quantum computing device 22c, and the fourth sub-quantum computing device 22d, respectively. The first wire W1, the second wire W2, the third wire W3, and the fourth wire W4 can include superconducting materials. For example, as a non-limiting example, the first wire W1, the second wire W2, the third wire W3, and the fourth wire W4 can each include aluminum (Al), niobium (Nb), indium (In), or a combination thereof.

[0143] Quantum entanglement can occur between quantum bits in a quantum computing device 23.

[0144] As mentioned above about Figures 1 to 16 As discussed, a quantum computing system may include, for example, a plurality of quantum computing devices stacked along a third direction. Each of the plurality of quantum computing devices may include a plurality of qubit chips, a readout cavity, and a storage cavity arranged along a first direction. Although a plurality of quantum computing devices are discussed for illustration, the embodiments are not limited thereto. The number of qubit chips in any one stacked quantum computing device is not limited to the exemplary disclosure herein, the number of qubit chips need not be the same in different steps of the quantum computing device, and the number of steps of the quantum computing device is not limited to the disclosure herein, as there are various examples with various numbers of steps. Thus, one or more embodiments demonstrate examples that can provide a quantum computing system or device with higher structural scalability.

[0145] Although this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and detail may be made to these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be considered merely descriptive and not for purposes of limitation. The description of features or aspects in each example should be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order and / or if components in the described systems, architectures, devices, or assemblies are combined in different ways and / or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is not limited by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as included in this disclosure.

Claims

1. A quantum computing device comprising: the first quantum bit chip; a readout cavity structure surrounding a first end portion of the first qubit chip; as well as a storage cavity structure surrounding the second end of the first quantum bit chip; Wherein, the first quantum bit chip includes: a first readout antenna, disposed in the readout cavity structure; a first storage antenna, disposed in the storage cavity structure; and a first qubit element disposed between the first readout antenna and the first storage antenna, and The first quantum bit element is arranged between the readout cavity structure and the storage cavity structure, and the readout cavity structure is spaced apart from the storage cavity structure.

2. The quantum computing device according to claim 1, wherein: The first quantum bit chip further includes: a first through pad, facing the first qubit element; and a first through-wiring electrically connected to the first through-pad, and The first through pad is closer to the first quantum bit element than the first through wiring.

3. The quantum computing device according to claim 2, further comprising: A bus chip is provided between the readout cavity structure and the storage cavity structure, Wherein, the bus chip includes: a connection pad configured to receive an electrical signal from outside the bus chip; a transmission pad facing the connection pad; and a transmission wiring electrically connected to the transmission pad, The transmission wiring is electrically connected to the first through wiring.

4. The quantum computing device according to claim 3, wherein: The transmission pad is configured to capacitively couple with the connection pad with respect to the received electrical signal.

5. The quantum computing device according to claim 3, wherein: The first quantum bit chip further includes: a first readout wiring electrically connecting the first readout antenna to the first qubit element; a first storage wiring electrically connecting the first storage antenna to the first qubit element; and a first qubit board, disposed on the bus chip, and The first quantum bit element, the first readout antenna, the first readout wiring, the first storage antenna and the first storage wiring are arranged on the first quantum bit board.

6. The quantum computing device according to claim 5, in, The first qubit element includes a first superconducting material pattern, a dielectric film, and a second superconducting material pattern stacked sequentially, and The first superconducting material pattern, the dielectric film and the second superconducting material pattern form a Josephson junction.

7. The quantum computing device according to claim 6, in, the first superconducting material pattern is electrically connected to the first readout antenna through the first readout wiring, and The second superconducting material pattern is electrically connected to the first storage antenna through the first storage wiring.

8. The quantum computing device according to claim 6, wherein: The first through pad is configured to be capacitively coupled with the second superconducting material pattern.

9. The quantum computing device of claim 3 , further comprising a second qubit chip spaced apart from the first qubit chip. in, The second quantum bit chip further comprises: a second readout antenna disposed in the readout cavity structure; a second storage antenna, disposed in the storage cavity structure; a second quantum bit element, disposed between the second readout antenna and the second storage antenna; a second through pad facing the second qubit element; and a second through-wiring electrically connected to the second through-pad, wherein the second through-pad is closer to the second qubit element than the second through-wiring, and Wherein, the second quantum bit element is arranged between the readout cavity structure and the storage cavity structure.

10. The quantum computing device according to claim 9, in, The bus chip further includes a high-frequency resonator disposed between the first qubit chip and the second qubit chip, and Wherein, the first quantum bit element and the second quantum bit element are both coupled to the high-frequency resonator.

11. The quantum computing device according to claim 10, in, The transmission wiring is electrically connected to the high frequency resonator, and The two ends of the high-frequency resonator are electrically connected to the first through-wiring and the second through-wiring, respectively.

12. The quantum computing device according to claim 9, in, The bus chip, the first quantum bit chip, the second quantum bit chip, the readout cavity structure, and the storage cavity structure are arranged in a lower sub-quantum computing device. The quantum computing device further includes: in an upper sub-quantum computing device disposed on the lower sub-quantum computing device, another bus chip having the configuration of the bus chip, another first quantum bit chip and a second quantum bit chip having corresponding configurations of the first quantum bit chip and the second quantum bit chip, another readout cavity structure having the configuration of the readout cavity structure, and another storage cavity structure having the configuration of the storage cavity structure, and The lower sub-quantum computing device is connected to the upper sub-quantum computing device via a connecting line.

13. The quantum computing device according to claim 12, in, Each of the lower sub-quantum computing device and the upper sub-quantum computing device includes a corresponding high-frequency resonator, which is configured to form quantum entanglement between all quantum bits of the lower sub-quantum computing device and the upper sub-quantum computing device.

14. The quantum computing device of claim 1 , further comprising: A bus chip is arranged between the readout cavity structure and the storage cavity structure.

15. The quantum computing device according to claim 1, further comprising a bus chip, wherein: The bus chip is arranged adjacent to the outward-facing sidewall of the readout cavity structure, the first qubit element is configured between the inward-facing sidewall of the readout cavity structure and the inward-facing sidewall of the storage cavity structure, and the bus chip is spatially distant from the first qubit element.

16. The quantum computing device of claim 15 , further comprising a second qubit chip spaced apart from the first qubit chip, the second qubit chip comprising a second qubit element, the second qubit element being disposed between an interior-facing sidewall of the readout cavity structure and an interior-facing sidewall of the storage cavity structure and spatially remote from the bus chip. in, The second quantum bit chip further comprises: a second readout antenna disposed in the readout cavity structure; and The second storage antenna is arranged in the storage cavity structure.

17. The quantum computing device of claim 16, wherein: the first qubit chip and the second qubit chip include respective through-wiring configured to provide electrical contact from the bus chip to respective through-pads of the first qubit chip and the second qubit chip, and Wherein, the respective through pads are configured to capacitively couple with the respective superconducting material patterns of the first qubit element and the second qubit element.

18. The quantum computing device of claim 1 , further comprising a first connector coupled to the first readout antenna, in, The first connector is configured to be inserted into the readout cavity structure.

19. The quantum computing device of claim 18, wherein: The first connector and the first readout antenna face each other.

20. The quantum computing device of claim 1, wherein: The readout cavity structure and the storage cavity structure include superconducting materials.

21. The quantum computing device according to claim 1, in, The first readout antenna extends toward the first qubit element such that a portion of the first readout antenna is disposed between the readout cavity structure and the storage cavity structure, and The first storage antenna extends toward the first quantum bit element, so that a portion of the first storage antenna is disposed between the readout cavity structure and the storage cavity structure.

22. The quantum computing device of claim 1 , further comprising: a shielding film surrounding the first quantum bit chip between the readout cavity structure and the storage cavity structure, Wherein, the shielding film comprises a superconducting material.

23. A quantum computing device comprising: A bus chip extending along a first direction; a storage cavity structure spaced apart from the bus chip in a second direction intersecting the first direction; a readout cavity structure, disposed between the bus chip and the storage cavity structure; as well as A plurality of quantum bit chips are sequentially arranged on the bus chip along the first direction, wherein the plurality of quantum bit chips extend into the storage cavity structure along the second direction, respectively, including extending through the readout cavity structure, respectively; The plurality of quantum bit chips each include: a corresponding readout antenna disposed in the readout cavity structure; a corresponding storage antenna disposed in the storage cavity structure; and a corresponding quantum bit element disposed between the corresponding readout antenna and the corresponding storage antenna. The bus chip includes a plurality of high-frequency resonators respectively arranged between the plurality of quantum bit chips, and Each of the corresponding quantum bit elements is coupled to a corresponding high-frequency resonator in the plurality of high-frequency resonators.

24. The quantum computing device according to claim 23, in, The readout cavity structure includes a plurality of readout cavities arranged along the first direction, Wherein, the storage cavity structure includes a plurality of storage cavities arranged along the first direction, wherein the corresponding readout antennas are respectively arranged in the plurality of readout cavities, Wherein, the corresponding storage antennas are respectively arranged in the plurality of storage cavities, wherein, in each of the plurality of qubit chips, the corresponding readout antenna and the corresponding qubit element are electrically connected to each other, and Wherein, in each of the plurality of quantum bit chips, the corresponding storage antenna and the corresponding quantum bit element are electrically connected to each other.

25. The quantum computing device of claim 24, further comprising a respective connector coupled to the respective readout antenna, in, The respective connectors are each configured to be inserted into the sensing cavity structure to be inserted into a corresponding sensing cavity of the plurality of sensing cavities.

26. The quantum computing device of claim 23, wherein: Each of the plurality of qubit chips comprises: Through wiring, coupled to corresponding quantum bit elements; and A connection wiring is provided between the through-wiring and a corresponding high-frequency resonator among the plurality of high-frequency resonators and is configured to electrically connect the through-wiring to the corresponding high-frequency resonator.

27. The quantum computing device of claim 26, wherein: For each of the plurality of qubit chips, the connection wiring extends from a corresponding region on the bus chip along the second direction to a corresponding region between the readout cavity structure and the storage cavity structure.

28. The quantum computing device of claim 26, wherein: The bus chip further includes: Connect the pads; a transmission pad facing the connection pad; and a transmission wiring provided between the transmission pad and a high-frequency resonator among the plurality of high-frequency resonators, and The transmission wiring is electrically connected to the transmission pad, the high-frequency resonator, and the through wiring corresponding to the quantum bit chip among the plurality of quantum bit chips.

29. The quantum computing device of claim 23, wherein: The corresponding quantum bit element is arranged between the readout cavity structure and the storage cavity structure.

30. The quantum computing device of claim 23, further comprising: an inner shielding film surrounding each of the plurality of qubit chips between the readout cavity structure and the storage cavity structure; as well as an external shielding film, for each of the plurality of qubit chips, the external shielding film jointly surrounding the bus chip and each of the plurality of qubit chips, Wherein, the inner shielding film and the outer shielding film include superconducting materials.

31. A quantum computing device comprising: The lower quantum computing device includes: a first sensing cavity structure and a first storage cavity structure, each extending along a first direction and spaced apart from each other in a second direction intersecting the first direction; and a plurality of first qubit chips, each of the first qubit chips being arranged in the second direction; An upper sub-quantum computing device is provided on the lower sub-quantum computing device and includes: a second readout cavity structure and a second storage cavity structure, respectively extending along the first direction and spaced apart from each other in the second direction; and a plurality of second qubit chips, each second qubit chip being arranged in the second direction; and a connecting line configured to electrically connect the lower sub-quantum computing device to the upper sub-quantum computing device, Each of the plurality of first qubit chips comprises: a first readout antenna, correspondingly disposed in the first readout cavity structure; a first storage antenna, correspondingly disposed in the first storage cavity structure; and a corresponding first qubit element, disposed between the correspondingly disposed first readout antenna and the correspondingly disposed first storage antenna, and In which, each of the multiple second quantum bit chips includes: a second readout antenna, which is correspondingly arranged in the second readout cavity structure; a second storage antenna, which is correspondingly arranged in the second storage cavity structure; and a corresponding second quantum bit element, which is arranged between the correspondingly arranged second readout antenna and the correspondingly arranged second storage antenna.

32. The quantum computing device of claim 31 , in, The lower sub-quantum computing device includes a first bus chip extending along the first direction between the first readout cavity structure and the first storage cavity structure, The upper sub-quantum computing device includes a second bus chip extending along the first direction between the second readout cavity structure and the second storage cavity structure. Wherein, the first bus chip includes: a first connection pad; a first transmission pad facing the first connection pad; and a first transmission wiring electrically connected to the first transmission pad, Wherein, the second bus chip includes: a second connection pad; a second transmission pad facing the second connection pad; and a second transmission wiring electrically connected to the second transmission pad, and The connecting wire electrically connects the first connecting pad and the second connecting pad.

33. The quantum computing device of claim 31 , in, The lower sub-quantum computing device includes a first bus chip, the first bus chip extending along the first direction and away from the first readout cavity structure and the first storage cavity structure in the second direction, The upper sub-quantum computing device includes a second bus chip, which extends along the first direction and is away from the second readout cavity structure and the second storage cavity structure in the second direction. Wherein, the first bus chip includes: a first connection pad; a first transmission pad facing the first connection pad; and a first transmission wiring electrically connected to the first transmission pad, Wherein, the second bus chip includes: a second connection pad; a second transmission pad facing the second connection pad; and a second transmission wiring electrically connected to the second transmission pad, and The connecting wire electrically connects the first connecting pad and the second connecting pad.

34. The quantum computing device of claim 31 , wherein: The connecting wire comprises a superconducting material.

35. The quantum computing device according to claim 31 , further comprising an interlayer shielding film provided between the lower sub-quantum computing device and the upper sub-quantum computing device. in, The interlayer shielding film includes a superconducting material.

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