Patterning method for semiconductor devices and structures resulting therefrom

Abstract

Embodiments of the invention provide a semiconductor device and a method of forming a semiconductor device. The method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, forming a second mask layer over the plurality of spacers, and patterning the second mask layer to form a first opening, wherein, in a plan view, a major axis of the opening extends in a direction perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form a second opening in the target layer, and filling the second opening in the target layer with a conductive material.

Description

[0001] This application is a divisional application of patent application number 201811355245.0, filed on November 14, 2018, entitled “Patterning method for semiconductor devices and structures resulting therefrom.” TECHNICAL FIELD

[0002] Embodiments of the present invention generally relate to the field of semiconductor, and more particularly, to semiconductor devices and methods of forming the same. BACKGROUND

[0003] As semiconductor devices continue to scale down, various processing techniques (e.g., photolithography) are adapted to allow for the fabrication of devices of ever- decreasing size. For example, as the density of gates increases, the manufacturing process of various components in the device (e.g., interconnect components above) are adapted to be compatible with the scaling of the device components as a whole. However, as the semiconductor process scales down to increasingly smaller process windows, the fabrication of these devices has approached and even exceeded the theoretical limits of photolithography equipment. As semiconductor devices continue to scale down, the desired spacing (i.e., pitch) between elements of the device is less than the pitch that can be fabricated using conventional optical masks and photolithography equipment. SUMMARY

[0004] According to one aspect of the present invention, a method of forming a semiconductor device is provided, comprising: forming a first mask layer over a target layer; forming a plurality of spacers over the first mask layer; forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, wherein, in plan view, a major axis of the opening extends in a direction perpendicular to a major axis of a spacer of the plurality of spacers; depositing a sacrificial material in the opening; patterning the sacrificial material; etching the first mask layer using the plurality of spacers and the patterned sacrificial material; etching the target layer using the etched first mask layer to form a second opening in the target layer; and filling the second opening located in the target layer with a conductive material.

[0005] According to another aspect of the present application, there is provided a method of forming a semiconductor device, comprising: forming a first cap layer over a second cap layer, the second cap layer being over a first mask layer, the first mask layer being over a dielectric layer; patterning an opening in the first cap layer, the opening having a target width; filling the opening with a first material to form a masking element; forming a second mask layer over the first cap layer, and patterning the second mask layer to form a first mask, the first mask comprising a plurality of openings; etching the first cap layer and the second cap layer using the first mask and the masking element, wherein the masking element prevents a portion of the second cap layer from being etched; patterning the first mask layer through the second cap layer to form a second mask; patterning the dielectric layer through the second mask, the patterning of the dielectric layer exposing a conductive feature located underneath the dielectric layer; and forming a wire in the dielectric layer, the wire contacting the conductive feature.

[0006] According to yet another aspect of the present application, there is provided a semiconductor device, comprising: a dielectric layer; a power rail extending through the dielectric layer, wherein sidewalls of the power rail comprise one or more kinks; a first set of interconnect lines located on a first side of the power rail and in the dielectric layer; and a second set of interconnect lines located on the first side of the power rail and in the dielectric layer, wherein a first kink of the one or more kinks is positioned laterally between the first set of interconnect lines and the second set of interconnect lines. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the application can be best understood from the following detailed description when read with the accompanying drawings. It is noted that, in accordance with the standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various components can be arbitrarily increased or decreased for the sake of a discussion of clarity.

[0008] FIG. 1 , FIG. 2 , FIG. 3 , FIG. 4 , FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 , FIG. 9 , FIG. 10 and FIG. 11 show cross-sectional views of various intermediate stages of manufacturing a semiconductor device according to some embodiments.

[0009] FIG. 12A , FIG. 12B , FIG. 13A , FIG. 13B , FIG. 14A , FIG. 14B , FIG. 15A ,FIG. 15B 、 FIG. 16A 、 FIG. 16B 、 FIG. 17A 、 FIG. 17B 、 FIG. 18A 、 FIG. 18B 、 FIG. 19A 、 FIG. 19B 、 FIG. 20A 、 FIG. 20B 、 FIG. 21A 、 FIG. 21B 、 FIG. 22A and FIG. 22B show cross-sectional and plan views of various intermediate stages in the fabrication of a semiconductor device according to some embodiments.

[0010] FIG. 23 and FIG. 24 show cross-sectional views of various intermediate stages in the fabrication of a semiconductor device according to some embodiments.

[0011] FIG. 25A and FIG. 25B show cross-sectional and plan views of intermediate stages in the fabrication of a semiconductor device according to some embodiments.

[0012] FIG. 26 is a flowchart of a method according to some embodiments.

[0013] FIG. 27 、 FIG. 28 、 FIG. 29 and FIG. 30 show plan views of a semiconductor device according to some embodiments.

[0014] FIG. 31 is a block diagram of a processing system according to some embodiments.

[0015] FIG. 32 is a plan view of a semiconductor device according to some embodiments.

[0016] FIG. 33A-FIG. 33B is a plan view of a virtual layout and a semiconductor device according to some embodiments.

[0017] FIG. 34 to FIG. 43 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device according to some embodiments.

[0018] FIG. 44A 、 FIG. 44B 、 FIG. 45A and FIG. 45B are cross-sectional and plan views of intermediate stages in the fabrication of a semiconductor device according to some embodiments.

[0019] FIG. 46 and FIG. 47 are cross-sectional views of intermediate stages in the fabrication of a semiconductor device according to some embodiments.

[0020] FIG. 48 is a flowchart of a method according to some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and the second component form in direct contact, and where additional components can form between them such that the first component and the second component do not form in direct contact. Furthermore, the application can be implemented in various examples with reference to the figures. The repeated use of references to the structure as being "one example" or "an example" does not mean that the same element is necessarily referred to in each instance. This phrase is used merely as shorthand notation indicating that at least one example of the element is shown. Likewise, the use of "another" example does not mean that a series of related examples is necessarily referred to.

[0022] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0023] A semiconductor device and a method of forming a semiconductor device are provided in accordance with some embodiments. In some embodiments, a patterning process is implemented to pattern lines located in a target layer of a semiconductor device. A dielectric layer is patterned using photolithography to form spacers. A patterned sacrificial material (sometimes referred to as a reverse material) is formed over the spacers. The patterned sacrificial material can include an inorganic material and is formed by patterning openings in a mask (openings that expose selected regions of the patterned lines) and depositing the inorganic material in the openings using a suitable film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. After the sacrificial material is formed, the sacrificial material is patterned by forming openings in the sacrificial material. The spacers and the sacrificial material are used to pattern an underlying mask layer, which in turn is used to pattern the target layer. The underlying target layer can be a layer for various purposes. For example, the target layer can be a low-k dielectric layer, where the mask layer is used to pattern openings. Subsequently, a conductive material can be filled in the openings of the low-k dielectric layer to define interconnect lines, where the interconnect lines are defined with line cuts by the patterned sacrificial material. The interconnect lines can have a fine pitch, and / or one or more line cuts can have a fine pitch, and / or the interconnect lines and line cuts with fine pitch can be formed using a simplified patterning process. For example, a single patterning process can be used to pattern the target layer to form fine pitch interconnect lines with one or more line cuts to pattern the target layer. Because the target layer is patterned in a single patterning process, and / or using the simplified process described herein, improved accuracy of the pattern can be achieved and manufacturing costs can be reduced. For example, if the target layer 102 is etched in two or more different processes, the actual pattern etched into the target layer 102 can differ from the desired pattern due to difficulties in accurately aligning the etch mask with the desired portions to be etched. Improved accuracy is possible when etching the target layer 102 using a single etch step and / or a simplified patterning process as described herein. In this way, multiple interconnect lines with multiple line cuts can be formed with the same size or substantially the same size, which allows for better control of the resistance of the interconnect lines. Additionally, manufacturing costs can be reduced due to the simplified process.

[0024] In some embodiments, the processes described herein can be used to form power rails and metal island structures with narrower power rails, metal islands with substantially similar sizes and / or groups of metal islands that are well aligned with other groups of metal islands. Due to the processes used to form the power rails and metal islands, kinks can be present in the formed power rails. The kinks can reduce the reliability of contacts to the power rails. To avoid the kinks, contacts to the power rails can be formed outside of a "contactless region" where kinks can be present at the edges of the power rails.

[0025] In some embodiments, an interconnect line can have one or more line cuts, where a line cut can refer to a physical separation between two adjacent portions of an interconnect line. A line cut can be formed after the interconnect line is formed by physically removing portions of the interconnect line. Alternatively, the interconnect line can be formed in a manner such that line cuts exist after the interconnect line is formed due to the process used to form the interconnect line. In some devices, multiple adjacent interconnect lines can have line cuts in the same location in a middle portion of the interconnect line. The line cuts can be made in a manner that leaves behind unwanted portions of one or more interconnect lines after the line cut. For example, line cuts can be formed in the same location in a group of adjacent interconnect lines. The interconnect lines in the group of adjacent interconnect lines can be connected to a via, where the via is located at a greater distance than a minimum distance from a line edge formed by the line cut, and the portion of the interconnect line located between the line edge formed by the line cut and the via can not be necessary or desirable in a particular design. It can be disadvantageous to not remove unnecessary or undesirable interconnect lines from a semiconductor device, for example, because the RC performance of the device can be reduced, and / or the spacing consumed by the unnecessary line edge can undesirably increase the size or footprint of the semiconductor device. In some embodiments, line ends can be removed from the semiconductor device being formed, thereby improving the RC performance of the semiconductor device, and / or reducing the size or footprint required by the device.

[0026] FIG. 1 to FIG. 25B Cross-sectional and / or plan views of intermediate stages of forming features in a target layer 102 located on a semiconductor device 100 are shown in accordance with some example embodiments. The target layer 102 is a layer in which patterns will be formed in accordance with embodiments of the present application. In some embodiments, the semiconductor device 100 is processed as part of a larger wafer. In such embodiments, after various features of the semiconductor device 100 (e.g., active devices, interconnect structures, etc.) are formed, a singulation process can be applied to scribe regions located between individual dies of the wafer in order to separate (also referred to as singulate) individual semiconductor dies from the wafer.

[0027] In some embodiments, the target layer 102 is an intermetallic dielectric (IMD) layer. In such embodiments, the target layer 102 includes a low-k dielectric material, where, for example, the low-k dielectric material has a dielectric constant (k-value) of less than 3.8, less than about 3.0, or less than about 2.5. In alternative embodiments, the target layer 102 is an IMD layer that includes a high-k dielectric material having a k-value of greater than 3.8. Openings can be patterned in the target layer 102 using an embodiment process, and wires and / or vias can be formed in the openings, as described below.

[0028] In some embodiments, the target layer 102 is a semiconductor substrate. The semiconductor substrate can be formed of a semiconductor material such as silicon, silicon germanium, etc. In some embodiments, the semiconductor substrate is a crystalline semiconductor substrate such as a crystalline silicon substrate, a crystalline silicon carbon substrate, a crystalline silicon germanium substrate, a group III-V compound semiconductor substrate, etc. The semiconductor substrate can be patterned with the embodiment processes, and subsequent process steps can be used to form shallow trench isolation (STI) regions in the substrate. Semiconductor fins can protrude from between the formed STI regions. Source / drain regions can be formed in the semiconductor fins, and a gate dielectric layer and a gate electrode layer can be formed over the channel region of the fins, forming a semiconductor device such as a fin field effect transistor (finFET).

[0029] In some embodiments, the target layer 102 is a conductive layer such as a metal layer or a polysilicon layer that is blanket deposited. The embodiment patterning processes can be applied to the target layer 102 to pattern semiconductor gates and / or dummy gates of a finFET. By using the embodiment processes to pattern the conductive target layer 102, the spacing between adjacent gates can be reduced and the gate density can be increased.

[0030] In FIG. 1 In some embodiments, the target layer 102 can be formed over a semiconductor substrate 104. The semiconductor substrate 104 can be formed of a semiconductor material such as a doped or undoped silicon or a semiconductor-on-insulator (SOI) substrate having an active layer. The semiconductor substrate 104 can include other semiconductor materials including germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates such as a multilayer substrate or a graded substrate can also be used. Devices (not shown) such as transistors, diodes, capacitors, resistors, etc. can be formed in and / or on the active surface of the semiconductor substrate 104. In other embodiments where the target layer 102 is a semiconductor substrate for forming a finFET, the semiconductor substrate 104 can be omitted.

[0031] Although FIG. 1The target layer 102 is shown in physical contact with the semiconductor substrate 104, but any number of intervening layers can be disposed between the target layer 102 and the semiconductor substrate 104. Such intervening layers can include an interlayer dielectric (ILD) layer (including a low-k dielectric and having a contact plug formed therein), other IMD layers (having wires and / or vias formed therein), one or more intervening layers (e.g., etch stop layers, adhesion layers, etc.), combinations thereof, etc. For example, an optional etch stop layer (not shown) can be disposed directly below the target layer 102. The etch stop layer can serve as a stop for an etch process subsequently performed on the target layer 102. The material and process used to form the etch stop layer depends on the material of the target layer 102. In some embodiments, the etch stop layer can be formed of silicon nitride, SiON, SiCON, SiC, SiOC, SiC x N y , SiO x , other dielectrics, combinations thereof, etc., and can be formed by plasma enhanced chemical vapor deposition (PECVD), low pressure CVD (LPCVD), plasma vapor deposition (PVD), etc. Other materials and processes can also be used.

[0032] The film stack also includes an anti-reflective coating (ARC) 106 formed over the target layer 102. The ARC 106 helps exposure and focus of an overlying photoresist layer (discussed below) during patterning of the photoresist layer. In some embodiments, the ARC 106 can be formed of SiON, silicon carbide, a material doped with oxygen (O) and nitrogen (N), etc. In some embodiments, the ARC 106 is substantially free of nitrogen and can be formed of an oxide. In such embodiments, the ARC 106 can also be referred to as a nitrogen-free ARC (NFARC). In some embodiments, the material composition of the ARC 106 can be selected to prevent reflection. The ARC 106 can be formed by plasma enhanced chemical vapor deposition (PECVD), high density plasma (HDP) deposition, etc. Other processes and materials can be used.

[0033] The film stack also includes a hard mask layer 108 formed over the ARC 106 and the target layer 102. The hard mask layer 108 can be formed of a material including metals (e.g., titanium nitride, titanium, tantalum nitride, tantalum, doped metal carbides (e.g., tungsten carbide), etc.) and / or non-metals (e.g., silicon nitride, boron nitride, silicon carbide, etc.). In some embodiments, the material composition of the hard mask layer 108 can be determined to provide a high etch selectivity with respect to, for example, the ARC 106 and / or the target layer 102. The hard mask layer 108 can be formed by PVD, radio frequency PVD (RF PVD), atomic layer deposition (ALD), etc. Other processes and materials can be used. In a subsequent processing step, a pattern is formed on the hard mask layer 108 using an embodiment patterning process. The hard mask layer 108 then serves as an etch mask for etching the target layer 102, where the pattern of the hard mask layer 108 is transferred to the target layer 102.

[0034] In some embodiments, the film stack also includes a dielectric layer 110 formed over the hard mask layer 108. In subsequent processing, the dielectric layer 110 can be used to form a plurality of spacers, which are used to pattern the target layer (see FIG. 18A to FIG. 18B and FIG. 19A to FIG. 19B ). The dielectric layer 110 can be formed of silicon oxide such as borophosphosilicate ethyl orthosilicate (BPTEOS) or undoped ethyl orthosilicate (TEOS) oxide, and can be formed by CVD, ALD, spin-on, etc. Other processes and materials can be used.

[0035] A three-layer masking layer 120 is formed on the film stack above the dielectric layer 110. The three-layer masking layer 120 includes a bottom layer 112, a middle layer 114 above the bottom layer 112, and an upper layer 116 above the middle layer 114. The upper layer 116 can be formed of a photoresist (e.g., a light-sensitive material) including an organic material, and can be a positive or negative photoresist material. In some embodiments, the bottom layer 112 can be formed of a polymer. The bottom layer 112 can also be a bottom anti-reflective coating (BARC) layer or an ash removable dielectric (ARD) layer (such as amorphous carbon). The middle layer 114 can include an inorganic material, where the inorganic material can be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), etc. The middle layer 114 has a high etch selectivity with respect to the upper layer 116 and the bottom layer 112. The individual layers of the three-layer masking layer 120 can be sequentially blanket deposited using, for example, a spin-on process. Other processes and materials can be used. Although a three-layer masking layer 120 is discussed herein, in other embodiments, the three-layer masking layer 120 can actually be a single-layer masking layer or a two-layer masking layer (e.g., including only the bottom layer 112 and the upper layer 116 without the middle layer 114). The type of masking layer used (e.g., single-layer masking layer, two-layer masking layer, or three-layer masking layer) can depend on the lithography process used to pattern the dielectric layer 110. For example, in an extreme ultraviolet (EUV) lithography process, a single-layer masking layer or a two-layer masking layer can be used.

[0036] In some embodiments, the upper layer 116 is patterned using a lithography process. Subsequently, the upper layer 116 is used as an etch mask for patterning the middle layer 114 (see FIG. 2 ). The middle layer 114 is then used as an etch mask for patterning the bottom layer 112, and then the bottom layer 112 is used to pattern the dielectric layer 110 (see FIG. 3 ). It has been observed that by using a three-layer photoresist (e.g., the three-layer photoresist 120) to etch a target layer (e.g., the dielectric layer 110), an increased precision of fine pitch patterns can be achieved in the target layer (e.g., the dielectric layer 110).

[0037] The upper layer 116 is patterned to form openings 122 therein using any suitable photolithography process. As an example of patterning openings 122 in the upper layer 116, a photomask (not shown) can be disposed over the upper layer 116. The upper layer 116 can then be exposed to a beam of radiation including ultraviolet (UV) or excimer laser light, such as a 248 nm beam from a krypton fluoride (KrF) excimer laser, a 193 nm beam from an argon fluoride (ArF) excimer laser, or a 157 nm beam from an F2excimer laser, etc., while the photomask masks regions of the upper layer 116. The exposure of the top photoresist layer can be implemented using an immersion lithography system or an extreme ultraviolet lithography system to improve resolution and reduce the minimum achievable pitch. One or more exposure steps can be implemented. A bake or cure operation can be implemented to harden the upper layer 116, and a developer can be used to remove exposed or unexposed portions of the upper layer 116 depending on whether a positive or negative resist is used. The openings 122 can have a strip shape in plan view (not shown). The minimum width Wl of the openings 122 can be about 19 nm. Other widths of the openings 122 can also be considered.

[0038] Referring to FIG. 2 After patterning the upper layer 116, the pattern of the upper layer 116 can be transferred to the middle layer 114 in an etching process. The etching process is anisotropic such that the openings 122 in the upper layer 116 extend through the middle layer 114 and have the same (or slightly smaller) dimensions in the middle layer 114 as they have in the upper layer 116. As part of etching the middle layer 114, the upper layer 116 can be consumed. FIG. 2 The resulting structure is shown in

[0039] As shown in FIG. 3 An etching process can be implemented to transfer the pattern of the middle layer 114 to the bottom layer 112, extending the openings 122 through the bottom layer 112. The etching process of the bottom layer 112 is anisotropic such that the openings 122 in the middle layer 114 extend through the bottom layer 112 and have substantially the same (or slightly smaller) dimensions in the bottom layer 112 as in the middle layer 114. As part of etching the bottom layer 112, the upper layer 116 can be consumed.

[0040] In FIG. 4In some embodiments, the etch process is anisotropic such that the openings 122 in the bottom layer 112 extend through the dielectric layer 110 and have the same (or slightly smaller) size in the dielectric layer 110 as they have in the bottom layer 112. Thus, the remaining portions of the dielectric layer 110 (e.g., portions of the dielectric layer 110 between the openings 122) define spacers 124. During etching of the dielectric layer 110, the intermediate layer 114 is consumed, and possibly at least partially consumed, is the bottom layer 112. In embodiments where the bottom layer 112 is not completely consumed when the dielectric layer 110 is etched, a gray-etch process can be implemented to remove remaining residue of the bottom layer 112. In FIG. 5 The remaining structure is depicted in FIG. 1C. In plan view, the gaps between the spacers 124 define areas where conductive lines will be formed in the target layer 102. The spacers 124 can have a line pitch PI greater than or equal to 30 nm.

[0041] In FIG. 6 In some embodiments, the bottom layer 126 can be a polymer, a bottom anti-reflective coating (BARC), or a gray-etchable dielectric (ARD) layer, among others. The intermediate layer 128 can include an inorganic material, where the inorganic material can be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), among others. The intermediate layer 128 can have a high etch selectivity with respect to the upper layer 132 and the bottom layer 126. The various layers of the masking layer 130 can be sequentially blanket deposited using, for example, a spin-on process. Other processes and materials can be used. Although a three-layer masking layer 130 is discussed herein, in other embodiments, the masking layer 130 can be a single-layer masking layer or a two-layer masking layer (e.g., including only the bottom layer 126 and the upper layer 132 without the intermediate layer 128).

[0042] In FIG. 7 In some embodiments, the upper layer 132 is patterned using a lithography process to form openings 134. Subsequently, the upper layer 132 is used as an etch mask for patterning the intermediate layer 128 (see FIG. 1E). The intermediate layer 128 is then used as an etch mask for patterning the bottom layer 126, and then the bottom layer 126 is used to define the periphery of the subsequently formed sacrificial material (see FIG. 1F). FIG. 7 ). The intermediate layer 128 is then used as an etch mask for patterning the bottom layer 126, and then the bottom layer 126 is used to define the periphery of the subsequently formed sacrificial material (see FIG. 1F). FIG. 10-FIG. 11 ).

[0043] Reference is made to FIG. 7The upper layer 132 can be patterned using any suitable photolithography process to form openings 134 therein. As an example of patterning the openings 134 in the upper layer 132, a photomask (not shown) can be disposed over the upper layer 132. The upper layer 132 can then be exposed to a beam of radiation comprising ultraviolet (UV) or excimer laser light, such as a 248 nm beam from a krypton fluoride (KrF) excimer laser, a 193 nm beam from an argon fluoride (ArF) excimer laser, or a 157 nm beam from an F2 excimer laser, etc., while the photomask masks regions of the upper layer 132. The exposure of the top photoresist layer can be implemented using an immersion lithography system or an extreme ultraviolet lithography system to improve resolution and reduce the minimum achievable pitch. A single exposure step or multiple exposure steps can be implemented. A bake or cure operation can be implemented to harden the upper layer 132, and a developer can be used to remove exposed or unexposed portions of the upper layer 132 depending on whether a positive or negative resist is used.

[0044] Referring to FIG. 8 After the upper layer 132 is patterned, the pattern of the upper layer 132 can be transferred to the middle layer 128 in an etching process. The etching process is anisotropic such that the openings 134 in the upper layer 132 extend through the middle layer 128 and have substantially the same (or slightly smaller) size in the middle layer 128 as they do in the upper layer 132. As part of etching the middle layer 128, the upper layer 132 can be consumed. FIG. 8 The resulting structure is shown in

[0045] As shown in FIG. 9 The etching process can be implemented to transfer the pattern of the middle layer 128 to the bottom layer 126 such that the openings 134 extend through the bottom layer 126. The etching process of the bottom layer 126 is anisotropic such that the openings 134 in the middle layer 128 extend through the bottom layer 126 and have substantially the same (or slightly smaller) size in the bottom layer 126 as they do in the middle layer 128. As part of etching the bottom layer 126, the upper layer 132 can be consumed. After the bottom layer 126 is patterned, the openings 134 can expose one or more spacers 124 formed by the remaining dielectric layer 110. The openings 134 can also expose portions of the hardmask layer 108 that extend between adjacent spacers 124.

[0046] In FIG. 10 A sacrificial material 136 is formed in the openings 134. As described in more detail below, the sacrificial material 136 will be further patterned in subsequent processing, and the patterned sacrificial material can be used to define a line cut between two adjacent wires to be formed in the target layer 102. Although FIG. 10The description describes the formation of sacrificial material in a single opening 134; however, in some embodiments, more than one opening 134 may be present, and sacrificial material may be formed in more than one opening 134 (e.g., to form additional line cuts). In some embodiments, sacrificial material 136 may be deposited in an opening 134 located above spacer 124 and above an exposed portion of hard mask layer 108. Sacrificial material may be formed along the sidewalls of intermediate layer 128 and along its top surface (or, if intermediate layer 128 has been removed, along the top surface of bottom layer 126).

[0047] In various embodiments, the sacrificial material 136 comprises an inorganic material. For example, the sacrificial material 136 may be an inorganic oxide such as titanium oxide, tantalum oxide, silicon oxide, etc. Other materials such as silicon nitride, silicon carbide, metal nitride, metal oxide, etc., may be used. The sacrificial material 136 may be selected at least in part considering the etch selectivity between the material of the sacrificial material 136 and the materials used to form the hard mask layer 108, the intermediate layer 128, and / or the underlayer 126. In some embodiments, the inorganic material is a low-temperature oxide (LTO). As used herein, the term "LTO" refers to an oxide deposited using a relatively low process temperature (e.g., 200°C or lower). It has been observed that in this embodiment, the low-temperature deposition process does not cause significant damage to the underlayer 126. Other materials may also be used.

[0048] The sacrificial material 136 can be formed using semiconductor film deposition processes such as CVD, PVD, ALD, spin coating, etc. Other processes can also be used. The semiconductor film deposition process can be a conformal process, in which a semiconductor film is formed on the sidewalls and bottom surface of the opening 134. As deposition continues, portions of the sacrificial material 136 located on the opposite sidewalls of the opening 134 merge, thereby filling the opening. As a result of the semiconductor film deposition process, the top surface of the sacrificial material 136 may not be flat.

[0049] Next, in FIG. 11 In this process, a planarization process (e.g., chemical mechanical polishing (CMP), dry etching, combinations thereof, etc.) is performed to remove excess portions of the sacrificial material 136 located outside the opening 134. In some embodiments (not shown), the planarization process may continue until the intermediate layer 128 and the portions of the sacrificial material adjacent to the intermediate layer 128 are also removed.

[0050] Next, an ashing process is used to remove the intermediate layer 128 and the bottom layer 126. After removing the bottom layer 126, sacrificial material 136 remains and covers portions of the spacers 124 and the hard mask layer 108. Removing the bottom layer 126 exposes portions of the other spacers 124 and the hard mask layer 108. FIG. 12A (Cross-section view) and FIG. 12BThe remaining structure is shown in plan view. FIG. 12A A cross-sectional view along FIG. 12B line A-A' shown in plan view of FIG. 12B In plan view, the sacrificial material 136 forms a rectangle having a major axis extending in a direction substantially perpendicular to the direction of the spacers 124. In this way, the line cut defined by the sacrificial material 136 is substantially perpendicular to the conductive lines formed in the recesses between adjacent spacers 124, which results in a wider coverage process window.

[0051] As shown in FIG. 9 to FIG. 12A to FIG. 12B The thickness of the sacrificial material 136 can be determined based at least in part on the thickness of the underlying layer 126. For example, by reducing the thickness of the underlying layer 126, the thickness of the sacrificial material 136 is also reduced. As described below, in some embodiments, if the sacrificial material 136 has a relatively thin thickness, it can not be necessary to perform a subsequent planarization process. In this way, manufacturing costs and time can be reduced.

[0052] In some embodiments, the length of the strip of sacrificial material 136 shown in FIG. 12A and FIG. 12B may be extended, for example, to extend the line cut to additional conductive lines. Although only one strip of sacrificial material 136 is shown in FIG. 12B in some embodiments, additional strips of sacrificial material 136 can be formed using the same or similar processes described above, for example, to form additional line cuts. In some embodiments, multiple strips of sacrificial material 136 can be formed, where each strip of sacrificial material 136 extends in a direction parallel to the other strips of sacrificial material 136 and perpendicular to the direction in which the spacers 124 extend in plan view.

[0053] Referring to FIG. 13A to FIG. 13B , a masking layer 140 is formed over the spacers 124, the hard mask layer 108, and the sacrificial material 136. The masking layer 140 can include a bottom layer 142, an intermediate layer 144, and an upper layer 148. Although a three-layer masking layer 140 is shown, in some embodiments, the masking layer 140 can be a single-layer masking layer or a double-layer masking layer as described above. In some embodiments, as shown in FIG. 14A , the bottom layer 142 can completely cover the sacrificial material 136 and can extend along the exposed spacers 124 and the hard mask layer 108.

[0054] In some embodiments, the upper layer 148 can be formed from a photoresist (e.g., a photosensitive material) that includes an organic material. The upper layer 148 can be formed from a positive photosensitive material or a negative photosensitive material. In some embodiments, the bottom layer 142 can be a polymer, a bottom anti-reflective coating (BARC), and / or an ashable removable dielectric (ARD) layer, etc. The middle layer 144 can include an inorganic material, where the inorganic material can be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), etc. The middle layer 144 has a high etch selectivity with respect to the upper layer 148 and the bottom layer 142. The various layers of the three-layer masking layer 140 can be sequentially blanket deposited using, for example, a spin-on process. Other processes and materials can be used.

[0055] In FIG. 14A to FIG. 14B the upper layer 148 is patterned using a lithographic process. Subsequently, the upper layer 148 is used as an etch mask for patterning the middle layer 144 (see FIG. 15A to FIG. 15B ). The middle layer 144 is then used as an etch mask for patterning the bottom layer 142 (see FIG. 16A to FIG. 16B ).

[0056] The upper layer 148 is patterned using any suitable lithographic process (e.g., the procedures discussed above) to form openings 146 therein. For example, a photomask (not shown) can be disposed over the upper layer 148. The upper layer 148 can then be exposed to a beam of radiation including ultraviolet (UV) or excimer laser light (such as a 248 nm beam from a krypton fluoride (KrF) excimer laser, a 193 nm beam from an argon fluoride (ArF) excimer laser, or a 157 nm beam from an F2 excimer laser, etc.) while the photomask masks regions of the upper layer 116. Immersion lithography systems or extreme ultraviolet lithography systems can be used to implement the exposure of the top photoresist layer to improve resolution and reduce the minimum achievable pitch. One or more exposure steps can be implemented. A bake or cure operation can be implemented to harden the upper layer 148, and a developer can be used to remove exposed or unexposed portions of the upper layer 148 depending on whether a positive or negative resist is used. The openings 146 can have a width W2, where in some embodiments W2 is approximately 50 nm.

[0057] Referring FIG. 15A to FIG. 15B , after the upper layer 148 is patterned, the pattern of the upper layer 148 can be transferred to the middle layer 144 in an etch process. The etch process is anisotropic such that the openings 146 in the upper layer 148 extend through the middle layer 144 and have the same (or slightly smaller) dimensions in the middle layer 144 as they do in the upper layer 148. FIG. 15A to FIG. 15B The resulting structure is shown in

[0058] As FIG. 16A to FIG. 16BAs shown, an etching process can be performed to transfer the pattern of the intermediate layer 144 to the underlayer 142 and the sacrificial material 136, whereby the opening 146 extends through the underlayer 142 and the sacrificial material 136. The etching process of the underlayer 142 is anisotropic, such that the opening 146 in the intermediate layer 144 extends through the underlayer 142 and has approximately the same (or slightly smaller) size in the underlayer 142 as in the intermediate layer 144. The etching process may include the use of CH4, Cl2, SF6, CH4, etc. x F y ,He,BCl3,N2,O2,H2,CF x CHF x Etching is performed using NF3, Ar, SiCl4, and combinations thereof.

[0059] As part of the etched bottom layer 142, the upper layer 148 may be consumed. After patterning the bottom layer 142, the opening 146 may expose the sidewalls of one or more spacers 124 formed by the remaining dielectric layer 110. The opening 146 may also expose portions of the hard mask layer 108 extending between adjacent spacers 124. In some embodiments, other portions of the spacers 124, such as the top surface, or other portions of the hard mask layer 108 may be exposed.

[0060] Next, refer to FIG. 17A to FIG. 17B For example, an ashing process can be used to remove any remaining portions of the bottom layer 142 and the intermediate layer 144. FIG. 17B As shown in the plan view, the sacrificial layer 136 has been patterned to form two discrete portions, each portion covering (at least partially) the gap between two adjacent spacers 124. Both discrete portions extend in a direction perpendicular to the direction in which the spacers 124 extend.

[0061] Next, refer to FIG. 18A to FIG. 18B A planarization process is performed to remove excess portions of the sacrificial material 136 and planarize the top surface of the sacrificial material 136 to be flush with the top surface of the spacer 124. In some embodiments, the planarization process includes one or more etching processes. For example, etching processes utilizing CH4, Cl2, SF6, CH4, etc., can be used. x F y ,He,SiCl4,HBr,N2,O2,H2,CF x CHF x Dry etching processes using NF3, Ar, NF3, etc. In some embodiments, wet etching processes using diluted hydrofluoric acid (DHF) as the etching chemical can be used. In other embodiments, polishing processes such as CMP can be used. FIG. 18A and FIG. 18B The resulting structure is shown. Along... FIG. 18B Obtain the line A-A' shown in the plan view.FIG. 18A A cross-sectional view. From FIG. 18A to FIG. 18B As can be seen, the planarization of the sacrificial material creates multiple discrete portions of the sacrificial material, each of which covers the gap between two adjacent spacers. In some embodiments, each discrete portion covers the area where a wire cut will be formed between two adjacent portions of the conductor.

[0062] In some embodiments, not implemented FIG. 18A to FIG. 18B The planarization process shown is not implemented therein. FIG. 18A to FIG. 18B In the embodiment of the planarization process shown, subsequent processes can continue, wherein the top surface of the sacrificial material 136 is offset from the top surface of the spacer 124. For example, as previously described... FIG. 9 to FIG. 12A to FIG. 12B In some embodiments, the thickness of the sacrificial material 136 can be controlled by controlling the thickness of the bottom layer 126 (e.g., ...). FIG. 9 to FIG. 12A to FIG. 12B (As shown). When the sacrificial material 136 is relatively thin, for example because the bottom layer 126 is formed to be relatively thin, FIG. 18A to FIG. 18B The planarization process described herein may be unnecessary. This could reduce manufacturing costs and / or manufacturing time.

[0063] FIG. 19A to FIG. 19B to FIG. 22A to FIG. 22B The patterning of hard mask layer 108 and target layer 102 is shown. FIG. 19A to FIG. 19B to FIG. 22A to FIG. 22B In each of the diagrams, a cross-sectional view of the diagram ending in "A" is obtained along line A-A' shown in the plan view of the corresponding diagram ending in "B".

[0064] refer to FIG. 19A to FIG. 19B The hard mask layer 108 is patterned using spacers 124 and sacrificial material 136 as etching masks to form openings 150. In this way, the pattern of spacers 124 and sacrificial material 136 is transferred to the hard mask layer 108. In some embodiments, etching the hard mask layer 108 includes anisotropic dry etching and / or wet etching. FIG. 19A and FIG. 19B The resulting structure is shown in the diagram. Along... FIG. 19A Obtain the line A-A' shown in the plan view. FIG. 19B Cross-sectional view.

[0065] like FIG. 19A and FIG. 19BAs shown, the remaining portion of the sacrificial material 136 prevents etching of the hardmask layer 108 located underneath the remaining portion of the sacrificial material 136 and effectively creates a break or "cut" in the opening 150 in the presence of the sacrificial material, otherwise creating a break or "cut" in the hardmask layer 108 located between two adjacent spacers 124. As will be discussed in detail below, the sacrificial material 136 creates a gap or "wire cut" between two adjacent portions of a wire when the pattern of the hardmask layer 108 is subsequently transferred to the target layer 102 and a conductive feature is formed in the recess.

[0066] After patterning the hardmask layer 108, a wet clean can be performed to remove any remaining portions of the spacers 124 and the sacrificial material 136. In FIG. 20A and FIG. 20B the resulting structure is shown.

[0067] Subsequently, in FIG. 21A and FIG. 21B the hardmask layer 108 is used as an etch mask to extend the openings 150 into the target layer 102. Etching the target layer 102 can include an anisotropic dry etch process and / or a wet etch process that sequentially etches through the ARC layer 106 to the target layer 102. The remaining portion of the target layer 102 can have the same pattern as the spacers 124 and the sacrificial material 136 of FIG. 19A to FIG. 19B . In this way, the target layer 102 is patterned in a single patterning step.

[0068] After patterning the openings 150, a wet clean process can be performed to remove any remaining portions of the hardmask layer 108 and the ARC layer 106. In FIG. 22A to FIG. 22B the resulting structure is shown.

[0069] After patterning the openings 150 in the target layer 102, features can be formed in the openings. In embodiments, the target layer 102 is a low-k dielectric and the patterned target layer 102 provides an IMD for an interconnect structure. Conductive features such as copper wires, copper vias, and / or cobalt plugs can be formed in the IMD.

[0070] Referring to FIG. 23 one or more liners 162 can be formed along the sidewalls and floor of the openings 150. The liners 162 can include TiO, TiN, TaO, TaN, Ru, Co, Ta, etc. and can provide a diffusion barrier, adhesion, and / or seed layer for the conductive features. The liners can be deposited using any suitable process such as PVD, CVD, ALD, etc.

[0071] Next, as shown in FIG. 24 the remaining portions of the openings 150 can be filled with a conductive material 164 such as copper using, for example, PVD, plating, etc. FIG. 23The conductive material 164 can be initially deposited to overfill the openings 150.

[0072] Referring to FIG. 25A to FIG. 25B , a planarization process is performed to remove remaining portions of the conductive material 164 above the target layer 102. Thus, a conductive feature can be formed in the target layer 102. In embodiments where the conductive feature is a wire, the areas under portions of the sacrificial material 136 when the patterned hard mask 108 is formed (see FIG. 2) are areas where the wire has a gap or "wire cut." FIG. 19A to FIG. 19B ) is an area where the wire has a gap or "wire cut."

[0073] As discussed above in connection with FIG. 12A and FIG. 12B , in some embodiments, the length of the strips of sacrificial material 136 shown in FIG. 12A and FIG. 12B may be extended, or additional strips of sacrificial material 136 can be formed. If the length of the sacrificial material 136 is extended, the wire cut shown in FIG. 25A and FIG. 25B may be extended, such that additional wires have the wire cut described. If multiple strips of sacrificial material 136 are formed, FIG. 25B the wires described can have additional wire cuts that are offset from the wire cut shown. By employing embodiments discussed herein, a fine pitch wire with a wire cut pitch of about 85.5 nm or greater can be formed. If an extreme ultraviolet lithography system is used in the patterning processes discussed herein, for example to pattern the upper layer 132 as discussed above in connection with FIG. 7 , a reduced wire cut pitch can be achieved. For example, a wire cut pitch of about 30 nm or greater can be achieved.

[0074] If the processes discussed herein are employed multiple times, wires with a wire cut pitch of about 30 nm or 48 nm or greater can be formed with fewer manufacturing defects and increased yield. For example, the processes discussed above in connection with FIG. 6 to FIG. 12A through FIG. 12B may be repeated multiple times to form multiple patterned sacrificial material lines (e.g., to form multiple adjacent wire cuts in subsequent processing), followed by additional processes discussed in connection with FIG. 13A to FIG. 13B through FIG. 25A to FIG. 25B to transfer wires with multiple adjacent wire cuts to a target layer. By additional processing, a wire cut pitch of about 30 nm or 48 nm or greater can be achieved. However, because the processes discussed in FIG. 6 to FIG. 12A through FIG. 12B are repeated multiple times, and the size of the interconnect wires is reduced, the size of the interconnect wires formed can vary slightly from the target size and / or alignment issues can occur.

[0075] Referring to FIG. 26This provides a method 200 for forming interconnects in a target layer. In step 168, for example, as... FIG. 1 to FIG. 3 As shown, the photoresist is patterned to form a mask. In step 170, for example, as... FIG. 4 As shown, a mask is used as an etching mask to etch the dielectric layer. In step 172, for example, as... FIG. 6 to FIG. 9 As shown, another photoresist is formed and patterned to form another mask. In step 174, for example, as... FIG. 10 to FIG. 11 As shown, sacrificial material is formed in the opening of the mask. In step 176, for example, as... FIG. 12A to FIG. 12B As shown, the mask is removed. In some embodiments, steps 172 to 176 may be repeated multiple times, for example, to form a conductor with multiple wire cuts having a small wire cut pitch. In step 178, for example, as... FIG. 13A to FIG. 13B to FIG. 15A to FIG. 15B As shown, another photoresist is formed and patterned to form another mask. In step 180, for example, as... FIG. 16A to FIG. 16B As shown, a mask is used to pattern the sacrificial material. In step 182, for example, as... FIG. 17A to FIG. 17B As shown, the mask is removed. In step 184, for example, as... FIG. 18A to FIG. 18B As shown, the sacrificial material is thinned. In step 186, for example, as... FIG. 19A to FIG. 19B As shown, the metal hard mask layer is etched. In step 188, for example, as... FIG. 21A to FIG. 21B As shown, a hard metal mask layer is used to pattern the target layer. In step 190, for example, as... FIG. 23 to FIG. 25A to FIG. 25B As shown, a wire with one or more line cuts is formed in the opening of the target layer.

[0076] In some embodiments, such as FIG. 25A to FIG. 25B As shown, the patterning method described herein can be used to form interconnects in a target layer. Interconnects can be formed with fine pitch, and multiple wire cuts can be formed with small wire cut pitch. Simplified patterning processes can be used to form interconnects with improved accuracy. For example, a single patterning process can be used to pattern the target layer to form fine-pitch interconnects with one or more wire cuts. Because the target layer is patterned in a single patterning process (or a simplified patterning process), improved patterning accuracy can be achieved. For example, if the target layer 102 is etched in two or more different processes, the pattern actually etched into the target layer 102 may differ from the desired pattern, for example, due to the difficulty in precisely aligning the etch mask with the portion to be etched. Improved accuracy is possible when the target layer 102 is etched using a single etch step and / or a simplified patterning process as described herein. Thus, multiple interconnects with one or more wire cuts can be formed with the same or substantially the same dimensions, which allows for better control of the interconnect resistance.

[0077] In some embodiments, the processes described above in connection with FIG. 1 to FIG. 25A through FIG. 25B The processes described can be used to form power rails and / or metal island structures, such as the power rail and metal island structures described in FIG. 27 to FIG. 30 In some embodiments, the processes described above in connection with FIG. 1 to 25A through FIG. 25B The processes described above in connection with FIG. 27 to FIG. 30 may be used to form the power rail and metal island structures described in FIG. 1 to FIG. 5 In some embodiments, as described above in connection with FIG. 6 to FIG. 18A through FIG. 18B A sacrificial material can be formed and patterned over the dielectric layer (as discussed in connection with FIG. 27 to FIG. 30 through FIG. 19A to FIG. 19B The pattern of the sacrificial material and the spacers can be transferred to the target layer, as shown in FIG. 22A to FIG. 22B through FIG. 23 to FIG. 25A Conductors can be formed in the patterned target layer to form the structures shown in FIG. 25B through FIG. 27 to FIG. 30

[0078] In some embodiments, the processes described herein in connection with FIG. 1 to FIG. 25A through FIG. 25B may be used to form narrower power rails and / or groups of metal islands that are well aligned with other groups of metal islands. Due to the processes used to form the power rails and metal islands, kinks can exist in the formed power rails. The kinks can reduce the reliability of contacts to the power rails. To avoid the kinks, the contacts to the power rails can be limited to portions of the power rails outside of a “no contact zone,” where the kinks can exist at the edges of the power rails.

[0079] FIG. 27 A power rail and metal island structure 2300 that can be formed in a target layer 2316 using processes as described herein is shown. In some embodiments, the target layer 2316 is the same as the target layer described in connection with FIG. 1 to FIG. 25A through FIG. 25B ​The target layer 102 described herein is the same as or similar. The power rail and metal island structure 2300 includes a power rail 2302. In some embodiments, the power rail 2302 facilitates the distribution of power such as Vdd or ground power within the device. For example, the power rail 2302 may be electrically connected to a power or ground node, and contacts (not shown) may be formed at different locations along the power rail 2302, electrically connected to the power rail 2302, and thereby connecting the power rail 2302 to a power or ground node. The processes described herein can be used to form the power rail 2302 with relatively small dimensions. For example, in some embodiments, the power rail 2302 may have a thickness T4 of about 55 nm or less.

[0080] The power rail and metal island structure 2300 may further include a metal island 2312. In some embodiments, the metal island 2312 may be used to distribute power and / or signals within the device. FIG. 27 As shown, the process described herein can be used to form an array of metal islands 2312 having a line pitch P2 greater than or equal to about 85.5 nm and a line pitch P5 greater than or equal to about 30 nm. Because the process described herein allows the array of metal islands 2312 to be formed with a fine line pitch and a fine line pitch, a greater number of metal islands 2312 can be formed in the spacing adjacent to the power rail 2302. Additionally, the process described herein can be used to form a group 2304 of metal islands 2312 that is well aligned with another group 2306 of metal islands 2312. In some embodiments, the group 2304 of metal islands is well aligned with another group 2306 of metal islands 2302, for example, because the same line pitch (i.e., the same sacrificial material 136 of the same strip) can be used to form the group 2304 and the group 2306 of metal islands. The sidewalls of the metal islands 2312 of the group 2304 of metal islands can be aligned with the sidewalls of the metal islands 2312 of the group 2306 of metal islands. Furthermore, as FIG. 27 As shown, the process described herein can be used to form a group of metal islands 2312 with a fine-line notch pitch P2 (such as greater than or equal to about 85.5 nm), wherein each metal island 2312 has the same or substantially the same dimensions as the other metal islands 2312 in the group. For example, in some embodiments, each metal island 2312 may have a length L1 of about 45 nm to about 60 nm.

[0081] In some embodiments, such as FIG. 28 As shown, the process described herein can be used to form a power rail and metal island structure 2400 in target layer 2416. In some embodiments, target layer 2416 is combined with... FIG. 1 to FIG. 25A to FIG. 25BThe depicted target layer 102 is the same or similar. The power rail and metal island structure 2400 includes a power rail 2402. In some embodiments, the power rail 2402 facilitates distribution of a power supply, such as Vdd or ground, in a device. The power rail 2402 can be similar to the power rail 2302 discussed above in connection with FIG. 27 For example, in some embodiments, the power rail 2402 can have a thickness T5 of about 55 nm or less. The power rail and metal island structure 2400 can also include a metal island 2412. As discussed above in connection with FIG. 27 the metal island 2312, the metal island 2412 can be the same or similar. The metal island 2412 can have a line cut pitch P3, where the line cut pitch P3 can be the same or similar to the line cut pitch P2 discussed above in connection with FIG. 27 the metal island 2312.

[0082] As FIG. 28 illustrated, the processes described herein for forming the power rail and metal island structure 2400 can also form kinks 2414 that extend into the power rail 2402. For example, the processes for forming the power rail and metal island structure can have inherent accuracy limitations, such as a limitation on the ability to align an etch mask with a particular portion of an underlying layer that is desired to be etched. The processing equipment used to form the power rail and metal island structure 2400 can have inaccuracies or defects. As such, the processes described herein can result in the formation of kinks at the edges of the power rail 2402. The kinks 2414 can reduce the reliability of any physical or electrical connections to the power rail 2402 that are formed in the edge regions of the power rail 2402, where the kinks 2414 can be formed. In some embodiments, the kinks 2414 can extend a distance Dl in the power rail 2402, where Dl is about 5 nm to about 8 nm.

[0083] In some embodiments, to avoid forming contacts that can be affected by one or more kinks 2414 and thus have reduced reliability, one or more contactless regions 2408 can be included along the edges of the power rail 2402 where the kinks 2414 are formed. For example, a semiconductor device can be designed and formed such that physical and / or electrical connections to the power rail 2402 are formed outside of the contactless regions 2408 of the power rail 2402. In some manufacturing processes, prior to formation, a computer-based processing system (e.g., a computer-aided design (CAD) system) can be used to design the semiconductor device and to determine the locations of the contactless regions 2408. FIG. 31The computer-based processing system 300 (discussed in detail below) is used to design semiconductor devices. This system enables the use of one or more design rules to guide designers in routing electrical connections within a virtual semiconductor device layout, for example, to ensure adherence to minimum distances specified by a particular processing technique in a given design. In some embodiments, a contactless region 2408 may be included as a design rule to prevent the formation of physical and / or electrical connections to the power rail 2402 within the contactless region 2408. Thus, when the design is completed and the semiconductor device is formed according to the planned design, all contacts to the power rail 2402 can be formed outside the contactless region 2408 according to the design rules.

[0084] In some embodiments, the contactless region 2408 may extend a distance D2 into the power rail 2402, wherein D2 is approximately 5 nm to approximately 10 nm. In embodiments, a plurality of contactless regions 2408 may be included (e.g., located on opposite sides of the power rail 2402), or only a single contactless region 2408 may be included.

[0085] FIG. 29 The diagram illustrates the formation of a power rail and metal island structure 2500 in a target layer 2516 according to some embodiments. In some embodiments, the target layer 2516 is combined with... FIG. 1 to FIG. 25A to FIG. 25B The target layer 102 described is the same as or similar to this. The above combination can be used. FIG. 1 to FIG. 25A to FIG. 25B The described process forms a power rail and metal island structure 2500. The power rail and metal island structure 2500 may include a power rail 2502 and a metal island 2512. The power rail 2502 may be the same as or similar to the power rail 2402, and the metal island 2512 may be the same as or similar to the metal island 2412.

[0086] In some embodiments, the combination can be used multiple times. FIG. 1 to FIG. 25A to FIG. 25B The specific process described, such as the combination above FIG. 6 to FIG. 12A to FIG. 12B The process described. In the 10nm technology node, the metal island 2512 may have a line-cut pitch P4 of approximately 30nm to 48nm. In some embodiments, inaccuracies that may occur during manufacturing (examples of which have been discussed above) may become more problematic as the pitch decreases. In some embodiments, it may be more difficult to manufacture multiple metal islands 2512 with the same or substantially similar dimensions when the pitch of the metal island (e.g., metal island 2512) decreases. Thus, when the pitch P4 of the metal island 2512 is approximately 30nm to 48nm, the dimensions of the metal island 2512 can be varied. For example, the length L2 of a particular metal island 2512 and the bonding... FIG. 27The depicted metal islands 2312 are of the same length LI. Other metal islands 2512 can have a length L3 of about 10 nm to about 35 nm.

[0087] As described above, in some embodiments, the above-described process is used in conjunction with FIG. 1 to FIG. 25A to FIG. 25B The accuracy of the pattern formed in the target layer 102 by the described process depends on the accuracy of the different processing steps (e.g., how accurately the patterning mask used for the patterning process is formed and / or how accurately the etching process can be performed in which the pattern of the upper mask is transferred to the underlying layer). In particular, when the target pitch of the metal islands 2512 is reduced to, for example, a pitch P4 of about 30 nm to 48 nm, slight deviations can occur in the desired pattern. The slight deviations can result in a slight misalignment of the groups of metal islands. For example, as shown, the group of metal islands 2504 is misaligned from the group of metal islands 2506. As described above, the misalignment can also result in the formation of kinks 2514. The kinks 2514 are the same as or similar to the kinks 2414 described above in conjunction with FIG. 29 Thus, the contactless region 2508 can be needed. The contactless region 2508 can be the same as or similar to the contactless region 2408 discussed above in conjunction with FIG. 27 Thus, the contactless region 2508 can be needed. The contactless region 2508 can be the same as or similar to the contactless region 2408 discussed above in conjunction with FIG. 28 Thus, the contactless region 2508 can be needed. The contactless region 2508 can be the same as or similar to the contactless region 2408 discussed above in conjunction with

[0088] In some embodiments, a single power rail and metal island structure can be formed that includes some or all of the features discussed above in conjunction with FIGS. 27-29 Thus, the contactless region 2508 can be needed. The contactless region 2508 can be the same as or similar to the contactless region 2408 discussed above in conjunction with FIG. 30 A power rail and metal island structure 2900 is shown. The metal structure 2900 can include portions formed to different specifications. For example, as discussed above in conjunction with FIG. 27 In a first portion, the power rail and metal island structure 2900 is formed to include the components of the power rail and metal island structure 2300. As discussed above in conjunction with FIG. 28 In a second portion, the power rail and metal island structure 2900 is formed to include the components of the power rail and metal island structure 2400. As discussed above in conjunction with FIG. 29 In a third portion, the power rail and metal island structure 2900 is formed to include the components of the power rail and metal island structure 2500.

[0089] As described above, a processing system, such as a computer, can be used to design and optimize a virtual layout of a semiconductor device to be formed. After the virtual layout is optimized on the processing system, the optimized layout can be used as a guide for subsequent formation of a semiconductor chip.

[0090] Reference is made to FIG. 31wherein a block diagram of elements of a processing system 300 is shown, wherein the processing system 300 can be used to generate a map showing a virtual layout of a semiconductor chip to be formed. The processing system 300 can include a processor 302 equipped with one or more input / output devices such as a video adapter / graphics processing unit ("GPU"). The processor 302 can include a central processing unit ("CPU") / DSP, memory, and a hardware accelerator connected to a bus 304.

[0091] The bus 304 can be one or more of several buses, including a memory bus or memory controller, a peripheral bus, or a video bus, among others. The CPU can be formed from any type of electronic data processor. The memory can be formed from any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), non-volatile random access memory ("NVRAM"), a combination of these, or the like. In an embodiment, the memory can include a ROM used at boot-up and a DRAM used for data storage while executing programs. The memory can store programs that enable a user to view, modify, and / or optimize a virtual layout of a semiconductor chip to be formed. The memory can store parameters, rules, and the like to assist a user in designing, modifying, and / or optimizing a virtual layout of a semiconductor chip to be formed. For example, the memory can store one or more design rules that can be used to ensure that minimum distances required for a particular technology or process are met, thereby optimizing a virtual layout of a semiconductor chip to be formed.

[0092] The video adapter / GPU provides an interface to connect an external input and output from the display 306 to the processor. The display 306 can display a virtual layout of a semiconductor chip to be formed. Other devices can be connected to the processor 302 and can use additional or individual interface cards. For example, a serial interface card (not shown) can be used to provide a serial interface for printers.

[0093] The processor 302 can also include a network interface (not shown) that can be a wired link, such as an Ethernet cable, and / or a wireless link to enable communication with a network, such as a cellular communications network. The network interface allows the processor to communicate with remote units via the network. In an embodiment, the processor 302 is connected to a local area network or wide area network to provide communication to remote devices, such as other processors, the Internet, remote storage facilities, and the like.

[0094] It should be noted that the processing system 300 can include other components. For example, the processing system 300 can include a power supply, cables, a motherboard, removable storage media, a housing, and the like. Although not shown, these other components can be considered part of the processing system 300.

[0095] In some embodiments, the planned semiconductor device can include wires, interconnects, and the layout of the semiconductor chip to be formed can be optimized by removing undesired portions of the wires. For example, a plurality of wires can have one or more wire cuts, which in some embodiments can be formed using the methods discussed above in connection with FIGS. 1-25B FIG. 1. The wire cuts can be formed in the middle portions of the wires. After forming the plurality of wires with one or more wire cuts, portions of the one or more wires can be unnecessary or undesirable. For example, as shown in FIG. 32 FIG. 3, wire 308 can be used to form electrical connections between first end 312 and via 316 of wire 308 and between second end 323 and via 318. Wire cut 320 can be formed between vias 316 and 318. As can be seen from FIG. 32 FIG. 3, portion 322 of wire 308 extending between wire cut 320 and via 316 can be unused (e.g., that portion 322 of the wire can not be needed for any desired electrical connections in the given layout). In some devices, unnecessary or undesirable metal lines can be disadvantageous in a semiconductor device. For example, unnecessary or undesirable metal lines can degrade the RC performance of the semiconductor device, and / or can disadvantageously increase the size and / or footprint of the semiconductor device.

[0096] In some embodiments, the wires can be formed in a manner that does not form unnecessary or unwanted wire ends, which can improve the RC performance of the semiconductor device and / or reduce the size or footprint of the semiconductor device. FIG. 33A Comparisons of the virtual layouts (e.g., 324, 330) to the physical conductive components (e.g., 326, 332) formed using the virtual layouts as a guide are shown. FIG. 33A Parameters that can be used to calculate a target cut width for wire cuts that can be used during formation of the physical wires are also shown (see FIGS. 34-47 ), which will allow for omission of unnecessary or undesirable wire ends in the formed semiconductor device, thereby improving the RC constant of the device and / or reducing the size or footprint of the semiconductor device.

[0097] FIG. 33A A virtual layout 324 overlaid on physical wire 326 is shown, where virtual layout 324 can be used as a guide to form physical wire 326. FIG. 33AA virtual layout 330 is also shown over the physical conductor 332, which can be used as a guide for forming the physical conductor 332. In the physical conductor 326, the portion extending between the via 328 and the line end 338 is unused, and it would be advantageous to remove or not form it in the semiconductor device being manufactured. In the physical conductor 332, the portion extending between the via 334 and the line end 336 is unused, and it would be advantageous to remove or not form it in the semiconductor chip being manufactured.

[0098] In each of physical conductors 326 and 332, EN is the width of the target virtual conductor cutout in the virtual layout, and W is the minimum distance between the edge of a virtual via in the virtual layout (e.g., 328 or 334) and the nearest edge of the target virtual conductor cutout EN. In some embodiments, W is a parameter defined by design rules of a specific technology, for example, to ensure that physical conductors 326 above via 328 and physical conductors above via 334 are not removed, for example, due to inaccuracies introduced by the processing techniques used to form the semiconductor device when using the virtual layout as a guide for forming a semiconductor device.

[0099] like FIG. 33A As shown, for example, due to inaccuracies introduced by various processing techniques or imperfections or deviations in the equipment used in the processing, the physical guides formed using a virtual layout as a guide can differ from the virtual layout in various aspects. FIG. 33A In this configuration, a physical conductor 326 is formed such that the line end 338 does not reach the planned line end of the virtual layout 324 (the virtual layout 324 is used as a guide for formation). In some embodiments, the distance between the line end 338 of the physical conductor 326 and the planned line end of the virtual layout 324 can vary within a maximum distance S. On the other hand, the physical conductor 332 can be formed such that the line end 336 extends beyond the planned line end of the virtual layout 330 by a maximum distance S. In other words, there may be a variation of + / -S or 2S between the planned line end of the planned conductor and the actual line end of the actual conductor, wherein the actual line end can be formed to extend the maximum distance S to the farthest point on either side of the planned line end. Thus, the actual line end can be formed within a 2S offset range of the planned line end. In some embodiments, S can be from about 0 nm to about 5 nm.

[0100] In some embodiments, during the formation of a semiconductor device, it may be desirable to align the planned line cut with specific locations on the conductor. For example, it may be desirable to position the central axis of the planned line cut so that it intersects the center point of line EN. However, the ability to achieve precise alignment may be limited due to the processing constraints discussed herein, and some variations may occur during normal processing. FIG. 33BIt is shown that in forming the actual device, the planned center axis 341 of the planned line cut 343 deviates from the center axis 345 of the actual line cut 347 formed using the planned line cut 343 as a guide. A coverage distance V can be defined, where V is the distance the line cut moves along the x-axis between the actual and planned positions (shown in FIG. 3B). FIG. 33B Referring again to FIG. 3A, FIG. 33A it is shown that the actual line cut 340 has been shifted so that the center axis 342 deviates from the center point of the dashed line EN. Referring to FIG. 3B, FIG. 33B In the actual manufacturing process, the line cut 347 can be positioned a distance V along the x-axis from the first side of the planned line cut 343, or a distance V along the x-axis from the second side, where the second side is opposite the first side. In some embodiments, V can be about 0 nm to about 6 nm. The value of V depends on the processing equipment used to form the line cut 340 and / or the leads 326 and 332, and any processing limitations or inaccuracies introduced by the equipment.

[0101] Variations in the target cut width CD can also be considered. For example, in some embodiments, it can be determined (e.g., using the virtual layout) that a line cut 340 having a target cut width CD is desired to remove an undesired line end of a particular lead. However, when the line cut 340 is used in forming a physical lead, the line cut 340 can have a different actual cut width than the target cut width CD, for example due to accuracy limitations of the processing technology or differences in the processing equipment. In some embodiments, the actual cut width can be wider than the target cut width CD by an amount Z (not shown). In some embodiments, the actual cut width can be narrower than the target cut width CD by an amount Z. Thus, a cut width variation of + / - Z or 2Z can be considered. In some embodiments, Z can be about 0 nm to about 1 nm.

[0102] In some embodiments, an optimal cut width CD can be determined based on the above parameters. The optimal cut width CD can be determined based on the following relationship:

[0103] Cut CD = 2X + S + 2 x (Z2+ V2)0 5,

[0104] where 2X is the target length of the virtual lead that is desired to be removed in the virtual layout, S is half of the offset range 2S, Z is half of the cut width variation 2Z, and V is the distance the line cut can move between the actual and planned positions. The determined optimal cut width CD can be used to form leads having removed unused line ends, as described below (see FIG. 4). Leads formed using line cuts having a cut width CD determined using this relationship can have a wider process window during formation of the leads. FIGS. 34-47

[0105] ​FIGS. 34-47 The diagram illustrates the formation of wires according to some embodiments. FIG. 34 In this process, a film stack 415 is formed over a semiconductor substrate 402. The film stack 415 includes a dielectric layer 404 formed over the semiconductor substrate 402, a dielectric layer 406 formed over the dielectric layer 404, a hard mask layer 408 formed over the dielectric layer 406, a second capping layer 410 formed over the hard mask layer 408, an etch stop layer 412 formed over the second capping layer 410, and a first capping layer 414 formed over the etch stop layer 412. Each layer is discussed in detail below.

[0106] like FIG. 34 As shown, a film stack 415 is formed over a semiconductor substrate 402. The semiconductor substrate 402 may be formed of a semiconductor material such as doped or undoped silicon or a semiconductor-on-insulator (SOI) substrate as the active layer. The semiconductor substrate 402 may include other semiconductor materials such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates such as multilayer substrates or gradient substrates may also be used. Devices such as transistors, diodes, capacitors, resistors, etc. (not shown) may be formed in and / or on the active surface of the semiconductor substrate 402. One or more interconnects and / or vias (not shown) may be included in the semiconductor substrate 402. For example, vias 416 are electrically connected to one or more devices (not shown) located in the semiconductor substrate 402 using one or more wires (not shown) and / or one or more conductive vias (not shown).

[0107] A dielectric layer 404 is formed over a semiconductor substrate 402. In some embodiments, the dielectric layer 404 is an inter-metal dielectric (IMD) layer. In this embodiment, the dielectric layer 404 comprises a low-k dielectric material having a dielectric constant (k value) less than 3.8, less than about 3.0, or less than about 2.5. In an alternative embodiment, the dielectric layer 404 is an IMD layer comprising a high-k dielectric material having a k value greater than 3.8. Other materials may also be used.

[0108] like FIG. 34 As shown, a via 416 is formed in dielectric layer 404. In some embodiments, via 416 can provide access from the dielectric layer 406 (see Figure 404). FIG. 47to electrical connections of the conductive lines in dielectric layer 404 to devices located in semiconductor substrate 402 (not shown). Via 416 can be formed, for example, by forming an opening in dielectric layer 404 using an acceptable photolithography process, such as those described herein. One or more liners can be deposited in the opening. Conductive material can then be deposited in the opening over the one or more liners, for example, using a plating process. After the plating process is complete, excess conductive material can overfill the opening and extend along the top surface of dielectric layer 404 (not shown). As shown in FIG. 4B, a planarization process, such as a chemical mechanical polishing process, can be used to remove the excess conductive material and to level the top surface of via 416 with the top surface of dielectric layer 404. Other processes can be used. FIG. 34

[0109] Dielectric layer 406 is formed over dielectric layer 404. In some embodiments, conductive lines will be formed in dielectric layer 404. The conductive lines can be formed in a manner that does not form undesirable line ends. Dielectric layer 406 can be formed using the same or similar processes described in connection with dielectric layer 404. In some embodiments, dielectric layer 404 has the same material composition as dielectric layer 406. In other embodiments, dielectric layer 404 has a different material composition than dielectric layer 406.

[0110] Hardmask layer 408 is formed over dielectric layer 406. Hardmask layer 408 can be formed from materials including metals (e.g., titanium nitride, titanium, tantalum nitride, tantalum, doped carbides of metals (e.g., tungsten carbide), etc.) and / or non-metals (e.g., silicon nitride, boron nitride, silicon carbide, etc.) and can be formed by PVD, radio frequency PVD (RF PVD), atomic layer deposition (ALD), etc. Other processes and materials can be used. In a subsequent processing step, a pattern is formed in hardmask layer 408 (see FIG. 4D). Hardmask layer 408 is then used as an etch mask for etching dielectric layer 406. FIGS. 44A-44B

[0111] Second cap layer 410 is formed over hardmask layer 408. Second cap layer 410 can be formed using silicon oxide such as borophosphosilicate ethyltrimethoxysilane (BPTEOS) or undoped ethyltrimethoxysilane (TEOS) oxide. In some embodiments, second cap layer 410 is low temperature oxide (LTO). As used herein, the term “LTO” refers to oxide deposited using a relatively low process temperature (e.g., 200 °C or less). Second cap layer 410 can be formed by PVD, CVD, ALD, spin-on, etc. Other processes and materials can be used.

[0112] Etch stop layer 412 is formed over second cap layer 410. In some embodiments, SiC, SiOC x , SiN, SiON x ​​An etch stop layer is formed. The etch stop layer 412 can be formed from a suitable material that has high etch selectivity relative to the first cover layer 414. The etch stop layer 412 can be formed by PVD, CVD, ALD, spin coating, etc. Other processes and materials can also be used.

[0113] A first capping layer 414 is formed over the etch stop layer 412. The first capping layer 414 can be formed using silicon oxide such as BPTEOS or undoped TEOS oxide. In some embodiments, the first capping layer 414 is LTO. The first capping layer 414 can be formed using the same material as the second capping layer 410. In other embodiments, the first capping layer 414 is formed of a different material than the second capping layer 410. The second capping layer 410 can be formed by PVD, CVD, ALD, spin coating, etc. Other processes and materials can be used.

[0114] exist FIG. 35 In this process, the first capping layer 414 is patterned to form an opening 418. The opening 418 covers the dielectric layer 406, where a mask 420 will be formed (see [link]). FIG. 37 The area of ​​) opening 418. The opening 418 can have the above-described combination. FIGS. 33A-33B The target width CD is defined as described herein. The aperture 418 can be formed using, for example, an acceptable photolithography process as described herein.

[0115] exist FIG. 36 In this process, a mask material 421 is disposed above the first cover layer 414 and in the opening 418, thereby filling the opening 418 with the mask material 421. In some embodiments, the mask material 421 comprises SiO2. x SiN x SiC x Metal oxides, metal nitrides, etc. In some embodiments, mask material 421 may comprise any suitable inorganic material having high etch selectivity relative to the material of hard mask layer 408. Mask material 421 may be formed by PVD, CVD, ALD, spin coating, etc. Other processes and materials may be used.

[0116] exist FIG. 37 In this process, excess portions of mask material 421 are removed to form mask 420. In some embodiments, a polishing process such as chemical mechanical polishing can be used to remove excess portions of the mask material 420. In other embodiments, an etching process can be used to remove excess portions of the mask material 420. After removing excess portions of the mask material 420, the upper and lower surfaces of the mask 420 are flush with the upper and lower surfaces of the first cover layer 414. Other processes and materials can be used.

[0117] like FIG. 37As shown, the first capping layer 414 and the mask 420 have a thickness T1, and the etch stop layer 412 has a thickness T2. In some embodiments, T1 is greater than or equal to half of the cut width CD, where, as described in connection with FIGS. 33A-33B As described, the cut width CD is determined. In other words, in some embodiments, T1 > 0.5 x CD. In some embodiments, the combined thickness of T1 and T2 satisfies the following relationship:

[0118] T1 + T2 = T3 x (1 + target OE% / sel(hard mask layer 408 / etch stop layer 412)).

[0119] where T1 is the thickness of the first capping layer 414, T2 is the thickness of the etch stop layer 412, T3 is the thickness of the hard mask layer 408, target OE% is a target over-etch percentage used in fabricating semiconductor devices, and sel(hard mask layer 408 / etch stop layer 412) is the etch selectivity of the hard mask layer 408 relative to the etch stop layer 412. When the above relationship is satisfied, when the hard mask layer is etched (see FIGS. 44A-44B ), the mask layer 420, the etch stop layer 412, and the first capping layer 414 will be consumed. As a result of the consumption of the mask layer 420, the etch stop layer 412, and the first capping layer 414, the hard mask layer 408 and the second capping layer 410 have a substantially uniform height after the etch process terminates. As such, subsequent etching of the dielectric layer 406 to form conductive lines therein will be able to be performed more reliably with fewer faults, and / or the etch window can be maintained and not undesirably reduced, which can result in difficulty in filling the openings in the dielectric layer 406 with conductive material.

[0120] In FIG. 38 , a three-layer masking layer is formed over the first capping layer 414 and the mask 420. The three layers include a bottom layer (sometimes also referred to as a lower layer) 422, a middle layer 424 located over the bottom layer 422, and an upper layer 426 located over the middle layer 424. According to some embodiments, the upper layer 426 can be formed of photoresist. Either a positive or negative photoactive material can be used. The middle layer 424 can be formed of an inorganic material, where the inorganic material can be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), etc. The bottom layer 422 can be a polymer or an anti-reflective type material. The middle layer 424 can have a high etch selectivity relative to the upper layer 426 and the bottom layer 422. Thus, the upper layer 426 can serve as an etch mask for patterning the middle layer 424, and the middle layer 424 can serve as an etch mask for patterning the bottom layer 422. Other materials can also be used.

[0121] In FIG. 39In some embodiments, the patterned upper layer 426 is used as an etch mask to etch the intermediate layer 424. In some embodiments, the patterned upper layer 426 is used as an etch mask to etch the intermediate layer 424 and the bottom layer 422. In some embodiments, the patterned upper layer 426 is used as an etch mask to etch the intermediate layer 424, the bottom layer 422, and the first cap layer 414. In some embodiments, the patterned upper layer 426 is used as an etch mask to etch the intermediate layer 424, the bottom layer 422, the first cap layer 414, the etch stop layer 412, and the second cap layer 410. FIG. 39 As shown, for example, due to limitations in the accuracy of processing techniques or variations in equipment used to form the semiconductor device, the sidewalls of the opening 428 are offset from the sidewalls of the mask 420.

[0122] Next, referring to FIG. 40 , the intermediate layer 424 is etched using the patterned upper layer 426 as an etch mask, such that the pattern of the upper layer 426 is transferred to the intermediate layer 424.

[0123] Referring to FIG. 41 , after the intermediate layer 424 is etched, the bottom layer 422 is patterned, with the intermediate layer 424 used as an etch mask. During the patterning of the bottom layer 422, the upper layer 426 can be consumed. The patterning of the bottom layer 422 exposes portions of the top surface of the mask 420 and portions of the top surface of the first cap layer 414. After the bottom layer 422 is patterned, any remaining portions of the intermediate layer 424 can be removed.

[0124] In some embodiments, the bottom layer 422 is then used as an etch mask to etch the underlying first cap layer 414, etch stop layer 412, and second cap layer 410. Any suitable etching process, such as wet etching or dry etching, can be used. In some embodiments, the etching process is anisotropic. As shown, the mask 420 prevents the portions 440 of the etch stop layer 412 and second cap layer 410 that are under the mask 420 from being etched. In this way, the size of the subsequent wire formed in the opening 428 is smaller than it would have been without the formation of the mask 420. As a result, a line end (e.g., an unused line end) is not formed. FIG. 42 FIG. 42 As shown, the mask 420 prevents the portions 440 of the etch stop layer 412 and second cap layer 410 that are under the mask 420 from being etched. In this way, the size of the subsequent wire formed in the opening 428 is smaller than it would have been without the formation of the mask 420. As a result, a line end (e.g., an unused line end) is not formed.

[0125] Referring to FIG. 43 , after the first cap layer 414, etch stop layer 412, and second cap layer 410 are patterned, the remaining portions of the bottom layer 422 are removed, for example, in an ashing process. In some embodiments, the patterning of the first cap layer 414, etch stop layer 412, and second cap layer 410 consumes the bottom layer, and the separate step of removing the bottom layer 422 can be omitted.

[0126] Next, the hard mask layer 408 is etched, extending the openings 428 and 429 into the hard mask layer 408. FIG. 44A and FIG. 44B Plan and cross-sectional views of the semiconductor device 400 after the hard mask layer 408 is etched are described. The plan view is taken along the line A-A’ shown in FIG. 44B FIG. 44A ​​A cross-sectional view of the structure is shown in FIG. 4B. Any suitable etching process, such as wet etching or dry etching, can be used to etch the hard mask layer 408. In some embodiments, the etching process is anisotropic. During etching of the hard mask layer 408, the mask layer 420, the etch stop layer 412, and the first cap layer 414 are consumed. As a result of the consumption of the mask layer 420, the etch stop layer 412, and the first cap layer 414, the hard mask layer 408 and the second cap layer 410 have a substantially uniform height after the etching process terminates. As such, subsequent etching of the dielectric layer 406 to form conductive lines therein will be able to be performed more reliably with fewer faults, and / or the etch window can be maintained and not undesirably reduced, which can result in difficulty filling the openings in the dielectric layer 406 with a conductive material.

[0127] In FIG. 45A and FIG. 45B , the dielectric layer 406 is etched using the hard mask layer 408 as an etching mask. The etching process extends the openings 428 and 429 into the dielectric layer 406. Any suitable etching process can be used. In some embodiments, the etching process is anisotropic. Etching of the dielectric layer 406 exposes the top surface of the dielectric layer 404 and the via 416. Although the via 416 has a rectangular top view in FIG. 45B , in other embodiments, the via 416 can have any suitable shape, including a circular shape, an elliptical shape, a polygonal shape, a square shape, etc.

[0128] In FIG. 46 , the openings 428 and 429 are filled with a conductive material 430. For example, in some embodiments, one or more liners (not shown) can be deposited in the openings 428 and 429 and on the top surface of the hard mask layer 408. The liners can include TiO, TiN, TaO, TaN, etc., and can provide a diffusion barrier layer, an adhesion layer, and / or a seed layer. The liners can be deposited using any suitable process, such as PVD, CVD, ALD, etc. The remaining portions of the openings 428 and 429 can then be filled with the conductive material 430, e.g., using a plating process. The liners and / or the conductive material 430 contact the via 416. Any suitable conductive material 430, such as copper or another metal, can be used. The resulting structure is shown in FIG. 46 .

[0129] In FIG. 47In some embodiments, a polishing process such as a chemical mechanical polishing process is used to remove excess conductive material 430. The polishing process can also remove the remaining portion of hard mask layer 408. After the polishing process is complete, a wire 444 has been formed in dielectric layer 406. The top surface of wire 444 is flush with the top surface of dielectric layer 406. Due to the use of mask 420, the length of wire 444A is reduced compared to the length of wire 444A if mask 420 were not used. Area 442 represents a section of wire 444A that should have been formed but has not been formed in semiconductor device 400 if mask 420 were not used.

[0130] In subsequent processing, additional dielectric layers with or without wires can be formed over dielectric layer 406. External contacts can be formed over semiconductor device 400 to enable electrical and / or physical connection of semiconductor device 400 to additional devices.

[0131] FIG. 48 A method according to some embodiments is shown. In step 502, the optimal width of a line cut is determined, for example, as discussed in connection with FIGS. 33A-33B In step 504, an opening having the optimal width is patterned in a first cap layer, for example, as shown in FIG. 35 In step 506, the opening is filled with a mask material, for example, as shown in FIG. 36 In step 508, the mask material is planarized, for example, as shown in FIG. 37 In step 510, a photoresist is deposited and patterned to form an opening, for example, as shown in FIGS. 38-41 In step 512, an etching process is performed using the mask, for example, as shown in FIG. 42 In step 514, a hard mask layer is patterned, for example, as shown in FIG. 44A and FIG. 44B In step 516, the dielectric layer is patterned using the patterned hard mask, for example, as shown in FIG. 45A and FIG. 45B In step 518, the opening in the dielectric layer is filled with a conductive material, for example, as shown in FIG. 46 In step 520, the conductive material is planarized, for example, as shown in FIG. 47

[0132] ​As described herein, semiconductor devices and methods of forming semiconductor devices are provided in accordance with some embodiments. A patterning process is implemented to pattern lines in a target layer of a semiconductor device. In some embodiments, a dielectric layer is patterned using photolithography, and a patterned sacrificial material (sometimes referred to as a reverse material) is formed over the patterned dielectric layer. After the sacrificial material is formed, the sacrificial material is patterned by forming openings in the sacrificial material. The patterned dielectric layer and the sacrificial material are used to pattern an underlying mask layer, where the mask layer is in turn used to pattern the target layer using a single patterning step. Subsequently, a conductive material can be filled in the openings of the low-k dielectric layer to define interconnect lines having line cuts defined by the patterned sacrificial material. The conductive lines can have a finer pitch than is achievable using other similar patterning processes, and / or the interconnect lines can be formed using a simplified patterning process with a finer pitch. For example, a single patterning process can be used to pattern the target layer to form fine pitch conductive lines having one or more line cuts. Because the target layer is patterned in a single patterning process and / or using a simplified process as described herein, improved accuracy of the pattern can be achieved. As such, multiple interconnect lines can be formed having the same size or substantially the same size, which allows for better control of the resistance of the interconnect lines.

[0133] In some embodiments, a target width of a line cut of a line end can be determined, for example, using a virtual layout as described herein. The determined optimal width can be used to form a mask during formation of a semiconductor device. The mask can prevent patterning of regions of a dielectric layer underlying the mask, thereby preventing formation of a line end in the dielectric layer during subsequent processing. As described herein, RC performance of a semiconductor device can be improved, and / or the size or footprint of a device can be reduced.

[0134] A method is provided according to some embodiments. The method includes forming a first mask layer over a target layer. The method also includes forming a plurality of spacers over the first mask layer. The method also includes forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where, in a plan view, a major axis of the opening extends in a direction perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening. The method also includes patterning the sacrificial material. The method also includes etching the first mask layer using the plurality of spacers and the patterned sacrificial material. The method also includes etching the target layer using the etched first mask layer to form a second opening in the target layer. The method also includes filling the second opening in the target layer with a conductive material. In an embodiment, patterning the sacrificial material includes patterning the sacrificial material using an extreme ultraviolet lithography process. In an embodiment, a gap between adjacent spacers of the plurality of spacers has a pitch of 85.5 nm or less. In an embodiment, the sacrificial material includes an inorganic material having a high etch selectivity relative to a material used to form the first mask layer. In an embodiment, the sacrificial material is a metal oxide or a metal nitride. In an embodiment, the method also includes planarizing the sacrificial material, where, after planarization, a top surface of the sacrificial material is flush with a top surface of the plurality of spacers. In an embodiment, after patterning the sacrificial material, the sacrificial material covers one or more gaps between adjacent spacers. In an embodiment, forming the plurality of spacers over the target layer includes: forming a tri-layer on a spacer layer; patterning a top layer of the tri-layer using lithography; etching a middle layer of the tri-layer through the patterned top layer; etching a bottom layer of the tri-layer through the middle layer; and etching the spacer layer through the bottom layer to form the plurality of spacers. In an embodiment, the method also includes planarizing the conductive material to form a plurality of interconnect lines, where two adjacent interconnect lines of the plurality of interconnect lines have a physical gap separating the two adjacent interconnect lines, the gap being disposed in an area underlying a portion of the sacrificial material, where the portion is left after patterning the sacrificial material.

[0135] A method is provided according to some embodiments. The method includes forming a first cap layer over a second cap layer, the second cap layer over a first mask layer, the first mask layer over a dielectric layer. The method also includes patterning an opening in the first cap layer, the opening having a target width. The method also includes filling the opening with a first material to form a masking element. The method also includes forming a second mask layer over the first cap layer, and patterning the second mask layer to form a first mask, the first mask including a plurality of openings. The method also includes etching the first cap layer and the second cap layer using the first mask and the masking element, wherein the masking element prevents a portion of the second cap layer from being etched. The method also includes patterning the first mask layer through the second cap layer to form a second mask. The method also includes patterning the dielectric layer through the second mask, the patterning of the dielectric layer exposing a conductive feature underlying the dielectric layer. The method also includes forming a wire in the dielectric layer, wherein the wire contacts the conductive feature. In embodiments, the target width of the opening is equal to: 2X + S + 2 x (Z2+ V2)0 5; where 2X is a target width of the opening in a virtual layout, S is half of a bias range 2S, Z is half of a cut width variation 2Z, and V is a distance that a line cut can move between an actual position and a planned position. In embodiments, the target width of the opening is determined by virtually designing a semiconductor device to be formed using a processing system. In embodiments, the masking element is formed of an inorganic material, wherein the inorganic material has a high etch selectivity with respect to a material of the second mask layer. In embodiments, a thickness of the first cap layer is greater than or equal to half of the target width of the opening. In embodiments, an etch stop layer is disposed between the first cap layer and the second cap layer, and a combined thickness of the first cap layer and the etch stop layer satisfies the following relationship: T1 + T2 = T3 x (1 + target OE% / SEL); where T1 is a thickness of the first cap layer, T2 is a thickness of the etch stop layer, T3 is a thickness of the second mask layer, target OE% is a target over-etch percentage for a processing technology, and SEL is an etch selectivity of the second mask layer with respect to the etch stop layer. In embodiments, the masking element is consumed during the patterning of the second mask layer.

[0136] A device is provided in accordance with some embodiments. The device includes a dielectric layer. The device also includes a power rail extending through the dielectric layer, wherein sidewalls of the power rail include one or more kinks. The device also includes a first set of interconnect lines in the dielectric layer on a first side of the power rail. The device also includes a second set of interconnect lines in the dielectric layer on the first side of the power rail, wherein a first kink of the one or more kinks is positioned laterally between the first set of interconnect lines and the second set of interconnect lines. In embodiments, a spacing between the first set of interconnect lines and the second set of interconnect lines is 85.5 nm or less. In embodiments, the device also includes a third set of interconnect lines in the dielectric layer on a second side of the power rail, the second side opposite the first side, wherein a size of an interconnect line of the first set of interconnect lines is the same as a size of an interconnect line of the second set of interconnect lines, and wherein sidewalls of the first set of interconnect lines are aligned with sidewalls of the second set of interconnect lines. In embodiments, all contacts to the power rail are formed a minimum distance from an edge of the power rail.

[0137] The foregoing has outlined rather generally the features of several embodiments in order that the detailed description that follows can be better understood. Those skilled in the art will appreciate that they can readily use the present application as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages that of the embodiments introduced herein. Those skilled in the art will realize that such equivalent constructions do not depart from the spirit and scope of the present application and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present application.

Claims

1. A semiconductor device comprising: a dielectric layer; a power rail extending through the dielectric layer, wherein a sidewall of the power rail comprises one or more kinks; a first set of interconnect lines on a first side of the power rail and in the dielectric layer; and a second set of interconnect lines on the first side of the power rail and in the dielectric layer, wherein a first kink of the one or more kinks is positioned laterally between the first set of interconnect lines and the second set of interconnect lines, wherein a spacing between the first set of interconnect lines and the second set of interconnect lines is less than 85.5 nm, wherein all contacts to the power rail are formed a minimum distance from an edge of the power rail, the minimum distance being 5 nm to 10 nm.

2. The semiconductor device of claim 1, wherein, a pitch between the first set of interconnect lines and the second set of interconnect lines is 85.5 nm or more.

3. The semiconductor device of claim 1, further comprising: a third set of interconnect lines on a second side of the power rail and in the dielectric layer, the second side being opposite the first side, wherein a width of an interconnect line in the first set of interconnect lines is the same as a width of an interconnect line in the second set of interconnect lines, and wherein sidewalls of the first set of interconnect lines in a length direction are aligned with sidewalls of the second set of interconnect lines in the length direction.

4. The semiconductor device of claim 1, wherein, the power rail comprises a contact-free zone at the sidewall of the power rail, the contact-free zone extending from the sidewall of the power rail to a distance of 5 nm to 10 nm from the power rail.

5. A semiconductor device comprising: a dielectric layer; a power rail extending through the dielectric layer, the power rail having a first sidewall and a second sidewall in a plan view, the first sidewall having a first kink; and a first set of islands in the dielectric layer, the first sidewall of the power rail facing the first set of islands, the first set of islands comprising a first island and a second island, the first kink being positioned laterally between the first island and the second island, wherein a spacing between the first island and the second island is less than 85.5 nm, wherein the first kink extends from the first sidewall of the power rail into the power rail to a first distance, wherein the power rail is free of contacts within the first distance from the first sidewall.

6. The semiconductor device of claim 5, further comprising: a second set of islands in the dielectric layer, the power rail being interposed between the first set of islands and the second set of islands. the second sidewall of the power rail has a second kink.

7. The semiconductor device of claim 6, wherein, the second set of islands comprises a third island and a fourth island, the second kink being interposed laterally between the third island and the fourth island.

8. The semiconductor device of claim 7, wherein, the first kink is interposed laterally between the third island and the fourth island.

9. The semiconductor device of claim 8, wherein, the first distance is 5 nm to 8 nm.

10. The semiconductor device of claim 5, wherein, the second kink extends from the second sidewall of the power rail into the power rail to a second distance, wherein the power rail is free of contacts within the second distance from the second sidewall.

11. The semiconductor device of claim 7, wherein, ​ 12. The semiconductor device of claim 5, wherein a pitch between the first island and the second island is 85.5 nm or more.

13. A semiconductor device, comprising: a dielectric layer; a power rail extending through the dielectric layer, the power rail having a first sidewall and a second sidewall in a plan view, the first sidewall having a first kink; and a first set of islands in the dielectric layer on a first side of the power rail, the first set of islands including a first island and a second island, a first end of the first island being in a first plane, a second end of the second island being in a second plane, the first kink being between the first plane and the second plane, wherein the first end of the first island and the second end of the second island are adjacent and opposite each other, a separation between the first plane and the second plane being less than 85.5 nm, wherein the power rail includes a contactless zone at the first sidewall of the power rail, the contactless zone extending from the first sidewall of the power rail to a distance of 5 nm to 10 nm in the power rail.

14. The semiconductor device of claim 13, further comprising: a second set of islands in the dielectric layer on a second side of the power rail, the second set of islands including a third island and a fourth island, the second sidewall of the power rail having a second kink, the second kink being between the first plane and the second plane.

15. The semiconductor device of claim 13, further comprising: a second set of islands in the dielectric layer on a second side of the power rail, the second set of islands including a third island and a fourth island, a third end of the third island being in a third plane, a fourth end of the fourth island being in a fourth plane, and the third end of the third island and the fourth end of the fourth island being adjacent and opposite each other, the second sidewall of the power rail having a second kink, the second kink being between the third plane and the fourth plane, the second side of the power rail being free of kinks between the first plane and the second plane.

16. The semiconductor device of claim 13, wherein, the first kink extending into the power rail to a distance of 5 nm to 8 nm.

17. The semiconductor device of claim 13, wherein, the first kink having a surface closest to the second sidewall in a third plane, the third plane being parallel to the first sidewall, the power rail being free of contacts between the first sidewall and the third plane.

18. The semiconductor device of claim 17, wherein, a distance between the first sidewall and the third plane being between 5 nm and 8 nm.

19. The semiconductor device of claim 13, further comprising one or more additional kinks in the first sidewall of the power rail.

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