Semiconductor device and method of forming the same

Abstract

A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate layer above the fin; and patterning the gate layer in a plasma etch tool using a plasma etch process to form a gate above the fin, wherein patterning the gate layer includes alternating turning on and off a top radio frequency (RF) source of the plasma etch tool during the plasma etch process; and alternating turning on and off a bottom RF source of the plasma etch tool during the plasma etch process, wherein there is a timing offset between a first time at which the top RF source is turned on and a respective second time at which the bottom RF source is turned on. Embodiments of the invention also relate to a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the continuous increase in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, repeatedly reducing the size of the smallest component can thus increase integration density, allowing more components to be integrated into a given area.

[0003] FinFET devices are increasingly being used in integrated circuits. A FinFET device has a three-dimensional structure that includes semiconductor fins protruding from a substrate. A gate structure, configured to control the flow of charge carriers within the conductive channels of the FinFET device, surrounds the semiconductor fins. For example, in a tri-gate FinFET device, the gate structure surrounds three sides of the semiconductor fin, thereby forming conductive channels on the three sides of the semiconductor fin. Summary of the Invention

[0004] According to one aspect of the present invention, a method for forming a semiconductor device is provided, the method comprising: forming a protruding fin over a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, wherein the patterned gate layer comprises: alternately turning on and off a top radio frequency source of the plasma etching tool during the plasma etching process; and alternately turning on and off a bottom radio frequency source of the plasma etching tool during the plasma etching process, wherein there is a timing offset between a first moment when the top radio frequency source is turned on and a corresponding second moment when the bottom radio frequency source is turned on.

[0005] According to another aspect of the present invention, a method for forming a semiconductor device is provided, the method comprising: forming a gate layer over a fin protruding above a substrate; forming a patterned mask over the gate layer; and etching the gate layer through the patterned mask to form a gate by performing a plasma etching process in a plasma etching tool, wherein the plasma etching tool has a top radio frequency power supply configured to generate plasma and a bottom radio frequency power supply configured to provide a bias voltage for etching, wherein etching the gate layer comprises: turning the top radio frequency power supply on and off at a first frequency, wherein the top radio frequency power supply has a first duty cycle during the plasma etching process; and turning the bottom radio frequency power supply on and off at the first frequency, wherein the bottom radio frequency power supply has a second duty cycle during the plasma etching process.

[0006] According to another aspect of the present invention, a semiconductor device is provided, comprising: a fin projecting over a substrate; a gate structure located over the fin; a gate spacer along a sidewall of the gate structure, wherein a bottom surface of the gate spacer facing the substrate extends closer to the substrate than an upper surface of the fin away from the substrate; and a source / drain region at least partially in the fin and adjacent to the gate spacer. Attached Figure Description

[0007] When with attachment Figure 1 When reading this invention, the various aspects will be best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A perspective view of a FinFET device according to some embodiments is shown.

[0009] Figures 2 to 13 and 14A to Figure 14C Various views of the FinFET device 100 are shown at various stages of manufacturing according to an embodiment.

[0010] Figure 15 A cross-sectional view of the plasma etching tool in the embodiment is shown.

[0011] Figures 16 to 20 Show control Figure 15 Various embodiments of methods for radio frequency (RF) power supplies for plasma etching tools.

[0012] Figure 21 The embodiment shown is in Figures 14A to 14C The diagram shows a cross-sectional view of a portion of the processed FinFET device 100.

[0013] Figure 22 The effects of adjusting the duty cycle of the RF source of the plasma etching tool used to form the gate structure on the structure of the FinFET device 100 are shown in some embodiments.

[0014] Figures 23 to 25 Cross-sectional views of various embodiments of gate structures formed by using different duty cycles of plasma etching tools to form the gate structure are shown.

[0015] Figure 26 , Figure 27 , Figure 28A , Figure 28B , Figure 29A , Figure 29B , Figure 30 , Figure 31 , Figure 32A and Figure 32BIllustrations according to embodiments Figures 14A to 14C A cross-sectional view of the FinFET device 100 during the additional manufacturing stage following the processing.

[0016] Figure 28C Examples shown Figure 28A A cross-sectional view of an optional embodiment of the FinFET device 100.

[0017] Figures 33 to 36 Cross-sectional views of the FinFET device 100A are shown at various stages of manufacturing according to an embodiment.

[0018] Figure 37 A flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments is shown. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various components of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, or embodiments where an additional component is formed between the first component and the second component such that the first component and the second component are not in direct contact.

[0020] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other) element or component as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. Throughout this discussion, unless otherwise stated, the same or similar reference numerals in different figures refer to the same or similar elements formed using the same or similar materials and the same or similar forming processes. Additionally, figures with the same numerals but different letters (e.g., 14A and 14B) show various views of the same device at the same processing stage.

[0021] Embodiments of the invention are discussed in the context of forming FinFET devices, and particularly in the context of controlling (e.g., adjusting) the profile (e.g., shape, volume) of the epitaxial source / drain regions of the FinFET device by controlling the amount of fin loss during the formation of the gate structure (e.g., dummy gate structure). Although the disclosed embodiments are discussed using FinFET devices as examples, the disclosed methods can also be used in other types of devices such as planar devices.

[0022] Figure 1 An example of a FinFET 30 is shown in perspective. The FinFET 30 includes a substrate 50 and a fin 64 projecting over the substrate 50. An isolation region 62 is formed on the opposite side of the fin 64, with the fin 64 projecting over the isolation region 62. A gate dielectric 66 runs along the sidewalls and is above the top surface of the fin 64, and a gate 68 is above the gate dielectric 66. A source / drain region 80 is located in the fin 64 and on the opposite side of the gate dielectric 66 and the gate 68. Figure 1 The reference cross sections used in the following figures are further illustrated. Cross section BB extends along the longitudinal axis of the gate 68 of the FinFET 30. Cross section AA is perpendicular to cross section BB and is along the longitudinal axis of the fin 64 in the direction of current flow, for example, between the source / drain regions 80. Cross section CC is parallel to cross section BB and spans the source / drain regions 80. Cross section DD is parallel to cross section AA but is outside the boundaries (e.g., sidewalls) of the fin 64. For clarity, the following figures refer to these reference cross sections.

[0023] Figures 2 to 13 and 14A to Figure 14C Various views (e.g., cross-sectional views, perspective views) of the FinFET device 100 at different stages of manufacturing according to an embodiment are shown. The FinFET device 100 is similar to Figure 1 It is a FinFET 30, but with multiple fins and multiple gate structures. Figures 2 to 4 A cross-sectional view of the FinFET device 100 along section BB is shown. Figures 5 to 13 and Figure 14A A cross-sectional view of the FinFET device 100 along section AA is shown. Figure 14B A cross-sectional view of the FinFET device 100 along section BB is shown. Figure 14C A perspective view of the FinFET device 100 is shown.

[0024] Figure 2A cross-sectional view of substrate 50 is shown. Substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate that is typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of substrate 50 may include germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0025] refer to Figure 3 Using techniques such as photolithography and etching to... Figure 2 The substrate 50 shown is patterned. For example, a mask layer, such as a pad oxide layer 52 and an overlying pad nitride layer 56, is formed over the substrate 50. The pad oxide layer 52 may be a thin film comprising, for example, silicon oxide formed using a thermal oxidation process. The pad oxide layer 52 may serve as an adhesion layer between the substrate 50 and the overlying pad nitride layer 56. In some embodiments, the pad nitride layer 56 is formed of silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof, and may be formed using, for example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0026] Photolithography can be used to pattern the mask layer. Typically, photolithography utilizes a photoresist material (not shown), which is deposited, irradiated (exposed), and developed to remove a portion of the photoresist. The remaining photoresist material protects underlying materials, such as the mask layer, from subsequent processing steps such as etching. In this example, the photoresist material is used to pattern the pad oxide layer 52 and the pad nitride layer 56 to form a patterned mask 58, such as... Figure 3 As shown.

[0027] The patterning mask 58 is then used to pattern the exposed portions of the substrate 50 to form trenches 61, thereby defining semiconductor fins 64 (e.g., 64A and 64B) between adjacent trenches 61, such as Figure 3As shown. In some embodiments, trenches are etched in the substrate 50 to form semiconductor fins 64 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching may be anisotropic. In some embodiments, trenches 61 may be parallel to each other and closely spaced relative to each other (viewed from top). In some embodiments, trenches 61 may be continuous and surround semiconductor fins 64. Semiconductor fins 64 may also be referred to fin 64 hereinafter.

[0028] Fin 64 can be patterned using any suitable method. For example, fin 64 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography with a self-aligned process, thereby allowing the creation of patterns with, for example, a spacing smaller than that that could be obtained using a single direct photolithography method. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers or material can then be used to pattern the fin.

[0029] Figure 4 This illustration shows the formation of an insulating material between adjacent semiconductor fins 64 to form an isolation region 62. The insulating material can be an oxide, such as silicon oxide, nitrides, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to transform it into another material, such as an oxide), or a combination thereof. Other insulating materials and / or other formation processes can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. Planarization processes such as chemical mechanical polishing (CMP) remove any excess insulating material and form the top surface of the isolation region 62 and the top surface of the coplanar (not shown) semiconductor fins 64. Patterned mask 58 (see...) Figure 3 It can also be removed through a planarization process.

[0030] In some embodiments, the isolation region 62 includes a pad, such as a pad oxide (not shown), at the interface between the isolation region 62 and the substrate 50 / semiconductor fin 64. In some embodiments, the pad oxide is formed to reduce crystal defects at the interface between the substrate 50 and the isolation region 62. Similarly, the pad oxide can also be used to reduce crystal defects at the interface between the semiconductor fin 64 and the isolation region 62. The pad oxide (e.g., silicon oxide) can be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 50, but other suitable methods can also be used to form the pad oxide.

[0031] Next, isolation region 62 is recessed to form shallow trench isolation (STI) region 62. The isolation region 62 is recessed such that the upper portion of semiconductor fin 64 protrudes between adjacent STI regions 62. The top surface of STI region 62 may have a flat surface, a convex surface, a concave surface (such as a recess), or a combination thereof, as shown. The top surface of STI region 62 may be formed as flat, convex, and / or concave by appropriate etching. Acceptable etching processes can be used to recess isolation region 62, such as etching processes that are selective to the material of isolation region 62. For example, dry etching or wet etching using dilute hydrofluoric acid (dHF) can be performed to recess isolation region 62.

[0032] After the fin 64 is formed, a gate dielectric 66 is formed over the fin 64, for example, by a thermal oxidation process. The gate dielectric 66 is later removed in a gate replacement process and is therefore also referred to as a pseudo-gate dielectric 66. Figure 4 In the example shown, the gate dielectric 66 is formed over the fin 64 (e.g., over the upper surface and sidewalls of the fin 64) rather than over the STI region 62. In other embodiments, the gate dielectric 66 may be formed, for example, by depositing gate dielectric material over the fin 64 and over the STI region 62. These and other variations are fully intended to be included within the scope of the invention.

[0033] Figures 2 to 4 An embodiment of forming fin 64 is shown, but the fin can be formed using various different processes. For example, the top portion of substrate 50 can be replaced with a suitable material, such as an epitaxial material suitable for the intended type of semiconductor device to be formed (e.g., N-type or P-type). Subsequently, substrate 50 having epitaxial material on top is patterned to form semiconductor fin 64 including epitaxial material.

[0034] As another example, a dielectric layer can be formed above the top surface of the substrate; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed so that the homoepitaxial structures protrude from the dielectric layer to form fins.

[0035] In yet another example, a dielectric layer can be formed above the top surface of the substrate; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using a material different from the substrate; and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form fins.

[0036] In embodiments where epitaxial materials or structures (e.g., heteroepitaxial or homoepitaxial structures) are grown, the grown material or structure can be doped in situ during growth, which eliminates the need for prior and subsequent implantation, although in-situ and implantation doping can be used together. Furthermore, it may be advantageous to epitaxially grow a material different in the NMOS region from the material in the PMOS region. In various embodiments, fin 64 may include silicon-germanium (Si... x Ge 1-x (where x can be between 0 and 1), silicon carbide, pure or nearly pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0037] Figures 5 to 14A This illustrates the use of a dual patterning technique to form a dummy gate 68 over a semiconductor fin 64. The dummy gate 68 and the dummy gate dielectric 66 are collectively referred to herein as the dummy gate structure 75. Note that, for simplicity, Figures 5 to 14A Not all functions are shown. For example, in Figures 5 to 14A The substrate 50 of the FinFET device 100 is not shown in the figure.

[0038] Now for reference Figure 5 A gate layer 68 is formed over a gate dielectric 66, which may be a semiconductor layer such as an amorphous silicon (a-Si) layer. Next, a dielectric layer 33 (e.g., a silicon carbon nitride (SiCN) layer) and a dielectric layer 35 (e.g., a silicon oxide (SiO) layer) are sequentially formed over the gate layer 68. In some embodiments, dielectric layers 33 and 35 are formed of different materials and may be used as hard mask layers and / or etch stop layers in subsequent etching processes to pattern the gate layer 68. Next, a core layer 36, such as an a-Si layer, is formed over the dielectric layer 35. To form each of the above layers (e.g., 68, 33, 35, and 36), a suitable deposition method may be used, such as CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0039] Next, in Figure 6 In this process, a photoresist layer is formed above the core layer 36, such as a three-layer photoresist layer including a bottom layer 37 (e.g., a bottom anti-reflective coating (BARC)), an intermediate layer 38 (e.g., an intermediate mask layer), and a top photoresist layer 39. Next, the top photoresist layer 39 is patterned, for example, using photolithography and patterning techniques, to form a patterned top photoresist layer 39.

[0040] Next, in Figure 7In this process, an oxide layer 41 is conformally formed over the patterned top photoresist layer 39 and the intermediate layer 38. In some embodiments, the oxide layer 41 is a silicon oxide layer formed by a low-temperature deposition process (e.g., a low-temperature ALD process). In some embodiments, the temperature of the low-temperature deposition process is between about 80°C and about 150°C, such as 100°C. The low temperature used in the deposition process helps to avoid damage to the patterned top photoresist layer 39. As an example, the thickness of the oxide layer 41 may be between a few angstroms and tens of angstroms (e.g., between 2 angstroms and 20 angstroms). In some embodiments, the oxide layer 41 protects / reinforces the sidewalls of the patterned top photoresist layer 39, such as after a subsequent etching process (which uses the patterned top photoresist layer 39 as an etching mask), the mandrel 36 (see Figure 8 The resulting structure has smooth (e.g., straight) sidewalls.

[0041] Next, in Figure 8 In this process, one or more anisotropic etching processes, such as dry etching (e.g., plasma etching), are performed to pattern the mandrel layer 36, and after the anisotropic etching processes, the patterned mandrel layer forms the mandrel 36. Figure 8 As shown, the pattern of the patterned top photoresist layer 39 is transferred onto the mandrel 36.

[0042] Next, in Figure 9 In this configuration, a spacer layer 42 is conformally formed above the mandrel 36 and above the dielectric layer 35. In some embodiments, the spacer layer 42 is a silicon nitride layer formed by a suitable formation method such as PVD, CVD, or ALD. As an example, the thickness of the spacer layer 42 may be, for example, about 260 angstroms.

[0043] Next, in Figure 10 In this process, an isotropic etching process is performed to remove the horizontal portions of the spacer layer 42 (e.g., the portions above the upper surface of the mandrel 36 and above the upper surface of the dielectric layer 35). The isotropic etching process also removes the mandrel 36. The remaining portions of the spacer layer 42, arranged along the sidewalls of the mandrel 36, form the spacer 42.

[0044] Next, in Figure 11 In the middle, it is possible Figure 10 A photoresist layer (e.g., three photoresist layers) is formed over the structure, which may include a bottom layer 43, an intermediate layer 44, and a top photoresist layer 45. The top photoresist layer 45 is then patterned, for example, using photolithography and etching techniques. Figure 11 In one example, the width of the patterned top photoresist layer 45 (e.g., the distance between its sidewalls) is greater than the width of the spacer 42, allowing dummy gates with different widths to be formed (see [example missing]). Figure 14AThe 68A and 68B in the series can be advantageously adapted to different design requirements to achieve different performance parameters of the device formed in different regions of the FinFET device 100.

[0045] Next, in Figure 12 In this process, an anisotropic etching process (e.g., plasma etching) is performed to transfer the pattern of the spacer 42 and the patterned top photoresist layer 45 to the dielectric layers 35 and 33. Figure 12 As shown, a portion of the spacer 42 may remain above the patterned dielectric layer 35.

[0046] Next, in Figure 13 In this process, appropriate deposition methods such as ALD, PVD, and CVD are used to... Figure 12 An oxide capping layer 47 (e.g., a silicon oxide layer) is conformally formed above the structure. Figure 7 Unlike the oxide layer 41 in the previous example, no oxide capping layer 47 is formed over the photoresist layer, and therefore, a high-temperature deposition process (e.g., between 300°C and 500°C) can be performed to form the oxide capping layer 47 and achieve a faster deposition rate. As an example, the thickness of the oxide capping layer 47 can be between a few angstroms and tens of angstroms, such as about 20 angstroms. In some embodiments, the oxide capping layer 47 protects / reinforces the sidewalls of the patterned dielectric layers 33 / 35, such as the gate 68 formed after a subsequent etching process (see...). Figure 14A It has an improved profile with smooth (e.g., straight) sidewalls.

[0047] Next, in Figure 14A In the process, an anisotropic etching process is performed to pattern the gate layer 68. Patterned dielectric layers 35 and 33 are used as a mask 70 in the anisotropic etching process to pattern the gate layer 68. After the anisotropic etching process, the remaining portion of the gate layer 68 forms dummy gates 68 (e.g., 68A and 68B). Note that, as mentioned above, dummy gate 68B has a larger width than dummy gate 68A to accommodate different design requirements. For simplicity, dummy gates 68 are shown as having the same width in the following figures; it should be understood that dummy gates 68 may have different widths in different regions of the device. After the anisotropic etching process, the gate dielectric 66 is exposed. Figure 14B Shown along section BB Figure 14A FinFET device 100. Figure 14C A perspective view of the FinFET device 100 is shown.

[0048] In some embodiments, the anisotropic etching process for patterning the gate layer 68 is a plasma etching process comprising multiple etching steps performed in sequence, and therefore may also be referred to as a multi-step plasma etching process. Reference will then be made to... Figure 14Cand Figures 15 to 20 This paper discusses the details of this multi-step plasma etching process.

[0049] exist Figure 14C The diagram shows four distinct positions L1, L2, L3, and L4 along the vertical direction of the dummy gate 68, where each of positions L1, L2, L3, and L4 corresponds to a plane parallel to the upper surface of the substrate 50 (see Figure 1). Figure 14B ). Figure 14C The fin top position FT is further shown, indicating the location of the top surface of fin 64 away from the substrate 50. In some embodiments, position L1 is located 50 nm above the top surface of fin 64. Position L2 is located 25 nm above the top surface of fin 64. Position L3 is located 20 nm below the top surface of fin 64. Position L4 is located 54 nm below the top surface of fin 64.

[0050] In some embodiments, the multi-step plasma etching process includes a first etching step, a second etching step, a third etching step, a fourth etching step, a fifth etching step, and a sixth etching step. The first etching step, also referred to as the Master Etching 1 (ME1) step, is performed to recess the gate layer 68 not covered by the mask 70 (e.g., not directly beneath it) from its top surface 68T to position L1. In other words, the ME1 step stops when position L1 is reached. In some embodiments, the ME1 etching step is a plasma etching process performed using a gas source comprising tetrafluoromethane (CF4), hydrogen bromide (HBr), and chlorine (Cl2). Compared to the third, fourth, and fifth etching steps, the ME1 etching step has a higher etching rate and is performed to rapidly remove the upper portion of the gate layer 68 not covered by the mask 70.

[0051] Following the ME1 etching step, a plasma process known as oxygen flushing is performed to oxidize the sidewalls of the gate layer 68. In some embodiments, oxygen flushing is performed by evacuating the gases, plasma, and / or byproducts of the previous etching step from the processing chamber (e.g., the chamber of a plasma etching tool), and then supplying oxygen plasma to the gate layer 68 such that an oxide (e.g., SiO) forms on the exposed sidewalls of the gate layer 68. The oxide (e.g., SiO) formed by oxygen flushing advantageously protects (e.g., strengthens) the sidewalls of the gate layer 68, resulting in a pseudo-gate 68 with an improved (e.g., straighter) sidewall profile. After oxygen flushing is complete, the oxygen plasma can be evacuated from the processing chamber.

[0052] Next, a second etching step, also known as the main etch 2 (ME2) step, is performed to further recess the gate layer 68 not covered by the mask 70 (e.g., not directly beneath it) to location L2. In other words, the ME2 step stops when location L2 is reached. In some embodiments, the ME2 step is the same plasma etching process as the ME1 step; for example, the ME2 step is performed using a gas source comprising CF4, HBr, and Cl2.

[0053] After the ME2 step is completed, a plasma process known as carbon dioxide (CO2) rinsing is performed to oxidize the sidewalls of the gate layer 68. In some embodiments, CO2 rinsing is performed by evacuating the processing chamber of the gas, plasma, and / or byproducts from the previous etching step, and then supplying the gate layer 68 with carbon dioxide plasma, such that an oxide (e.g., SiO) forms on the exposed sidewalls of the gate layer 68. The oxide (e.g., SiO) formed by CO2 rinsing advantageously protects (e.g., strengthens) the sidewalls of the gate layer 68, resulting in a pseudo-gate 68 with an improved (e.g., straighter) sidewall profile. After CO2 rinsing is complete, the carbon dioxide plasma can be evacuated from the processing chamber.

[0054] Next, a third etching step, also known as the Smooth Landing 1-1 (SL1-1) step, is performed to further recess the gate layer 68 not covered by the mask 70 (e.g., not directly beneath it) to location L3. In other words, the SL1-1 step stops at location L3. In some embodiments, the SL1-1 step is a plasma etching process performed using a gas source comprising HBr and Cl2. Note that the gas source CF4 used in steps ME1 and ME2 is not used in step SL1-1, which results in a slower etching rate but better control over the sidewall profile of the formed dummy gate 68.

[0055] In some embodiments, during step SL1-1, the top RF power supply 113 of the plasma etching tool 200 for the multi-step plasma etching process (see...) Figure 15 The power of the RF power supply is between approximately 250W and approximately 350W, and the bottom RF power supply 117 (see...) Figure 15 The power (also known as bias power) is between approximately 800W and approximately 900W. See below for reference. Figures 15 to 20 Details are provided regarding the plasma etching tool 200, the top RF power supply 113, and the bottom RF power supply 117. Furthermore, during the SL1-1 step, the volume percentage of HBr in the gas source (e.g., a mixture of HBr and Cl2) is between approximately 60% and 88%, and the volume percentage of Cl2 in the gas source is between approximately 12% and approximately 40%.

[0056] After step SL1-1 is completed, a plasma process known as nitrogen rinsing is performed to form nitrides (e.g., SiN) on the sidewalls of gate layer 68. In some embodiments, nitrogen rinsing is performed by evacuating the processing chamber of gases, plasma, and / or byproducts from the previous etching step, and then supplying nitrogen plasma to gate layer 68, such that nitrides (e.g., SiN) are formed on the exposed sidewalls of gate layer 68. The nitrides (e.g., SiN) formed by nitrogen rinsing advantageously protect (e.g., strengthen) the sidewalls of gate layer 68, resulting in a dummy gate 68 with an improved (e.g., straighter) sidewall profile. After nitrogen rinsing is complete, the nitrogen plasma can be evacuated from the processing chamber.

[0057] In some embodiments, during oxygen flushing, carbon dioxide flushing, and nitrogen flushing processes, byproducts such as polymers are generated and deposited along the sidewalls of the gate layer 68. These byproducts can serve as a protective layer on the sidewalls of the gate layer 68, but may also be more difficult to remove by plasma etching processes (e.g., SL1-1, SL1-2). With advanced semiconductor processing techniques, the space between adjacent fins 64 becomes increasingly smaller, and plasma etching processes (e.g., SL1-1 or SL1-2) become increasingly difficult to reach the bottom of the narrow space between adjacent fins 64. In other words, at the bottom of the narrow space between adjacent fins 64, the plasma etching process may be less efficient (e.g., with a lower etching rate). To compensate for the reduced etching rate at the bottom of the narrow space between adjacent fins 64, the currently disclosed method uses oxygen flushing at location L1 (potentially generating more polymer byproducts), carbon dioxide flushing at location L2 (potentially generating less polymer), and nitrogen flushing at location L3 (potentially generating even fewer polymer byproducts). As a result, the sidewall profile of the formed dummy gate 68 is... Figure 14C The entire vertical direction is well controlled, and the target sidewall profile and performance requirements can be achieved.

[0058] Next, a fourth etching step, also known as the Smooth Landing 1-2 (SL1-2) step, is performed to further recess the gate layer 68 not covered by the mask 70 (e.g., not directly beneath it) to location L4. In other words, the SL1-2 step stops at location L4. In some embodiments, the SL1-2 step is a plasma etching process performed using a gas source comprising HBr and Cl2.

[0059] In some embodiments, during steps SL1-2, the power of the top RF power supply 113 of the plasma etching tool for the multi-step plasma etching process is between about 250 W and about 350 W, and the power of the bottom RF power supply 117 is between about 600 W and about 700 W. Furthermore, during steps SL1-2, the volume percentage of HBr in the gas source (e.g., a mixture of HBr and Cl2) is between about 40% and about 60%, and the volume percentage of Cl2 in the gas source is between 40% and about 60%.

[0060] For steps SL1-1 and SL1-2, the mixing ratio between HBr and Cl2 in the gas source can be calculated by the ratio between the flow rates of HBr and Cl2 to achieve the target sidewall profile of the dummy gate 68. For example, to achieve a wider lower portion (e.g., a wider width between opposing sidewalls) of the dummy gate 68 (see... Figure 23 68L in the middle) and narrower at the top (e.g., having a narrower width between opposite sidewalls) (see Figure 23 The sidewall profile of 68U) in the SL1-1 step can be adjusted to a mixing ratio of HBr and Cl2 to 8:1, and the mixing ratio of HBr and Cl2 in the SL1-2 step can be adjusted to 1.8:1.

[0061] As another example, in order to achieve the pseudo-gate 68 on the upper part (see...) Figure 24 68U in the middle and the lower part (see 68U in the middle) and the lower part (see 68U Figure 24 The 68L) have sidewall profiles of the same width between their opposite sidewalls. The mixing ratio between HBr and Cl2 in step SL1-1 can be adjusted to 3:1, and the mixing ratio between HBr and Cl2 in step SL1-2 can be adjusted to 1:1.

[0062] As yet another example, to achieve a narrower lower section for the dummy gate 68 (see...) Figure 25 (68L in the middle) and wider at the top (see Figure 25 The sidewall profile of 68U) in the SL1-1 step can be adjusted to a mixing ratio of HBr and Cl2 to 1.6:1, and the mixing ratio of HBr and Cl2 in the SL1-2 step can be adjusted to 0.6:1.

[0063] Still referencing Figure 14CAfter steps SL1-2 are completed, a fifth etching step, also known as Smooth Landing 2 (SL2), is performed to remove the remaining portion of the gate layer 68 disposed between adjacent dummy gates 68 (e.g., the remaining portion extending along the upper surface of the isolation region 62 between adjacent dummy gates 68), thereby separating the adjacent dummy gates 68. In some embodiments, step SL2 is a plasma etching process performed using a gas source comprising HBr and Cl2. Step SL2 is similar to steps SL1-2, but with increased bias power. Reference will be made below. Figures 15 to 20 This paper discusses the effects of bias power and the detailed methods for its control.

[0064] Next, a sixth etching step, also known as the bottom removal (DF) step, is performed to remove the portion of the gate layer 68 located at the bottom of the dummy gate 68 (e.g., at the location of the dummy gate 68 contact isolation region 62) and the outer sidewalls of the dummy gate 68. In some embodiments, the DF step is a plasma etching process performed using a gas source including HBr. Unlike steps SL1-1 and SL1-2, Cl2 is not used in the DF step.

[0065] Figure 15 A cross-sectional view of the plasma etching tool 200 in an embodiment is shown. In some embodiments, the plasma etching tool 200 is used to perform a multi-step plasma etching process to form a dummy gate 68. Figure 15 In this example, the plasma etching tool 200 has a housing 115 surrounding a processing chamber. A gas tank 119 stores the processing gas used in the plasma etching. The gas is fed into the processing chamber through a pipe 125 and a valve 123.

[0066] Figure 15 One or more top RF power supplies 113 (also referred to as top RF sources) are further shown arranged above the cover 111 of the plasma etching tool 200. Additionally, a bottom RF power supply 117 (also referred to as a bottom RF source) is electrically coupled to a support 121 of the plasma etching tool 200. The support 121 is used to support the wafer during the plasma etching process, wherein one or more FinFET devices 100 are formed on the wafer.

[0067] In some embodiments, the top RF power supply 113, when turned on, ignites a gas source into plasma used in a plasma etching process. The bottom RF power supply 117, when turned on, provides a bias voltage to the support 121, causing charged particles (e.g., ions) in the plasma to be attracted (e.g., by the electric field induced by the bias voltage) toward the wafer on the support 121. In some embodiments, bombardment of the charged particles on the wafer removes target material (e.g., exposed portions of the gate layer 68).

[0068] Figures 16 to 20 Show control Figure 15 Various embodiments of the radio frequency (RF) power supply for plasma etching tools. Although the disclosed methods can also be used to control RF power sources for other etching steps in a multi-step plasma etching process, each embodiment of the method can be used to control the top RF power supply 113 and the bottom RF power supply 117 during the SL1-1 and SL1-2 steps of the multi-step plasma etching process described above.

[0069] Now for reference Figure 16 , Figure 16 Curve 131 shows the power of the top RF power supply 113, and curve 133 shows the power of the bottom RF power supply 117. Figure 16 In the diagram, the X-axis represents time, and the Y-axis represents power. The times of curve 131 and curve 133 are aligned along the X-axis. For clarity, each curve 131 or 133 has its own zero-power point along the Y-axis. Figure 16 In the diagram, the value HV corresponds to the power when the top RF power is turned on, while the value LV corresponds to the power when the bottom RF power is turned on.

[0070] exist Figure 16 During the plasma etching steps (e.g., SL1-1 and SL1-2), the bottom RF power supply is periodically switched on and off at a predetermined frequency (e.g., between about 0.1 kHz and about 1 kHz) (see curve 133), while the top RF power supply (see curve 131) remains on throughout the plasma etching steps. Figure 16 The diagram shows two consecutive switching cycles of the bottom RF power supply, where each switching cycle (also referred to as an on / off cycle or a cycle) has a duration T, which is the reciprocal of the switching frequency. Throughout the reference... Figures 16 to 20 In the discussion, it is assumed that the top RF power supply and the bottom RF power supply have the same period T or the same switching frequency. For example... Figure 16 As shown, in each switching cycle, the bottom RF power supply is turned on for a predetermined duration T. 导通 Duration T 导通 This is also referred to as the on-time of the corresponding RF power supply (e.g., the bottom RF power supply) during the switching cycle or period T. 导通 The ratio of T to T (e.g., T) 导通 The duty cycle ( / T) is referred to as the duty cycle of the corresponding RF power supply (e.g., the bottom RF power supply). In some embodiments, the duty cycle of the bottom RF power supply is between a few percent (e.g., 4%) and about 20%, such as 4%, 8%, or 12%.

[0071] exist Figure 16 In one embodiment, a bias voltage is applied at the support 121 during the on-time of the bottom RF power supply (see...). Figure 15 Furthermore, the plasma etching exhibits good anisotropy. During each cycle T, anisotropic etching ceases during the off-time of the bottom RF power supply (e.g., when the corresponding RF power supply is turned off), and sufficient time is available for the plasma etching byproducts (e.g., polymers) to be evacuated from the processing chamber of the plasma etching tool 200. Since excessive accumulation of etching byproducts on the dummy gate 68 adversely affects the sidewall profile of the dummy gate 68, this method is less suitable than a reference method where both the top and bottom RF power supplies are continuously on throughout the etching process. Figure 16 The method (referred to as the bias pulse method) achieves a better (e.g., straight) sidewall profile for the formed pseudo-gate 68.

[0072] Figure 17 This illustrates another method (also known as the synchronous pulse method) for controlling the top and bottom RF power supplies during a plasma etching process. Figure 17 In the middle, the top RF power supply and the bottom RF power supply are periodically switched on and off. Figure 17 In this example, the on-time of the top RF power supply (see curve 131) is synchronized (e.g., aligned) with the on-time of the bottom RF power supply (see curve 133). In other words, the top and bottom RF power supplies are turned on and off simultaneously and have the same duty cycle. This means that the top RF power supply generates plasma only when a bias voltage is applied to the support 121 to induce anisotropic etching, and no plasma is generated when no bias voltage is applied to the support 121. This advantageously reduces lateral etching, which can occur when the top RF power supply is on and the bottom RF power supply is off. As a result, Figure 17 The synchronous pulse method shown can achieve improved sidewall profiles (e.g., straight sidewall profiles).

[0073] Figure 18 This illustrates another method (also known as the transition pulse method) for controlling the top and bottom RF power supplies during a plasma etching process. Figure 18 In the middle, the top RF power supply and the bottom RF power supply are periodically switched on and off, and have the same duty cycle. However, in Figure 18 In the example, there is a time offset T between the on-time of the top RF power supply (see curve 131) and the on-time of the bottom RF power supply (see curve 133). Δ In other words, during each switching cycle, the top RF power supply and the bottom RF power supply are switched on and off at different times. Figure 18 In the example, during each switching cycle, at T 导通 The top RF power is turned on for the duration of T, and then turned off; after the top RF power is turned off, at T 导通The bottom RF power is switched on for a specified duration and then switched off. Therefore, in Figure 18 In each switching cycle, the conduction time between the top RF power supply and the bottom RF power supply does not overlap. In other words, the time offset T Δ Greater than Figure 18 T in 导通 In some embodiments, the time offset T Δ Between approximately 5% and approximately 15% of the duration T of each switching cycle.

[0074] The transition pulse method disclosed herein allows some charged particles (e.g., ions, electrons) in the plasma (generated when the top RF power is applied) to recombine and become electrically neutral, thereby reducing the plasma energy before applying a bias voltage (when the bottom RF power is applied) for anisotropic etching. If the plasma energy is too high, some charged particles in the plasma may be difficult to control by the electric field induced by the bias voltage and may travel in directions other than towards the support 121 when the bias voltage is applied, thereby reducing the anisotropy of the plasma etching process. By reducing the plasma energy before applying the bias voltage, the disclosed transition pulse method achieves improved anisotropy in the plasma etching process and a better sidewall profile for the dummy gate 68.

[0075] Figure 19 and Figure 20 Show Figure 18 An alternative embodiment of the transition pulse method. Specifically, Figure 19 This illustrates a transition pulse method, wherein the time offset T between the on-time of the top RF power supply and the on-time of the bottom RF power supply is... Δ Less than the conduction time T 导通 The duration, and the top RF power supply and the bottom RF power supply have the same duty cycle. Figure 20 In the embodiment, the duty cycle of the top RF power supply (corresponding to the on-time T) 导通1 The duty cycle (corresponding to the on-time T) is different from (e.g., smaller than) the bottom RF power supply. 导通2 ).exist Figure 20 In the middle, the time offset T between the conduction time of the top RF power supply and the conduction time of the bottom RF power supply Δ Greater than the conduction time T 导通1 The duration of this time, therefore, the bottom RF power is switched on after the top RF power is switched off. Of course, this is a non-limiting example, and the time offset T... Δ With conduction time T 导通1 Other relationships between them are also possible and are fully intended to be included within the scope of this invention.

[0076] In some embodiments, the transition pulse method disclosed herein (e.g., Figure 18 The SL1-1 and SL1-2 steps of the multi-step plasma etching process are used to form the dummy gate 68. In an embodiment, Figure 21 Shown in Figures 14A to 14C The diagram shows a cross-sectional view along section AA of a portion of the FinFET device 100 after processing using the transition pulse method for the SL1-1 and SL1-2 etching steps. To illustrate the relative positions of the individual elements of the FinFET device 100, Figure 21 The isolation region 62 and the dummy gate 68 are further shown in the lower portion 68L (e.g., along the section DD) outside the boundary of the fin 64, which is not in the section AA and is indicated by dashed lines. Note that the lower portion 68L of the dummy gate 68 is disposed below the upper surface 66U of the gate dielectric 66 and the outer boundary of the fin 64, and the upper portion 68U of the dummy gate 68 is disposed above the upper surface 66U.

[0077] Figure 21 Two dummy gate structures 75 are shown, each dummy gate structure 75 including a dummy gate 68 and an underlying dummy gate dielectric 66. (See diagram) Figure 21 As shown, each dummy gate 68 has a first width W1 measured at the upper surface 66U of the gate dielectric 66, a second width W2 measured at a depth H1 (e.g., 27 nm) from the upper surface 66U, and a third width W3 measured at a depth H2 (e.g., 49 nm) from the upper surface 66U. Figure 21 Also shown is fin loss FL, which represents the depth of a recess 65 formed in the upper surface of the fin 64 between the dummy gates 68 (e.g., the distance between the upper surface 66U and the deepest point of the recess 65), wherein the recess 65 is caused by a multi-step plasma etching process for forming the dummy gates 68.

[0078] By adjusting the process parameters (e.g., duty cycle) of the plasma etching steps (e.g., SL1-1, SL1-2), the size of the dummy gate (e.g., W1, W1, and W3) and the size of the recess 65 (e.g., FL) can be adjusted to achieve the target values. Note that the recess 65 will be further extended in subsequent processing to prepare for the growth of the epitaxial source / drain region 80 (e.g., see...). Figure 28A Since the size of the recess 65 determines the size (e.g., volume) of the epitaxial source / drain region 80, the currently disclosed method (e.g., the transition pulse method) provides an additional tuning knob for tuning the size of the recess 65 used to grow the epitaxial source / drain region 80.

[0079] As semiconductor manufacturing processes continue to advance, component sizes are shrinking. With the distance between adjacent gates 68 becoming increasingly smaller, the spacing between gates 68 may become a major factor determining the size of the recess 65 and the volume of the subsequently formed epitaxial source / drain region 80. After the gates 68 are formed, the ability to adjust the size of the recess 65 used to grow the epitaxial source / drain region 80 may be limited. Currently disclosed methods (e.g., see...) Figures 16 to 20 This allows the size of the recess 65 to be tuned when the gate 68 is formed, thus providing an additional way to manipulate the volume of the epitaxial source / drain region 80 by adjusting the process parameters used to form the gate 68.

[0080] Figure 22 The dimensions of a FinFET device 100 are shown according to some embodiments when a transition pulse method is used in the SL1-1 and SL1-2 steps of a multi-step plasma etching process. Figure 22 In the process, the distance H3 between the upper surface 66U of the EPI growth indicator gate dielectric 66 and the upper surface 80U of the subsequently formed epitaxial source / drain region 80 (see...) Figure 28A A positive value of H3 indicates that the upper surface 80U is higher than the upper surface 66U (e.g., further from the substrate 50), and a negative value of H3 means that the upper surface 80U is higher than the upper surface 66U. Figure 22 The outline of the dummy gate 68 (labeled as the Poly outline) and the outline of the subsequently formed metal gate (labeled as the metal gate outline) are also shown. A transition pulse method with a duty cycle of 4% in step SL1-1 and a duty cycle of 7% in step SL1-2 is used as a reference data point. Figure 22 The results are shown for three additional transition pulse methods with duty cycles of 4%, 8%, and 12% for SL1-1 and SL1-2 steps. It can be seen that by adjusting the duty cycle, different shapes and sizes of various components for the FinFET device 100 can be achieved.

[0081] Figures 23 to 25 A cross-sectional view of a portion of a FinFET device 100 is shown, using different process parameters (e.g., duty cycle) for steps SL1-1 and SL1-2. Figures 23 to 25 The cross-sectional diagram in the middle is similar to Figure 21 . Figure 23 This corresponds to a 4% duty cycle for steps SL1-1 and SL1-2, which corresponds to... Figure 22 The example shown is 4% / 4%. Figure 24 This corresponds to an 8% duty cycle for steps SL1-1 and SL1-2, which corresponds to... Figure 22 The example shown is 8% / 8%. Figure 25 This corresponds to a 12% duty cycle for steps SL1-1 and SL1-2, which corresponds to Figure 22The example shown is 12% / 12%. In Figures 23 to 25 In the example shown, fin loss (e.g., the depth of groove 65) increases with increasing duty cycle. Figure 23 In this configuration, the dummy gate 68 has a wider lower portion 68L and a narrower upper portion 68U. Figure 24 In this configuration, the dummy gate 68 has straight sidewalls (e.g., the lower portion 68L has the same width as the upper portion 68U). Figure 25 In the middle, the dummy gate 68 has a narrower lower portion 68L and a wider upper portion 68U.

[0082] Figure 26 , Figure 27 , Figure 28A , Figure 28B , Figure 29A , Figure 29B , Figure 30 , Figure 31 , Figure 32A and Figure 32B Illustrations according to embodiments Figures 14A to 14C A cross-sectional view of the FinFET device 100 during the additional manufacturing stage following the processing. Figure 26 , Figure 27 , Figure 28A , Figure 29A , Figure 30 , Figure 31 and Figure 32A This is a cross-sectional view along section AA. Figure 28B It is a cross-sectional view along section CC. Figure 29B and Figure 32B This is a cross-sectional view along section BB.

[0083] exist Figure 26 In this process, a spacer layer 87 is formed (e.g., conformally formed) over the dummy gate structures 75 (e.g., 75A, 75B, and 75C) and over the fins 64. The spacer layer 87 may be formed of materials such as silicon nitride, silicon oxynitride, silicon carbonitride, nitride, or combinations thereof, and may be formed using, for example, thermal oxidation, CVD, or other suitable deposition processes. Figure 26 Examples show that there is almost no fin loss after a multi-step plasma etching process. Figures 33 to 36 The discussion therein illustrates another embodiment of fin loss following a multi-step plasma etching process.

[0084] Next, as Figure 27As shown, a recess 86 is formed in the fin 64 adjacent to (e.g., between and / or immediately adjacent to) the dummy gate structure 75. In some embodiments, the recess 86 is formed by an anisotropic etching process, for example, using the dummy gate structure 75 as an etching mask, but any other suitable etching process may also be used. In some embodiments, the recess 65 (e.g., see...) is formed by... Figures 23 to 25 It extends further into the fin 64 to form a groove 86.

[0085] Next, as Figure 28A As shown, a source / drain region 80 is formed in the groove 86. The source / drain region 80 is formed by epitaxially growing material in the groove 88 using a suitable method such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or a combination thereof.

[0086] like Figure 28A As shown, the epitaxial source / drain region 80 may have a surface that protrudes from the corresponding surface of the fin 64 (e.g., protrudes above the non-recessed portion of the fin 64) and may have a facet. The source / drain regions 80 of adjacent fins 64 may merge to form a continuous epitaxial source / drain region 80 (see...). Figure 28B In some embodiments, the source / drain regions 80 of adjacent fins 64 do not merge together, but remain separate source / drain regions 80 (see...). Figure 28C In some embodiments, the resulting FinFET is an n-type FinFET, and the source / drain region 80 includes silicon carbide (SiC), silicon phosphide (SiP), phosphorus-doped silicon carbide (SiCP), etc. In some embodiments, the resulting FinFET is a p-type FinFET, and the source / drain region 80 includes SiGe and p-type impurities, such as boron or indium.

[0087] The epitaxial source / drain region 80 can be implanted with dopants to form the source / drain region 80, followed by an annealing process. The implantation process may include forming and patterning a mask, such as a photoresist, to cover the area of ​​the FinFET device 100 that will be protected from the implantation process. The source / drain region 80 may have a diameter between approximately 1E19 cm. -3 Approximately 1E21 cm -3 The concentration of impurities (e.g., dopants) is within a certain range. P-type impurities, such as boron or indium, can be implanted into the source / drain region 80 of the P-type transistor. N-type impurities, such as phosphorus or arsenide, can be implanted into the source / drain region 80 of the N-type transistor. In some embodiments, the epitaxial source / drain region can be doped in situ during growth.

[0088] Next, as Figure 29A As shown, in Figure 28A A contact etch stop layer (CESL) 89 is formed over the structure shown. CESL 89 serves as an etch stop layer in subsequent etch processes and may include suitable materials such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, and may be formed by suitable formation methods such as CVD, PVD, or combinations thereof.

[0089] Next, a first interlayer dielectric (ILD) 90 is formed over CESL 89 and over the dummy gate structures 75 (e.g., 75A, 75B, and 75C). In some embodiments, the first ILD 90 is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or undoped silicate glass (USG) and can be formed by suitable formation methods such as CVD, PECVD, or FCVD. A planarization process such as CMP can be performed to remove the mask 70 and the portion of CESL 89 disposed over the gate 68. After the planarization process, the top surface of the first ILD 90 is flush with the top surface of the gate 68.

[0090] Figure 29B Show Figure 29A The diagram shows a cross-sectional view of the FinFET device 100, but along section BB. (As shown) Figure 29B As shown, gate 68 is disposed above fins 64A and fin 64B and extends continuously from fin 64A to fin 64B. Gate spacer 87 is formed between gate 68 and the first ILD 90. Subsequently, a post-gate process (sometimes referred to as a replacement gate process) is performed to replace the dummy gate 68 and dummy gate dielectric 66 with an active gate (also referred to as a replacement gate or metal gate) and an active gate dielectric material.

[0091] Next reference Figure 30 The dummy gate structures 75A, 75B, and 75C are replaced with active gate structures 97A, 97B, and 97C, respectively. According to some embodiments, to form the active gate structure 97 (e.g., 97A, 97B, or 97C), the gate 68 and the gate dielectric 66 directly beneath the gate 68 are removed during an etching step, such that trenches (not shown) are formed between the gate spacers 87. Each trench exposes a channel region of the corresponding fin 64. During dummy gate removal, the dummy gate dielectric layer 66 can be used as an etch stop layer when the dummy gate 68 is etched. The dummy gate dielectric layer 66 can then be removed after the dummy gate 68 has been removed.

[0092] Next, a gate dielectric layer 94, a barrier layer 96, a work function layer 98, and a gate electrode 99 are formed in a recess for replacing the gate 97. The gate dielectric layer 94 is conformally deposited in the recess, such as on the top surface and sidewalls of the fin 64, on the sidewalls of the gate spacer 87, and on the top surface of the first ILD 90 (not shown). According to some embodiments, the gate dielectric layer 94 comprises silicon oxide, silicon nitride, or a multilayer thereof. In other embodiments, the gate dielectric layer 94 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 94 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. Methods for forming the gate dielectric layer 94 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc.

[0093] Next, a barrier layer 96 is conformally formed over the gate dielectric layer 94. The barrier layer 96 may include a conductive material such as titanium nitride, but alternatively, other materials such as tantalum nitride, titanium, or tantalum may be used. The barrier layer 96 may be formed using a CVD process such as PECVD. However, alternatively, other methods such as sputtering, metal-organic chemical vapor deposition (MOCVD), or ALD may be used.

[0094] Next, a work function layer 98, such as a P-type work function layer or an N-type work function layer, is formed in a recess above the barrier layer 96. Exemplary P-type work function metals that may be included in the gate structure of a P-type device include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function materials, or combinations thereof. Exemplary N-type work function metals that may be included in the gate structure of an N-type device include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof. The work function value is associated with the material composition of the work function layer; therefore, the material of the work function layer is selected to tune its work function value so that a target threshold voltage Vt is achieved in the device to be formed. The work function layer can be deposited by CVD, physical vapor deposition (PVD), and / or other suitable processes.

[0095] Next, a seed layer (not shown) is conformally formed over the barrier layer 96. The seed layer may include copper, titanium, tantalum, titanium nitride, tantalum nitride, or combinations thereof, and may be deposited by ALD, sputtering, PVD, or the like. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. For example, the seed layer includes a titanium layer and a copper layer above the titanium layer.

[0096] Next, a gate electrode 99 is deposited over the seed layer and fills the remaining portion of the trench. The gate electrode 99 can be made of a metallic material such as Cu, Al, W, a combination thereof, or multiple layers thereof, and can be formed by, for example, electroplating, electroless plating, or other suitable methods. After forming the gate electrode 99, a planarization process such as CMP can be performed to remove excess portions of the gate dielectric layer 94, barrier layer 96, work function layer 98, seed layer, and gate electrode 99 above the top surface of the first ILD 90. The resulting remaining portions of the gate dielectric layer 94, barrier layer 96, work function layer 98, seed layer, and gate electrode 99 thus form the replacement gate 97 of the resulting FinFET device 100.

[0097] Next reference Figure 31 A second ILD 92 is formed above the first ILD 90. A contact opening 93 is formed through the second ILD 92 to expose replacement gates 97 (e.g., 97A, 97B, and 97C). Similarly, a contact opening 91 is formed through the first ILD 90 and the second ILD 92 to expose the source / drain region 80.

[0098] In an embodiment, the second ILD 92 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 92 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. Contact openings 91 and 93 can be formed using photolithography and etching. The etching process etches through CESL 89 to expose the source / drain region 80. The etching process may over-etch, so the contact opening 91 may extend into the source / drain region 80, and the bottom of the contact opening 91 may be flush with (e.g., at the same height and the same distance from the substrate) or below (e.g., closer to the substrate) the upper surface 64U of the fin 64.

[0099] After forming the contact openings 91 / 93, a silicide region 95 is formed over the source / drain region 80. In some embodiments, the silicide region 95 is formed by first depositing a metal (e.g., silicon, germanium) capable of reacting with a semiconductor material to form a silicide or germanide region (such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof) over the exposed portion of the source / drain region 80, and then performing a thermal annealing process to form the first silicide region 95. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although region 95 is referred to as a silicide region, region 95 can also be a germanide region or a silicon-germanide region (e.g., a region comprising both silicides and germanides).

[0100] Next, in Figure 32AIn the illustrated embodiment, contacts 102 (e.g., 102A, 102B, also referred to as contact plugs) are formed in contact openings 91 and 93. Each of the contacts 102 includes a barrier layer 101, a seed layer 103, and a conductive material 105, and is electrically connected to an underlying conductive component (e.g., a replacement gate 97 or a silicide region 95). Contact 102A, electrically coupled to the replacement gate 97, may be referred to as a gate contact, while contact 102B, electrically coupled to the silicide region 95, may be referred to as a source / drain contact. The materials and formation methods of the barrier layer 101, seed layer 103, and conductive material 105 may be the same as or similar to those discussed above for the barrier layer 96, seed layer, and gate electrode 99 of the replacement gate 97, respectively, and therefore details are not repeated. Figure 32A In this illustration, all contacts 102 are shown in the same cross-section. Of course, this is merely an example and not a limitation. Contacts 102 may be in different cross-sections.

[0101] Figure 32B Show Figure 32A The FinFET device 100, but along the cross section BB. Figure 14B A contact 102 is shown above each of fins 64A and 64B. The contact 102 is electrically coupled to the replacement gate 97. The number and location of the contacts 102 are for illustrative purposes only and are not limiting; other numbers and locations are possible and are fully intended to be included within the scope of the invention.

[0102] Figures 33 to 36 Cross-sectional views of the FinFET device 100A are shown at various stages of manufacturing according to an embodiment. Figure 33 The FinFET device 100A in the middle is similar to Figure 26 The FinFET device 100 is shown, but fin loss occurs in the fin 64 due to the multi-step plasma etching process that forms the dummy gate 68. Due to the fin loss, a groove 65 extends below the upper surface 64U of the fin, and a spacer layer 87 also extends below the upper surface 64U of the fin.

[0103] Next, in Figure 34 In this process, an anisotropic etching process is performed to form the gate spacer 87, and then the groove 65 is further extended into the fin 64 to form the groove 86. The process is similar to that described above for the FinFET device 100, so the details will not be repeated here.

[0104] Next, in Figure 35 In the middle, an epitaxial source / drain region 80 is formed in the groove 86. Figure 35 In the example, the upper surface 80U of the source / drain region 80 is located at a distance H below the upper surface 64U of the fin 64, and Figure 35The volume of the source / drain region 80 in the middle can be smaller than Figure 28A The volume within. Therefore, Figure 35 The example illustrates an instance of adjusting the volume of the source / drain region 80 by adjusting the fin loss during the formation of the dummy gate 68. In some embodiments, the distance H is between about 0 nm and about 5 nm. In some embodiments, the upper surface of the source / drain region 80U is substantially flush with the bottom surface of the gate spacer 87 closest to the substrate 50. In some embodiments, as Figure 35 As shown by the dashed line 80U', the upper surface of the source / drain region 80 is below the bottom surface of the gate spacer 87. According to some embodiments, by confining the epitaxial source / drain region 80 (e.g., through the STI boundary and / or a deeper gate spacer 87), the epitaxial structure of the source / drain region 80 can be formed in a more uniform size, thereby bringing more uniform device performance to the formed device.

[0105] Next, in Figure 36 Similar to the discussion above regarding the FinFET device 100A, it forms CESL 89, first ILD 90, second ILD 92, silicide region 95, and contact 102.

[0106] Figure 37 A flowchart illustrating a method 1000 for forming a semiconductor device according to some embodiments is shown. It should be understood that... Figure 37 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 37 The steps shown.

[0107] refer to Figure 37 In step 1010, a fin protruding above the substrate is formed. In step 1020, a gate layer is formed above the fin. In step 1030, a plasma etching process is used to pattern the gate layer in a plasma etching tool to form a gate above the fin, wherein patterning the gate layer includes: alternately turning on and off a top radio frequency (RF) source of the plasma etching tool during the plasma etching process; and alternately turning on and off a bottom RF source of the plasma etching tool during the plasma etching process, wherein there is a timing offset between a first moment when the top RF source is turned on and a corresponding second moment when the bottom RF source is turned on.

[0108] The embodiments offer advantages. For example, the disclosed method for controlling the radio frequency (RF) power supply of a plasma etching tool provides additional tuning points for controlling the size and / or shape of the recesses (e.g., 65, 86) to epitaxially grow the source / drain regions 80. In advanced semiconductor manufacturing, controlling the size and / or shape of the recesses is becoming increasingly difficult due to the small spacing between the gates 68. The method disclosed herein allows for additional control and flexibility in controlling the size and / or shape of the recesses while forming the gates 68, without requiring additional processing.

[0109] In one embodiment, a method of forming a semiconductor device includes: forming a fin protruding over a substrate; forming a gate layer over the fin; and using a plasma etching process to pattern the gate layer in a plasma etching tool to form a gate on the fin, wherein patterning the gate layer includes: alternately turning on and off a top radio frequency (RF) source of the plasma etching tool during the plasma etching process; and alternately turning on and off a bottom RF source of the plasma etching tool during the plasma etching process, wherein there is a timing offset between a first moment when the top RF source is turned on and a corresponding second moment when the bottom RF source is turned on. In one embodiment, the top RF source is configured to ignite a gas source in the plasma etching tool into plasma when turned on, and wherein the bottom RF source is configured to provide a bias voltage for etching the gate layer when turned on. In one embodiment, the gas source includes hydrogen bromide and chlorine, wherein the method further includes adjusting the sidewall profile of the gate by adjusting the flow rate ratio between hydrogen bromide and chlorine. In an embodiment, the method further includes controlling the amount of fin loss caused by the plasma etching process by adjusting a first duty cycle of the top RF source or by adjusting a second duty cycle of the bottom RF source. In an embodiment, the plasma etching process removes a top portion of the fin to form a groove in the fin, wherein the method further includes forming a gate spacer along the sidewall of the gate and along the sidewall of the fin exposed by the groove; performing another plasma etching process to further extend the groove into the fin; and forming a source / drain region in the extended groove. In an embodiment, the method further includes forming a dielectric material around the gate spacer and above the source / drain region; and replacing the gate with a metal gate. In an embodiment, the top RF source is turned on and off at a first frequency, and the bottom RF source is turned on and off at a second frequency the same as the first frequency. In an embodiment, during the plasma etching process, the first duty cycle of the top RF source is the same as the second duty cycle of the bottom RF source. In an embodiment, during the cycle of the plasma etching process, a timing offset greater than the on-time of the top RF source is present, wherein the cycle of the plasma etching process is the same as the reciprocal of the first frequency. In one embodiment, during the plasma etching process cycle, the timing offset is less than the on-time of the top RF source, wherein the period of the plasma etching process is the same as the reciprocal of the first frequency. In another embodiment, during the plasma etching process, the first duty cycle of the top RF source differs from the second duty cycle of the bottom RF source.

[0110] In one embodiment, a method of forming a semiconductor device includes: forming a gate layer over a fin protruding above a substrate; forming a patterned mask over the gate layer; and etching the gate layer through the patterned mask to form a gate by performing a plasma etching process in a plasma etching tool, wherein the plasma etching tool has a top radio frequency (RF) power supply configured to generate plasma and a bottom RF power supply configured to provide a bias voltage for etching, wherein etching the gate layer includes: turning the top RF power supply on and off at a first frequency, wherein the top RF power supply has a first duty cycle during the plasma etching process; and turning the bottom RF power supply on and off at the first frequency, wherein the bottom RF power supply has a second duty cycle during the plasma etching process. In one embodiment, the top RF source and the bottom RF power supply are turned on at different times during the plasma etching process. In one embodiment, the first duty cycle of the top RF power supply and the second duty cycle of the bottom RF power supply are the same. In another embodiment, the first duty cycle of the top RF power supply and the second duty cycle of the bottom RF power supply are different. In one embodiment, during the plasma etching process, the first moment when the top RF power is turned on precedes the most recent second moment when the bottom RF power is turned on. In another embodiment, the plasma etching process removes the top portion of the fin remote from the substrate to form a groove in the fin, wherein the method further includes: deepening the groove into the fin by performing an etching process; and growing source / drain material in the deepened groove.

[0111] In one embodiment, a semiconductor device includes: a fin projecting above a substrate; a gate structure above the fin; a gate spacer along a sidewall of the gate structure, wherein a bottom surface of the gate spacer facing the substrate extends closer to the substrate than an upper surface of the fin that is away from the substrate; and a source / drain region, at least partially in the fin and adjacent to the gate spacer. In another embodiment, the upper surface of the fin contacts the gate dielectric layer of the gate structure.

[0112] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art will understand that they can readily use the invention as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of the invention.

Claims

1. A method of forming a semiconductor device, the method comprising: forming a protruding fin over a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etch tool using a plasma etch process to form a gate over the fin and to remove a top portion of the fin away from the substrate to form a recess in the fin, wherein patterning the gate layer comprises: alternating turning on and off a top radio frequency source of the plasma etch tool during the plasma etch process; and alternating turning on and off a bottom radio frequency source of the plasma etch tool during the plasma etch process, wherein the top radio frequency source is turned on and off at a first frequency and the bottom radio frequency source is turned on and off at a second frequency that is the same as the first frequency, wherein there is a timing offset between a first time from turning off to turning on the top radio frequency source and a corresponding second time from turning off to turning on the bottom radio frequency source, wherein the timing offset is greater than a turn on time of the top radio frequency source during the plasma etch process, wherein a period of the plasma etch process is an inverse of the first frequency.

2. The method of claim 1, wherein, the top radio frequency source is configured to ignite a gas source in the plasma etch tool into a plasma when turned on, and wherein the bottom radio frequency source is configured to provide a bias voltage for etching the gate layer when turned on.

3. The method of claim 2, wherein, the gas source comprises hydrogen bromide and chlorine, wherein the method further comprises adjusting a sidewall profile of the gate by adjusting a flow ratio between hydrogen bromide and chlorine.

4. The method of claim 1, further comprising: an amount of fin loss caused by the plasma etch process is controlled by adjusting a first duty cycle of the top radio frequency source or by adjusting a second duty cycle of the bottom radio frequency source.

5. The method of claim 1, wherein, the plasma etch process removes a top portion of the fin to form a recess in the fin, wherein the method further comprises: forming a gate spacer along a sidewall of the gate and along a sidewall of the fin exposed by the recess; performing another plasma etch process to further extend the recess into the fin; and forming a source / drain region in the extended recess.

6. The method of claim 5, further comprising: forming a dielectric material around the gate spacer and over the source / drain region; and replacing the gate with a metal gate. the method further comprises forming a gate spacer along a sidewall of the gate.

7. The method of claim 1, wherein, during the plasma etch process, a first duty cycle of the top radio frequency source is the same as a second duty cycle of the bottom radio frequency source.

8. The method of claim 1, wherein, the gate layer is an amorphous silicon layer.

9. The method of claim 1, wherein, the sidewall profile of the gate has a same width between opposing sidewalls of an upper portion and a lower portion of the gate.

10. The method of claim 3, wherein, during the plasma etch process, a first duty cycle of the top radio frequency source is different than a second duty cycle of the bottom radio frequency source.

11. The method of claim 1, wherein, the second duty cycle is in a range of 4% to 20%.

12. The method of claim 11, wherein, 13. A method of forming a semiconductor device, the method comprising: forming a gate layer over a fin protruding above a substrate; forming a patterned mask over the gate layer; and ​ etching the gate layer includes: turning on and off the top RF power at a first frequency, wherein the top RF power has a first duty cycle during the plasma etch process; and turning on and off the bottom RF power at the first frequency, wherein the bottom RF power has a second duty cycle during the plasma etch process, wherein, in the plasma etch process, the top RF power is switched from off to on at a first time, and the bottom RF power is switched from off to on at a second time different from the first time; deepening the recess into the fin by performing an etch process; and growing source / drain material in the deepened recess.

14. The method of claim 13, wherein, the second duty cycle is in a range of 4% to 20%.

15. The method of claim 13, wherein, the first duty cycle of the top RF power is the same as the second duty cycle of the bottom RF power.

16. The method of claim 13, wherein, the first duty cycle of the top RF power is different from the second duty cycle of the bottom RF power.

17. The method of claim 13, wherein, during the plasma etch process, the first time that the top RF power is switched from off to on is before the closest second time that the bottom RF power is switched from off to on.

18. The method of claim 13, wherein, the gate layer is an amorphous silicon layer.

19. A semiconductor device, comprising: a fin protruding above a substrate; a gate structure above the fin; a gate spacer along sidewalls of the gate structure, wherein a bottom surface of the gate spacer facing the substrate extends closer to the substrate than an upper surface of the fin away from the substrate; and a source / drain region at least partially in the fin and adjacent to the gate spacer, wherein the upper surface of the source / drain region away from the substrate is flush with the bottom surface of the gate spacer.

20. The semiconductor device of claim 19, wherein, the upper surface of the fin contacts a gate dielectric layer of the gate structure.

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