Electronic component having a semiconductor die having a low-ohmic portion with an active area and a high-ohmic portion on a dielectric layer

Abstract

An electronic component having a semiconductor die with a low-ohmic portion and a high-ohmic portion on a dielectric layer is disclosed. An electronic component (100) includes a molding layer (102) and a semiconductor die (104), the semiconductor die (104) including a low-ohmic first portion (142) and a high-ohmic second portion (144), wherein the first portion (142) has an active region (140), and the second portion (144) is arranged on the molding layer (102).

Description

Technical Field

[0001] Various embodiments generally relate to electronic components, packages, and methods of manufacturing electronic components. Background Art

[0002] A package may refer to an enclosed electronic component that has electrical connections extending out of the enclosure and is mountable to an electronic peripheral, such as on a printed circuit board.

[0003] Packaging costs are an important driver for industry. Related to this are performance, size and reliability. Different packaging solutions are diverse and must respond to the needs of the application. Summary of the invention

[0004] There may be a need to provide the possibility to manufacture electronic components with a focus on reducing process complexity while maintaining high device reliability.

[0005] According to an exemplary embodiment, an electronic component is provided, which includes a molding layer and a semiconductor die, the semiconductor die including a low-ohmic first portion and a high-ohmic second portion, wherein the first portion has an active area and the second portion is arranged on the molding layer.

[0006] According to another exemplary embodiment, a package is provided, comprising: an electronic component, the electronic component comprising a dielectric layer and a semiconductor die, the semiconductor die comprising a low-ohmic first part and a high-ohmic second part, wherein the first part has an active area and the second part is arranged on the dielectric layer; and an encapsulant, which encapsulates at least a portion of the electronic component.

[0007] According to yet another exemplary embodiment, a method for manufacturing an electronic component is provided, wherein the method comprises: providing a semiconductor wafer comprising a plurality of semiconductor dies, each semiconductor die comprising a low-ohmic first portion and a high-ohmic second portion, wherein each first portion has an active area; arranging the second portion on a molding layer; and thereafter separating the semiconductor wafer on the molding layer into a plurality of separate electronic components, each electronic component comprising at least one semiconductor die and a portion of the molding layer.

[0008] According to an exemplary embodiment, an electronic component and a corresponding package can be provided, wherein the semiconductor die is equipped with a low (or lower) ohmic portion and a high (or higher) ohmic portion. Advantageously, the high ohmic portion can be (preferably directly) connected to a (preferably substantially planar or flat) dielectric (preferably molded) layer, while the low ohmic portion with the active chip area can be facing away from the dielectric layer. With this configuration, since both the semiconductor die and the dielectric layer can be made very thin, highly compact electronic components and packages can be manufactured. Since (multiple) integrated circuit elements can be arranged only in the low ohmic portion, the ohmic losses during the operation of the packaged electronic component can also be low. The high ohmic portion can provide support during manufacturing, can simplify processing and can be partially removed by thinning before completing the manufacture of the electronic component or package. At the same time, while the dielectric layer can be used as a support, a simple electrical connection of the active area is possible. By using a simple dielectric layer (particularly a molded layer) as a support, the effort of manufacturing and monomerizing the electronic component can be significantly reduced. Furthermore, such concepts can be utilized to achieve reliable device-to-device isolation and improved high frequency performance.

[0009] Description of Further Exemplary Embodiments

[0010] In the following, further exemplary embodiments of electronic components, packages and methods will be explained.

[0011] In the context of the present application, the term "electronic component" may in particular cover semiconductor dies (in particular power semiconductor dies), active electronic devices (such as transistors), passive electronic devices (such as capacitors or inductors or ohmic resistors), sensors (such as microphones, light sensors or gas sensors), semiconductor-based light emitting devices (such as light emitting diodes (LEDs) or lasers), actuators (e.g. loudspeakers) and microelectromechanical systems (MEMS). In particular, an electronic component may comprise a semiconductor die having at least one integrated circuit element (such as a diode or a transistor) in a surface portion thereof.

[0012] In the context of the present application, the term "semiconductor die" may particularly refer to a bare die of semiconductor material, which may also include electrically insulating structures and conductive structures in the semiconductor material, and which may have at least one integrated circuit element monolithically integrated in the semiconductor material. Thus, a semiconductor die may be a small piece of semiconductor material on which a given functional circuit is prepared. Such an integrated circuit may be produced in large quantities on a single semiconductor wafer, for example, using a process such as photolithography. The processed semiconductor wafer may then be separated into many pieces, each containing a copy of the circuit. Each of these pieces may be referred to as a semiconductor die. The semiconductor die implemented according to an exemplary embodiment may be formed using silicon technology, gallium nitride technology, silicon carbide technology, etc.

[0013] In the context of the present application, the terms "low-ohmic semiconductor portion" and "high-ohmic semiconductor portion" may particularly refer to different integrated connected portions of a semiconductor die having different conductivity values. More specifically, the low-ohmic semiconductor portion may have a higher conductivity value than the high-ohmic semiconductor portion. For example, the low-ohmic semiconductor portion may be a crystalline semiconductor (particularly silicon) portion, and the high-ohmic semiconductor portion may be a high-resistance semiconductor (particularly silicon) portion. In one embodiment, the low-ohmic semiconductor portion and the high-ohmic semiconductor portion may be separated by a dielectric layer therebetween. In such an embodiment, the semiconductor die may be embodied as a SOI (silicon on insulator) die.

[0014] In the context of the present application, the term “active area” may particularly refer to a section of a semiconductor die in which at least one integrated circuit element (eg a transistor, a diode, etc.) is monolithically integrated.

[0015] In the context of the present application, the term "dielectric layer" may particularly refer to a flat or sheet-like body made of an electrically insulating material. For example, such a dielectric material may be a molding compound or another dielectric such as a polymer.

[0016] In the context of the present application, the term "molding layer" may particularly refer to a flat or sheet-like body made of a molding or molding compound material. For example, the molding may include or consist of a resin, such as an epoxy resin. It is also possible that the molding includes such a resin and additionally includes filler particles in the resin matrix.

[0017] In the context of the present application, the term "package" may particularly refer to an electronic device that may include one or more electronic components, preferably mounted on a carrier (wherein the carrier may include or consist of: a single part, a plurality of parts joined via an encapsulation or other packaging components, or a subassembly of the carrier). The (plurality) constituent parts of the package may be at least partially encapsulated by the encapsulation. Optionally, one or more conductive interconnect bodies (such as bonding wires and / or clamps) may be implemented in the package, for example for electrically coupling the electronic components to the carrier.

[0018] In the context of the present application, the term "encapsulant" may particularly refer to a substantially electrically insulating material surrounding at least a portion of an electronic component (and optionally surrounding at least a portion of a carrier) to provide mechanical protection, electrical insulation and optionally contribute to heat removal during operation. In particular, the encapsulant may be a molding compound. The molding compound may include a matrix of a flowable and hardenable material and filler particles embedded therein. For example, the filler particles may be used to adjust the properties of the molded component, in particular to increase thermal conductivity.

[0019] In an embodiment of the package, the dielectric layer is a molded layer, in particular a molded foil, or a curable layer, in particular a temperature curable layer.

[0020] In an embodiment, the mold layer comprises or consists of a mold foil. When embodied as a foil, the mold layer may be flexible and may contribute only to a very small extent to the thickness of the electronic component and the package. For example, the mold foil may have a thickness in the range from 2 μm to 200 μm.

[0021] In an embodiment, the molding layer comprises or consists of a molding plate. The molding plate may provide greater robustness, but may also have a greater thickness. For example, the molding plate may be rigid and may have a thickness in the range from 250 μm to 1 mm.

[0022] In an embodiment, the molding layer is a double molding layer (i.e. having exactly two layers of molding material, which may be interconnected), for example may include or consist of a molding plate and a molding foil. The corresponding material selection of the double molding layer may allow fine tuning of the properties of the electronic components in the package.

[0023] In an embodiment, the molding layer comprises a resin matrix (which is particularly made of epoxy resin) and filler particles (which are particularly made of metal oxide) in the resin matrix. The matrix material may be curable. The filler particles may be used to adjust the physical properties of the molding material (such as thermal conductivity, electrical insulation, thermal expansion coefficient, high frequency properties, etc.).

[0024] In an embodiment, the active area has at least one integrated circuit element. One or more circuit elements may be monolithically integrated in the semiconductor die (preferably, the low-ohmic portion of the semiconductor die). At least one conductive pad of the back-end-of-line (BEOL) structure may be an exposed conductive area coupled to at least one integrated circuit element of the active area for connecting the electronic assembly to an external electronic peripheral device.

[0025] In an embodiment, the electronic assembly includes an adhesive layer between the molding layer and the semiconductor die. The adhesive layer can inhibit undesirable delamination of the electronic assembly and the package.

[0026] In an embodiment, the active region has a thickness of less than 1 μm, in particular a thickness in the range from 50 nm to 500 nm, more in particular a thickness in the range from 100 nm to 200 nm. Thus, the partial volume processed by semiconductor technology can be very small.

[0027] In an embodiment, the semiconductor die is substantially free of unprocessed semiconductor material. This can result in highly compact electronic components and packages, since substantially all of the semiconductor material throughout the thickness of the semiconductor die can contribute to forming functional integrated circuit elements.

[0028] In another embodiment, the semiconductor die has untreated semiconductor material having a thickness of less than 150 μm, in particular less than 30 μm. With such a small thickness, the configuration of the electronic components and the package can still be very compact. However, keeping some untreated semiconductor material can avoid the risk of accidentally damaging the active area of ​​the semiconductor die during thinning of the wafer during production.

[0029] In an embodiment, the semiconductor die has a thickness in the range from 1 μm to 200 μm, in particular in the range from 10 μm to 40 μm, more particularly in the range from 20 μm to 30 μm. In particular, very thin semiconductor dies may be used, for example semiconductor dies with a thickness of less than 50 μm, preferably in the range from 20 μm to 30 μm. If the thickness is even significantly less than 20 μm, heat removal may become more difficult. If the thickness becomes significantly greater than 30 μm, the electrical influence of the semiconductor material, in particular the silicon material, may become greater.

[0030] In an embodiment, the high-ohmic second part of the semiconductor die is made of a high-resistance semiconductor material, in particular a semiconductor material having a resistivity of at least 500Ωcm, in particular at least 1000Ωcm. Advantageously, such a high-ohmic semiconductor can be provided at a low cost. Therefore, the more expensive low-ohmic semiconductor part (for example, made of crystalline silicon) can be substantially limited to the extension of the active area to keep the manufacturing cost low. In any case, the high-ohmic semiconductor material that realizes the supporting function and simplifies the processing of the semiconductor wafer can be partially removed later by thinning, so that its higher resistance does not damage the performance and reliability of the packaged electronic component as a whole. For example, the low-ohmic semiconductor part can have a resistivity less than 100Ωcm, in particular less than 10Ωcm. For example, the resistivity of the low-ohmic semiconductor part can be in the range of from 1Ωcm to 100Ωcm, in particular in the range of from 1Ωcm to 10Ωcm.

[0031] In an embodiment, the semiconductor die is a silicon-on-insulator (SOI) die. Silicon-on-insulator (SOI) technology can be used to prepare silicon semiconductor devices in a layered silicon-insulator-silicon substrate to reduce parasitic capacitance within the device, thereby improving performance. SOI-based semiconductor dies have specific properties: silicon junctions can be arranged on electrical insulators such as silicon dioxide. Alternatively, the electrical insulator used to manufacture the substrate of the electronic components and packages according to the exemplary embodiments can be made of another dielectric material such as sapphire, so that the semiconductor die according to such an embodiment can be referred to as a silicon-on-sapphire die. The selection of an appropriate insulator can be made according to the intended application. For example, sapphire can be a suitable choice for radio frequency (RF) applications.

[0032] In an embodiment, an electronic component includes a conductive back-end-of-line (BEOL) structure on a major surface of a semiconductor die, the major surface of the semiconductor die being opposite to another major surface of the semiconductor die on a molding layer. BEOL may be a part of integrated circuit manufacturing, where individual integrated circuit elements (such as transistors, capacitors, etc.) are interconnected with wiring (i.e., metallization layers (e.g., using copper, aluminum, etc.)) on a wafer. BEOL may be considered to start when the first metal layer is deposited on the wafer. Thus, the BEOL structure may be directly connected to the active area of ​​the semiconductor die. The mentioned BEOL structure may include at least one of the group consisting of: one or more pads, contacts, insulating layers, metal levels, and bonding sites for die-to-package connections. The semiconductor die may be sandwiched between a dielectric layer or molding layer on one side and a BEOL structure on the other side.

[0033] In an embodiment, the electronic component includes at least one conductive protrusion that protrudes beyond the BEOL structure. Such a protrusion may include, for example, a column, a stud, a bump, a ball, etc., which protrudes beyond the flat base of the BEOL structure. Such a protrusion may be configured to facilitate solder connection of the electronic component when forming the basis of a package (which may have a carrier for carrying the electronic component with a solder connection between it and the electronic component) or when mounted (and soldered) on a mounting substrate such as a printed circuit board. In an embodiment, the protrusion may have a low-ohmic base structure with a solder cap on top of it.

[0034] In an embodiment, the semiconductor die is an active semiconductor die, in particular a high frequency semiconductor die. A semiconductor die configured to provide power gain may be an active semiconductor die. Such an active semiconductor die may inject power into the circuit to which it belongs and may control the current within the circuit. Examples for active semiconductor dies are transistor dies, rectifier dies or thyristor dies. In terms of high frequency technology, the semiconductor die may be configured, for example, to operate in a frequency range from about 20 kHz to about 300 GHz.

[0035] In an embodiment, the molded layer in the electronic component or package has been fully cured and is made of a material having adhesive properties in the uncured state. For example, curing may refer to the polymerization and / or crosslinking of the molded layer material, more specifically the polymerization and / or crosslinking of its resin (e.g., epoxy resin). Before curing, the molded layer may be viscous and may thus be suitably attached to a semiconductor die or semiconductor wafer. After curing (which may be triggered, for example, by supplying thermal energy to the molded layer), polymerization or crosslinking may cause an intrinsic connection to be formed between the molded layer and (multiple) semiconductor dies, wherein the adhesive properties at the outer surface of the molded layer may be lost upon curing.

[0036] In an embodiment, the package includes a carrier, which is partially encapsulated by an encapsulant and electrically connected to the electronic component. In the context of the present application, the term "carrier" may particularly refer to a supporting structure (which may be at least partially conductive) that serves as a mechanical support for one or more electronic components to be mounted thereon, and which may also contribute to the electrical interconnection between (multiple) dies and the peripheral devices of the package. In other words, the carrier may implement a mechanical support function and an electrical connection function. The carrier may include or be composed of a single component, a plurality of components joined via an encapsulation or other packaged components, or a subassembly of the carrier.

[0037] For example, the carrier may be a leadframe type carrier, ie a structured metal plate. When the carrier forms part of a leadframe, it may include a die pad and one or more leads.

[0038] In another embodiment, the carrier comprises a stack consisting of a central electrically insulating and thermally conductive layer, such as a ceramic layer, which is covered on two opposite main surfaces by respective electrically conductive layers, such as copper layers or aluminum layers, wherein the respective electrically conductive layers may be continuous or patterned layers. In particular, the carrier may also be embodied as a direct copper bonding (DCB) substrate or a direct aluminum bonding (DAB) substrate.

[0039] In particular, the BEOL structures described above on the main surface of the semiconductor die may be electrically connected to an at least partially conductive carrier. Thus, the connection between the BEOL structures and the carrier may simultaneously provide both a mechanical connection between the electronic component and the carrier as well as an electrical coupling therebetween.

[0040] In an embodiment, the encapsulant is a molding compound, in particular a molding compound having different material properties than the dielectric layer. By selecting different materials for the molding layer of the electronic component and the encapsulant of the package, a specific adaptation of the required properties (supporting the semiconductor die during processing on the component level, reliable mechanical protection and electrical decoupling on the packaging level) can be adjusted individually for the two molding structures.

[0041] The molding compound may include a matrix of flowable and hardenable material and filler particles embedded therein. For example, the filler particles may be used to adjust the properties of the molded component, in particular to increase thermal conductivity. For example, molding may be accomplished by injection molding, transfer molding, or compression molding.

[0042] In an embodiment, the encapsulation may be an overmolding of the corresponding electronic components by the encapsulant after separation from the wafer. However, one or more electrical contacts for accessing the encapsulated semiconductor die from the outside of the package may remain exposed. Such contacts may involve a conductive carrier on which the electronic components may be mounted in the interior of the package.

[0043] In an embodiment, the method comprises temporarily connecting a carrier wafer to the semiconductor wafer before arranging, and removing the carrier wafer from the semiconductor wafer before detaching. For example, such a temporary carrier wafer may be a glass plate that may be reused multiple times.

[0044] In an embodiment, the method comprises thinning the semiconductor wafer before attaching the semiconductor wafer to the molding layer, in particular by removing at least or exclusively material of the second portion. For example, the thinning may be achieved mechanically by grinding, by laser ablation and / or chemically (e.g. by wet etching). It is also possible that at least two of the above-mentioned and / or other thinning techniques may be combined.

[0045] In an embodiment, the method includes temporarily connecting the dicing foil to the molding layer before or after the arrangement, and removing the dicing foil from the electronic component during or after the separation. The dicing foil or dicing tape can be a foil or tape used during wafer dicing, that is, separating the sheet of semiconductor material after the processing on the wafer level. The dicing foil can keep the semiconductor die together during the separation or singulation process. For the purpose of stability, the dicing foil can be mounted to a thin frame (e.g., made of metal). The separated semiconductor die can then be removed from the dicing tape, for example, by a pick-and-place tool. The singulated semiconductor die with the molding layer on one side can then be further processed, for example, it can be assembled to a mounting substrate and / or can be encapsulated according to a package.

[0046] In an embodiment, the method comprises embedding the conductive protrusions on the conductive back-end-of-line (BEOL) structures on the main surface of the semiconductor wafer in a temporary (i.e. later removed) bonding structure, which in particular connects the semiconductor wafer to a carrier wafer. The temporary bonding structure may temporarily connect the carrier wafer to the semiconductor wafer and may be soft enough to temporarily accommodate the protrusions without risk of damage. The temporary bonding structure may be removed from the electronic component before singulation, preferably without residues remaining at the electronic component.

[0047] In an embodiment, the method comprises separating by at least one of the group consisting of mechanical sawing, laser sawing and etching.These separation techniques may also be combined.

[0048] In an embodiment, the semiconductor die is configured as a power semiconductor die. Thus, the semiconductor die can be used for power applications in, for example, the automotive field, and can, for example, have at least one integrated insulated gate bipolar transistor (IGBT) and / or at least one transistor of another type (such as MOSFET, JFET, etc.) and / or at least one integrated diode. Such an integrated circuit element can be, for example, made using silicon technology or based on a wide bandgap semiconductor (such as silicon carbide or gallium nitride). The semiconductor power die or chip can include one or more field effect transistors, diodes, inverter circuits, half bridges, full bridges, drivers, logic circuits, further devices, etc.

[0049] As a substrate or wafer forming the basis of the semiconductor die, a semiconductor substrate may be used, preferably a silicon substrate. It is also possible to implement a germanium substrate or a III-V semiconductor material. For example, exemplary embodiments may be implemented using gallium nitride or silicon carbide technology.

[0050] Furthermore, exemplary embodiments may utilize standard semiconductor processing techniques, such as appropriate etching techniques (including isotropic etching techniques and anisotropic etching techniques, in particular plasma etching, dry etching, wet etching), patterning techniques (which may involve photolithography masks), deposition techniques (such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputtering, etc.).

[0051] The above and other objects, features and advantages will become apparent from the following description and appended claims taken in conjunction with the accompanying drawings in which like parts or elements are designated by like reference numerals. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The accompanying drawings, which are included to provide a further understanding of exemplary embodiments and constitute a part of this specification, illustrate exemplary embodiments.

[0053] In the attached picture:

[0054] Figure 1 A cross-sectional view of an electronic assembly is illustrated according to an exemplary embodiment.

[0055] Figures 2 to 9 A cross-sectional view of a structure obtained during performance of a method of manufacturing an electronic component on a wafer level according to an exemplary embodiment is illustrated.

[0056] Fig.10 A cross-sectional view of a package according to an exemplary embodiment is illustrated.

[0057] Fig.11 A cross-sectional view of a package according to another exemplary embodiment is illustrated. DETAILED DESCRIPTION

[0058] The illustrations in the figures are schematic and not to scale.

[0059] Before the exemplary embodiments will be described in more detail with reference to the figures, some general considerations will be summarized based on the exemplary embodiments that have been developed.

[0060] According to exemplary embodiments, an electronic component, a package and a method for manufacturing a semiconductor component are provided, which can preferably operate based on thin wafer technology. (Multiple) monolithically integrated circuit elements of the active area of ​​the semiconductor component can be arranged in the low-ohmic portion of the semiconductor wafer or die. The low-ohmic silicon portion can be placed on the high-ohmic silicon portion. High-ohmic silicon (e.g., having a specific resistance of about 1k Ohmcm) is extremely advantageous at very high frequencies (e.g., in the GHz range), where the high-ohmic silicon can be essentially transparent.

[0061] Linearity and low loss are important performance factors in high-performance RF (radio frequency) circuits.

[0062] However, active and passive integrated circuit components and the capacitive and inductive interactions of these circuit components and traces with the semiconductor substrate can cause performance limitations. Therefore, some components require the substrate to be removed or significantly thinned. For this purpose, carrier technology can be used to stabilize thin wafers and chips.

[0063] According to exemplary embodiments, expensive carriers may be unnecessary and a reduction in manufacturing effort may thus be achieved. In particular, an electronic component or package according to exemplary embodiments may include a semiconductor die (e.g. an active RF semiconductor die) having little or thin untreated high-ohmic silicon in the back dimension, or even substantially no such silicon. For example, the corresponding bare semiconductor die may be provided with a back-end-of-line (BEOL) metallization structure having a contact connection to the top side. Furthermore, it may be possible to provide bumps or pillars (e.g. made of copper) or balls on the BEOL structure.

[0064] Exemplary embodiments may also provide a dielectric (particularly molded) layer or backside protective film at the back side of the electronic component. Such a dielectric layer may stabilize the electronic component or a wafer as a preform thereof. The dielectric layer or film may preferably be made of a molded-like material having adhesive properties.

[0065] Such a structure can be advantageously used in a simple and cost-effective separation process, since only thin components need to be isolated with a thin mold film. Thus, a simple separation method can be used for singulation.

[0066] Advantageously, example embodiments may make a thick permanent glass sheet unnecessary, as it may be sufficient, for example, to attach a molding layer or film directly or indirectly to the semiconductor die.

[0067] Thus, exemplary embodiments may use a composite of a semiconductor die and a mold layer, the mold layer acting as an isolation carrier. The opportunity to omit conventional bulky carrier wafers made of glass, silicon, or ceramics may reduce the size and manufacturing effort of the electronic assembly. In particular, high sawing effort for singulation of semiconductor dies or chips may also be unnecessary. This may allow for improved device-to-device isolation and improved RF performance, while keeping the manufacturing process simple.

[0068] Exemplary embodiments may provide an electronic component without free charge carriers outside the active chip range, which may contribute to nonlinearity, losses and / or isolation limitations. Exemplary embodiments may therefore be highly suitable for high-performance RF devices, RF switches, LNA (low noise amplifier) ​​devices, and millimeter wave devices.

[0069] Replacing conventional insulating substrates with molded or mold-like films or layers can reduce the size and manufacturing effort of electronic components. In the corresponding electronic components, the back side of the semiconductor die or chip can be covered with a film of molding compound or plastic material or plastic composite. The obtained electronic component can be used as a chip level package without further processing using packaging technology. However, it is also possible to encapsulate the obtained electronic component, for example by encapsulation.

[0070] Figure 1 A cross-sectional view of an electronic assembly 100 is illustrated according to an exemplary embodiment.

[0071] The illustrated electronic component 100 includes a mold layer 102 configured as a film as a substrate. Therefore, the mold layer 102 is embodied as a mold foil 106 here. A bare semiconductor die 104 is attached on top of the mold foil 106. The semiconductor die 104 can be, for example, a silicon chip, and can include a low-ohmic or relatively low-ohmic first portion 142 and a high-ohmic or relatively high-ohmic second portion 144. For example, the low (relatively low) ohmic first portion 142 can be made of crystalline silicon. In contrast, the high (higher) ohmic second portion 144 can be, for example, made of high-resistance silicon. For example, the high-ohmic second portion 144 can have a resistivity of 1 kΩcm. In contrast, the low-ohmic first portion 142 can have a significantly lower resistivity, for example, 10 Ωcm.

[0072] As shown, the first portion 142 has an active region 140 in which one or more integrated circuit components ( Figure 1 104 is not shown). For example, when the semiconductor die 104 is configured for power semiconductor applications, such an integrated circuit element may be, for example, a field effect transistor or a diode. In particular, the semiconductor die 104 may be an active semiconductor die 104 and may be configured for high frequency applications.

[0073] The second portion 144 may be directly connected to the molding layer 102. However, as shown in detail 137, it is also possible to arrange an adhesive layer 154 between the molding layer 102 and the second portion 144 of the semiconductor die 104. As can be taken from detail 137, the adhesive layer 154 may be sandwiched between the molding layer 102 and the semiconductor die 104 for further promoting adhesion between the molding layer 102 and the bare semiconductor die 104.

[0074] No monolithically integrated circuit elements are formed in the second portion 144 , which therefore may contain no active regions.

[0075] The second portion 144 is combined with the portion of the first portion 142 that is directly connected to the second portion 144, thereby forming an untreated semiconductor material having a thickness B (e.g., slightly less than 25 μm). The entire thickness D of the semiconductor die 104 can be, for example, 25 μm. The thickness L of the active area 140 in the low-ohmic first portion 142 can be DB. More specifically, the active area 140 can, for example, have a thickness L of less than 1 μm (e.g., 150 nm). The vertical thickness d2 of the second portion 144 can be greater than the vertical thickness d1 of the first portion 142. For example, d2 can be at least 10 times greater than d1. Therefore, Figure 1 The illustrations are not true to scale.

[0076] On its front side, the electronic component 100 comprises an electrically conductive back-end-of-line (BEOL) structure 110 configured as a layer. The BEOL structure 110 may function as a redistribution layer and comprises one or more electrically insulating layers 141 having electrically conductive traces 143 thereon and / or therein. In particular, the BEOL structure 110 may comprise pads 146. The BEOL structure 110 may be formed directly on an upper main surface of the semiconductor die 104. The upper main surface is arranged opposite to a lower main surface of the semiconductor die 104, which may be in direct physical contact with the molding layer 102 or may be separated from the molding layer 102 only by an adhesive layer 154. The BEOL structure 110 may be directly connected to the active side of the semiconductor die 104, i.e. the active area 140.

[0077] As shown, conductive protrusions 111 protrude beyond BEOL structure 110 for connection purposes. Each of these protrusions 111 may include a stud or pillar 131 (e.g., a copper pillar) and a solder cap 133 of solderable material (e.g., AgSn or another solderable alloy) on top of the pillar 131.

[0078] For example, in Figure 1 In the case shown in FIG. 1 , the mold layer 102 may have been cured (i.e., may be fully cross-linked or polymerized). Preferably, the material of the mold layer 102 is configured so that it has adhesive properties in an uncured state. This material property simplifies the connection between the mold layer 102 and the semiconductor die 104 during the manufacturing process and before curing.

[0079] As in Figure 1As shown in detail 135 of the molding layer 102, the molding layer 102 may include a resin matrix 150 (e.g., made of epoxy resin) and filler particles 152 embedded in the resin matrix 150. The filler particles 152 may be made of metal oxides (e.g., aluminum oxide, calcium oxide, magnesium oxide, manganese oxide), silicon oxide, and / or ceramic materials (such as aluminum nitride). In addition, other filler particles 152 may be used to adjust the electrical conductivity, thermal conductivity, thermal expansion coefficient, etc. of the molding layer 102.

[0080] For example, in Figure 1 The electronic component 100 shown in FIG. 1 can be used as follows: it can be surface mounted on a printed circuit board (PCB) (not shown), for example. However, it is also possible to encapsulate the electronic component 100 to form a package 120, such as in FIG. Fig.10 and Fig.11 As shown in.

[0081] Figures 2 to 9 A cross-sectional view of a structure obtained during performance of a method of manufacturing the electronic component 100 according to an exemplary embodiment is illustrated.

[0082] Reference Figure 2 , shows a fully processed device wafer 130. Wafer 130 is a semiconductor wafer that includes Figure 2 The wafer 130 is configured as a silicon-on-insulator (SOI) wafer. This means that the wafer 130 has a layer of a low-ohmic first portion 142 of the semiconductor dies 104 that are integrally connected. The layer of the first portion 142 is made of a crystalline silicon material with a relatively high electrical conductivity. In addition, the wafer 130 has a layer of a high-ohmic second portion 144 of the semiconductor dies 104 that are integrally connected. The layer of the second portion 144 can be partially made of an amorphous silicon material with a relatively low electrical conductivity. Each of the plurality of semiconductor dies 104 therefore has a low-ohmic first portion 142 and a high-ohmic second portion 144, wherein the first portion 142 has an active area 140. For illustration purposes, Figure 2 The actual thickness of each portion 142, 144 is not truly reflected in proportion. In fact, the thickness of the first portion 142 is much smaller than the thickness of the second portion 144 (see Figure 1 description).

[0083] Furthermore, the layers of the first portion 142 may be separated from the layers of the second portion 144 by an electrically insulating layer 153, such as a silicon oxide layer. Thus, the wafer 130 is a silicon-on-insulator wafer.

[0084] Wafer 130 includes a plurality of semiconductor dies 104 that are still integrally connected, each semiconductor die 104 having an active area 140, although in Figure 2 Only one semiconductor die 104 is shown in FIG. 1 . The active area 140 of each semiconductor die 104 has a conductive pad 146 (at the back end of line (BEOL) structure 110) connected to the back end of line (BEOL) structure 110. Figure 2 Not shown, see Figure 1 ) monolithically integrated circuit elements 148 (eg transistors, diodes, RF circuit elements, etc.). Each active region 140 forms part of the provided low-ohmic first portion 142 and may have a thickness L, for example, in the range from 100 nm to 200 nm.

[0085] The BEOL structure 110 is provided on the upper main surface of the semiconductor wafer 130. An electrically conductive protrusion 111 protrudes upwards from the BEOL structure 110 for each semiconductor die 104 which is still integrally connected.

[0086] In order to obtain Figure 3 In the structure shown in FIG. 1 , the conductive protrusion 111 is embedded in a temporary bonding structure 138. The bonding structure 138 can be made of a thermoplastic adhesive or a UV (ultraviolet radiation) hardenable adhesive, which adheres under surface tension and can be removed later without residue. The bonding structure 138 can therefore be a non-permanent bond.

[0087] Furthermore, a carrier wafer 132 (eg, made of glass) is temporarily connected to the semiconductor wafer 130 using a bonding structure 138 between the carrier wafer 132 and the semiconductor wafer 130 .

[0088] therefore, Figure 3 The device wafer 130 is shown assembled to a recoverable carrier wafer 132 via an adhesive structure 138 .

[0089] Reference Figure 4 ,exist Figure 3 The structure shown in FIG. 1 is shown upside down and thinned at the exposed side of the device wafer 130. Figure 4 , the thinning of the semiconductor wafer 130 is performed by removing parts of the material of the high-ohmic second part 144. In the embodiment shown, neither the material of the electrically insulating layer 153 nor the material of the low-ohmic first part 142 is removed. This is illustrated in detail 155.

[0090] in other words, Figure 4 The result of thinning the device wafer 130 from the back side to a target silicon thickness D of, for example, 25 μm is shown. The thinning may be achieved, for example, by a mechanical process and / or a chemical-mechanical process and / or a chemical wet etching process.

[0091] Reference Figure 5 The molded layer 102, which is configured as a molded film or foil 106, is attached to the exposed surface of the second portion 144 after thinning. The molded layer 102 may be attached to the exposed surface of the second portion 144, for example, by lamination, pressure molding, transfer molding, or using a separate adhesive layer (in Figure 5 Not shown, for comparison Figure 1 The molding layer 102 is connected to the wafer 130 by bonding with reference numeral 154 in FIG.

[0092] Thus, the mold tape or mold foil 106 is assembled or mounted as a back side protection foil to the back side of the wafer 130. Furthermore, in other embodiments, it is possible to apply a mold compound instead of or in addition to providing the mold foil 106. Furthermore, further processes such as curing and / or annealing may be performed subsequently.

[0093] As in Figure 6 As shown in FIG. 1 , it is possible to temporarily connect the dicing foil 134 to the mold layer 102. In one embodiment, after the dicing foil 134 has been performed according to Figure 5 After the processing, the dicing foil 134 can be attached to the mold layer 102 on the wafer 130. Figure 6 The dicing tape or foil 134 is shown assembled or mounted to the back die protection mold foil 106 which has been previously connected to the device wafer 130 .

[0094] In another embodiment, it may advantageously be possible to provide the foils 106 , 134 as prefabricated double foils, which are then connected to the (thinned) wafer 130 (not shown) in one process.

[0095] In order to obtain Figure 7 , the (optional) carrier wafer 132 can then be removed from the semiconductor wafer 130, since it is no longer needed as a support for processing. The non-permanent bonding structure 138 can then also be removed, preferably without residue.

[0096] Thus, the carrier wafer 130 and the adhesive structure 138 may be separated in preparation for subsequent singulation of the manufactured electronic assembly 100 .

[0097] Reference Figure 8, the semiconductor wafer 130 on the molding layer 102 can then be separated into a plurality of separate electronic assemblies 100, each electronic assembly 100 including one (or more) semiconductor die 104, a portion of the molding layer 102 and a portion of the BEOL structure 110 and one or more protrusions 111. For example, the separation can be achieved by laser ablation. More generally, singulation can be accomplished by mechanical sawing, laser sawing and / or etching. As shown, the dicing foil 134 still holds the singulated electronic assemblies 100 together.

[0098] therefore, Figure 8 Individual semiconductor chips or dies 104 are shown being separated by mechanical sawing, laser sawing, or a combination of laser sawing / ablation and mechanical sawing.

[0099] As in Fig. 9 As shown in FIG. 1 , it is then possible to separate the electronic component 100 from the dicing foil 134 , for example by means of a pick and place tool (not shown).

[0100] In other words, the singulation process may be followed by a pick and place process for taking the individual electronic components 100 to a destination (e.g., a packaging tool) for subsequent creation as in Fig.10 or Fig.11 The package 120 is shown in FIG.

[0101] Fig.10 A cross-sectional view of a package 120 is illustrated according to an exemplary embodiment.

[0102] The package 120 may be obtained by: Figure 8 and Fig. 9 After the singulation process shown in FIG. 1 , the electronic component 100 is encapsulated (particularly overmolded) with a molded encapsulant 122 (which may be in the same manner as in FIG. Figure 1 or Fig. 9 ). More specifically, the encapsulant 122 may be a molding compound. For example, the encapsulant 122 may be formed by injection molding, compression molding, transfer molding, etc.

[0103] The illustrated package 120 thus comprises an electronic component 100 having a dielectric (e.g., molded) layer 102 and a semiconductor die 104, as well as a BEOL structure 110 and a protrusion 111. For example, the dielectric layer 102 is made of a temperature-curable material. The semiconductor die 104 comprises a crystalline silicon low-ohmic first portion 142 and a high-ohmic second portion 144, which can be made of a silicon material having a lower electrical conductivity than the material of the first portion 142 (e.g., at least partially crystalline, polycrystalline and / or amorphous silicon material). As shown, the first portion 142 has an active area 140 with a monolithically integrated circuit element 148. The second portion 144 is arranged directly on (i.e., above or below) the dielectric layer 102. An encapsulant 122 of molded type encapsulates the electronic component 100 as well as the carrier 124. The molding material of the encapsulant 122 on the one hand and the molding material of the dielectric layer 102 on the other hand can be different.

[0104] As already mentioned, package 120 comprises a conductive carrier 124, which may be of leadframe type, for example embodied as a patterned copper sheet. Alternatively, carrier 124 may be a printed circuit board (PCB), a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or the like.

[0105] The carrier 124 is partially encapsulated by the encapsulation 122 and is partially exposed relative to the encapsulation 122. The conductive connection structure 145 allows the package 120 to be electrically connected to an electronic peripheral device by soldering, for example, to a mounting substrate (such as a printed circuit board (PCB), not shown) on which the package 120 can be mounted. Furthermore, the carrier 124 is electrically connected to the electronic component 100 by soldering the solder cap 133 of the protrusion 111 of the electronic component 100 to the upper surface of the carrier 124 configured as a board. As a result, the conductive BEOL structure 110 on one main surface of the semiconductor die 104 is connected to the carrier 124 via the protrusion 111.

[0106] according to Fig.10 The package 120 can thus be formed on the basis of an ultra-thin chip, without a carrier plate in the package but only with the mold foil 106 as a tiny support.

[0107] Fig.11 A cross-sectional view of a package 120 according to another exemplary embodiment is illustrated.

[0108] Fig.11 Examples and Fig.10 The embodiments of the invention differ in particular in that according to Fig.11, the dielectric layer 102 is a double molded layer composed of a mold plate 108 and a mold foil 106. The mold foil 106 is arranged between the mold plate 108 and the semiconductor die 104.

[0109] Therefore, according to Fig.11 The package 120 may be formed based on an ultra-thin chip with a mold foil 106 and an additional mold plate 108 as an additional support.

[0110] It should be noted that the term "comprising" does not exclude other elements or features, and "one" or "an" does not exclude a plurality. In addition, elements described in association with different embodiments may be combined. It should also be noted that reference symbols should not be interpreted as limiting the scope of the claims. In addition, the scope of the present application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, material compositions, devices, methods and steps described in the specification. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, devices, methods or steps within their scope.

Claims

1. An electronic component configured to be encapsulated to form a package, the electronic component comprising: Molding layer; as well as A semiconductor die includes a low-ohmic semiconductor portion and a high-ohmic semiconductor portion, wherein the low-ohmic semiconductor portion has an active area and the high-ohmic semiconductor portion is arranged on a molding layer.

2. The electronic component according to claim 1, wherein the molded layer comprises a molded foil, and / or The molding layer includes a molding plate. The electronic component according to claim 1 , wherein the molded layer is a double molded layer.

4. The electronic component according to claim 1, wherein the molding layer comprises: Resin matrix; and filler particles in a resin matrix, wherein the resin matrix comprises an epoxy resin, and wherein the filler particles comprise a metal oxide. 5 . The electronic component as claimed in claim 1 , wherein the active region comprises at least one transistor and / or at least one diode.

6. The electronic assembly of claim 1, further comprising an adhesive layer between the molding layer and the semiconductor die.

7. The electronic component of claim 1, wherein the active region has a thickness of less than 1 μm.

8. The electronic assembly of claim 1, wherein the semiconductor die comprises an unprocessed semiconductor material, the unprocessed semiconductor material having a thickness of less than 150 μm. 9 . The electronic assembly of claim 1 , wherein the semiconductor die has a thickness in a range from 1 μm to 200 μm.

10. The electronic assembly of claim 1, wherein: The high-ohmic semiconductor portion comprises a semiconductor material having a resistivity of at least 500 Ωcm; and / or The low-ohmic semiconductor portion includes a semiconductor material having a resistivity less than 100 Ωcm; and / or The semiconductor die is a silicon-on-insulator die; and / or The semiconductor die includes at least one material selected from the group consisting of silicon, germanium, gallium nitride, gallium arsenide, indium phosphide, silicon carbide, sapphire, diamond, and diamond-like coatings.

11. The electronic assembly of claim 1, further comprising an electrically conductive back-end process structure on a major surface of the semiconductor die, the major surface of the semiconductor die being opposite to another major surface of the semiconductor die on the molding layer.

12. The electronic assembly of claim 11, wherein the back end process structure is directly connected to the active area of ​​the semiconductor die.

13. The electronic assembly of claim 11, further comprising at least one conductive protrusion protruding beyond the back-end structure.

14. The electronic assembly of claim 1, wherein the semiconductor die is a high frequency semiconductor die.

15. The electronic component according to claim 1, wherein the mold layer is cured and has adhesive properties in an uncured state.

16. The electronic component according to claim 1, wherein the low-ohmic semiconductor portion is a crystalline silicon portion, and wherein the high-ohmic semiconductor portion is a high-resistance silicon portion.

17. The electronic component of claim 1, wherein the low-ohmic semiconductor portion and the high-ohmic semiconductor portion are separated by a dielectric layer therebetween. 18 . The electronic component according to claim 1 , wherein the low-ohmic semiconductor portion has a resistivity in a range from 1 Ωcm to 10 Ωcm, and wherein the high-ohmic semiconductor portion has a resistivity of at least 500 Ωcm.

19. A package comprising: The electronic component according to claim 1, comprising a dielectric layer as a molding layer; as well as An encapsulant encapsulates at least a portion of the electronic component.

20. The package of claim 19, wherein the dielectric layer comprises a molded foil, and / or a curable layer, and / or a temperature curable layer.

21. The package of claim 19, further comprising: a carrier at least partially encapsulated by the encapsulant and electrically connected to the electronic component; and / or an electrically conductive back-end structure on a major surface of the semiconductor die and connected to the at least partially electrically conductive carrier, The encapsulant is a molding compound having different material properties than the dielectric layer.

22. A method of manufacturing an electronic component, wherein the method comprises: providing a semiconductor wafer including a plurality of semiconductor dies, each semiconductor die including a low-ohmic semiconductor portion and a high-ohmic semiconductor portion, wherein each low-ohmic semiconductor portion has an active region; disposing a high-ohmic semiconductor portion on the molding layer; as well as The semiconductor wafer and the molding layer are then separated into a plurality of separate electronic assemblies, each electronic assembly including at least one of the semiconductor dies and a portion of the molding layer.

23. The method according to claim 22, further comprising: temporarily connecting the carrier wafer to the semiconductor wafer prior to placement and removing the carrier wafer from the semiconductor wafer prior to separation; and / or thinning the semiconductor wafer by removing material of at least the high-ohmic semiconductor portion before connecting the semiconductor wafer to the molding layer; and / or temporarily connecting the dicing foil to the molding layer before or after arranging, and removing the dicing foil from the electronic component during or after separation; and / or embedding conductive protrusions on conductive back-end process structures on the major surface of the semiconductor wafer in a temporary bonding structure that connects the semiconductor wafer to a carrier wafer; and / or Separation is performed by at least one of mechanical sawing, laser sawing and etching; and / or After separation, each electronic component is encapsulated by an encapsulant.

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