A circuit board for monitoring via process

Abstract

The present invention discloses a circuit board for monitoring a via process, wherein the circuit board is a multi-layer board, including an N-type well layer, an active area layer, a polysilicon layer, a silicon barrier layer, a contact hole layer, a first metal layer, a via layer and a second metal layer arranged in sequence from bottom to top; a first PCM test strip and a via are arranged on the circuit board; the first pad and the fourth pad are both connected to the first metal layer connected to the via, and the second pad and the third pad are both connected to the second metal layer connected to the via; wherein the via process is monitored by inputting current to the first pad and the third pad, and according to the voltage at both ends of the second pad and the fourth pad. If the resistance of the semiconductor device tested by the circuit board provided by the present invention is greater than the resistance tested by the PCM, it means that the via process of the semiconductor device is unqualified, otherwise, it means that the via process of the semiconductor device is qualified.

Description

Technical Field

[0001] The invention relates to the field of circuit boards, and in particular to a circuit board for monitoring a via hole process. Background Art

[0002] PCM (Process Control Monitor) testing refers to monitoring process control through electrical parameters and is a means of reflecting product quality.

[0003] In the current prior art, it is found that semiconductor devices that have passed the PCM test still have the problem of open vias during use. Therefore, the current PCM test structure can no longer meet the needs of semiconductor testing, and a new test structure needs to be developed to monitor the via process. Summary of the invention

[0004] The technical problem to be solved by the present invention is to overcome the above-mentioned defects in the prior art and provide a circuit board for monitoring the via process.

[0005] The present invention solves the above technical problems through the following technical solutions:

[0006] A first aspect of the present invention provides a circuit board for monitoring a via process, wherein the circuit board is a multi-layer board, comprising an N-type well layer, an active region layer, a polysilicon layer, a silicon barrier layer, a contact hole layer, a first metal layer, a via layer, and a second metal layer arranged in sequence from bottom to top;

[0007] The circuit board is provided with a first PCM test strip and a via hole;

[0008] The first PCM test strip is provided with a first pad, a second pad, a third pad and a fourth pad, the first pad and the fourth pad are both connected to the first metal layer connected to the via hole, and the second pad and the third pad are both connected to the second metal layer connected to the via hole;

[0009] Wherein, current is input into the first pad and the third pad, and the via process is monitored according to the voltage across the second pad and the fourth pad.

[0010] Preferably, the via is connected to several pieces of polysilicon through the first metal layer and the contact hole.

[0011] Preferably, the area of ​​each piece of polysilicon is 100 μm*100 μm.

[0012] Preferably, the number of the polysilicon is 16 pieces.

[0013] Preferably, the current is 1 mA.

[0014] A second aspect of the present invention provides a circuit board for monitoring a via process, wherein the circuit board is a multi-layer board, comprising an N-type well layer, an active region layer, a polysilicon layer, a silicon barrier layer, a contact hole layer, a first metal layer, a via layer, and a second metal layer arranged in sequence from bottom to top;

[0015] The circuit board is provided with a second PCM test strip and a plurality of vias connected in series;

[0016] The second PCM test strip is provided with a fifth pad and a sixth pad, the fifth pad is connected to the second metal layer connected to the first via hole, and the sixth pad is connected to the second metal layer connected to the last via hole;

[0017] Wherein, a voltage is applied to the fifth pad and the sixth pad, and the via process is monitored according to the current between the fifth pad and the sixth pad.

[0018] Preferably, the number of the via holes is 1000.

[0019] Preferably, each via is connected to polysilicon with an area of ​​100 μm*100 μm through the first metal layer and the contact hole.

[0020] The positive and progressive effect of the present invention is that by setting the circuit board as a multi-layer, the via is connected to the polysilicon, so that the via structure can evaluate the influence of the polysilicon storage charge on the via process. If the resistance of the semiconductor device tested by the circuit board provided by the present invention is greater than the resistance tested by the PCM, it means that the via process of the semiconductor device is unqualified, otherwise, it means that the via process of the semiconductor device is qualified. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the internal structure of a circuit board for monitoring a via process provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention is further described below by way of examples, but the present invention is not limited to the scope of the examples.

[0023] In view of the problem that semiconductor devices that have passed the PCM test still have open vias during use, the inventors have found through research that all failed devices are connected to polysilicon resistors. The good conductivity of polysilicon allows it to collect charges from plasma etching, making the POLYMER (polymer) produced by via etching more easily adsorbed on the side walls of the etching window and causing open vias. Based on this, the inventors designed a circuit board that connects vias to polysilicon for monitoring the via process. If the resistance of the semiconductor device tested by the circuit board provided by the present invention is greater than the resistance tested by the PCM, it means that the via process of the semiconductor device is unqualified; otherwise, it means that the via process of the semiconductor device is qualified.

[0024] Example 1

[0025] This embodiment provides a circuit board for monitoring a via hole process, wherein the circuit board is a multi-layer board, such as Figure 1 As shown, it includes an N-type well (NW) layer, an active area (ACT) layer, a polysilicon (POLY) layer, a silicon barrier layer (SBK), a contact hole (CNT) layer, a first metal layer (ME1), a via (VIA) layer and a second metal layer (ME2) which are arranged in sequence from bottom to top.

[0026] Figure 1 In the present invention, ILD (Inter Layer Dielectric) is used to isolate the device from the first metal layer, while IMD (Inter Metal Dielectric) is used to isolate the first metal layer from the second metal layer.

[0027] In an optional embodiment, the characteristic line width of the N-type well layer is 3μm, the characteristic line width of the active area layer is 3μm, the characteristic line width of the polysilicon layer is 1.2μm, the characteristic line width of the silicon barrier layer is 3μm, the characteristic line width of the contact hole layer is 0.4μm, the characteristic line width of the first metal layer is 1μm, the characteristic line width of the via layer is 0.45μm, and the characteristic line width of the second metal layer is 1.6μm.

[0028] The circuit board is provided with a first PCM test strip and a via. In an optional embodiment, the via is connected to a plurality of polysilicon blocks through the first metal layer and the contact hole. In a specific example, the number of the polysilicon blocks is 16.

[0029] In an optional implementation manner, the area of ​​each piece of polysilicon is 100 μm*100 μm.

[0030] In another optional implementation, the area of ​​the polysilicon is 24 μm*24 μm.

[0031] The first PCM test strip is provided with a first pad, a second pad, a third pad and a fourth pad, the first pad and the fourth pad are both connected to the first metal layer connected to the via hole, and the second pad and the third pad are both connected to the second metal layer connected to the via hole.

[0032] Wherein, current is input into the first pad and the third pad, and the via process is monitored according to the voltage across the second pad and the fourth pad.

[0033] In this embodiment, current is input to the first pad and the third pad, and the voltage across the second pad and the fourth pad is detected. If the voltage value is greater than a preset voltage, it indicates that the resistance of the semiconductor device increases and the via process fails. If the voltage value is less than or equal to the preset voltage, it indicates that the resistance of the semiconductor device does not increase and the via process passes. The value of the preset voltage is determined based on the product of the resistance of the semiconductor device obtained through the PCM test and the input current.

[0034] In a specific example, a current of 1 mA is input to the first pad and the third pad. If the voltage across the second pad and the fourth pad is greater than 3.5 mV, it indicates that the via process is unqualified.

[0035] Example 2

[0036] The present embodiment provides a circuit board for monitoring a via process, wherein the circuit board is a multi-layer board, including an N-type well layer, an active area layer, a polysilicon layer, a silicon barrier layer, a contact hole layer, a first metal layer, a via layer, and a second metal layer arranged in sequence from bottom to top.

[0037] The circuit board is provided with a second PCM test strip and a plurality of via holes connected in series.

[0038] The second PCM test strip is provided with a fifth pad and a sixth pad, the fifth pad is connected to the second metal layer connected to the first via hole, and the sixth pad is connected to the second metal layer connected to the last via hole.

[0039] Wherein, a voltage is applied to the fifth pad and the sixth pad, and the via process is monitored according to the current between the fifth pad and the sixth pad.

[0040] In this embodiment, a voltage is applied to the fifth pad and the sixth pad, and the current between the fifth pad and the sixth pad is detected. If the current value is less than the preset current, it means that the resistance of the semiconductor device increases and the via process fails. If the current value is greater than or equal to the preset current, it means that the resistance of the semiconductor device does not increase and the via process passes. The value of the preset current is determined according to the ratio of the applied voltage to the resistance obtained by the semiconductor device after the PCM test.

[0041] In a specific example, the number of the via holes is 1000.

[0042] In an optional implementation manner, each via is connected to polysilicon with an area of ​​100 μm*100 μm through the first metal layer and the contact hole.

[0043] In this embodiment, a piece of polysilicon is connected under each via, and each via is connected in series. Since the failure mode is that the polysilicon absorbs charges, the POLYMER (polymer) becomes heavier and difficult to remove, the sensitivity of the circuit board provided in this embodiment is better than that of the circuit board in Example 1.

[0044] The following table is an experimental comparison result for the existing structure (via not connected to polysilicon), Example 1 (via connected to polysilicon) and Example 2 (several series vias connected to polysilicon):

[0045] Table 1

[0046]

[0047] In Table 1, the initial condition refers to normal polymer removal using a normal process machine, the over-etching experiment refers to increasing the over-etching by 50%, and the polymer deterioration experiment refers to grouping experiments using a machine with weaker polymer removal capability. Delta = (experimental condition - initial condition) / initial condition * 100%.

[0048] It can be seen from the experimental results in Table 1 that the over-etching experiment has a more obvious impact on the via process; and the circuit board of Example 1 is more sensitive than the existing structure, and the circuit board of Example 2 is more sensitive than the circuit board of Example 1.

[0049] In an optional implementation manner, the first PCM test strip, the second PCM test strip, and a plurality of vias are arranged simultaneously on a same circuit board.

[0050] Although the specific embodiments of the present invention are described above, it should be understood by those skilled in the art that this is only for illustration and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.

Claims

1. A circuit board for monitoring a via process, characterized in that: The circuit board is a multi-layer board, including an N-type well layer, an active area layer, a polysilicon layer, a silicon barrier layer, a contact hole layer, a first metal layer, a via layer and a second metal layer arranged in sequence from bottom to top; The circuit board is provided with a first PCM test strip and a via hole; The first PCM test strip is provided with a first pad, a second pad, a third pad and a fourth pad, the first pad and the fourth pad are both connected to the first metal layer connected to the via hole, and the second pad and the third pad are both connected to the second metal layer connected to the via hole; Wherein, the via process is monitored by inputting current into the first pad and the third pad and according to the voltage across the second pad and the fourth pad; The via is connected to a plurality of polysilicon blocks through the first metal layer and the contact hole.

2. The circuit board according to claim 1, wherein: The area of ​​each piece of polysilicon is 100μm*100μm.

3. The circuit board according to claim 1, characterized in that: The number of the polysilicon is 16 pieces.

4. The circuit board according to claim 1, wherein: The current is 1 mA.

5. A circuit board for monitoring a via process, characterized in that: The circuit board is a multi-layer board, including an N-type well layer, an active area layer, a polysilicon layer, a silicon barrier layer, a contact hole layer, a first metal layer, a via layer and a second metal layer arranged in sequence from bottom to top; The circuit board is provided with a second PCM test strip and a plurality of vias connected in series; The second PCM test strip is provided with a fifth pad and a sixth pad, the fifth pad is connected to the second metal layer connected to the first via hole, and the sixth pad is connected to the second metal layer connected to the last via hole; wherein a voltage is applied to the fifth pad and the sixth pad, and a via process is monitored according to a current between the fifth pad and the sixth pad; Each via is connected to the polysilicon through the first metal layer and the contact hole.

6. The circuit board according to claim 5, characterized in that: The number of the via holes is 1000.

7. The circuit board according to claim 5, characterized in that: Each via is connected to polysilicon with an area of ​​100 μm*100 μm through the first metal layer and the contact hole.

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