Semiconductor package including semiconductor chip and capacitor

Abstract

Semiconductor package including semiconductor chip and capacitor. A semiconductor package may include a capacitor and a semiconductor chip mounted on a package substrate. The capacitor may be disposed between the package substrate and the first semiconductor chip, and the capacitor may support the first semiconductor chip.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor packaging technology, and more particularly, to a semiconductor package including a semiconductor chip and a capacitor. Background Art

[0002] Various attempts have been made to integrate multiple semiconductor chips into a single package structure. Since multiple semiconductor chips are arranged in a semiconductor package, the structure of the semiconductor package becomes increasingly complex. In addition, in order to ensure the electrical characteristics required by the semiconductor package, the demand for passive components to be provided in the semiconductor package is increasing. Due to the complex structure of the semiconductor package, it is increasingly difficult to ensure space for placing passive components in the semiconductor package. Summary of the invention

[0003] In one embodiment, a semiconductor package includes: a package substrate; a first semiconductor chip disposed on the package substrate; and at least one capacitor disposed between the package substrate and the first semiconductor chip, wherein the at least one capacitor supports the first semiconductor chip.

[0004] In another embodiment, a semiconductor package includes: a package substrate; at least one capacitor disposed on the package substrate; and a first semiconductor chip disposed only on the at least one capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a perspective view showing a semiconductor package according to one embodiment.

[0006] Figure 2 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0007] Figure 3 is a perspective view showing a semiconductor package according to one embodiment.

[0008] Figure 4 is a block diagram illustrating an electronic system employing a memory card including a package according to one embodiment.

[0009] Figure 5 is a block diagram illustrating an electronic system including a package according to one embodiment. DETAILED DESCRIPTION

[0010] The terms used herein may correspond to words selected with consideration of their function in the embodiments presented, and the meanings of these terms may be interpreted differently according to the ordinary skill in the art to which the embodiments belong. If detailed definitions are made, the terms may be interpreted according to the definitions. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by ordinary technicians in the art to which the embodiments belong.

[0011] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and are not used to indicate a specific order or quantity of elements.

[0012] It should also be understood that when an element or layer is referred to as being "on," "above," "below," "under," or "outside" another element or layer, the element or layer may be in direct contact with the other element or layer, or intervening elements or layers may be present. Other words used to describe the relationship between elements or layers should be interpreted in a similar manner (e.g., "between" versus "directly between" or "adjacent" versus "directly adjacent").

[0013] Spatially relative terms, such as "under," "below," "lower," "above," "upper," "top," and "bottom," etc., may be used to describe the relationship of one element and / or feature to other elements and / or features, for example, as shown in the figures. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and / or operation in addition to the orientation shown in the figures. For example, when the device in the figures is turned over, elements described as being below and / or below other elements or features will be oriented as being above the other elements or features. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatially relative descriptions used herein will be interpreted accordingly.

[0014] According to various embodiments, the semiconductor package may include an electronic device such as a semiconductor chip or a semiconductor die. A semiconductor chip or a semiconductor die may be obtained by dividing a semiconductor substrate such as a wafer into multiple pieces using a die sawing process. The semiconductor chip may correspond to a memory chip, a logic chip, an integrated circuit (ASIC) chip, an application processor (AP), a graphics processing unit (GPU), a central processing unit (CPU), or a system on chip (SoC). The memory chip may include a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a NAND-type flash memory circuit, a NOR-type flash memory circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit, or a phase change random access memory (PcRAM) circuit integrated on a semiconductor substrate. The logic chip may include a logic circuit integrated on a semiconductor substrate. Semiconductor packaging can be used in communication systems, such as mobile phones, electronic systems associated with biotechnology or health care, or wearable electronic systems. Semiconductor packaging can be applied to the Internet of Things (IOT).

[0015] Throughout the specification, the same reference numerals denote the same elements. Even though a reference numeral may not be mentioned or described with reference to one figure, it may be mentioned or described with reference to another figure. Furthermore, even though a reference numeral is not shown in one figure, it may be shown in another figure.

[0016] Figure 1 is a perspective view schematically showing a semiconductor package 10 according to one embodiment.

[0017] Reference Figure 1 , the semiconductor package 10 may include a package substrate 100, a first semiconductor chip 200, and a capacitor 300. At least one capacitor 300 may be disposed between the package substrate 100 and the first semiconductor chip 200. A plurality of capacitors 300 may be disposed on the first surface 101 of the package substrate 100 while being spaced apart from each other. Since the first semiconductor chip 200 is disposed on the capacitor 300, a structure in which the capacitor 300 supports the first semiconductor chip 200 may be configured. The capacitor 300 may be used as a support member for supporting the first semiconductor chip 200. The capacitor 300 may be disposed while overlapping with the first semiconductor chip 200. Since the capacitor 300 overlaps with the first semiconductor chip 200, the area required to arrange the capacitor 300 on the package substrate 100 may be reduced. Compared with the case where the capacitor and the first semiconductor chip are disposed side by side without overlapping each other, the area of ​​the package substrate 100 occupied by the capacitor 300 and the first semiconductor chip 200 may be reduced.

[0018] Figure 2 is a cross-sectional view schematically showing a semiconductor package 10 according to one embodiment. Figure 2 The semiconductor package 10 is schematically shown along Figure 1 The cross-sectional shape of the line X1-X2.

[0019] Reference Figure 1 and Figure 2 , the capacitor 300 may be introduced in the form of a multilayer ceramic capacitor (MLCC). The capacitor 300 may include a capacitor body 310, a first external terminal 320, and a second external terminal 330. The capacitor body 310 may include internal electrodes 312 provided as a plurality of layers in a dielectric layer 311. The dielectric layer 311 may be formed by laminating a plurality of sub-dielectric layers. The internal electrodes 312 may be interlaced between the sub-dielectric layers and alternate with each other.

[0020] The first external terminal 320 and the second external terminal 330 may be respectively disposed at both ends of the capacitor body 310. The first external terminal 320 may include a first layer 321 and a second layer 322 having different metal materials. The first layer 321 of the first external terminal 320 may be connected to some of the internal electrodes 312 and may be electrically coupled to some of the internal electrodes 312. The first layer 321 of the first external terminal 320 may include a metal layer, such as a copper (Cu) layer. The second layer 322 of the first external terminal 320 may be provided as a metal layer covering the first layer 321 of the first external terminal. The second layer 322 of the first external terminal 320 may include a nickel (Ni) layer that prevents contamination or oxidation of the copper (Cu) layer. The second layer 322 of the first external terminal 320 may also include a gold (Au) layer covering the nickel (Ni) layer. The gold (Au) layer may be a bonding layer that bonds or couples the first external terminal 320 to other elements.

[0021] The package substrate 100 may include a conductive landing finger 110 on the first surface 101. The conductive landing finger 110 may refer to a portion of a circuit wiring structure disposed in the package substrate 100. The first external terminal 320 of the capacitor 300 may be coupled or bonded to the conductive landing finger 110 through a conductive adhesive layer 350. The conductive adhesive layer 350 may be introduced as a solder layer containing solder.

[0022] The first external terminal 320 may be coupled to the package substrate 100 so that the capacitor 300 may be electrically coupled to the package substrate 100. The second external terminal 330 of the capacitor 300 may be located at an end opposite to the first external terminal 320, with the capacitor body 310 interposed between the second external terminal 330 and the first external terminal 320. The capacitor 300 may be mounted on the package substrate 100 in a manner that the first external terminal 320, the capacitor body 310, and the second external terminal 330 are sequentially stacked in a direction substantially perpendicular to the first surface 101 of the package substrate 100. The capacitor 300 may be mounted on the package substrate 100 substantially perpendicular to the first surface 101 of the package substrate 100.

[0023] The second external terminal 330 may include a first layer 331 and a second layer 332 having different metal materials. The second external terminal 330 may have a layer structure substantially the same as the first external terminal 320. The first layer 331 of the second external terminal 330 may be connected to the remaining internal electrodes 312 and may be electrically coupled to the remaining internal electrodes 312. The first layer 331 of the second external terminal 330 may include a metal layer, such as a copper (Cu) layer. The second layer 332 of the external terminal 330 may be provided as a metal layer covering the first layer 331 of the second external terminal 330. The second layer 332 of the second external terminal 330 may include a composite layer of a nickel (Ni) layer and a gold (Au) layer.

[0024] Reference Figure 2 , the first semiconductor chip 200 may be supported by at least one capacitor 300. A portion 330-1 of a second external terminal 330 of the capacitor 300 may overlap with the first semiconductor chip 200, so that the capacitor 300 may support the first semiconductor chip 200. A portion of the first semiconductor chip 200 may be coupled or bonded to the overlapping portion 330-1 of the second external terminal 330 through the insulating adhesive layer 230. The insulating adhesive layer 230 may be used to fix the first semiconductor chip 200 to the capacitor 300.

[0025] Another part 330-2 of the second external terminal 330 may not be blocked by the first semiconductor chip 200 and may be exposed to the outside of the first semiconductor chip 200. The package substrate 100 may include a first bonding finger 130 located below the first surface 101. The first bonding wire 410 may be wire bonded so that one end of the first bonding wire 410 is bonded to the exposed portion 330-2 of the second external terminal 330, and the other end of the first bonding wire 410 may be bonded to the first bonding finger 130. The first bonding wire 410 may electrically connect the second external terminal 330 to the package substrate 100. The second layer 332 of the second external terminal 330 may include a gold (Au) layer as a surface layer. When the first bonding wire 410 is a gold (Au) wire, the first bonding wire 410 may be easily bonded and connected to the gold (Au) layer of the second external terminal 330.

[0026] The first semiconductor chip 200 may include a first chip pad 201 and a second chip pad 202 disposed to be spaced apart from the first chip pad 201. The first chip pad 201 and the second chip pad 202 may be connection terminals for applying electrical signals to the first semiconductor chip 200.

[0027] The second bonding wire 420 may perform wire bonding to connect the exposed portion 330-2 of the second external terminal 330 to the first chip pad 201 of the first semiconductor chip 200. The second bonding wire 420 may electrically connect the second external terminal 330 of the capacitor 300 to the first semiconductor chip 200. The first bonding wire 410 and the second bonding wire 420 may electrically connect the first semiconductor chip 200 to the first bonding finger 130 of the package substrate 100.

[0028] The ground terminal 131 may be disposed under the second surface 102 opposite to the first surface 101 of the package substrate 100. The package substrate 100 may include a first internal wiring 132 connecting the first bonding finger 130 to the ground terminal 131. When the first bonding finger 130 is connected to the ground terminal 131, the first bonding wire 410 and the second bonding wire 420 may provide an electrical path for grounding the first semiconductor chip 200. In this case, the second external terminal 330, which is one terminal of the capacitor 300, may be connected to an electrical path configured to ground the semiconductor chip 200.

[0029] The third bonding wire 430 may perform wire bonding to directly connect the second chip pad 202 of the first semiconductor chip 200 to the second bonding finger 150 of the package substrate 100. When the second bonding finger 150 is connected to the power terminal 135, the third bonding wire 430 may provide an electrical path to supply power to the first semiconductor chip 200.

[0030] The power terminal 135 may be disposed under the second surface 102 of the package substrate 100. The second internal wiring 133 connecting the second bond finger 150 to the power terminal 135 may be disposed in the package substrate 100. The second bond finger 150 may be disposed to be spaced apart from the first bond finger 130 and the conductive placement finger 110. The third internal wiring 134 may be disposed in the package substrate 100 to electrically connect the conductive placement finger 110 to the second bond finger 150.

[0031] The first external terminal 320, which is another terminal of the capacitor 300, may be electrically connected to the power terminal 135 through the conductive placement finger 110, the third internal wiring 134, and the second internal wiring 133 connected to the first external terminal 320. In one embodiment, the third internal wiring 134 may be electrically connected to the power terminal 135. In addition, the capacitor 300 may be electrically connected to the first semiconductor chip 200 through the first external terminal 320, the conductive placement finger 110, the third internal wiring 134, the second bonding finger 150, and the third bonding wire 430. Therefore, the first external terminal 320, which is another terminal of the capacitor 300, may be connected to another electrical path for supplying power to the first semiconductor chip 200.

[0032] In this way, since the capacitor 300 is electrically connected between an electrical path that grounds the first semiconductor chip 200 and another electrical path that supplies power to the semiconductor chip 200, the capacitor 300 may function as a decoupling capacitor that reduces noise during operation of the first semiconductor chip 200. In one embodiment, the third bonding wire 430 may form an electrical path that grounds the first semiconductor chip 200, and the first bonding wire 410 and the second bonding wire 420 may form an electrical path that supplies power to the first semiconductor chip 200. In this case, the capacitor 300 may also be electrically connected between the electrical path that grounds the first semiconductor chip 200 and the electrical path that supplies power to the first semiconductor chip 200.

[0033] Since the capacitor 300 can be mounted at a position where the capacitor 300 overlaps the first semiconductor chip 200, the area of ​​the region of the package substrate 100 where the capacitor 300 is mounted can be ensured. Therefore, a greater number of capacitors 300 can be mounted on the package substrate 100, and the noise reduction effect can be further increased due to the decoupling effect from a large number of capacitors 300. Therefore, the electrical characteristics of the semiconductor package 10 can be improved.

[0034] Figure 3 FIG. 2 is a perspective view schematically showing a semiconductor package 20 according to an embodiment. Figure 3 In, with Figure 1 and Figure 2 The same reference numerals will be understood to refer to the same components.

[0035] Reference Figure 3 , the semiconductor package 20 may include a capacitor 300, a first semiconductor chip 200, a stacked structure 500 of second semiconductor chips 501, 502 and 503, and a third semiconductor chip 600. The stacked structure 500 of the second semiconductor chips 501, 502 and 503 may be disposed on the package substrate 100 to be separated from the capacitor 300. The second semiconductor chip 502 of the second level and the second semiconductor chip 503 of the third level may be sequentially and vertically stacked on the second semiconductor chip 501 of the first level. The second semiconductor chips 501, 502 and 503 of the first, second and third levels may be stacked at positions offset from each other by a predetermined distance. The second semiconductor chips 501, 502 and 503 of the first, second and third levels may be vertically stacked in the stepped stacked structure 500.

[0036] The first semiconductor chip 200 may be supported by the capacitor 300 to have a height equal to that of the stacked structure 500 of the second semiconductor chip. The third semiconductor chip 600 may be further stacked on the stacked structure 500 of the first semiconductor chip 200 and the second semiconductor chip. The third semiconductor chip 600 may be supported by the stacked structure 500 of the first semiconductor chip 200 and the second semiconductor chip. The second semiconductor chips 501, 502, and 503 may be electrically connected to the package substrate 100 through bonding wires (not shown). The third semiconductor chip 600 may be electrically connected to the package substrate 100 through other bonding wires (not shown).

[0037] The third semiconductor chip 600 may have a larger size than the first semiconductor chip 200 or the second semiconductor chips 501, 502, and 503. When the third semiconductor chip 600 is larger than the second semiconductor chips 501, 502, and 503, a portion 601 of the third semiconductor chip 600 may protrude from the side surface of the stacked structure 500 of the second semiconductor chips 501, 502, and 503 to be cantilevered (overhung). The stacked structure of the capacitor 300 and the first semiconductor chip 200 may support the cantilevered portion 601 of the third semiconductor chip 600. Therefore, it may not be necessary to introduce an additional support to support the cantilevered portion 601 of the third semiconductor chip 600.

[0038] The second semiconductor chips 501 , 502 , and 503 constituting the stack structure 500 may include DRAM memory chips. The third semiconductor chip 600 may include a NAND memory chip. The first semiconductor chip 200 may include a controller that controls the second semiconductor chips 501 , 502 , and 503 and the third semiconductor chip 600 .

[0039] Although not shown, a sealing material may be provided to cover the package substrate 100 , and to cover and protect the capacitor 300 , the first semiconductor chip 200 , the stack structure 500 of the second semiconductor chips 501 , 502 , and 503 , and the third semiconductor chip 600 .

[0040] According to an embodiment of the present disclosure, a semiconductor package structure can be provided, in which a capacitor is arranged to support a semiconductor chip. The capacitor can be arranged while overlapping the semiconductor chip. With this arrangement structure, space for setting passive components in the semiconductor package can be ensured. Therefore, the space utilization rate in the semiconductor package can be improved.

[0041] Figure 4 7800 is a block diagram showing an electronic system including a memory card 7800 using at least one semiconductor package according to an embodiment. The memory card 7800 may include a memory 7810 (e.g., a nonvolatile memory device) and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read out stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one semiconductor package according to an embodiment.

[0042] The memory 7810 may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 to store data or read out stored data in response to a read / write request from the host 7830.

[0043] Figure 5 8710 is a block diagram showing an electronic system 8710 including at least one semiconductor package according to an embodiment. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be connected to each other through a bus 8715 providing a data movement path.

[0044] In one embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include at least one semiconductor package according to an embodiment of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands to be executed by the controller 8711, and the like.

[0045] The memory 8713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0046] The electronic system 8710 may further include an interface 8714, which is configured to send data to and receive data from a communication network. The interface 8714 may be of a wired type or a wireless type. For example, the interface 8714 may include an antenna, or a wired transceiver or a wireless transceiver.

[0047] The electronic system 8710 may be a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0048] If the electronic system 8710 is a device capable of performing wireless communications, the electronic system 8710 can be used in a communication system by using technology such as code division multiple access (CDMA), global system for mobile communications (GSM), North American digital cellular (NADC), enhanced time division multiple access (E-TDMA), wideband code division multiple access (WCDMA), CDMA2000, long term evolution (LTE), or wireless broadband Internet (Wibro).

[0049] The concept of the present invention has been disclosed in conjunction with some of the embodiments described above. It should be understood by those skilled in the art that various modifications, additions and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered restrictive, but illustrative. The scope of the present invention is not limited to the above description, but is defined by the appended claims, and all different features within the equivalent range should be interpreted as being included in the present invention.

[0050] CROSS-REFERENCE TO RELATED APPLICATIONS

[0051] This application claims priority from Korean Application No. 10-2020-0046328, filed on Apr. 16, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: Package substrate; a first semiconductor chip, wherein the first semiconductor chip is disposed on the packaging substrate; as well as at least one capacitor disposed between the packaging substrate and the first semiconductor chip, wherein the at least one capacitor supports the first semiconductor chip, Wherein, the capacitor comprises: a capacitor body; and a first external terminal and a second external terminal, wherein the first external terminal and the second external terminal are respectively disposed at two ends of the capacitor body, wherein the first external terminal is coupled to the package substrate, and wherein the second external terminal supports the first semiconductor chip, and wherein a portion of the second external terminal is exposed and not covered by the first semiconductor chip, The semiconductor package further includes a first bonding wire electrically connecting the portion of the second external terminal to the package substrate.

2. The semiconductor package according to claim 1, wherein The second external terminal includes a nickel layer and a gold layer. 3 . The semiconductor package according to claim 1 , further comprising an insulating adhesive layer bonding the first semiconductor chip to the second external terminal. 4 . The semiconductor package according to claim 1 , further comprising a second bonding wire connecting the portion of the second external terminal to the first semiconductor chip.

5. The semiconductor package according to claim 4, wherein: The first bonding wire and the second bonding wire provide an electrical path connecting the first semiconductor chip to the package substrate.

6. The semiconductor package according to claim 4, wherein: The package substrate includes conductive placement fingers, and the first external terminal is bonded to the conductive placement fingers through a conductive adhesive layer.

7. The semiconductor package according to claim 6, wherein: The conductive adhesive layer includes a solder layer.

8. The semiconductor package according to claim 6, wherein: The package substrate further includes bonding fingers electrically connected to the conductive placement fingers through internal wiring, and The semiconductor package further includes a third bonding wire connecting the first semiconductor chip to the bonding finger.

9. The semiconductor package according to claim 8, wherein: The third bonding wire provides an electrical path for supplying power to the first semiconductor chip, and The first bonding wire and the second bonding wire ground the first semiconductor chip.

10. The semiconductor package according to claim 8, wherein The third bonding wire grounds the first semiconductor chip, and The first bonding wire and the second bonding wire provide an electrical path for supplying power to the first semiconductor chip.

11. The semiconductor package according to claim 1, further comprising: a stacked structure including a second semiconductor chip and disposed on the package substrate to be separated from the capacitor; as well as A third semiconductor chip is supported by the stacked structure of the second semiconductor chips and the first semiconductor chip.

12. The semiconductor package according to claim 1, wherein The capacitor includes a multilayer ceramic capacitor.

13. A semiconductor package, comprising: Package substrate; at least one capacitor, wherein the at least one capacitor is disposed on the packaging substrate; as well as a first semiconductor chip, the first semiconductor chip being arranged only on the at least one capacitor, Wherein, the capacitor comprises: a capacitor body; and a first external terminal and a second external terminal, wherein the first external terminal and the second external terminal are respectively disposed at two ends of the capacitor body, wherein the first external terminal is coupled to the package substrate, and wherein the second external terminal supports the first semiconductor chip, and wherein a portion of the second external terminal is exposed and not covered by the first semiconductor chip, The semiconductor package further includes a first bonding wire electrically connecting the portion of the second external terminal to the package substrate.

Images