Semiconductor package and method of manufacturing semiconductor package

Abstract

A semiconductor device package includes a first die directly bonded to a second die at an interface, wherein the interface includes a conductor and a conductor bond. The semiconductor device package also includes an encapsulant surrounding the first die and the second die and a plurality of through holes extending through the encapsulant. The plurality of through holes are disposed adjacent to the first die and the second die. The semiconductor device package also includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through holes. The plurality of thermal vias are disposed on a surface of the second die and adjacent to the first die. According to an embodiment of the present application, a method for manufacturing a semiconductor package is also provided.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor package and a method of manufacturing the semiconductor package. Background Art

[0002] The semiconductor industry has experienced rapid development due to the continuous improvement of the integration density of many electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density comes from the iterative reduction of the minimum component size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, there is a demand for smaller and more creative semiconductor die packaging technologies. An example of such a packaging system is the stacked package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] According to one embodiment of the present application, a semiconductor device package is provided, comprising: a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor and a conductor bond; an encapsulant surrounding the first die and the second die; a plurality of through holes extending through the encapsulant, wherein the plurality of through holes are arranged adjacent to the first die and the second die; a plurality of thermal vias extending through the encapsulant, wherein the plurality of thermal vias are arranged on a surface of the second die and adjacent to the first die; and a redistribution structure electrically connected to the first die, the second die, and the plurality of through holes.

[0004] According to another embodiment of the present application, a semiconductor package is provided, including: a first die bonded to a second die, wherein a back side of the first die is directly bonded to a front side of the second die; an encapsulant encapsulating the first die and the second die; a redistribution structure electrically connected to the first die and the second die; a plurality of thermal vias extending from a surface of the first die to a surface of the encapsulant opposite to the redistribution structure; and a plurality of through holes extending from the redistribution structure to a surface of the encapsulant opposite to the redistribution structure.

[0005] According to another embodiment of the present application, a method for manufacturing a semiconductor package is provided, including: hybrid bonding a first die and a second die; depositing a seed layer over the first die and the second die and along the side walls of the first die and the second die; plating a plurality of thermal vias on the surface of the seed layer over the first die; encapsulating the first die, the second die, and the plurality of thermal vias in an encapsulant; planarizing the encapsulant to expose the second die and the plurality of thermal vias; and forming a redistribution structure on an opposite side of the second die as the first die.

[0006] Embodiments of the present application relate to integrated circuit packages and methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various embodiments of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1A to 1M Cross-sectional views are shown of intermediate steps in fabricating a semiconductor package in accordance with some embodiments.

[0009] Figure 2 A cross-sectional view of a semiconductor package in accordance with some embodiments is shown.

[0010] Figure 3 A cross-sectional view of a semiconductor package in accordance with some embodiments is shown.

[0011] FIG. 4A to FIG. 4C Cross-sectional views are shown of intermediate steps in fabricating a semiconductor package in accordance with some embodiments.

[0012] Figure 5 A cross-sectional view of a semiconductor package in accordance with some embodiments is shown.

[0013] Figure 6 A cross-sectional view of a semiconductor package in accordance with some embodiments is shown.

[0014] FIG. 7A to FIG. 7D Cross-sectional views are shown of intermediate steps in fabricating a semiconductor package in accordance with some embodiments.

[0015] Figure 8 A cross-sectional view of a semiconductor package in accordance with some embodiments is shown.

[0016] Fig. 9 A cross-sectional view of a semiconductor package in accordance with some embodiments is shown.

[0017] FIG. 10A to FIG. 10C Cross-sectional views are shown of intermediate steps in fabricating a semiconductor package in accordance with some embodiments.

[0018] Fig.11 A cross-sectional view of a semiconductor package in accordance with some embodiments is shown.

[0019] Fig.12 A cross-sectional view of a semiconductor package in accordance with some embodiments is shown. DETAILED DESCRIPTION

[0020] In order to implement the different components of the present invention, the following disclosure provides many different embodiments or examples. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an additional component formed between the first component and the second component so that the first component and the second component are not in direct contact. Moreover, the present invention may repeat reference numbers and / or letters in various examples. This repetition is only for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. Spatially relative position terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0022] According to some embodiments, the stacked die (e.g., a first die bonded to a second die) is encapsulated in an insulating material, and a heat dissipation structure (e.g., a substrate) is bonded to the back side of the second die and the insulating material. In some embodiments, the heat dissipation structure is a semiconductor substrate using metal-to-metal bonding, which improves heat dissipation in the complete package and improves adhesion between the heat dissipation structure and the second die. In other embodiments, the heat dissipation structure is bonded using another bonding configuration (e.g., dielectric-to-dielectric bonding, semiconductor-to-semiconductor bonding, etc.).

[0023] Figures 1A to 1M is a method for forming a semiconductor package 400 (see Figure 1M ) is a cross-sectional view of an intermediate step in the process.

[0024] Reference Figure 1A, a semiconductor die 200 is shown. The die 200 may be a bare chip semiconductor die (e.g., an unpackaged semiconductor die). For example, the die 200 may be a logic die (e.g., an application processor (APs), a central processing unit, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a hybrid memory cube (HBCs), a static random access memory (SRAM) die, a wide input / output (wideIO) memory die, a magnetoresistive random access memory (mRAM) die, a resistive random access memory (rRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front end (AFE) die, a biomedical die, etc.).

[0025] The die 200 may be processed according to an applicable manufacturing process to form an integrated circuit in the die 200. For example, the die 200 includes a semiconductor substrate 202, such as doped or undoped silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 202 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0026] Devices such as transistors, diodes, capacitors, resistors, etc. may be formed in and / or on the semiconductor substrate 202 and may be interconnected by an interconnect structure 206, which, for example, includes metallization patterns 206A in one or more dielectric layers 206B on the semiconductor substrate 202. The interconnect structure 206 electrically connects the devices on the substrate 202 to form one or more integrated circuits.

[0027] The die 200 each also includes a through-via 204, which can be electrically connected to a metallization pattern in the interconnect structure 206. The through-via 204 can include a conductive material (e.g., copper, etc.) and can extend from the interconnect structure 206 into the substrate 202. An insulating barrier layer 208 can be formed around at least a portion of the through-via 204 in the substrate 202. The insulating barrier layer 208 can include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., and can be used to physically and electrically isolate the through-via 204 from the substrate 202. In subsequent processing steps, the substrate 202 can be thinned to expose the through-via 204 (see FIG. 2 ). Figure 1CAfter thinning, the through-via 204 provides an electrical connection from the back side of the substrate 202 to the front side of the substrate 202 .

[0028] Each die 200 also includes contact pads 210 that allow the interconnect structures 206 and devices on the substrate 202 to make external connections. The contact pads 210 may include copper, aluminum (e.g., 28K aluminum), or other conductive materials. The contact pads 210 are located on what may be referred to as an active side or front side 220 of the die 200. The active side / front side 220 of the die 200 may refer to a side of the semiconductor substrate 202 on which active devices are formed. The back side 222 of the die 200 may refer to a side of the semiconductor substrate opposite to the active side / front side.

[0029] Passivation film 212 is disposed on interconnect structure 206, and contact pad 210 is exposed at a top surface of passivation film 212. Passivation film 212 may include silicon oxide, silicon oxynitride, silicon nitride, etc. In some embodiments, contact pad 210 may extend over a top surface of passivation film 212.

[0030] The die 200 may be formed as part of a larger wafer (e.g., connected to other die 200). In some embodiments, the die 200 may be separated from each other before packaging. The separation process may include mechanical sawing, laser cutting, plasma cutting, combinations thereof, etc. In other embodiments, the die 200 is separated after the die 200 is integrated into a semiconductor package. For example, the die 200 may be packaged while still connected as part of a wafer.

[0031] In some embodiments, a chip probe (CP) test can be applied to each die 200 (e.g., through contact pads 210). The CP test checks the electrical functionality of the die 200, and the die that passes the CP test is called a known good die (KGD). The die 200 that fails the CP test is discarded or repaired. In this way, a KGD for packaging is provided, which reduces waste and the expense of packaging defective die.

[0032] After the CP test, a passivation layer 214 is formed on the contact pads 210 and the interconnect structure 206 of each KGD. The passivation layer 214 may include silicon oxide, silicon oxynitride, silicon nitride, etc. The passivation layer 214 may protect the contact pads 210 during subsequent packaging processes as described herein.

[0033] exist Figure 1B In the embodiment, the die 200 is attached face down to the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 102 may be a wafer, so that multiple packages may be formed on the carrier substrate 102 at the same time. Figure 1BOnly a single die 200 is shown in FIG. 1 , but multiple dies 200 may be attached to the carrier substrate 102 for simultaneous processing. For example, the die 200 may be attached to the carrier substrate 102 after singulation using a chip-on-wafer (CoW) process, or the die 200 may be attached to the carrier substrate 102 before singulation using a wafer-on-wafer (WoW) process. The die 200 is disposed face-down so that the front side 220 of the die 200 faces the carrier substrate 102, and the back side 222 of the die 200 faces away from the carrier substrate 102.

[0034] In some embodiments, the die 200 is attached to the carrier substrate 102 by the release layer 104, and the passivation layer 214 of the die 200 may contact the release layer 104. The release layer 104 may be formed of a polymer-based material, and the release layer may be removed from the die 200 and other structures thereon to be formed in subsequent steps together with the carrier substrate 102. In some embodiments, the release layer 104 is an epoxy-based thermal release material such as a light-to-heat conversion (LTHC) release coating, which loses its viscosity when heated. In other embodiments, the release layer 104 may be an ultraviolet (UV) glue, which loses its adhesive properties when exposed to UV light. The release layer 104 may be dispensed in liquid form and cured, may be a laminated film laminated on the carrier substrate 102, or may be the like. In other embodiments, the die 200 may be, for example, melt-bonded to the carrier 102 by melt-bonding the passivation layer 214 to the carrier 102 and the die is directly melt-bonded to the carrier 102. The fusion bonding may form a dielectric to semiconductor bond between the passivation layer 214 and the carrier 103. In such an embodiment, the release layer 104 is omitted.

[0035] exist Figure 1C In the embodiment, a thinning process may be applied to the die 200 to expose the through hole 204. The thinning removes the portion of the substrate 202 above the through hole 204. In some embodiments, the thinning may further remove the barrier layer (e.g., barrier layer 208, see Figure 1A ) at a lateral portion of the through-hole 204. The thinning process may include performing chemical mechanical polishing (CMP), grinding, etch back (e.g., wet etching), combinations thereof, etc. In some embodiments, the thinning process may recess the substrate 202 so that the through-hole 204 extends beyond the back side of the substrate 202. This may be achieved, for example, by a selective etching process that selectively etches the substrate 202 without significantly etching the through-hole 204.

[0036] exist Figure 1D2, a dielectric layer 106 is deposited over the substrate 202 and around a portion of the through-hole 204. For example, the dielectric layer 106 may be deposited around a portion of the through-hole 204 that extends above the substrate 202. The dielectric layer 106 may include silicon oxide, silicon nitride, silicon oxynitride, etc., and the dielectric layer 106 may be deposited using a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. The dielectric layer 106 may be deposited to initially cover the through-hole 204. A planarization step may then be performed to make the surfaces of the through-hole 204 and the dielectric layer 106 substantially flush.

[0037] exist Figure 1E In the embodiment of the present invention, die 300 is bonded to die 200, for example, in a hybrid bonding configuration. Die 300 may have a structure similar to that described for die 200 and will not be described again herein. The materials and formation processes of components in die 300 may be found by referring to similar components in die 200, where similar components in die 200 begin with the number "2", which corresponds to components in die 300 and has a reference number beginning with the number "3". In a particular embodiment, die 300 is a memory die, but other types of dies may also be used.

[0038] The die 300 is disposed face-down so that the front side 320 of the die 300 faces the die 200 and the back side 322 of the die 300 faces away from the die 200. The die 300 is bonded to the dielectric layer 106 on the back side of the die 200 and the through-hole 204 in the die 200. For example, the passivation layer of the die 300 can be directly bonded to the dielectric layer 106, and the contact pad 310 of the die 300 can be directly bonded to the through-hole 204. In one embodiment, the bond between the passivation layer 314 is an oxide-to-oxide bond or the like. The hybrid bonding process also directly bonds the contact pad 310 of the die 300 to the through-hole 204 of the die 200 by direct metal-to-metal bonding. Therefore, the electrical connection between the die 200 and the die 300 is provided by the physical connection of the contact pad 310 to the through-hole 204.

[0039] As an example, the hybrid bonding process begins by aligning the die 200 with the die 300, for example, by applying a surface treatment to one or more of the dielectric layer 106 or the passivation layer 314. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to one or more of the dielectric layer 106 or the passivation layer 314. Then, the hybrid bonding process may continue to align the contact pad 310 with the through hole 204. When the die 200 and the die 300 are aligned, the contact pad 310 may overlap with the corresponding through hole 204. Next, the hybrid bonding includes a pre-bonding step, during which each die 200 is placed in contact with the corresponding die 300. The pre-bonding may be performed at room temperature (e.g., between about 21° C. and about 25° C.). The hybrid bonding process continues with an anneal, for example, at a temperature between about 150° C. and about 400° C. for a duration between about 0.5 hours and about 3 hours, to allow the metal (e.g., copper) in the contact pad 310 and the metal (e.g., copper) of the through-hole 204 to diffuse into each other, thereby forming a direct metal-to-metal bond. Although only a single die 300 is shown bonded to the die 200, other embodiments may include multiple dies 300 bonded to the die 200. In such embodiments, the multiple dies 300 may be in a stacked configuration (e.g., having multiple stacked dies 300) and / or a side-by-side configuration.

[0040] Die 300 may have a smaller surface area than die 200. Die 200 extends laterally beyond die 300 and exposes a portion of dielectric layer 106 after die 200 and die 300 are bonded. With a portion of dielectric layer 106 exposed, an optional heat sink 112 may be attached to dielectric layer 106 to surround die 300. Heat sink 112 may be one or more silicon dies (see, e.g., Figure 1F ), a silicon ring around one or more sides of die 300 (see, e.g., Figure 1G The heat dissipation component 112 may not have any active components and / or may not have any passive components. Therefore, in some embodiments, the heat dissipation component 112 may be referred to as a dummy component.

[0041] The heat sink 112 may be bonded to the dielectric layer 106 by a dielectric-to-dielectric bond using, for example, a raw oxide, a thermal oxide, etc. formed at the bottom surface of the heat sink 112. The dielectric-to-dielectric bonding process may include applying a surface treatment to the oxide on one or more of the dielectric layers 106 or the heat sink 112. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to the oxide on one or more of the dielectric layers 106 or the heat sink 112. Then, the heat sink 112 may be aligned with the dielectric layer 106, and the two may be pressed together to initiate pre-bonding of the heat sink 112 to the die 200. The pre-bonding may be performed at room temperature (e.g., between about 21°C and about 25°C). After the pre-bonding, an annealing process may be applied by, for example, heating the heat sink 112 at a temperature between about 150°C and about 400°C for a duration of about 0.5 hours to about 3 hours. The annealing process of bonding the heat dissipation member 112 to the die 200 and the die 300 to the die 200 may be performed simultaneously, so that separate anneals do not need to be performed.

[0042] In other embodiments, the heat dissipation component 112 may be omitted (see, for example, Figure 2 and Figure 3 In such an embodiment, the surface area of ​​die 300 may be smaller than the surface area of ​​die 200 (see, e.g., Figure 2 ). Optionally, the surface area of ​​die 300 may be the same as the surface area of ​​die 200, and die 300 may be connected to die 200 (see, for example, Figure 3 ). For example, in some embodiments, die 300 can be bonded to die 200 while die 300 and die 200 are still integrated in their respective wafers using a wafer-to-wafer (WoW) bonding process. In other embodiments, singulated die 300 can be bonded to die 200 using a chip-to-wafer (CoW) bonding process while die 200 is still integrated in the wafer.

[0043] exist Figure 1H Insulating material 114 is formed over die 200, around die 300, and around heat sink 112 (if present). In some embodiments, for example, insulating film 114 is a molding compound (e.g., epoxy, resin, moldable polymer, etc.) that is formed or shaped using, for example, a mold (not shown), wherein the mold has a border or other feature for retaining insulating material 114 when applied. Such a mold can be used to pressure mold insulating material 114 around die 300 to force insulating material 114 into openings and recesses, thereby eliminating air pockets in insulating material 114, etc.

[0044] In some embodiments, the insulating material 114 is a dielectric including oxide, nitride, oxynitride, etc. formed over the die 200. In such embodiments, the insulating material 114 may include silicon nitride, silicon oxide, silicon oxynitride, or other dielectric materials, and may be formed by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or other processes.

[0045] Also like Figure 1H As shown, the insulating material 114 can be planarized by, for example, grinding, chemical mechanical polishing (CMP) processes, etc. After planarization, the top surfaces of the encapsulant 114, the die 300, and the heat sink 112 (if present) are substantially flush. The heat sink 112 provides heat dissipation from the surface of the die 200 through the insulating material 114.

[0046] exist Fig. 1I In the embodiment of the present invention, a conductive bonding layer 116 is formed over the die 300, the heat dissipation structure 112 (if present), and the insulating material 114. In some embodiments, the bonding layer 116 includes one or more conductive layers (e.g., metal layers), such as an optional adhesion layer 116A, an optional diffusion barrier layer 116B, and a conductive layer 116C. Each layer in the bonding layer 116 can be deposited by PVD, CVD, ALD, electroplating, etc. The adhesion layer 116A can include titanium, aluminum, tantalum, combinations thereof, etc. The adhesion layer 116A helps to bond the layer 116B and the layer 116C to the die 300, the heat dissipation structure 112 (if present), and the insulating material 114, and the adhesion layer 116A can be omitted in some embodiments. The diffusion barrier layer 116B can include titanium, titanium nitride, tantalum, tantalum nitride, cobalt, combinations thereof, etc. Diffusion barrier layer 116B can be used to prevent or at least reduce the diffusion of the material of conductive layer 116C into the underlying components of the package, and in some embodiments, diffusion barrier layer 116B can be omitted. Conductive layer 116C can include copper, aluminum, indium, combinations thereof, etc. Conductive layer 116C can be used as a bonding interface for the substrate in subsequent process steps. Using a conductive layer as a bonding interface can have advantages, such as improved heat dissipation and adhesion in the resulting package structure.

[0047] exist Figure 1J In the embodiment, a substrate 120 is provided. After the substrate 120 is attached to the die 200 and the die 300, the substrate 120 may be selected to provide heat dissipation (see Figure 1K For example, the substrate 120 may be a silicon substrate, a glass substrate (eg, a glass substrate having a thermal conductivity in a range of about 1.5 w / mK to about 5 w / mK, etc.). In some embodiments, the substrate 120 may not have any active devices and / or any passive devices.

[0048] Likewise Figure 1J As shown, a conductive bonding layer 118 is formed over the substrate 120. In some embodiments, the bonding layer 118 includes one or more conductive layers (e.g., metal layers), such as an optional adhesion layer 118A, an optional diffusion barrier layer 118B, and a conductive layer 118C. Each layer in the bonding layer 118 can be deposited by PVD, CVD, ALD, electroplating, etc. The adhesion layer 118A can include titanium, aluminum, tantalum, combinations thereof, etc. The adhesion layer 118A helps to bond the layer 118B and the layer 118C to the substrate 120, and the adhesion layer 118A can be omitted in some embodiments. The diffusion barrier layer 118B can include titanium, titanium nitride, tantalum, tantalum nitride, cobalt, combinations thereof, etc. The diffusion barrier layer 118B can be used to prevent or at least reduce the diffusion of the material of the conductive layer 118C into the underlying substrate 120, and the diffusion barrier layer 118B can be omitted in some embodiments. The conductive layer 118C can include copper, aluminum, indium, combinations thereof, etc. Conductive layer 118C may be used as a bonding interface to the substrate in subsequent process steps. Using a conductive layer as a bonding interface may have advantages such as improved heat dissipation and adhesion in the resulting package structure.

[0049] The material of the conductive layer 118C may be the same as or different from the material of the conductive layer 116C (see Fig. 1I ). For example, in some embodiments, conductive layer 116C and conductive layer 118C may each be a copper layer, a gold layer, etc. In some embodiments, conductive layer 116C is a copper layer, and conductive layer 118C is a gold layer; alternatively, conductive layer 116C is a gold layer, and conductive layer 118C is a copper layer. In some embodiments, conductive layer 116C is an indium layer, and conductive layer 118C is a gold layer; alternatively, conductive layer 116C is a gold layer, and conductive layer 118C is an indium layer.

[0050] exist Figure 1K In the embodiment, the substrate 120 is bonded to the die 200 and the die 300 by directly bonding the bonding layer 116 to the bonding layer 118. Directly bonding the bonding layer 116 and the bonding layer 118 can form a metal-to-metal bond (e.g., a copper-copper bond, a copper-gold bond, a gold-gold bond, an indium-gold bond, etc.) between the conductive layer 116C and the conductive layer 118C. Bonding the substrate 120 may include aligning the bonding layer 116 and the bonding layer 118, and pressing the two together to initiate pre-bonding of the substrate 120 to the die 200 and the die 300. The pre-bonding may be performed at room temperature (e.g., between about 21° C. and about 25° C.). After the pre-bonding, an annealing process may be applied by, for example, heating at a temperature between about 150° C. and about 400° C. for about 0.5 hours to about 3 hours, so that the metals (e.g., copper, gold, indium, etc.) in the bonding layer 116 and the bonding layer 118 diffuse into each other, thereby forming a direct metal-to-metal bond.

[0051] Substrate 120 may provide improved heat dissipation to die 200 and die 300. For example, die 300, heat sink 112 (if present), and bonding layers 116 and 118 may provide a heat dissipation path from die 200 to die 300. In addition, substrate 120 may serve as a carrier that provides physical support to die 200 and die 300. Thus, the reliability and durability of the device may be improved.

[0052] exist Figure 1L In the embodiment, carrier substrate separation is performed to debond (separate) carrier substrate 102 from die 200. According to some embodiments, debonding includes projecting light such as laser or UV light onto release layer 104 so that release layer 104 decomposes under the heat of the light and carrier substrate 102 can be removed. After carrier substrate 102 is removed, an opening is formed through passivation layer 214 to expose a portion of contact pad 210. For example, the opening is formed using laser drilling, etching, etc.

[0053] Then in Figure 1M In the embodiment of the present invention, a conductive connector 122 is formed on the contact pad 210. The conductive connector 122 may be a BGA connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel plating-electroless palladium immersion gold technology (ENEPIG), etc. The conductive connector 122 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the electrical connector 122 is formed by first forming a solder layer by a commonly used method such as evaporation, electroplating, printing, solder transfer, ball planting, etc. Once the solder layer is formed on the structure, reflow can be performed to shape the material into a desired bump shape. In another embodiment, the conductive connector 122 is a metal column (such as a copper column) formed by sputtering, printing, electronic plating, chemical plating, CVD, etc. The metal column may be free of solder and have a substantially vertical sidewall. In some embodiments, a metal capping layer (not shown) is formed on the top of the metal column connector 122. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof and may be formed by an electroplating process.

[0054] Thus, a semiconductor package 400 is formed. The package substrate 400 has a first die 200 and a second die 300 hybrid-bonded to the first die. For example, the first die 200 may be bonded to the second die 300 by a combination of a dielectric-to-dielectric bond and a metal-to-metal bond. In some embodiments, the first die 200 is bonded to the second die 300 without any intermediate solder region. An insulating material 114 is disposed around the second die 300, and one or more heat dissipation features 112 extend through the insulating material 114 from a surface of the first die 200. The substrate 120 is bonded to the opposite side of the second die 300 as the first die 200 using, for example, direct metal-to-metal bonding. For example, the conductive bonding layer 116 and the insulating material 114 over the second die 300 may be directly bonded to a conductive bonding layer 118 formed on a silicon substrate. The substrate 120 provides heat dissipation and support in the semiconductor package 400.

[0055] In an embodiment where the die 200 is packaged as a portion of a wafer, singulation may be applied to separate the semiconductor package 400 from other simultaneously formed semiconductor packages. As a result of singulation, the substrate 120, the conductive bonding layer 116, the conductive bonding layer 118, the insulating material 114, and the die 200 may all be connected.

[0056] Figure 2 A cross-sectional view of a semiconductor package 410 according to some alternative embodiments is shown. Semiconductor package 410 can be similar to semiconductor package 400, where the same reference numerals indicate the same elements formed using the same process. In semiconductor package 410, heat sink 112 is omitted. Die 200 can be wider than die 300 and extend laterally beyond die 300.

[0057] Figure 3 A cross-sectional view of a semiconductor package 420 according to some alternative embodiments is shown. Semiconductor package 420 may be similar to semiconductor package 400, wherein the same reference numerals indicate the same elements formed using the same process. In semiconductor package 420, heat sink 112 is omitted. Die 200 may have the same width as die 300 and be connected thereto.

[0058] FIG. 4A to FIG. 4C 1 shows a cross-sectional view of an intermediate stage in forming a semiconductor package according to some embodiments. Figure 4A In the figure, it is shown that Fig. 1I and Figure 1J The structures described are similar in structure, wherein the same reference numerals indicate the same elements formed using the same process. Figure 4AIn FIG. 1 , bonding layer 116 is omitted from over die 200 and die 300 . In addition, bonding layer 118 is omitted from substrate 120 . Figure 4A In the embodiment, substrate 120 is aligned with die 300, insulating material 114, and heat sink 112 so that the exposed surface of substrate 120 faces the exposed surface of die 300, insulating material 114, and heat sink 112. This is indicated by arrow 152.

[0059] exist Figure 4B In the embodiment of the present invention, for example, direct bonding is used to directly bond substrate 120 to die 300, insulating material 114, and heat sink 112 without depositing any intermediate bonding layers. In some embodiments, direct bonds are formed between substrate 120 and die 300, and direct bonds may also be formed between heat sink 112 and substrate 120.

[0060] As an example of directly bonding the substrate 120, a surface treatment may be performed on the substrate 120. The surface treatment includes forming a raw oxide or a thermal oxide on the surface of the substrate 120. The surface treatment may further include a plasma treatment process, and the process gas used to generate the plasma may be a hydrogen-containing gas, including a first gas containing hydrogen (H2) and argon (Ar), a second gas containing H2 and nitrogen (N2), or a third gas including H2 and helium (He). Through this treatment, for example, by interacting with the raw oxide or thermal oxide present at the surface of the substrate 120, the number of OH groups at the surface of the substrate 120 increases. Next, the substrate 120 is pressed against the tube core 300, the insulating material 114, and the heat dissipation component 112 to form a weak bond. Subsequently, annealing is performed to strengthen the weak bond and form a molten bond. During the annealing, the H of the OH bond is degassed, thereby forming a Si-O-Si bond between the substrate 120 and the tube core 300, thereby strengthening the bond.

[0061] Substrate 120 may provide improved heat dissipation to die 200 and die 300. For example, die 300 and heat sink 112 (if present) may provide a heat dissipation path from die 200 to die 300. In addition, substrate 120 may serve as a carrier that provides physical support to die 200 and die 300. Thus, device reliability and durability may be improved. Figure 4C It is shown that (for example, as above in Figure 1L to Figure 1M The resulting package is then subjected to processing as described in to remove the carrier 102 and form the connectors 122.

[0062] Figure 5A cross-sectional view of a semiconductor package 510 according to some optional embodiments is shown. Semiconductor package 510 can be similar to semiconductor package 500, where the same reference numerals indicate the same elements formed using the same process. For example, in semiconductor package 510, substrate 120 is directly bonded to die 300 without any intermediate bonding layer. In semiconductor package 510, heat sink 112 is omitted, and die 200 can be wider than die 300 and extend laterally beyond die 300.

[0063] Figure 6 A cross-sectional view of a semiconductor package 520 according to some optional embodiments is shown. Semiconductor package 520 can be similar to semiconductor package 500, where the same reference numerals indicate the same elements formed using the same process. For example, in semiconductor package 520, substrate 120 is directly bonded to die 300 without any intermediate bonding layer. In semiconductor package 520, heat sink 112 is omitted, and die 200 can be wider than die 300 and connected to die 300.

[0064] FIG. 7A to FIG. 7D 6 shows a cross-sectional view of an intermediate step in forming a semiconductor package 600 according to some embodiments. Fig. 7A In the figure, it is shown that Fig. 1I and Figure 1J The structures described are similar in structure, wherein the same reference numerals indicate the same elements formed using the same process. Fig. 7A In FIG. 1 , bonding layer 116 is omitted from over die 200 and die 300 . In addition, bonding layer 118 is omitted from substrate 120 . Fig. 7A In the embodiment, the dielectric bonding layer 152 is deposited on the carrier substrate 120. The dielectric bonding layer 152 may include silicon oxide, silicon oxynitride, etc. and may be deposited by CVD, PVD, ALD, etc. Alternatively, the dielectric bonding layer 152 may be deposited on the die 300, the heat sink 112, and the insulating material 114 instead of on the substrate 120 (see Figure 7B ).

[0065] exist Fig. 7A and Figure 7B In the embodiment, substrate 120 is placed with die 300, insulating material 114, and heat sink 112 such that the exposed surface of substrate 120 faces the exposed surface of die 300, insulating material 114, and heat sink 112. This is indicated by arrow 154.

[0066] exist Figure 7CIn the embodiment of the present invention, for example, the substrate 120 is bonded to the die 300, the insulating material 114, and the heat sink 112 using the dielectric bonding layer 152 to form a dielectric-to-semiconductor bond. In some embodiments, the dielectric-to-semiconductor bond is formed between the dielectric bonding layer 152 and the die 300 and between the heat sink 112 and the substrate 120. In some embodiments, the dielectric-to-semiconductor bond is formed between the dielectric bonding layer 152 and the substrate 120.

[0067] Substrate 120 may provide improved heat dissipation to die 200 and die 300. For example, die 300 and heat sink 112 (if present) may provide a heat dissipation path from die 200 to substrate 120. Additionally, substrate 120 may serve as a carrier that provides physical support to die 200 and die 300. Thus, device reliability and durability may be improved. Fig.7D It is shown that (for example, as above in Figure 1L to Figure 1M The resulting package is then processed (as described in ) to remove the carrier 102 and form the connectors 122. Thus, a semiconductor package 600 is formed.

[0068] Figure 8 A cross-sectional view of a semiconductor package 610 according to some alternative embodiments is shown. Semiconductor package 610 can be similar to semiconductor package 600, where the same reference numerals indicate the same elements formed using the same process. For example, in semiconductor package 610, substrate 120 is bonded to die 300 via dielectric bonding layer 152. In semiconductor package 610, heat sink 112 is omitted, and die 200 can be wider than die 300 and extend laterally beyond die 300.

[0069] Fig. 9 A cross-sectional view of a semiconductor package 620 according to some alternative embodiments is shown. Semiconductor package 620 can be similar to semiconductor package 600, where the same reference numerals indicate the same elements formed using the same process. For example, in semiconductor package 620, substrate 120 is bonded to die 300 via dielectric bonding layer 152. In semiconductor package 620, heat sink 112 is omitted, and die 200 has the same width as die 300 and is connected to die 300.

[0070] FIG. 10A to FIG. 10C 7 shows a cross-sectional view of an intermediate stage in forming a semiconductor package 700 in accordance with some embodiments. Fig. 10A In the figure, it is shown that Fig. 1I and Figure 1J The structures described are similar in structure, wherein the same reference numerals indicate the same elements formed using the same process. Fig. 10A, bonding layer 116 is omitted from over die 200 and die 300. Additionally, bonding layer 118 is omitted from substrate 120. A first dielectric bonding layer 152A is formed on substrate 120, and a second dielectric bonding layer 152B is formed on die 300, insulating material 114, and heat sink 112. Dielectric bonding layer 152A and dielectric bonding layer 152B are substantially similar to dielectric bonding layer 152 and can be formed of similar materials using similar processes as described above.

[0071] Substrate 120 is aligned with die 300 , insulating material 114 , and heat sink 112 so that the exposed surface of substrate 120 faces the exposed surfaces of die 300 , insulating material 114 , and heat sink 112 . This is indicated by arrow 156 .

[0072] exist Fig. 10B In the embodiment, for example, the substrate 120 is bonded to the die 300, the insulating material 114, and the heat sink 112 using the dielectric bonding layer 152A and the dielectric bonding layer 152B to form a dielectric-to-dielectric bond. In some embodiments, a dielectric-to-dielectric bond is formed between the dielectric bonding layer 152A and the dielectric bonding layer 152B.

[0073] As an example of forming a dielectric-to-dielectric bond, a surface treatment may be performed on the dielectric bonding layer 152A and / or the dielectric bonding layer 152B. The surface treatment may further include a plasma treatment process, and the process gas used to generate the plasma may be a hydrogen-containing gas, including a first gas containing hydrogen (H2) and argon (Ar), a second gas containing H2 and nitrogen (N2), or a third gas including H2 and helium (He). Through this treatment, a plurality of OH groups are provided at the surface of the dielectric bonding layer 152A and / or the dielectric bonding layer 152B. Next, the dielectric bonding layer 152A is pressed against the dielectric bonding layer 152B to form a weak bond. Subsequently, annealing is performed to strengthen the weak bond and form a molten bond. During the annealing, the H of the OH bond is degassed, so that a Si-O-Si bond is formed between the dielectric bonding layer 152A and the dielectric bonding layer 152B, thereby strengthening the bond.

[0074] Substrate 120 may provide improved heat dissipation to die 200 and die 300. For example, die 300 and heat sink 112 (if present) may provide a heat dissipation path from die 200 to die 300. In addition, substrate 120 may serve as a carrier that provides physical support to die 200 and die 300. Thus, device reliability and durability may be improved. Fig. 10C It is shown that (for example, as above in Figure 1L to Figure 1M The resulting package is then processed (as described in ) to remove the carrier 102 and form the connector 122. Thus, the semiconductor package 700 is formed.

[0075] Fig.11 A cross-sectional view of a semiconductor package 710 according to some alternative embodiments is shown. Semiconductor package 710 may be similar to semiconductor package 700, where the same reference numerals indicate the same elements formed using the same process. For example, in semiconductor package 710, substrate 120 is bonded to die 300 via dielectric bonding layer 152A and dielectric bonding layer 152B. In semiconductor package 710, heat sink 112 is omitted, and die 200 may be wider than die 300 and extend laterally beyond die 300.

[0076] Fig.12 A cross-sectional view of a semiconductor package 720 according to some optional embodiments is shown. Semiconductor package 720 can be similar to semiconductor package 700, where the same reference numerals indicate the same elements formed using the same process. For example, in semiconductor package 720, substrate 120 is bonded to die 300 through dielectric bonding layer 152A and dielectric bonding layer 152B. In semiconductor package 720, heat sink 112 is omitted, and die 200 has the same width as die 300 and is connected to die 300.

[0077] According to some embodiments, the stacked die (e.g., a first die bonded to a second die) is encapsulated in an insulating material, and a substrate is bonded to the back side of the second die and the insulating material. The substrate can provide structural support and heat dissipation. In some embodiments, the substrate is bonded using metal-to-metal bonding, which improves heat dissipation in the complete package and improves adhesion between the substrate and the second die. In other embodiments, the substrate is bonded using another bonding configuration (e.g., with or without an intermediate dielectric bonding layer).

[0078] In some embodiments, a device package includes a first die directly bonded to a second die at an interface, wherein the interface includes a conductor and a conductor bond; an encapsulant surrounding the first die and the second die; a plurality of through-holes extending through the encapsulant, wherein the plurality of through-holes are disposed adjacent to the first die and the second die; a plurality of thermal vias extending through the encapsulant, wherein the plurality of thermal vias are disposed on a surface of the second die and adjacent to the first die; and a redistribution structure electrically connected to the first die, the second die, and the plurality of through-holes. Optionally, in some embodiments, the first die further includes: a semiconductor substrate, wherein a dielectric layer of the second die is directly bonded to the semiconductor substrate at the interface; and a through-substrate via extending through the semiconductor substrate, wherein a contact pad of the second die is directly bonded to the through-substrate via at the interface. Optionally, in some embodiments, the through-substrate via electrically connects the second die to the redistribution structure. Optionally, in some embodiments, the dielectric layer of the first die is directly connected to the dielectric layer of the second die at the interface, and wherein the contact pad of the first die is directly connected to the contact pad of the second die at the interface. Optionally, in some embodiments, the first die includes a through hole extending through the semiconductor substrate, wherein the through hole extends higher than the semiconductor substrate. Optionally, in some embodiments, the device package also includes a passivation dielectric layer disposed above the second die and along the sidewall of the first die. Optionally, in some embodiments, the passivation dielectric layer is disposed between the bottom surface of the plurality of thermal vias and the top surface of the second die. Optionally, in some embodiments, the device package also includes a contact pad on the through hole and the passivation dielectric layer, wherein the contact pad electrically connects the through hole to the redistribution structure. Optionally, in some embodiments, the plurality of thermal vias are electrically isolated from any active devices in the first die and the second die. Optionally, in some embodiments, the plurality of thermal vias are electrically connected to active devices in the first die.

[0079] In some embodiments, a package includes: a first die bonded to a second die, wherein the back side of the first die is directly bonded to the front side of the second die; an encapsulant encapsulating the first die and the second die; a redistribution structure electrically connected to the first die and the second die; a plurality of thermal vias extending from a surface of the first die to a surface of the encapsulant opposite to the redistribution structure; and a plurality of through-holes extending from the redistribution structure to a surface of the encapsulant opposite to the redistribution structure. Optionally, in some embodiments, the first die includes: a semiconductor substrate directly bonded to a dielectric layer of the second die; and a through-hole extending through the semiconductor substrate, wherein a contact pad of the second die is directly bonded to the through-hole. Optionally, in some embodiments, each of the plurality of thermal vias includes a seed layer on the back side of the first die. Optionally, in some embodiments, in a plan view, the plurality of thermal vias extend beyond a sidewall of the second die. Optionally, in some embodiments, the plurality of through vias surround the first die and the second die in a plan view.

[0080] In some embodiments, a method includes hybrid bonding a first die to a second die; depositing a seed layer over and along the sidewalls of the first die and the second die; plating a plurality of thermal vias on a surface of the seed layer over the first die; encapsulating the first die, the second die, and the plurality of thermal vias in an encapsulant; planarizing the encapsulant to expose the second die and the plurality of thermal vias; and forming a redistribution structure on an opposite side of the second die as the first die. Optionally, in some embodiments, the method further includes attaching the first die to a carrier before hybrid bonding the first die to the second die, wherein the seed layer is deposited over the carrier; plating a plurality of through-holes on a surface of the seed layer over the carrier. Optionally, in some embodiments, hybrid bonding the first die to the second die includes: directly bonding the dielectric layer of the second die to the semiconductor substrate of the first die; and directly bonding the contact pads in the dielectric layer of the second die to the through-holes extending through the semiconductor substrate of the first die. Optionally, in some embodiments, the method further comprises removing the first die and the second die from the first carrier before forming the redistribution structure; and attaching the second carrier to a side of the second die opposite to the first die. Optionally, in some embodiments, the method further comprises removing the seed layer from the sidewalls of the first die, the sidewalls of the second die, and the top surface of the second die after plating the plurality of thermal vias.

[0081] According to one embodiment of the present application, a semiconductor device package is provided, comprising: a first die, directly bonded to a second die at an interface, wherein the interface comprises a conductor and a conductor bond; an encapsulant, surrounding the first die and the second die; a plurality of through holes, extending through the encapsulant, wherein the plurality of through holes are arranged adjacent to the first die and the second die; a plurality of thermal vias, extending through the encapsulant, wherein the plurality of thermal vias are arranged on the surface of the second die and adjacent to the first die; and a redistribution structure, electrically connected to the first die, the second die, and the plurality of through holes. In some embodiments, the first die further comprises: a semiconductor substrate, wherein the dielectric layer of the second die is directly bonded to the semiconductor substrate at the interface; and a through-substrate via extending through the semiconductor substrate, wherein the contact pad of the second die is directly bonded to the through-substrate via at the interface. In some embodiments, the through-substrate via electrically connects the second die to the redistribution structure. In some embodiments, the dielectric layer of the first die is directly connected to the dielectric layer of the second die at the interface, and wherein the contact pad of the first die is directly connected to the contact pad of the second die at the interface. In some embodiments, the first die includes a through hole extending through the semiconductor substrate, wherein the through hole extends higher than the semiconductor substrate. In some embodiments, the semiconductor device package also includes a passivation dielectric layer above the second die and below the second die. In some embodiments, the passivation dielectric layer is disposed between a bottom surface of the plurality of thermal vias and a top surface of the second die. In some embodiments, the semiconductor device package also includes a contact pad passing through the dielectric layer and on the through hole and the passivation dielectric layer, wherein the contact pad electrically connects the through hole to the redistribution structure. In some embodiments, the plurality of thermal vias are electrically isolated from any active devices in the first die and the second die. In some embodiments, the plurality of thermal vias are electrically connected to active devices in the first die.

[0082] According to another embodiment of the present application, a semiconductor package is provided, comprising: a first die bonded to a second die, wherein the back side of the first die is directly bonded to the front side of the second die; an encapsulant encapsulating the first die and the second die; a redistribution structure electrically connected to the first die and the second die; a plurality of thermal vias extending from a surface of the first die to a surface of the encapsulant opposite to the redistribution structure; and a plurality of through holes extending from the redistribution structure to a surface of the encapsulant opposite to the redistribution structure. In some embodiments, the first die comprises: a semiconductor substrate directly bonded to a dielectric layer of the second die; and a through hole extending through the semiconductor substrate, wherein a contact pad of the second die is directly bonded to the through hole. In some embodiments, each of the plurality of thermal vias comprises a seed layer on the back side of the first die. In some embodiments, wherein the plurality of thermal vias extend beyond the sidewall of the second die in a plan view. In some embodiments, wherein the plurality of through holes surround the first die and the second die in a plan view.

[0083] According to another embodiment of the present application, a method for manufacturing a semiconductor package is provided, comprising: hybrid bonding a back side of a first die to a front side of a second die, a portion of the back side of the first die being exposed by the second die; depositing a seed layer over the portion of the back side of the first die and the back side of the second die and along the side walls of the first die and the second die; plating a plurality of thermal vias on the surface of the seed layer over the portion of the back side of the first die; encapsulating the first die, the second die, and the plurality of thermal vias in an encapsulant; planarizing the encapsulant to expose the second die and the plurality of thermal vias; and forming a redistribution structure on the opposite side of the second die as the first die. In some embodiments, the method for manufacturing a semiconductor package further comprises: attaching the first die to a carrier before hybrid bonding the first die to the second die, wherein the seed layer is deposited over the carrier; and plating a plurality of through holes on the surface of the seed layer over the carrier. In some embodiments, hybrid bonding the first die to the second die includes: directly bonding the dielectric layer of the second die to the semiconductor substrate of the first die; and directly bonding the contact pads in the dielectric layer of the second die to the through-holes extending through the semiconductor substrate of the first die. In some embodiments, the method of manufacturing a semiconductor package also includes: removing the first die and the second die from the first carrier before forming the redistribution structure; and attaching the second carrier to a side of the second die opposite the first die. In some embodiments, the method of manufacturing a semiconductor package also includes removing the seed layer from the sidewalls of the first die, the sidewalls of the second die, and the back side of the second die after plating the plurality of thermal vias.

[0084] The parts of several embodiments are discussed above so that those skilled in the art can better understand various aspects of the present invention. It should be understood by those skilled in the art that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. It should also be appreciated by those skilled in the art that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device package, comprising: a first die directly bonded to a second die at an interface, wherein the interface includes a conductor and a conductor bond, the first die including a semiconductor substrate and a plurality of through vias extending through the semiconductor substrate; an encapsulant surrounding the first die and the second die; a plurality of thermal vias extending through the encapsulant, wherein the plurality of thermal vias are disposed on a top surface of the first die and adjacent to the second die; a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias; a first conductive bonding layer on the second die and the encapsulant; and The substrate is bonded to the first conductive bonding layer through a second conductive bonding layer, wherein the first conductive bonding layer is in physical contact with the second conductive bonding layer.

2. The semiconductor device package according to claim 1, wherein: The dielectric layer of the second die is directly bonded to the semiconductor substrate at the interface; and The contact pads of the second die are directly bonded to the through vias at the interface.

3. The semiconductor device package according to claim 1, wherein: The through via electrically connects the second die to the redistribution structure.

4. The semiconductor device package according to claim 1, wherein: The dielectric layer of the first die is directly connected to the dielectric layer of the second die at the interface, and wherein the contact pads of the first die are directly connected to the contact pads of the second die at the interface.

5. The semiconductor device package according to claim 4, wherein: The through hole extends higher than the semiconductor substrate. 6 . The semiconductor device package of claim 5 , further comprising a passivation dielectric layer over the first die.

7. The semiconductor device package according to claim 6, wherein: The passivation dielectric layer is disposed between bottom surfaces of the plurality of thermal vias and the top surface of the first die.

8. The semiconductor device package according to claim 6, further comprising a contact pad on the through hole and the passivation dielectric layer, wherein: The contact pad electrically connects the through via to the redistribution structure.

9. The semiconductor device package according to claim 1, wherein: The plurality of thermal vias are electrically isolated from any active devices in the first die and the second die.

10. The semiconductor device package according to claim 1, wherein: The plurality of thermal vias are electrically connected to active devices in the first die.

11. A semiconductor package, comprising: a first die bonded to a second die, wherein a back side of the first die is directly bonded to a front side of the second die; an encapsulant on a back side of the first die exposed by the second die and encapsulating the second die; a redistribution structure located on the front side of the first die and electrically connected to the first die and the second die; a plurality of thermal vias extending from a back side of the first die exposed by the second die to a surface of the encapsulant opposite the redistribution structure; and A plurality of through vias extend from the redistribution structure to a back side of the first die.

12. The semiconductor package according to claim 11, wherein: The first tube core comprises: a semiconductor substrate directly bonded to the dielectric layer of the second die; and A through-via extends through the semiconductor substrate, wherein the contact pad of the second die is directly bonded to the through-via. 13 . The semiconductor package of claim 11 , wherein each of the plurality of thermal vias comprises a seed layer on a back side of the first die exposed by the second die.

14. The semiconductor package according to claim 11, wherein The plurality of thermal vias extend beyond a sidewall of the second die in a plan view.

15. The semiconductor package according to claim 11, wherein The plurality of through vias surround the first die and the second die in a plan view.

16. A method for manufacturing a semiconductor package, comprising: hybrid bonding a back side of a first die to a front side of a second die, a portion of the back side of the first die being exposed by the second die; depositing a seed layer over the portion of the back side of the first die and the back side of the second die and along the sidewalls of the first die and the sidewalls of the second die; plating a plurality of thermal vias on a surface of the seed layer over the portion of the back side of the first die; encapsulating the first die, the second die, and the plurality of thermal vias in an encapsulant; planarizing the encapsulant to expose the second die and the plurality of thermal vias; as well as A redistribution structure is formed on an opposite side of the second die as the first die.

17. The method according to claim 16, further comprising: attaching the first die to a carrier prior to hybrid bonding the first die to the second die, wherein the seed layer is deposited over the carrier; and A plurality of through holes are plated on a surface of the seed layer above the carrier.

18. The method according to claim 16, wherein: Hybrid bonding the first die to the second die includes: directly bonding the dielectric layer of the second die to the semiconductor substrate of the first die; and Contact pads in the dielectric layer of the second die are directly bonded to through vias extending through the semiconductor substrate of the first die.

19. The method according to claim 16, further comprising: before forming the redistribution structure, removing the first die and the second die from a first carrier; as well as A second carrier is attached to a side of the second die opposite the first die.

20. The method of claim 16, further comprising removing a seed layer from sidewalls of the first die, sidewalls of the second die, and a top surface of the second die after plating the plurality of thermal vias.

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