Memory device and method of forming a memory device

Abstract

A memory device and a method of forming a memory device are disclosed herein. The memory device includes: a resistance memory array including a first resistance memory cell; a step contact structure adjacent to the resistance memory array; and an intermetallic dielectric layer located above the step contact structure. The memory device also includes: a first diode and a second diode located above the intermetallic dielectric layer. The memory device also includes: a first conductive via electrically coupling the first diode to a first resistor of the first resistance memory cell; and a second conductive via electrically coupling the second diode to a second resistor of the first resistance memory cell.

Description

Technical Field

[0001] Embodiments of the present application relate to memory devices and methods of forming memory devices. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of individual electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continually reducing minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0004] Some embodiments of the present application provide a memory device, including: a resistance memory array, including a first resistance memory cell; a step contact structure adjacent to the resistance memory array; an intermetallic dielectric layer located above the step contact structure; a first diode and a second diode located above the intermetallic dielectric layer; a first conductive via electrically coupling the first diode to a first resistor of the first resistance memory cell; and a second conductive via electrically coupling the second diode to a second resistor of the first resistance memory cell.

[0005] Other embodiments of the present application provide a memory device, including: a first memory cell, including a first transistor, a first resistor, and a second resistor, wherein the first resistor is coupled to a first bit line and the second resistor is coupled to a second bit line; a first diode, connected to a first electrode of the first resistor; a second diode, connected to a second electrode of the second resistor, the first electrode of the first resistor being located above the second electrode of the second resistor; a first conductive via, connected to the first diode; a second conductive via, connected to the second diode; and an intermetallic dielectric layer, wherein the first diode, the second diode, the first conductive via, and the second conductive via are embedded in the intermetallic dielectric layer.

[0006] Still other embodiments of the present application provide a method for forming a memory device, comprising: forming a resistive memory array in a first region of a multilayer stack of material, the resistive memory array comprising a first memory cell; exposing a first resistor and a second resistor of the first memory cell by forming a stepped contact structure adjacent to the resistive memory array; forming a first diode above the stepped contact structure, the first diode being electrically coupled to the first resistor; and forming a second diode above the stepped contact structure, the second diode being electrically coupled to the second resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 A cross-sectional view of a device structure that may be formed over a substrate in accordance with some embodiments is shown.

[0009] Figures 2 to 7 Perspective, cross-sectional, and top views of intermediate stages in fabricating a 3D stackable resistive random access memory (RRAM) array are shown in accordance with an embodiment.

[0010] Figure 8 A perspective view of a 3D memory device incorporating a 3D stackable RRAM array and a first stepped contact structure is shown in accordance with some embodiments.

[0011] Fig. 9 , Fig. 10A and Fig. 10B A cross-sectional view illustrating an intermediate step in forming a first stepped contact structure in accordance with some embodiments.

[0012] Fig.11 is a two-dimensional diagram representing several cross-sectional views of stacked memory cells and a first stepped contact structure of a 3D memory device according to some embodiments.

[0013] Fig.12 is a circuit diagram of an equivalent circuit for stacked memory cells according to some embodiments.

[0014] Fig.13 A cross-sectional view of an interconnect structure according to some embodiments is shown.

[0015] Fig.14A A perspective view of a second 3D memory device incorporating a 3D stackable RRAM array and a second stepped contact structure according to some other embodiments is shown.

[0016] Fig. 14B A cross-sectional view of a stepped contact structure according to some embodiments is shown.

[0017] Fig.15 is a two-dimensional diagram representing several cross-sectional views of stacked memory cells and a second stepped contact structure of a second 3D memory device according to some embodiments.

[0018] Fig.16 A cross-sectional view of a stepped contact structure according to some other embodiments is shown.

[0019] Fig.17 is a two-dimensional diagram representing several cross-sectional views of stacked memory cells and a stepped contact structure of a second 3D memory device according to some other embodiments. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0022] Various embodiments of the present invention provide a 3-dimensional (3D) memory array (e.g., RRAM memory array) including a plurality of stacked memory cells (e.g., 1T2R memory cells), and including a first diode formed over a first resistor of the memory cell electrically connected to the first resistor of the memory cell and a second diode formed over a second resistor of the memory cell electrically connected to the second resistor of the memory cell. Therefore, the first diode and the second diode may be referred to herein as BEOL compatible diodes. In addition, the 3D memory array and the step contact structure may be formed by a multilayer stack of materials used in the manufacturing process. The resulting 3D memory array may also have a reduced height and / or increased device density. In addition, embodiments of the present invention provide a memory cell (e.g., 1T2R) that prevents write interference problems during a write operation to a target resistor of the memory cell. For example, during a write operation to a target resistor of the memory cell, leakage current is prevented from flowing through the bit line of the non-target resistor of the memory cell due to a diode electrically connected to a non-target resistor.

[0023] Figures 1 to 7 1 shows cross-sectional views of various intermediate steps in fabricating a 3D memory array according to some embodiments. Figure 1 , a device structure 103 is shown. The device structure 103 includes a substrate 50, which may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type dopant or an n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulating layer is provided on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0024] Figure 1Also shown is a circuit of the device structure 103 that may be formed above the substrate 50. The circuit includes an active device (e.g., a transistor) located at the top surface of the substrate 50. The transistor may include a gate dielectric layer 202 located above the top surface of the substrate 50 and a gate electrode 204 located above the gate dielectric layer 202. Source / drain regions 206 are disposed in the substrate 50 on opposite sides of the gate dielectric layer 202 and the gate electrode 204. Gate spacers 208 are formed along the sidewalls of the gate dielectric layer 202 to separate the source / drain regions 206 from the gate electrode 204 by an appropriate lateral distance. In some embodiments, the transistor may be a planar field effect transistor (FET), a fin field effect transistor (finFET), a nano field effect transistor (nanoFET), etc.

[0025] The first ILD 210 surrounds and isolates the source / drain regions 206, the gate dielectric layer 202, and the gate electrode 204, and the second ILD 212 is located above the first ILD 210. The source / drain contacts 214 extend through the second ILD 212 and the first ILD 210 and are electrically coupled to the source / drain regions 206, and the gate contact 216 extends through the second ILD 212 and is electrically coupled to the gate electrode 204. An interconnect structure 220 (including one or more stacked dielectric layers 224 and conductive features 222 formed in the one or more stacked dielectric layers 224) is located above the second ILD 212, the source / drain contacts 214, and the gate contact 216. Although Figure 1 Two of the stacked dielectric layers 224 are shown, but it should be understood that the interconnect structure 200 may include any number of stacked dielectric layers 224 having conductive features 222 disposed therein. The interconnect structure 220 may be electrically connected to the gate contact 216 and the source / drain contacts 214 to form a functional circuit. In some embodiments, the functional circuit formed by the interconnect structure 220 may include a logic circuit, a memory circuit, a sense amplifier, a controller, an input / output circuit, an image sensor circuit, etc., or a combination thereof. Although Figure 1 Transistors formed over substrate 50 are discussed, but other active devices (eg, diodes, etc.) and / or passive devices (eg, capacitors, resistors, etc.) may also be formed as part of the functional circuits.

[0026] exist Figure 2 in Figure 2The first multilayer stack 101 is formed above the device structure 103 of FIG. 1 . For the purpose of simplicity and clarity, detailed components of the device structure 103 (e.g., substrate 50, transistors, ILD, and interconnect structure 120) may be omitted from subsequent figures. Although the first multilayer stack 101 is shown as being adjacent to and in physical contact with the device structure 103, any number of intermediate layers may be disposed between the device structure 103 and the first multilayer stack 101. For example, one or more interconnect layers (e.g., redistribution structures) including conductive features in an insulating layer (e.g., a low-k dielectric layer) may be disposed between the device structure 103 and the first multilayer stack 101. In some embodiments, the conductive features may be patterned to provide power lines, ground lines, and / or signal lines for active devices embedded within the device structure 103.

[0027] like Figure 2 As shown, according to some embodiments, the first multilayer stack 101 includes a first series 105a of material layers and a second series 105b of material layers stacked above the first series 105a of material layers. In some embodiments, in an arrangement such as a 3D stacked RRAM device, the first series 105a of layers can be used to ultimately form a first circuit (e.g., a first resistive random access memory (RRAM) cell), and the second series 105b can be used to ultimately form a second circuit stacked above the first circuit (e.g., a second RRAM cell). In addition, the first multilayer stack 101 can be further used to ultimately form a first access transistor for accessing the first circuit and a second access transistor for accessing the second circuit. According to some embodiments, the first access transistor and the second access transistor are formed as nanostructure field effect transistors (NSFETs) and are coupled to the first circuit and the second circuit in a shared access transistor configuration for circuit designs such as 1T2R 3D stacked RRAM devices, etc.

[0028] Although an embodiment of a first multilayer stack 101 having two multilayer series of material layers (e.g., 105a and 105b) is shown, it should be understood that any suitable number of multilayer series of material layers may be formed in the first multilayer stack 101, depending on the desired design of the 3D stacked RRAM device. For example, the first multilayer stack 101 may be formed with more than two multilayer series 105 of material layers, such as three, four, or even more than four multilayer series 105 of material layers. In addition, NSFET transistors may be formed as shared access transistors, etc. All such combinations of the first multilayer stack 101 and access transistors are within the scope of the embodiments.

[0029] According to some embodiments that will eventually form a 1T2R RRAM device, the first multilayer stack 101 is formed to include an isolation layer 107 , a channel layer 109 , a metal line layer 111 , and a dielectric memory layer 113 .

[0030] The first multilayer stack 101 can be formed by first depositing a first layer of a metal line layer 111 over the device structure 103. The metal line layer 111 may include one or more layers, such as a glue layer, a barrier layer, a diffusion layer, and a filling layer, and may be formed using metals and / or metal alloys, such as aluminum (Al), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), silver (Ag), gold (Au), copper (Cu), nickel (Ni), chromium (Cr), hafnium (Hf), ruthenium (Ru), tungsten (W), platinum (Pt), alloys thereof, and the like. In some embodiments, the metal line layer 111 includes a glue layer and a conductive layer. The glue layer may be formed of a metal nitride (e.g., titanium nitride, tantalum nitride, zirconium nitride, hafnium nitride, and the like). The conductive layer may be formed of a metal (e.g., tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), and the like). The material of the glue layer is a material having good adhesion to the material of the upper surface of the device structure 103, and the material of the conductive layer is a material having good adhesion to the material of the glue layer. The glue layer and the conductive layer can each be formed by an acceptable deposition process such as atomic layer deposition, chemical vapor deposition, etc. Once deposited, the material of the metal line layer 111 can be planarized using an optional planarization process.

[0031] A first layer of dielectric memory layer 113 may be formed over metal line layer 111. Dielectric memory layer 113 may be formed as a conformal thin oxide film. According to some embodiments, dielectric memory layer 113 may be formed using one or more layers of acceptable dielectric materials suitable for storing digital values, such as hafnium oxide (HfO2); hafnium zirconium oxide (HfZrO2); (1-x) Zr x O2); zirconium oxide (ZrO2); titanium oxide (TiO2); nickel oxide (NiO); tantalum oxide (TaO x ); copper oxide (Cu2O); niobium pentoxide (Nb2O5); aluminum oxide (Al2O3); combinations thereof, etc. The material of the dielectric memory layer 113 may be formed by an acceptable deposition process such as ALD, CVD, PVD, etc. Once deposited, the material of the dielectric memory layer 113 may be planarized using a process such as chemical mechanical planarization, an etch-back process, a combination thereof, etc.

[0032] Once the dielectric memory layer 113 has been formed, a second layer of the metal wire layer 111 may be formed over the dielectric memory layer 113 using any layers, materials, and processes suitable for forming the first layer of the metal wire layer 111. In some embodiments, the second layer of the metal wire layer 111 includes a glue layer and a conductive layer. The glue layer may be formed of a metal nitride that has good adhesion to the material of the dielectric memory layer 113, and the material of the conductive layer is a material that has good adhesion to the material of the glue layer. Once the metal wire layer 111 has been deposited, an optional planarization process may be performed to planarize the material of the metal wire layer 111.

[0033] Once the second layer of metal wire layer 111 has been formed, a first layer of channel layer 109 may be formed over metal wire layer 111. According to some embodiments, channel layer 109 may be formed by depositing a thin film oxide semiconductor material (e.g., zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), polysilicon, amorphous silicon, indium gallium zinc tin oxide (IGZTO), combinations thereof, etc.) using, for example, a deposition process such as CVD, ALD, PVD, combinations thereof, etc. However, any suitable material and deposition process may be used to form channel layer 109. According to some embodiments, materials such as IGZO, IGZTO, etc. may be used to form a thin film oxide semiconductor material as the first layer of channel layer 109. Such materials may be used to form structurally sound components at low temperatures, such as those used in front end of line (FEOL) processes. Thus, the first layer of channel layer 109 may be formed as a structurally sound layer of thin film oxide semiconductor material in a FEOL process used to form such a channel layer 109.

[0034] Once the first layer of channel layer 109 has been formed, a third layer of metal wire layer 111 may be formed over dielectric memory layer 113 using any layers, materials, and processes suitable for forming the first layer of metal wire layer 111. In some embodiments, the third layer of metal wire layer 111 includes a glue layer and a conductive layer. The glue layer may be formed of a metal nitride that has good adhesion to the material of channel layer 109, and the material of the conductive layer is a material that has good adhesion to the material of the glue layer. Once metal wire layer 111 has been deposited, an optional planarization process may be performed to planarize the material of metal wire layer 111.

[0035] Once the third layer of metal line layer 111 has been formed, a second layer of dielectric memory layer 113 may be formed over metal line layer 111 using any layers, materials, and processes suitable for forming the first layer of dielectric memory layer 113. In some embodiments, the second layer of dielectric memory layer 113 may be formed as a conformal thin oxide film using the same oxide film material (e.g., zinc oxide (ZnO)) as the first layer of dielectric memory layer 113. In other embodiments, different oxide film materials may be used for the first and second layers of dielectric memory layer 113.

[0036] Once the second layer of dielectric memory layer 113 has been formed, a fourth layer of metal wire layer 111 may be formed over dielectric memory layer 113 using any layers, materials, and processes suitable for forming the first layer of metal wire layer 111. In some embodiments, the fourth layer of metal wire layer 111 includes a glue layer and a conductive layer. The glue layer may be formed of a metal nitride that has good adhesion to the material of dielectric memory layer 113, and the material of the conductive layer is a material that has good adhesion to the material of the glue layer. Once metal wire layer 111 has been deposited, an optional planarization process may be performed to planarize the material of metal wire layer 111. Thus, a first series of material layers 105a has been formed.

[0037] Once the first series of material layers 105a have been formed, a first of the isolation layers 107 may be deposited as a bulk layer (e.g., oxide) over the first series of material layers 105a. The isolation layer 107 may be a dielectric material (e.g., silicon oxide (SiO2), SiN, SiON, etc.). The isolation layer 107 may be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. Once deposited, an optional annealing process (e.g., rapid thermal annealing, oxidation densification, etc.) and / or an optional planarization process (e.g., chemical mechanical planarization) may be performed to harden and / or planarize the isolation layer 107. In some embodiments, an optional layer of isolation layer 107 is deposited over the device structure 103 prior to forming the first series of material layers 105a.

[0038] Once the isolation layer 107 has been formed over the first series of material layers 105a, a second series of material layers 105b may be formed over the first series 105a. The second series of layers 105b may be formed using any layers, materials, and processes suitable for forming the first series 105a of layers. In some embodiments, the second series 105b of layers includes the same material layers and layer sequences as the first series 105a, but the material layers and layer sequences may also be different. In the embodiment shown, the second series 105b includes the same material layers and the same layer sequence as the first series 105a.

[0039] In some embodiments, more series of material layers may be formed in first multilayer stack 101 in a stacked fashion until a desired topmost series of material layers has been formed. Any suitable number of series of material layers may be formed in first multilayer stack 101. In the illustrated embodiment, first multilayer stack 101 includes two series of material layers, a first series of layers 105a and a second series of layers 105b stacked above first series of layers 105a.

[0040] Figure 2 Also shown is a first region 115 of the first multilayer stack 101. According to some embodiments, the first region 115 may be designated for forming a 3D stacked memory array. In addition, a second region 117 of the first multilayer stack 101 is adjacent to the first region 115 and may be designated for forming a stepped contact structure for external connection to the 3D stacked memory array.

[0041] Figure 3 It is shown that a gate trench 201 is formed in a word line region 203 of a first multilayer stack 101 according to some embodiments. The word line region 203 may also be referred to herein as a word line region. The gate trench 201 may be formed by first forming a photoresist (not shown) above the first multilayer stack 101. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. The photoresist may be patterned to expose the surface of the topmost layer of the first multilayer stack 101 in the desired location of the gate trench 201. The gate trench 201 may be patterned using one or more photolithography processes including a double patterning process or a multiple patterning process.

[0042] According to some embodiments, a first etch chemistry that is selective to the topmost exposed layer of the first multilayer series 105 of material layers and relatively non-selective to layers below the topmost exposed layer of the first multilayer series 105 can be used to form a gate trench 201 that passes through the topmost exposed layer of the first multilayer series 105 and stops on layers below the topmost exposed layer of the first multilayer series 105. Thus, the layer below the topmost exposed layer of the first multilayer series 105 becomes the next topmost exposed layer of the first multilayer series 105 of material layers. A second etch chemistry that is selective to the next topmost exposed layer of the first multilayer series 105 and relatively non-selective to layers below the next topmost exposed layer of the first multilayer series 105. Thus, the layer below the next topmost exposed layer of the first multilayer series 105 becomes the next topmost exposed layer of the first multilayer series 105. The process may continue using a suitable etching chemistry to remove the next topmost exposed layer of the first multilayer series 105 and stop on a layer of the first multilayer series 105 that is below the next topmost exposed layer of the first multilayer series 105 until the gate trench 201 has been etched through the first multilayer stack 101 and stops on the topmost layer of the device structure 103. For example, chlorine or a fluorine-based gas (such as chlorine (Cl2) or hydrogen fluoride (HF), etc.) may be used to selectively etch the material (e.g., ZnO) of the channel layer 109 without substantially removing the dielectric material (e.g., SiO2) of the isolation layer 107 of the first multilayer series 105. A wet etching chemistry including phosphorus (e.g., H3PO4, etc.) may be used to selectively etch the isolation layer 107 without substantially removing the material (e.g., Ti) of the channel layer 109 and / or the metal line layer 111. In other embodiments, a single etching process may be used to remove all materials of the series of material layers and stop on the topmost layer of device structure 103 , such as utilizing an etching process selective to all materials of first multilayer stack 101 and / or using a timed etching process.

[0043] According to some embodiments, a timed etching process may be used to stop etching the gate trench 201 after the trench has reached a desired depth. For example, the timed etching process may be timed to stop at the surface of the device structure 103, but the timed etching process may be timed to etch into the device structure 103 to a desired depth. According to some embodiments, an optional contact etch stop layer (not shown) may be provided at the interface between the device structure 103 and the first multilayer stack 101. The optional contact etch stop layer may include a dielectric material having an etching rate different from that of the material of the upper layer of the first multilayer stack 101, such as silicon nitride, silicon oxide, silicon oxynitride, etc. In such an embodiment, before forming the first multilayer stack 101, the optional contact etch stop layer is formed over the device structure 103 by a suitable deposition process (e.g., atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc.), and the first multilayer stack 101 is formed over the optional contact etch stop layer. In addition, an additional etching process may be used to remove the material of the optional contact etch stop layer, thereby exposing the device structure 103 at the bottom of the gate trench 201.

[0044] Once patterned, the remaining portion of the first multilayer stack 101 between the gate trenches 201 forms a plurality of strips 205. Thus, the gate trenches 201 are separated by the strips 205. Figure 3 The illustrated embodiment shows that each of the strips 205 has the same width, but the width of the strips 205 of one 3D stacked memory array located in one area of ​​the first multilayer stack 101 can be larger or thinner than the strips 205 of another 3D stacked memory array located in another area of ​​the first multilayer stack 101. According to some embodiments, each of the gate trenches 201 can have a consistent width throughout. In other embodiments, the gate trenches 201 and therefore the strips 205 can have tapered sidewalls so that the width of each of the strips 205 increases continuously in a direction toward the substrate 50. In such an embodiment, each of the layers of the first multilayer stack 101 can have a different width in a direction perpendicular to the sidewalls of the strips 205. In addition, the gate trenches 201 can also extend to the second region 117 ( Figure 2 As shown), the second region 117 is divided into different regions, so as to finally form a stepped contact structure, as shown below. Figure 8 described.

[0045] Figure 4 1 shows a line release process for forming the nanostructure 301 from the channel layer 109. According to some embodiments, once the gate trench 201 has been formed, the spacers and / or photoresist (eg, Figure 2), and a mask layer (not shown) for a line release process may be formed and patterned over the first multilayer stack 101 to expose the word line region 203. In other embodiments, the spacers and / or photoresist layer used to form the gate trenches 201 may be retained, and a mask layer for a line release process may be formed over the spacers and the photoresist layer. In such an embodiment, a mask layer may be formed over the photoresist and / or spacers and then patterned to expose the gate trenches 201 and / or strips 205 ( Figure 2 shown).

[0046] According to some embodiments, the mask layer can be a conductive material or a non-conductive material, and can be selected from a group including silicon nitride, silicon oxynitride, amorphous silicon, polycrystalline silicon (poly silicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide and metal. The mask layer can be deposited by physical vapor deposition (PVD), CVD, ALD, sputtering deposition or other techniques for depositing the selected material. Once the material of the mask layer has been deposited, the material can be patterned using, for example, photolithographic masking and etching processes. Once the mask layer is patterned, the exposed portions of the photoresist and / or spacers are removed using one or more suitable removal processes (e.g., ashing, selective etching, combinations thereof, etc.).

[0047] Once the mask layer has been formed and patterned, the sidewalls of the gate trench 201 and thus the Figure 4 The sidewalls of the strips 205 shown are exposed. Thus, the material of the first multilayer stack 101 of the strips 205 can be removed from between the channel layers 109 during the line release process step and can be removed from between the device structure 103 and the channel layer 109. Thus, the remaining material of the strips 205 (e.g., the channel layer 109) forms a nanostructure 301 between the source / bitline regions 303 of the first multilayer stack 101. The nanostructure 301 may also be referred to herein as a wire, a nanowire, a sheet, and / or a nanosheet. In an embodiment, the material to be removed of the strips 205 is removed using a wet etching process that selectively removes those materials without significantly removing the material of the channel layer 109 that is located within the wordline region 203 and without significantly removing any material within the source / bitline region 303 of the first multilayer stack 101. However, any other suitable removal process may be utilized.

[0048] For example, in an embodiment, a phosphorus-containing etching chemistry (e.g., H3PO4) may be used to selectively remove other materials of the first multilayer stack 101 without substantially removing the material of the semiconductor channel region (e.g., zinc oxide (ZnO)) and / or the material of the device structure 103. However, in other embodiments, any other suitable etchant may be used to selectively remove any other material of the first multilayer stack 101 without substantially removing the material of the channel layer 109 (e.g., zinc oxide (ZnO)) and / or the material of the device structure 103.

[0049] By removing other materials of the first multilayer stack 101, the sides of the nanostructures 301 are exposed and separated from each other in the wordline region 203. The nanostructures 301 form a channel structure between the opposing source / bitline regions 303. In some embodiments, the adjustment of the etching process is selectively used to form the nanostructure 301, and can be adjusted so that the nanostructure 301 is formed to have a smooth surface or include a plurality of surfaces with small planes. Therefore, the nanostructure 301 can be formed to have different contour shapes (e.g., circular, square, rectangular, hexagonal, octagonal, etc.). In the embodiment shown, the nanostructure 301 is formed to have a square contour, and its channel width is approximately the same as the original thickness of the nanostructure 301, but the etching process can also be used to reduce these thicknesses.

[0050] Once the nanostructures 301 have been formed, any remaining portions of the mask layer, the remaining spacers, and / or the remaining photoresist may be removed using one or more suitable removal processes (e.g., wet etching, dry etching, etc.) utilizing one or more etchants that are selective to the materials of the mask layer, the remaining spacers, and / or the remaining photoresist. However, any suitable removal process may be utilized.

[0051] Figure 5The gate dielectric material 401 is shown formed on the sidewalls of the source / bit line regions 303 in the word line region 203 of the first multilayer stack 101 and on the exposed surfaces of the nanostructures 301 between the sidewalls of the source / bit line regions 303 within the word line region 203 of the first multilayer stack 101. The gate dielectric material 401 is formed as a conformal thin film. According to some embodiments, the gate dielectric material 401 may be formed using one or more layers of acceptable dielectric materials suitable for storing digital values, such as multilayer dielectrics (e.g., oxide-nitride-oxide (ONO), nitride-oxide-nitride (NON), etc.); other dielectrics (e.g., silicon oxynitride (SiON), silicon nitride (SiN), etc.); ferroelectric (FE) materials, such as hafnium zirconium oxide (HfZrO); zirconium oxide (ZrO); undoped hafnium oxide (HfO); doped hafnium oxide (e.g., HfLaO using lanthanum (La) as a dopant, HfSiO using silicon (Si) as a dopant, HfAlO using aluminum (Al) as a dopant, etc.); combinations thereof, etc. The material of the gate dielectric material 401 may be formed by an acceptable deposition process such as ALD, CVD, PVD, etc.

[0052] Figure 6The formation of a fully wrapped wordline structure 501 formed above the gate dielectric material 401 within the wordline region 203 of the first multilayer stack 101 is shown. Once the gate dielectric material 401 has been deposited, a planarization process (e.g., chemical mechanical planarization (CMP)) may be performed to remove the gate dielectric material 401 at the top of the first multilayer stack 101. Thus, the metal line layer 111 may be exposed for further processing. The fully wrapped wordline structure 501 may include one or more layers, such as a glue layer, a barrier layer, a diffusion layer, and a filling layer. In some embodiments, the fully wrapped wordline structure 501 includes a glue layer and a conductive layer. The glue layer may be formed of a metal nitride, such as titanium nitride, tantalum nitride, zirconium nitride, hafnium nitride, and the like. The conductive layer may be formed of a metal, such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, and the like. The material of the glue layer is a material having good adhesion to the material of the gate dielectric material 401, and the material of the conductive layer is a material having good adhesion to the material of the glue layer. In an embodiment where the gate dielectric material 401 is formed of an oxide such as an oxide-nitride-oxide (ONO) film, the glue layer may be titanium nitride and the conductive layer may be tungsten. The glue layer and the conductive layer may each be formed by an acceptable deposition process such as ALD, CVD, PVD, etc. The material of the all-around wordline structure 501 may fill and overfill the remaining opening in the wordline region 203 and may be formed over the top surface of the first multilayer stack 101 outside the wordline region 203. The conductive layer fills the remaining area of ​​the gate trench 201. Once deposited, the material of the all-around wordline structure 501 and the gate dielectric material 401 may be planarized with the topmost layer of the first multilayer stack 101 using a process such as chemical mechanical planarization, an etch-back process, a combination thereof, etc.

[0053] Go to Figure 7 , which shows a diagram according to some embodiments Figure 6 The structure shown forms a 3D stacked memory array 600. The 3D stacked memory array 600 includes a plurality of first stacked memory cells 613 (e.g., 1T2R memory cells). In the embodiment shown, each of the first stacked memory cells 613 includes a transistor (e.g., a first transistor T1, a second transistor T2) and two resistors (e.g., a first resistor R1, a second resistor R2) for which values ​​can be set / reset during a write operation. For example, when a write voltage (V W ) and places a word line voltage (V WL ), a write operation can be performed to set / reset to the value stored in the first resistor R1. Similarly, a write operation can be performed to set the write voltage (V W) is placed on the metal source / bit line 603 adjacent to the second resistor R2 and the word line voltage (V WL ) is placed on the all-around gate 605 of the first transistor T1 to set / reset the value stored by the second resistor R2. Similar write operations can be performed on the second transistor T2, the third resistor R3, and the fourth resistor R4. Although embodiments of the memory array 600 have been described using, for example, a 1T2R configuration, other embodiments (not shown) such as a 2T2R configuration may also be utilized. Instead of one common transistor with two resistors (e.g., 1T2R), in a 2T2R configuration, each memory cell 613 may be formed with two transistors and two resistors (e.g., R1 and R2). The two transistors of the 2T2R configuration may be formed with independent channel regions 109 separated by an optional layer (not shown) of the isolation layer 107. Therefore, the two transistors of the 2T2R configuration may operate independently of each other using one of the two resistors (e.g., R1 and R2) during a write operation.

[0054] In addition, in the final formation of the 3D memory device, the 3D stacked memory array 600 can be formed with a stepped contact structure and a BEOL-compatible diode, as discussed in detail below. Therefore, a robust design is provided for the stacked memory cell 613, which prevents write interference problems from occurring during write operations to the resistor. More details on the operation of the stacked memory cell 613 are provided below with respect to the equivalent circuit design of the memory circuit 1200. The isolation layer 107 isolates the stacked memory cells 613 from each other. In addition, the gate isolation plug 601 isolates the fully surrounding gates 605 of adjacent stacks of the first stacked memory cell from each other. According to some embodiments, the fully surrounding gate 605 and the gate isolation plug 601 can be formed by first forming a fully surrounding word line structure 501 ( Figure 6 The word line gaps are formed by etching the word line structure 501 with a word line gap (as shown). The word line gaps can be formed using any photolithography and etching techniques suitable for etching the material of the fully surrounding word line structure 501. The etching can be anisotropic. In some embodiments, the word line gaps can be formed by a series of appropriate etchings (e.g., dry etching and / or wet etching). According to some embodiments, dry etching is performed using a fluorine-based gas (e.g., C4F6) mixed with hydrogen (H2) or oxygen (O2) gas to remove the conductive layer of the fully surrounding word line structure 501, and wet etching is performed using a nitric acid (HNO3) and hydrofluoric acid (HF) solution to remove the glue layer of the fully surrounding word line structure 501. However, other suitable removal processes can be used to remove material from the word line gaps. Therefore, the fully surrounding word line structure 501 is separated into a single structure of the fully surrounding gate 605 by the word line gaps.

[0055] Once the wordline gap has been formed by the all-around wordline structure 501, the gate isolation plug 601 can be formed using any acceptable dielectric material and / or deposition process for forming the gate dielectric material 401. For example, the gate isolation plug 601 can be formed using a dielectric material (e.g., silicon oxide) and an acceptable deposition process (e.g., ALD) to fill and / or overfill the wordline gap, respectively. Once filled and / or overfilled, the gate isolation plug 601 can be planarized (e.g., by CMP) to remove excess material of the gate isolation plug 601 located outside the wordline gap, and to remove excess material of the gate dielectric material 401 located above the top of the first multilayer stack 101. Thus, the top of the gate isolation plug 601, the gate dielectric material 401, and the all-around gate 605 are coplanar with the top of the first multilayer stack 101, and the different structures of the all-around gate 605 are isolated from each other by the gate isolation plug 601. The nanostructure 301 ( Figure 4 109 and surrounded by the gate dielectric material 401, as described above. The all-around gate 605 surrounds the channel regions of the first transistor T1 and the second transistor T2 and is separated from the nanostructure 301 by the gate dielectric material 401. During the line release process described above, the metal source / bit line 603 of the first transistor T1 and the second transistor T2 is formed by the metal line layer 111. The gate dielectric material 401 isolates the all-around gate 605 from the sidewalls of the channel layer 109 and the metal source / bit line 603. The gate dielectric material 401 also isolates the all-around gate 605 from the sidewalls of the first resistor R1 and the second resistor R2.

[0056] In the illustrated embodiment, the first resistor R1 is coupled to the metal source / bit line 603 on the first side of the first transistor T1. The second resistor R2 is coupled to the metal source / bit line 603 on the second side of the first transistor T1. Each of the first resistor R1 and the second resistor R2 includes a resistive memory film 611 and a top electrode 609. During the line release process described above, the resistive memory film 611 is formed by the dielectric memory layer 113. The resistive memory films 611 are respectively coupled to the metal source / bit line 603 on the opposite side of the first transistor T1. During the line release process described above, the top electrode 609 is formed by the metal line layer 111. Each of the top electrodes 609 is respectively coupled to the resistive memory films 611 of the first resistor R1 and the second resistor R2. The resistive memory film 611 may have at least two states (a high resistance state and a low resistance state), which may correspond to two logic states, namely, a set and a reset state. The state of the resistance memory film 611 can be determined by applying a voltage to the resistance memory film 611 and determining the current flowing through the resistance memory film 611 (e.g., determining whether the resistance memory film 611 is in a high resistance state or a low resistance state to read the corresponding bit stored by the resistance memory film 611). In the illustrated embodiment, the resistance memory film 611 of the first resistor R1 is coupled to the metal source / bit line 603 on one side of the channel layer 109 of the first transistor T1, and the resistance memory film 611 of the second resistor R2 is coupled to the metal source / bit line 603 on the other side of the channel layer 109 of the first transistor T1. Therefore, the first transistor T1 can be a shared access transistor for activating a read / write operation of any one of the first resistor R1 and the second resistor R2.

[0057] exist Figure 7In the illustrated embodiment, the second stacked memory cell 613 is formed by the second series 105b of the material layer and is stacked above the first stacked memory cell 613 formed by the first series 105a of the material layer. In the illustrated embodiment, each of the second stacked memory cells 613 includes a second transistor T2 and two resistors (e.g., a third resistor R3 and a fourth resistor R4). The resistive memory film 611 of the third resistor R3 is coupled to the metal source / bit line 603 on one side of the channel layer 109 of the second transistor T2, and the resistive memory film 611 of the fourth resistor R4 is coupled to the metal source / bit line 603 on the other side of the channel layer 109 of the second transistor T2. Therefore, the second transistor T2 can be a shared access transistor for read / write operations for activating any one of the third resistor R3 and the fourth resistor R4. In the illustrated embodiment, the gate dielectric material 401 isolates the full surround gate 605 from the sidewalls of the multilayer stack 101 in the source / bit line region 303. Furthermore, the gate isolation plug 601 isolates the fully surrounding gate 605 of the adjacent stack of the second stacked memory cell 613 .

[0058] Figure 8 is a perspective view of a second 3D memory device 850 including a stepped contact structure 800 adjacent to a second 3D stacked memory array 600 according to some embodiments. In particular, Figure 8 A stair contact structure 800 is shown formed in the second region 117 of the second multilayer stack 101 adjacent to the second 3D stacked memory array 600 formed within the first region 115 of the second multilayer stack 101 according to some embodiments. While the illustrated embodiment is directed to forming the stair contact structure 800 in the second region 117 of the second multilayer stack 101, it should be understood and appreciated that a similarly designed stair structure may be appropriately formed within the second region 117 of the second multilayer stack 101 adjacent to the 3D stacked memory array 600. All such combinations of stair structures and memory arrays are within the scope of the embodiments.

[0059] Figure 8 Also shown is a first intermetallic dielectric (IMD) layer 803 formed over the stepped contact structure 800. The first IMD layer 803 is formed within the gate trench 201 extending into the second region 117 of the second multilayer stack 101 and over the exposed surface of the stepped contact structure 800. In addition, Figure 8 Shown are a diode 801 formed over the first IMD layer 803 , a conductive contact 805 formed over the diode 801 and the all-around gate 605 , and a conductive inter-layer via (TIV) 807 electrically coupling the diode 801 and the conductive contact 805 to the stepped contact structure 800 .

[0060] According to some embodiments, the stepped contact structure 800 is Figure 8 The portion associated with the first cut line AA in the step contact structure 800 provides contact to the bit line of the transistor formed in the second 3D stacked memory array 600. Therefore, the portion associated with the first cut line AA of the step contact structure 800 may be referred to herein as a bit line step portion, a BL step portion, a bit line step, a BL step, etc. In addition, in the embodiment shown, the portion of the step contact structure 800 associated with the first cut line AA is Figure 8 The portion associated with the second cut line BB in the step contact structure 800 provides contact to the source line of the transistor formed in the second 3D stacked memory array 600. Therefore, the portion of the step contact structure 800 associated with the second cut line BB may be referred to herein as a source line step portion, an SL step portion, a source line step, an SL step, etc.

[0061] Fig. 9 Shown along Figure 8 800. In the embodiment shown, the stepped contact structure 800 is formed so that portions of the metal source / bit line 603 and portions of the top electrode 609 of each of the second multilayer series 105 are exposed. The stepped contact structure 800 can be formed by multiple etching processes, as an example, where each of the etching processes is implemented by using a different etching mask (e.g., a patterned photoresist) to expose different portions of the second 3D memory device 850 for removal, and by etching for different durations to achieve different etching depths. During the etching of the formation of the stepped contact structure 800, the second 3D stacked memory array 600 can remain protected by the etching mask.

[0062] like Fig. 9 As shown, a portion of each of the second multilayer series 105 that is laterally away from the second 3D stacked memory array 600 is removed to form a stepped contact structure 800. The area of ​​the removed portion of the second multilayer series 105 increases in a vertical direction away from the device structure 103. For example, the higher the metal source / bit line 603 and / or the top electrode 609 is within the second multilayer series 105 (the farther from the device structure 103), the more area of ​​the upper layer within the second multilayer series 105 is removed to expose portions of the metal source / bit line 603 and / or the top electrode 609.

[0063] The step contact structure 800 can be formed by first placing a photoresist 901 above the second multilayer stack 101 after forming the second 3D stacked memory array 600. The photoresist 901 can be formed by using a spin coating technique and can be patterned using an acceptable photolithography technique. The patterned photoresist 901 can expose a portion of the second multilayer stack 101 in the second region 117 while masking the remaining portion of the second multilayer stack 101. Once the photoresist 901 has been patterned, a step etching process suitable for the material to be removed can be used to remove one or more layers of the second multilayer stack 101 in the exposed portion (e.g., the first step region 903a). The step etching process can be any acceptable etching process, such as by wet etching or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic.

[0064] According to some embodiments, etching may remove portions of one or more material layers of the second multilayer stack 101 that are exposed in the first step region 903a, and may stop on a material layer located below the removed one or more material layers. In some embodiments, a recursive etching process may be used, such that the photoresist 901 is patterned to expose a first desired portion of the topmost layer of the isolation layer 107 (e.g., the first step region 903a), and then the patterned photoresist 901 is used as a mask in a step of the recursive etching process to transfer its pattern into the topmost layer of the isolation layer 107. Once transferred, portions of the second multilayer stack 101 are exposed, and the topmost layer of the isolation layer 107 may be used as a hard mask in another step of the recursive etching process to transfer the pattern of the hard mask into one or more layers of the second multilayer stack 101. Once transferred, portions of the layers below the second multilayer stack 101 are exposed in the stepped contact structure 800.

[0065] In some embodiments, the layers of the second multilayer stack 101 can be used as an etch stop layer to control the removal of material during the various etching steps of the recursive etching process. In some embodiments, the etching process can be a timed process to control the removal of material during the etching process. All such etching processes and all such combinations of such etching processes can be used to form the stepped contact structure 800 and are within the scope of the embodiments.

[0066] Once the first stepped region 903a has been exposed, the exposed portion of the second multilayer stack 101 located in the first stepped region 903a is etched using the photoresist 901 as a mask in a stepped etching process. One or more etching steps may be performed in the first stepped region 903a until the desired layer has been exposed. Once the desired layer of the second multilayer stack 101 has been exposed, the photoresist 901 may be trimmed to expose another portion of the second multilayer stack 101 located in the second stepped region 903b while masking the remaining portion of the second multilayer stack 101 located outside the second stepped region 903b. The exposed portion of the second multilayer stack 101 located in the second stepped region 903b may be etched by repeating the stepped etching process using the trimmed photoresist as a mask.

[0067] The trimming of the photoresist 901 and the step etching process may be repeated until a desired number of step contact regions 905 have been exposed. In the illustrated embodiment, eight step contact regions (e.g., 905a, 905b, 905c, 905d, 905e, 905f, 905g, and 905h) are exposed, with the last trimming of the photoresist 901 exposing the eighth step contact region 905h. However, more or fewer step contact regions 905 may be formed based on the desired structure of the 3D memory device. For example, in a second multilayer stack 101 that includes a smaller number of metal source / bit lines 603 and / or top electrodes 609 (e.g., four), fewer step contact regions 905 (e.g., four) may be formed. As another example, in a second multilayer stack 101 including a greater number of metal source / bit lines 603 and / or top electrodes 609 (e.g., nine, ten, eleven, twelve, etc.), more stepped contact regions 905 (e.g., nine, ten, eleven, twelve, etc.) may be formed. The stepped contact structure 800 may be formed with any suitable number of stepped contact regions 905.

[0068] continue Fig. 10A Once the step contact structure 800 has been formed, a first IMD layer 803 is formed over the step contact structure 800. In some embodiments, before forming the first IMD layer 803, the step contact structure 800 is divided into a bit line step portion and a source line step portion, such as Figure 7 In such an embodiment, the first IMD layer 803 fills the stepped trench and isolates the bit line stepped portion from the source line stepped portion.

[0069] According to some embodiments, the first IMD layer 803 is formed using, for example, silicon oxide, silicon nitride, etc., and is formed by a suitable method such as CVD, PVD, ALD, etc. Once formed, according to some embodiments, the first IMD layer 803 is then planarized using the coplanar surfaces of the isolation layer 107, the gate dielectric material 401, the gate isolation plug 601, and the all-around gate 605 in the first region 115 of the second multilayer stack 101. The first IMD layer 803 can be planarized using a process such as chemical mechanical planarization (CMP). The photoresist 901 can be removed using, for example, an ashing process before planarizing the first IMD layer 803. In some embodiments, the photoresist 901 can be removed using a CMP process, an ashing process, a combination thereof, etc. during planarizing the first IMD layer 803.

[0070] Fig. 10A Also shown is a conductive TIV 807 formed through the bit line step portion of the step contact structure 800 in accordance with some embodiments. In the illustrated embodiment, the conductive TIV 807 is formed at the step contact regions 905 (e.g., 905a, 905d, 905e, and 905h, as shown) of the top electrode 609. Fig. 9 According to some embodiments, a conductive TIV 807 is also formed through the first IMD layer 803. Fig. 10A The conductive TIV 807 shown provides an external connection to the top electrode 609 of the bit line ladder structure of the second 3D stacked memory array 600 .

[0071] In embodiments where the conductive TIV 807 is a conductive pillar (e.g., tungsten, copper, aluminum, titanium, alloys, combinations thereof, etc.), the conductive TIV 807 can be formed by first forming the first IMD layer 803 over the first region 115 and the second region 117 of the second multilayer stack 101. Once formed, the first IMD layer 803 is patterned using suitable photolithography and etching processes to form openings through the first IMD layer 803 and expose areas of the step contact region 905 in the desired location of the conductive TIV 807. Once the openings have been formed, the openings can be filled and / or overfilled with a conductive fill material (e.g., W, Al, Cu, etc.) using a suitable deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.). Once deposited, a planarization process can be performed to planarize the top surface of the conductive TIV 807 to be coplanar with the surface of the first IMD layer 803.

[0072] Fig. 10AAlso shown is a diode 801 formed of a first conductive type oxide semiconductor layer 1001 and a second conductive type oxide semiconductor layer 1003 according to some embodiments. The diode 801 can be formed by first depositing a bulk layer of the first conductive type oxide semiconductor layer 1001 to a desired thickness over the coplanar surfaces of the first IMD layer 803 and the conductive TIV 807. Suitable oxide materials that can be used for the first conductive type oxide semiconductor layer 1001 include materials such as zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), etc., and can be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. The first conductive type oxide semiconductor layer 1001 can be doped using any suitable doping process (e.g., in-situ during epitaxial growth, implantation after deposition, combinations thereof, etc.) to have a first conductivity type (e.g., p-type, n-type, p-type, etc.). + Type, etc.). In an embodiment where the first conductivity type is p-type, the first conductivity type oxide semiconductor layer 1001 may be doped using a dopant such as boron hydride (e.g., diborane B2H6). However, any suitable material, deposition process, dopant, and / or doping process may be used to form the first conductivity type oxide semiconductor layer 1001. In an embodiment where the first conductivity type is n-type, the first conductivity type oxide semiconductor layer 1001 may be doped using a dopant such as phosphine (PH3). However, any suitable material, deposition process, dopant, and / or doping process may be used to form the first conductivity type oxide semiconductor layer 1001.

[0073] Once deposited, the first conductivity type oxide semiconductor layer 1001 is planarized using, for example, CMP. Thus, the first conductivity type oxide semiconductor layer 1001 is formed over the conductive TIV 807 and is electrically coupled to the conductive TIV 807 through the first IMD layer 803 to the top electrode 609 of the bit line ladder structure.

[0074] The second conductive type oxide semiconductor layer 1003 can be formed by depositing a bulk layer of a second oxide semiconductor material over the first conductive type oxide semiconductor layer 1001 to a desired thickness. The second conductive type oxide semiconductor layer 1003 can be formed using any oxide material and process suitable for forming the first conductive type oxide semiconductor layer 1001. The second oxide semiconductor material can be formed using the same oxide material as the first oxide semiconductor material, but a different oxide material can also be used. However, the second oxide semiconductor material is formed to be oppositely doped to the material of the first conductive type oxide semiconductor layer 1001. For example, when using p-type or p-type +In the embodiment where the first conductive type oxide semiconductor layer 1001 is doped with an n-type dopant, the second conductive type oxide semiconductor layer 1003 is doped to have a second conductive type (e.g., n-type). In other embodiments where the first conductive type oxide semiconductor layer 1001 is doped with an n-type dopant, the second conductive type oxide semiconductor layer 1003 is doped to have a second conductive type (e.g., p-type or p-type). + Once deposited, the second conductivity type oxide semiconductor layer 1003 is planarized using, for example, CMP. Thus, the second conductivity type oxide semiconductor layer 1003 is formed over the first conductivity type oxide semiconductor layer 1001 and is electrically coupled to the first conductivity type oxide semiconductor layer 1001.

[0075] Once formed, the first conductivity type oxide semiconductor layer 1001 and the second conductivity type oxide semiconductor layer 1003 are then patterned using suitable photolithography and etching processes to form a diode 801. The diode 801 is formed at a desired location above the conductive TIV 807 of the bit line step contact structure. Therefore, the formation of the diode 801 is compatible with the back end of line (BEOL) process.

[0076] Fig. 10A Also shown is a first set of conductive contacts 805 formed for external connection to the diode 801 according to some embodiments. The conductive contacts 805 can be formed by first depositing a second IMD layer 1005 over the surface of the first IMD layer 803 and the diode 801. In some embodiments, the second IMD layer 1005 can also be formed over the coplanar surface of the isolation layer 107, the gate dielectric material 401, the gate isolation plug 601, and the all-around gate 605 in the first region 115 of the second multilayer stack 101. During further processing of the stepped contact structure 800 in the second multilayer stack 101, the second IMD layer 1005 can be used as a protective layer in the first region 115. In other embodiments, a different protective layer (not shown) is formed over the first region 115 before forming the second IMD layer 1005. The second IMD layer 1005 can be formed using any material and process suitable for forming the first IMD layer 803. Once formed, the second IMD layer 1005 is patterned using suitable photolithography and etching processes to form openings through the second IMD layer 1005 in the desired locations of the conductive contacts 805. Thus, the diode 801 is exposed through the openings in the second IMD layer 1005.

[0077] Fig. 10AAlso shown is a conductive contact 805 formed for connection to the diode 801 in accordance with some embodiments. In some embodiments, an optional silicidation process uses a suitable material such as titanium, nickel, cobalt or erbium to reduce the Schottky barrier height of the conductive contact 805. However, other metals such as platinum, palladium, etc. may also be used for the optional silicidation process. In some embodiments, the optional silicidation process is implemented using a blanket deposition of a suitable metal layer in the opening and over the exposed area of ​​the diode 801. The blanket deposition is followed by an annealing step that reacts the metal layer with the exposed second oxide semiconductor material (e.g., ZnO) below the diode 801. The unreacted metal is then removed, such as using a selective etching process. In other embodiments, the optional silicidation process is omitted.

[0078] The conductive contact 805 may be formed by depositing a conductive material (such as W, Al, Cu, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi, combinations of these, etc.) in the opening and over the exposed area of ​​the diode 801 or over the optional silicide contact (if present). The conductive material may be deposited using processes such as sputtering, chemical vapor deposition, electroplating, electroless plating, etc. to fill and / or overfill the opening. Once filled or overfilled, any conductive material deposited outside the opening may be removed using a planarization process such as chemical mechanical polishing (CMP). However, any suitable deposition process and planarization process may be utilized.

[0079] Once the first set of conductive contacts 805 have been formed to the diode 801 , a bit line 1007 may be formed over the conductive contacts 805 . Fig. 10A The first set of conductive contacts 805 are also designated as first and second bit lines BL1 and BL2 associated with the first access transistor T1 and third and fourth bit lines BL3 and BL4 associated with the second access transistor T2 of the second 3D stacked memory array 600. The conductive contacts 805 form external connections between the bit lines 1007 of the second 3D stacked memory array 600 and signal lines, power lines, and ground lines in the underlying active devices and / or device structures 103.

[0080] Go to Fig. 10B, which shows a second set of conductive TIVs 807 formed through the source line step portion of the step contact structure 800 in accordance with some embodiments. The second set of conductive TIVs 807 provide external connections to the metal source / bit lines 603 in the source line step structure associated with the second 3D stacked memory array 600. In the illustrated embodiment, the second set of conductive TIVs 807 are formed in the step contact regions 905 (e.g., 905b, 905c, 905f, and 905g, as shown) of the metal source / bit lines 603 located in the source line step portion. Figure 8 The second set of conductive TIVs 807 may be formed using any of the materials and processes used to form the first set of conductive TIVs 807 in the bit line step portion discussed above. The second set of conductive TIVs 807 may be formed during the process used to form the first set of conductive TIVs 807, but they may also be formed in a different process step.

[0081] Fig. 10B Also shown is the formation of a second set of conductive contacts 805 for connecting to the second set of conductive TIVs 807 in accordance with some embodiments. The second set of conductive contacts 805 can be formed by first forming openings through the second IMD layer 1005 and exposing the second set of conductive TIVs 807 in desired locations of the second set of conductive contacts 805. The openings for the second set of conductive contacts 805 can be formed during the process of forming the openings for the first set of conductive contacts 805. The second set of conductive contacts 805 can be formed using any material and process suitable for forming the first set of conductive contacts 805. The second set of conductive contacts 805 is formed by depositing and planarizing a conductive material in the openings and over the exposed areas of the second set of conductive TIVs 807 or over the optional silicide contacts (if present). However, any suitable deposition process and planarization process can be utilized.

[0082] Once the second set of conductive contacts 805 have been formed to the conductive TIVs 807 in the source line portion of the stepped contact structure 800 , source lines 1009 may be formed over the conductive contacts 805 . Fig. 10B Each of the source lines 1009 is also designated as a first source line SL1 and a second source line SL2 associated with the first access transistor T1 and a third source line SL3 and a fourth source line SL4 associated with the second access transistor T2 in the second 3D stacked memory array 600. The second set of conductive contacts 805 form external connections between the source lines 1009 of the second 3D stacked memory array 600 and signal lines, power lines, and ground lines in the underlying active devices and / or device structures 103.

[0083] In addition, a third set of conductive contacts 805 may also be formed to fully surround the gate 605 ( Figure 8 ). In embodiments where the second IMD layer 1005 is formed over the first region 115, openings for the third set of conductive contacts 805 may be formed in the first region 115, and the third set of conductive contacts 805 may be formed to the all-around gate 605 during the process of forming the second set of conductive contacts 805 to the conductive TIV 807 and / or the first set of conductive contacts 805 to the diode 801. Thus, the third set of conductive contacts 805 may use the same materials and techniques used to form the other sets of conductive contacts 805. However, the third set of conductive contacts 805 may also be formed in different processing steps than those used to form the other sets of conductive contacts 805, and may be formed using different materials and / or techniques than those used to form the other conductive contacts 805. In some embodiments, the third set of conductive contacts 805 may be formed using materials and / or techniques suitable for forming the third set of conductive contacts 805 to the all-around gate 605. Once the third set of conductive contacts 805 have been formed to the all-around gate 605 of the second 3D stacked memory array 600, word lines 1101 may be formed over the third set of conductive contacts 805 using any material and process suitable for forming source lines 1009 and / or bit lines 1007. Fig.11 The third set of conductive contacts 805 provide external connections between the word lines 1101 of the second 3D stacked memory array 600 and signal lines, power lines, and ground lines in the underlying active devices and / or semiconductor die.

[0084] More interlayer dielectric layers (not shown separately) and other conductive features (also not shown separately) may be formed over the conductive contacts 805, source lines 1009, bit lines 1007, and / or word lines 1101 to provide more external connections to the second 3D memory device 850. Examples of more conductive features include, but are not limited to, conductive vias, contact plugs, redistribution layers, contact traces, integrated passive devices, under-bump metallization layers, integrated fan-out devices, interposers, and external contacts. However, any suitable dielectric layers and / or conductive features may be utilized, and all such features are fully intended to be included within the scope of the embodiments.

[0085] Now go to Fig.11 , which is a two-dimensional diagram of a second stacked memory cell 613 (e.g., 1T2R) in a second 3D stacked memory array 600 and an adjacent staircase contact structure 800 according to some embodiments. Although the components of the second stacked memory cell 613 are shown in a two-dimensional diagram, it should be understood that the first source line SL1, the second source line SL2, the word line WL, the first bit line BL1, and the second bit line BL2 may be located across Figure 8 FIG. 8 is a diagram showing a second 3D memory device 850 in different cross-sections.

[0086] continue Fig.11 , in such an embodiment of the second stacked memory cell 613, the diode 801 is formed adjacent to the first IMD layer 803 at the end of the conductive TIV 807 opposite the top electrode 609. The diode 801 is embedded within the second IMD layer 1005, and the conductive contact 805 is electrically coupled to the diode 801 for external bit line connection (e.g., BL1, BL2) to the second stacked memory cell. According to some embodiments, the diode 801 is formed as a pn-type diode, wherein the p-type material of the diode 801 faces the conductive TIV 807, and the n-type material faces the conductive contact 805. In other embodiments, the diode 801 can be formed to have the opposite orientation, such that the n-type material of the diode 801 faces the conductive TIV 807, and the p-type material faces the conductive contact 805. The word line 1101 is electrically coupled to the all-around gate 605 , which provides shared access through the channel layer 109 between the first and second source lines SL1 and SL2 and the first and second resistors R1 and R2 , respectively.

[0087] Fig.12 is the memory circuit 1200 according to some embodiments and Fig.11 An equivalent circuit diagram of the second stacked memory cell 613 (eg, 1T2R) shown in FIG. Fig.12 Also shown is a current 1201 through the memory circuit 1200 during a write operation to the first resistor R1 according to some embodiments. During the write operation, the write voltage V W can be placed on the first bit line BL1 of the memory circuit 1200, a reference voltage (eg, ground (0V)) can be placed on the second bit line BL2, and a word line voltage V WL is placed on the word line WL to activate the second transistor T2. Therefore, the current 1201 flows through the second transistor T2 to the source line SL, which is set according to the write voltage V placed on the first bit line BL1. W To set the resistance of the first resistor R1. Fig.12 It also shows that due to the write voltage V W With the second diode D2 reverse biased, the leakage current 1203 is prevented from flowing through the second bit line BL2. Thus, a write disturb condition to the second resistor R2 is avoided during a write operation to the first resistor R1, which provides the second 3D memory device 850 with a highly robust memory cell.

[0088] During the write operation to the second resistor R2, the write voltage V W is placed on the second bit line BL2, and a reference voltage (eg, 0V) is placed on the first bit line BL1. In response to the word line voltage V WLThe second transistor T2 is activated by placing it on the word line WL. The current 1201 flows through the second transistor T2 to the source line SL. The source line SL is connected to the write voltage V W The resistance of the second resistor R2 is set. W With the first diode D1 reverse biased, during a write operation to the second resistor R2, leakage current 1203 is prevented from passing through the first bit line BL1. Therefore, a write disturb condition to the first resistor R1 is also avoided during a write operation to the second resistor R2, which provides a highly robust memory cell for the second 3D memory device 850.

[0089] Fig.13 A cross-sectional view of an interconnect structure 1300 is shown according to some embodiments, the interconnect structure 1300 including a conductive via 1180 for electrically coupling one or more of a bit line 1007, a source line 1009, and / or a word line 1101 of a second 3D memory device 850 to a first device region 1301 of the device structure 103. In some embodiments, the first device region 1301 is adjacent to the stepped contact structure 800 and includes signal lines, power lines, and ground lines of active devices and / or a first functional semiconductor die. The first device region 1301 may include embedded logic devices such as a central processing unit (CPU), a signal processor, an input / output port, a system memory, and / or an auxiliary storage device.

[0090] According to some embodiments, the device structure 103 includes a substrate 50, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which can be doped (e.g., with a p-type dopant or an n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0091] Fig.13Also shown is a circuit that may be formed over the substrate 50 to form a circuit embedded within the device structure 103. The circuit includes an active device (e.g., a transistor) located at the top surface of the substrate 50. The transistor may include a gate dielectric layer 202 located over the top surface of the substrate 50 and a gate electrode 204 located over the gate dielectric layer 202. Source / drain regions 206 are disposed in the substrate 50 on opposite sides of the gate dielectric layer 202 and the gate electrode 204. Gate spacers 208 are formed along the sidewalls of the gate dielectric layer 202 to separate the source / drain regions 206 from the gate electrode 204 by an appropriate lateral distance. In some embodiments, the transistor may be a planar field effect transistor (FET), a fin field effect transistor (finFET), a nano field effect transistor (nanoFET), etc.

[0092] The first ILD layer 210 surrounds and isolates the source / drain regions 206, the gate dielectric layer 202, and the gate electrode 204, and the second ILD layer 212 is located above the first ILD layer 210. The source / drain contacts 214 extend through the second ILD layer 212 and the first ILD layer 210 and are electrically coupled to the source / drain regions 206, and the gate contact 216 extends through the second ILD layer 212 and is electrically coupled to the gate electrode 204. The interconnect structure 220 (including one or more stacked dielectric layers 224 and conductive features 222 formed in the one or more stacked dielectric layers 224) is located above the second ILD layer 212, the source / drain contacts 214, and the gate contact 216. Although Fig.12 Two of the stacked dielectric layers 224 are shown, but it should be understood that the interconnect structure 220 may include any number of stacked dielectric layers 224 having conductive features 222 disposed therein. The interconnect structure 220 may be electrically connected to the gate contact 216 and the source / drain contacts 214 to form a functional circuit. In some embodiments, the functional circuit formed by the interconnect structure 220 may include a logic circuit, a memory circuit, a sense amplifier, a controller, an input / output circuit, an image sensor circuit, etc., or a combination thereof. Although Fig.12 Transistors formed over substrate 50 are discussed, but other active devices (eg, diodes, etc.) and / or passive devices (eg, capacitors, resistors, etc.) may also be formed as part of the functional circuits.

[0093] The interconnect structure 1300 is formed over the device structure 103 by first forming the first IMD layer 803 over the device structure 103 and forming the second IMD layer 1005 over the first IMD layer 803, as discussed above. Once the first IMD layer 803, the second IMD layer 1005, and (if provided) the topmost dielectric layer of the interconnect structure 220 have been formed, suitable photolithography and etching processes may be used to form openings through these ILD layers in the desired locations of the conductive vias 1180. Thus, the contact areas of the conductive features 222 are exposed through the openings.

[0094] For example, the conductive vias 1180 may extend through the second IMD layer 1005, the first IMD layer 803, and / or the stacked dielectric layer 224 to electrically connect the bit lines 1007, the source lines 1009, and / or the word lines 1101 to the underlying circuitry of the interconnect structure 220 and active devices on the substrate 50. In some embodiments, wiring and / or power lines to and from the memory array may be provided by an interconnect structure formed above the second 3D stacked memory array 600 in addition to or in lieu of the interconnect structure 220. Thus, the second 3D memory device 850 may be completed.

[0095] In embodiments where the conductive contact 805 is a conductive pillar (e.g., tungsten, copper, aluminum, titanium, alloys, combinations thereof, etc.), the conductive contact 805 may be formed by first forming a first IMD layer 803 over the first region 115 and the second region 117 of the second multilayer stack 101. Once formed, the first IMD layer 803 is patterned using suitable photolithography and etching processes to form openings through the interlayer dielectric layer and expose regions of the word line 1101 and / or the step contact region 905 in the desired location of the conductive contact 805. Once the opening has been formed, the opening may be filled and / or overfilled with a conductive fill material (e.g., W, Al, Cu, etc.) using a suitable deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.). Once the conductive contact 805 has been deposited, a planarization process may be performed to planarize the top surface of the conductive contact 805 to be coplanar with the surface of the interlayer dielectric layer. According to some embodiments, once the conductive contacts 805 have been formed, an interlayer dielectric layer (not shown) may remain to allow for further processing of the second 3D stacked memory array 600 .

[0096] Now go to Fig.14A , which shows a third 3D memory device 1450 according to some other embodiments. The third 3D memory device 1450 is similar to the second 3D memory device 850 ( Figure 8), except that the diode 801 is formed adjacent to the top electrode 609 of the first resistor R1 and the second resistor R2 instead of being formed over the first IMD layer 803. According to some embodiments, the third 3D memory device 1450 can be formed using a last intermetal dielectric (IMD) layer process.

[0097] Fig. 14B Shown through Fig.14A A cross-sectional view of the stepped contact structure 800 along the cutting line AA. Fig. 14B Similar to Fig. 10A , except that the diode 801 is disposed adjacent to the top electrode 609 rather than being disposed above the first IMD layer 803 and the conductive TIV 807 above the diode 801. The stepped contact structure 800 may use the same structure as described above with respect to Fig. 9 According to some embodiments, once the stepped contact structure 800 has been formed, the diode 801 can be formed by first placing a mask (e.g., photoresist) over the first region 115 and the second region 117 of the third 3D memory device 1450. The mask (not shown) can be formed and patterned using any of the materials and processes used to form the photoresist 901 described above. Once formed, the mask is patterned to form openings through the mask in the desired locations of the diode 801, so that the top electrode 609 is exposed through the openings in the mask.

[0098] Once the opening has been formed, a first conductivity type oxide semiconductor layer 1001 is deposited within the opening and over the top electrode 609 using a selective growth process. According to some embodiments, the selective growth process may be a bottom-up process for forming the first conductivity type oxide semiconductor layer 1001 substantially at the bottom of the opening and not along the sidewalls of the opening. The selective growth process may be a timed process so that the first conductivity type oxide semiconductor layer 1001 is formed over the top electrode 609 to a desired thickness.

[0099] In addition, the first conductive type oxide semiconductor layer 1001 can be formed using any material suitable for forming a bulk layer of the first conductive type oxide semiconductor layer 1001 described above. The first conductive type oxide semiconductor layer 1001 can be doped using any of the above-described doping processes (e.g., in situ during epitaxial growth) to have a first conductive type (e.g., p-type). However, any suitable material, deposition process, and / or doping process can be used to form the first conductive type oxide semiconductor layer 1001. According to some embodiments, the first conductive type oxide semiconductor layer 1001 can be planarized and / or the thickness can be reduced to a desired height using, for example, an optional etching process. Therefore, the first conductive type oxide semiconductor layer 1001 is formed above the top electrode 609 of the bit line portion of the stepped contact structure 800 and is electrically coupled to the top electrode 609 of the bit line portion of the stepped contact structure 800.

[0100] The second conductive type oxide semiconductor layer 1003 may be formed to a desired thickness using a selective growth process within the opening over the first conductive type oxide semiconductor layer 1001. According to some embodiments, the selective growth process may be a bottom-up process for forming the second conductive type oxide semiconductor layer 1003 substantially not along the sidewalls of the opening at the bottom of the opening over the first conductive type oxide semiconductor layer 1001. The selective growth process may be a timed process such that the second conductive type oxide semiconductor layer 1003 is formed to a desired thickness over the first conductive type oxide semiconductor layer 1001.

[0101] In addition, the second conductive type oxide semiconductor layer 1003 can be formed using any material suitable for forming a bulk layer of the second conductive type oxide semiconductor layer 1003 described above. The second conductive type oxide semiconductor layer 1003 can be doped using any of the above-described doping processes (e.g., in-situ during the epitaxial growth process) to have a second conductive type (e.g., n-type) doped opposite to the first conductive type (e.g., p-type). However, any suitable material, deposition process, and / or doping process can be used to form the second conductive type oxide semiconductor layer 1003. In some embodiments, the second conductive type oxide semiconductor layer 1003 can be planarized and / or the thickness can be reduced to a desired height using, for example, an optional etching process. Therefore, the diode 801 including the first conductive type oxide semiconductor layer 1001 and the second conductive type oxide semiconductor layer 1003 is formed above the top electrode 609 in the bit line portion of the step contact structure 800 and is electrically coupled to the top electrode 609 in the bit line portion of the step contact structure 800. Once the diode 801 has been formed, the mask can be removed using a suitable removal process (e.g., ashing).

[0102] With the mask removed, the surface of the diode 801 and the stepped contact structure 800 not covered by the diode 801 is exposed. Thus, the first IMD layer 803 can be formed over the stepped contact structure 800 and the diode 801 using any suitable materials and processes described above. In addition, a conductive TIV 807 can be formed through the first IMD layer 803 to the diode 801 by first forming an opening through the first IMD layer 803. Once the opening through the first IMD layer 803 has been formed, the diode 801 is exposed at the bottom of the opening. Then, the conductive TIV 807 is formed to the diode 801 using any of the materials and processes described above. Once formed, the conductive TIV 807 is planarized using the surface of the first IMD layer 803.

[0103] In addition, a second IMD layer 1005 is formed over the planar surface of the first IMD layer 803 and / or isolation layer 107 and a conductive contact 805 is formed through the second IMD layer 1005 down to the conductive TIV 807, as described above. In addition, a conductive TIV 807 is formed through the first IMD layer 803 to the metal source / bit line 603, and a conductive contact 805 is formed over the conductive TIV 807 in the source line structure portion of the step contact structure 800, as described above. In addition, a conductive contact 805 is formed over the all-around gate 605 of the second 3D stacked memory array 600, as described above.

[0104] Once the conductive contacts 805 have been formed, a bit line 1007 is formed over the conductive contacts 805 for external connection to the diode 801 in the stepped contact structure 800. In addition, a source line 1009 is formed over the conductive contacts 805 for external connection to the metal source / bit line 603 in the stepped contact structure 800. In addition, a word line 1101 is formed over the conductive contacts 805 for external connection to the all-around gate 605 of the second 3D stacked memory array 600, as described above. According to some embodiments, the bit line 1007, the source line 1009, and the word line 1101 electrically couple the third 3D memory device 1450 to the interconnect structure 1300 in the first device region 1301. As described above, the interconnect structure 1300 electrically couples one or more of the bit lines 1007, source lines 1009 and / or word lines 1101 to one or more active devices and / or signal lines, power lines and ground lines of a first functional semiconductor die (e.g., an embedded logic device, a central processing unit (CPU), a signal processor, an input / output port, a system memory and / or an auxiliary storage device).

[0105] Now go to Fig.15, which is a two-dimensional diagram of a second stacked memory cell 613 (e.g., 1T2R) and an adjacent staircase contact structure 800 in a third 3D memory device 1450 according to some embodiments. Although the components of the second stacked memory cell 613 are shown in the two-dimensional diagram, it should be understood that the first source line SL1, the second source line SL2, the word line WL, the first bit line BL1, and the second bit line BL2 may be located across Fig.14A 14. In different cross-sections of a third 3D memory device 1450.

[0106] continue Fig.15 , the graph is similar to Fig.11 , except that diode 801 is formed adjacent to top electrode 609 instead of being formed on top of first IMD layer 803 and conductive TIV 807 is formed above diode 801. Diode 801 is embedded within second IMD layer 1005 and conductive contact 805 is electrically coupled to conductive TIV 807 for external bit line connection (e.g., BL1, BL2) to second stacked memory cell. According to some embodiments, diode 801 is formed as a pn-type diode, wherein the p-type material of diode 801 faces top electrode 609 and the n-type material faces conductive TIV 807. In other embodiments, diode 801 may be formed with the opposite orientation, such that the n-type material of diode 801 faces top electrode 609 and the p-type material of diode 801 faces conductive TIV 807. The word line 1101 is electrically coupled to the all-around gate 605 , which provides shared access through the channel layer 109 between the first and second source lines SL1 and SL2 and the first and second resistors R1 and R2 , respectively.

[0107] Now go to Fig.16 , which illustrates a cross-sectional view of a cutting line AA of a stepped contact structure 800 of a third 3D memory device 1450 formed by using an IMD layer-first process according to some other embodiments. Fig.16 The formation of the step contact structure 800 is similar to Fig. 14B The formation of the stepped contact structure 800 is shown, except that a first IMD layer 803 is formed before forming the diode 801 over the top electrode 609 .

[0108] According to some embodiments, the step contact structure 800 may use the above-mentioned Fig. 9The step contact structure 800 may be formed by any of the materials and processes described above. Once the step contact structure 800 has been formed, a first IMD layer 803 may be formed above the step contact structure 800 using any of the suitable materials and processes described above. The diode 801 may be formed by first placing a mask (e.g., a photoresist) above the first region 115 and the second region 117 of the third 3D memory device 1450, as described above. Any material and process for forming the photoresist 901 described above may be used to form and pattern a mask (not shown). Once formed, the patterned mask is formed to form an opening through the mask in the desired position of the diode 801, so that the first IMD layer 803 is exposed through the opening in the mask. The mask is then used to form an opening through the first IMD layer 803, thereby exposing the top electrode 609 at the bottom of the opening.

[0109] Once the top electrode 609 is exposed at the bottom of the opening, a diode 801 may be formed at the bottom of the opening by depositing a first conductivity type oxide semiconductor layer 1001 and a second conductivity type oxide semiconductor layer 1003 within the opening and over the top electrode 609. The first conductivity type oxide semiconductor layer 1001 and the second conductivity type oxide semiconductor layer 1003 may be formed substantially without being along the sidewalls of the opening at the bottom of the opening using a selective growth process (e.g., bottom-up deposition). The selective growth process may also be a timed process so that the first conductivity type oxide semiconductor layer 1001 and the second conductivity type oxide semiconductor layer 1003 are formed to a desired thickness of the diode 801 over the top electrode 609. In addition, each of the first conductivity type oxide semiconductor layer 1001 and the second conductivity type oxide semiconductor layer 1003 is oppositely doped (e.g., in situ during epitaxial growth), as discussed above. For example, the first conductivity type oxide semiconductor layer 1001 may be doped with a first conductivity type (e.g., p-type), and the second conductivity type oxide semiconductor layer 1003 may be doped with a second conductivity type (e.g., n-type).

[0110] Once the diode 801 has been formed, a dielectric fill material 1601 is deposited over the diode 801 to fill and / or overfill the opening. The dielectric fill material 1601 can be formed using any material and process suitable for forming the first IMD layer 803. According to some embodiments, the material used to form the dielectric fill material 1601 is the same as the material used to form the first IMD layer 803. In other embodiments, the material used to form the dielectric fill material 1601 is different from the material used to form the first IMD layer 803. Once formed, the dielectric fill material 1601 can be planarized (e.g., CMP) using the second IMD layer 1005 to remove any excess dielectric fill material 1601 outside the opening.

[0111] Conductive TIV 807 can be formed by first forming an opening through dielectric fill material 1601, exposing diode 801 at the bottom of the opening. The opening through dielectric fill material 1601 can be formed using any material and process suitable for forming an opening for conductive TIV 807 in first IMD layer 803 as described above.

[0112] Once the openings have been formed through the dielectric fill material 1601, the conductive TIV 807 is then formed to the diode 801 using any of the materials and processes described above. Once formed, the conductive TIV 807 is planarized using the surfaces of the first IMD layer 803 and the dielectric fill material 1601. In addition, the second IMD layer 1005 can be formed as described above. The conductive contact 805 can be formed through the second IMD layer 1005 and electrically connected to the conductive TIV 807, as described above. According to some embodiments, the bit line 1007 is formed to the conductive contact 805 and electrically couples one or more of the diodes to the interconnect structure 1300 in the first device region 1301.

[0113] Additionally, a conductive TIV 807 may be formed in the source line structure portion of the stepped contact structure 800 by first forming an opening through the first IMD layer 803, exposing the metal source / bit line 603 through the opening. Once formed, the conductive TIV 807, second IMD layer 1005, conductive contacts 805, source line 1009, and word line 1101 may be formed as described above.

[0114] Reference now Fig.17 , which is a two-dimensional diagram of a second stacked memory cell 613 (e.g., 1T2R) and an adjacent staircase contact structure 800 in a third 3D memory device 1450 according to some embodiments. Although the components of the second stacked memory cell 613 are shown in a two-dimensional diagram, it should be understood that the first source line SL1, the second source line SL2, the word line WL, the first bit line BL1, and the second bit line BL2 may be located across Fig.14A 14. In different cross-sections of a third 3D memory device 1450.

[0115] continue Fig.17 , the graph is similar to Fig.15, except that the dielectric fill material 1601 surrounds the conductive TIV 807 disposed above the diode 801. The diode 801, the dielectric fill material 1601, and the remaining conductive TIV 807 are embedded within the second IMD layer 1005, and the conductive contact 805 is electrically coupled to the conductive TIV 807 for external bit line connection (e.g., BL1, BL2) to the second stacked memory cell 613. According to some embodiments, the diode 801 is formed as a pn-type diode, wherein the p-type material of the diode 801 faces the top electrode 609, and the n-type material faces the conductive TIV 807. In other embodiments, the diode 801 can be formed to have an opposite orientation, such that the n-type material of the diode 801 faces the top electrode 609, and the p-type material faces the conductive TIV 807. The word line 1101 is electrically coupled to the all-around gate 605 , which provides shared access through the channel layer 109 between the first source line SL1 and the first resistor R1 and between the second source line SL2 and the second resistor R2 .

[0116] Embodiments of the present invention have some advantageous features. A 3-dimensional (3D) memory array (e.g., RRAM memory array) including a plurality of stacked memory cells (e.g., 1T2R memory cells) is formed, and it includes forming a first diode above a first resistor of the memory cell and forming a second diode above a second resistor of the memory cell. Therefore, the first diode and the second diode may be referred to as BEOL compatible diodes herein. In addition, the source line and the bit line corresponding to each memory cell are formed in the same layer, which allows the height and aspect ratio of the multilayer stack used in the manufacturing process to be reduced. The resulting 3D memory array may also have a reduced height and / or increased device density. Therefore, the memory density of the resulting 3D memory array may be twice the memory density of a memory array of the same chip size. In addition, embodiments of the present invention provide a memory cell (e.g., 1T2R) that prevents write interference problems during a write operation to a target resistor of the memory cell. For example, during a write operation to a target resistor of a memory cell, leakage current is prevented from flowing through the bit line of the non-target resistor of the memory cell due to the reverse bias of the diode attached to the non-target resistor.

[0117] According to an embodiment, a memory device includes: a resistance memory array including a first resistance memory cell; a step contact structure adjacent to the resistance memory array; an intermetallic dielectric layer located above the step contact structure; a first diode and a second diode located above the intermetallic dielectric layer; a first conductive via electrically coupling the first diode to a first resistor of the first resistance memory cell; and a second conductive via electrically coupling the second diode to a second resistor of the first resistance memory cell. In an embodiment of the memory device, the first conductive via is connected to a first top electrode of the first resistor, and the second conductive via is connected to a second top electrode of the second resistor. In an embodiment of the memory device, a first bit line is electrically coupled to the first resistor, and a second bit line is electrically coupled to the second resistor, wherein the first bit line and the second bit line are at least partially disposed in the first resistance memory cell. In an embodiment of the memory device, the first bit line is connected to a first resistance memory film of the first resistor, and the second bit line is connected to a second resistance memory film of the second resistor. In an embodiment of the memory device, the first resistance memory cell includes a first transistor, and the memory device further includes: a third conductive via connected to a first source line, the first source line is electrically coupled to the first transistor; and a fourth conductive via connected to a second source line, the second source line is electrically coupled to the first transistor. In an embodiment of the memory device, the first transistor includes a gate dielectric and a full surround gate surrounding a channel region of the first transistor, wherein the channel region of the first transistor separates the first source line from the second source line and separates the first bit line from the second bit line. In an embodiment, the memory device further includes: a second resistance memory cell located above the first resistance memory cell; a third diode and a fourth diode located above the intermetallic dielectric layer; a fifth conductive via electrically coupling the third diode to a third resistor of the second resistance memory cell; and a sixth conductive via electrically coupling the fourth diode to a fourth resistor of the second resistance memory cell.

[0118] In another embodiment, a memory device includes: a first memory cell including a first transistor, a first resistor, and a second resistor, wherein the first resistor is coupled to a first bit line and the second resistor is coupled to a second bit line; a first diode connected to a first electrode of the first resistor; a second diode connected to a second electrode of the second resistor, the first electrode of the first resistor being located above the second electrode of the second resistor; a first conductive via connected to the first diode; a second conductive via connected to the second diode; and an intermetallic dielectric layer, wherein the first diode, the second diode, the first conductive via, and the second conductive via are embedded in the intermetallic dielectric layer. In an embodiment of the memory device, the first diode includes a first conductive type semiconductor oxide layer adjacent to the first electrode of the first resistor. In an embodiment of the memory device, the first diode includes a second conductive type semiconductor oxide layer adjacent to the first conductive type semiconductor oxide layer. In an embodiment of the memory device, the first conductive type semiconductor oxide layer is p-type and the second conductive type semiconductor oxide layer is n-type. In an embodiment, the memory device further comprises: a third conductive via connected to the first source line; and a fourth conductive via connected to the second source line, the third conductive via and the fourth conductive via being embedded in the intermetallic dielectric layer. In an embodiment of the memory device, the first transistor comprises a fully surrounding gate surrounding the first channel region of the first transistor. In an embodiment, the memory device further comprises: a second memory cell located above the first memory cell, the second memory cell comprising a second transistor, a third resistor and a fourth resistor, wherein the third resistor is coupled to the third bit line and the fourth resistor is coupled to the fourth bit line; a third diode connected to the third electrode of the third resistor; a fourth diode connected to the fourth electrode of the fourth resistor, the third electrode of the third resistor being located above the fourth electrode of the fourth resistor; a fifth conductive via connected to the third diode; and a sixth conductive via connected to the fourth diode, wherein the third diode, the fourth diode, the fifth conductive via and the sixth conductive via are embedded in the intermetallic dielectric layer. In an embodiment of the memory device, the fully surrounding gate surrounds the second channel region of the second transistor.

[0119] In yet another embodiment, the method includes: forming a resistive memory array in a first region of a multilayer stack of materials, the resistive memory array including a first memory cell; exposing a first resistor and a second resistor of the first memory cell by forming a stepped contact structure adjacent to the resistive memory array; forming a first diode above the stepped contact structure, the first diode electrically coupled to the first resistor; and forming a second diode above the stepped contact structure, the second diode electrically coupled to the second resistor. In an embodiment, the method also includes: forming an intermetallic dielectric layer above the stepped contact structure; forming a first contact via through the intermetallic dielectric layer to the first resistor; and forming a second contact via through the intermetallic dielectric layer to the second resistor, wherein forming the first diode and the second diode includes: depositing a first conductive type semiconductor oxide layer above the intermetallic dielectric layer; depositing a second conductive type semiconductor oxide layer above the first conductive type semiconductor oxide layer; and forming a first diode connected to the first contact via and forming a second diode connected to the second contact via by patterning the first conductive type semiconductor oxide layer and the second conductive type semiconductor oxide layer. In an embodiment of the method, forming the first diode includes forming the first diode in direct contact with the first resistor, forming the second diode includes forming the second diode in direct contact with the second resistor, and wherein the method further includes: forming an intermetallic dielectric layer over the first diode, the second diode, and the stepped contact structure; forming a first contact via through the intermetallic dielectric layer to the first diode; and forming a second contact via through the intermetallic dielectric layer to the second diode. In an embodiment, the method further includes: forming an intermetallic dielectric layer over the stepped contact structure; exposing the first resistor and the second resistor by forming an opening in the intermetallic dielectric layer; forming a diode by depositing a first conductive type semiconductor oxide material over the first resistor and the second resistor at the bottom of the opening and depositing a second conductive type semiconductor oxide over the first conductive type semiconductor oxide material at the bottom of the opening; filling the opening with a dielectric material; and forming a conductive via through the dielectric material to each of the diodes. In an embodiment of the method, forming the first conductive type semiconductor oxide material includes using a p-type dopant, and wherein forming the second conductive type semiconductor oxide material includes using an n-type dopant.

[0120] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A memory device, comprising: A resistance memory array including a first resistance memory cell including a first transistor; a stepped contact structure adjacent to the resistance memory array; an intermetallic dielectric layer, located above the stepped contact structure; A first diode and a second diode, located above the intermetallic dielectric layer; a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell, the first resistor being coupled to a metal source / bit line on a first side of the first transistor; as well as A second conductive via electrically couples the second diode to a second resistor of the first resistive memory cell, the second resistor being coupled to a metal source / bit line on a second side of the first transistor.

2. The memory device according to claim 1, wherein: The first conductive via is connected to a first top electrode of the first resistor, and wherein the second conductive via is connected to a second top electrode of the second resistor.

3. The memory device according to claim 2, wherein: A first bit line is electrically coupled to the first resistor, and a second bit line is electrically coupled to the second resistor, wherein the first bit line at least partially and the second bit line at least partially are disposed in the first resistance memory cell.

4. The memory device according to claim 3, wherein: The first bit line is coupled to a first resistance memory film of the first resistor, and wherein the second bit line is coupled to a second resistance memory film of the second resistor.

5. The memory device according to claim 4, wherein: The memory device further comprises: a third conductive via connected to a first source line electrically coupled to the first transistor; and A fourth conductive via is connected to a second source line, and the second source line is electrically coupled to the first transistor.

6. The memory device according to claim 5, wherein: The first transistor includes a gate dielectric and a fully wrapped gate surrounding a channel region of the first transistor, wherein the channel region of the first transistor separates the first source line from the second source line and separates the first bit line from the second bit line.

7. The memory device according to claim 6, further comprising: a second resistance memory unit, located above the first resistance memory unit; a third diode and a fourth diode, located above the intermetallic dielectric layer; a fifth conductive via electrically coupling the third diode to a third resistor of the second resistance memory cell; as well as A sixth conductive via electrically couples the fourth diode to a fourth resistor of the second resistance memory cell.

8. A memory device comprising: a first memory cell comprising a first transistor, a first resistor, and a second resistor, wherein the first resistor is coupled to a first bit line and the second resistor is coupled to a second bit line; a first diode connected to a first electrode of the first resistor, the first resistor being coupled to a metal source / bit line on a first side of the first transistor; a second diode connected to a second electrode of the second resistor, the first electrode of the first resistor being located above the second electrode of the second resistor, the second resistor being coupled to a metal source / bit line on a second side of the first transistor; a first conductive via connected to the first diode; a second conductive via connected to the second diode; and An inter-metal dielectric layer, wherein the first diode, the second diode, the first conductive via, and the second conductive via are embedded in the inter-metal dielectric layer.

9. The memory device according to claim 8, wherein: The first diode includes a first conductivity-type semiconductor oxide layer adjacent to the first electrode of the first resistor.

10. The memory device according to claim 9, wherein: The first diode includes a second conductivity-type semiconductor oxide layer adjacent to the first conductivity-type semiconductor oxide layer.

11. The memory device according to claim 10, wherein: The first conductive type semiconductor oxide layer is a p-type, and the second conductive type semiconductor oxide layer is an n-type.

12. The memory device according to claim 11, further comprising: a third conductive via connected to the first source line; as well as A fourth conductive via is connected to the second source line, and the third conductive via and the fourth conductive via are embedded in the intermetal dielectric layer.

13. The memory device according to claim 12, wherein: The first transistor includes a fully surrounding gate surrounding a first channel region of the first transistor.

14. The memory device according to claim 13, further comprising: a second memory cell located above the first memory cell, the second memory cell comprising a second transistor, a third resistor and a fourth resistor, wherein the third resistor is coupled to a third bit line, and the fourth resistor is coupled to a fourth bit line; a third diode connected to a third electrode of the third resistor; a fourth diode connected to a fourth electrode of the fourth resistor, the third electrode of the third resistor being located above the fourth electrode of the fourth resistor; a fifth conductive via connected to the third diode; and A sixth conductive via is connected to the fourth diode, wherein the third diode, the fourth diode, the fifth conductive via and the sixth conductive via are embedded in the intermetal dielectric layer.

15. The memory device according to claim 14, wherein: The all-around gate surrounds a second channel region of the second transistor.

16. A method of forming a memory device, comprising: forming a resistive memory array in a first region of the multilayer stack of materials, the resistive memory array comprising a first memory cell having a first transistor; exposing a first resistor and a second resistor of the first memory cell by forming a step contact structure adjacent to the resistance memory array; forming a first diode over the stepped contact structure, the first diode electrically coupled to the first resistor, the first resistor coupled to a metal source / bit line on a first side of the first transistor; as well as A second diode is formed over the stepped contact structure, the second diode being electrically coupled to the second resistor, which is coupled to a metal source / bit line on a second side of the first transistor.

17. The method according to claim 16, further comprising: forming an intermetallic dielectric layer over the stepped contact structure; forming a first contact via through the intermetal dielectric layer to the first resistor; as well as forming a second contact via through the intermetal dielectric layer to the second resistor, wherein forming the first diode and the second diode comprises: depositing a first conductivity type semiconductor oxide layer over the intermetallic dielectric layer; depositing a second conductivity type semiconductor oxide layer over the first conductivity type semiconductor oxide layer; and The first diode connected to the first contact via is formed and the second diode connected to the second contact via is formed by patterning the first conductive type semiconductor oxide layer and the second conductive type semiconductor oxide layer.

18. The method according to claim 16, wherein: Forming the first diode comprises forming the first diode in direct contact with the first resistor, wherein forming the second diode comprises forming the second diode in direct contact with the second resistor, and wherein the method further comprises: forming an intermetallic dielectric layer over the first diode, the second diode, and the stepped contact structure; forming a first contact via through the intermetal dielectric layer to the first diode; and A second contact via is formed through the intermetal dielectric layer to the second diode.

19. The method according to claim 16, further comprising: forming an intermetallic dielectric layer over the stepped contact structure; exposing the first resistor and the second resistor by forming an opening in the intermetal dielectric layer; forming a diode by depositing a first conductivity type semiconductor oxide material over the first and second resistors at the bottom of the opening and depositing a second conductivity type semiconductor oxide over the first conductivity type semiconductor oxide material at the bottom of the opening; filling the opening with a dielectric material; as well as Conductive vias are formed through the dielectric material to each of the diodes.

20. The method according to claim 19, wherein: Forming the first conductivity type semiconductor oxide material includes using a p-type dopant, and wherein forming the second conductivity type semiconductor oxide material includes using an n-type dopant.

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