Universal Output Current Regulation for Flyback Converters

Abstract

The present invention is entitled "Universal Output Current Regulation for a Flyback Converter". The present invention discloses a universal primary-only output current regulation for a flyback converter. A controller determines a peak sense resistor voltage in response to a desired average output current of the flyback converter during a continuous conduction mode of operation. After the power switch transistor is turned on, the controller monitors the sense resistor voltage to determine when the sense resistor voltage is equal to the peak sense resistor voltage. When the sense resistor voltage is equal to the peak sense resistor voltage, the controller turns off the power switch transistor to maintain the average output current of the flyback converter equal to the desired average output current.

Description

Technical Field

[0001] The present application relates generally to flyback converters and, more particularly, to flyback converters with primary-only output current regulation. Background Art

[0002] Flyback converters have various modes in which the output current must be regulated rather than the output voltage. For example, there is an output current limit that cannot be exceeded during charging of a battery in a mobile device. If the output current reaches the output current limit during charging, the flyback converter must switch from a constant output voltage regulation mode to a constant output current regulation mode to avoid exceeding the output current limit. In addition, flyback converters used to power light emitting diodes (LEDs) are typically operated in a constant current regulation mode.

[0003] To operate in constant current mode, the flyback converter may include a sense resistor on the secondary side of the transformer to measure the output current. The secondary side controller may then transmit the output current value to the primary side controller via a ground isolated communication channel such as an optocoupler, which then adjusts the switching of the primary side power switch accordingly. However, the sense resistor introduces losses and thus reduces efficiency. Furthermore, the need for an opto-isolator increases manufacturing cost and complexity.

[0004] In order to avoid the need for a secondary-side sensing resistor, primary-only output current sensing flyback converters have been developed. But primary output current sensing in such devices is only valid during discontinuous conduction mode (DCM). In DCM operation, the output load is such that after the power switch is turned off, the secondary winding current (output current) then ramps down from the peak current to zero current. The delay from the primary switch disconnect time to the time when the secondary winding current ramps down to zero in DCM operation is represented as the transformer reset time. Conventional primary-only current sensing uses the transformer reset time to estimate the output current. But this estimate of the output current is only valid during DCM operation. During times of high load, the flyback converter can transition from DCM operation to continuous current mode (CCM). In CCM operation, when the power switch is turned on again, the secondary winding current has not yet ramped down to zero. Therefore, there is a need in the art for improved primary-only current sensing techniques and systems to function in continuous conduction mode. Summary of the invention

[0005] According to a first aspect of the present disclosure, a controller for a flyback converter is provided, the controller comprising: a logic circuit configured to calculate a peak sensing resistor voltage of a current switching cycle of a power switching transistor in response to an expected average output current of the flyback converter during a continuous conduction operation mode; a comparator configured to compare the peak sensing resistor voltage with a sensing resistor voltage; and a switch driver configured to disconnect the power switching transistor in the current switching cycle in response to an output signal from the comparator indicating that the sensing resistor voltage is equal to the peak sensing resistor voltage.

[0006] According to a second aspect of the present disclosure, a method for operating a flyback converter during a continuous conduction mode is provided, the method comprising: measuring a turn-on time of a power switch transistor in a previous switching cycle of the power switch transistor to provide a measured turn-on time; turning on the power switch transistor in a current switching cycle of the power switch transistor; calculating a peak sense resistor voltage in response to a desired average output current, the measured turn-on time, an input voltage to the flyback converter, a turns ratio of a transformer in the flyback converter, and a period of the current switching cycle; and turning off the power switch transistor in the current switching cycle in response to a sense resistor voltage being equal to the peak sense resistor voltage to maintain the average output current of the flyback converter equal to the desired average output current.

[0007] According to a third aspect of the present disclosure, a flyback converter is provided, the flyback converter comprising: a transformer, the transformer comprising a primary winding; a power switch transistor, the power switch transistor connected to the primary winding; a sense resistor, the sense resistor being connected in series with the power switch transistor; and a controller, the controller being configured to control the cycle of the power switch transistor so that in a current cycle of the power switch transistor, a sense resistor voltage on the sense resistor is equal to a peak sense resistor voltage to control the average output current of the flyback converter to be equal to the desired average output current, the peak sense resistor voltage being a function of: the desired average output current of the flyback converter, the period of the current cycle of the power switch transistor, an input voltage to the flyback converter, a measured on-time of the power switch transistor in a previous cycle of the power switch transistor, a magnetizing inductance of the transformer, and a turns ratio of the transformer.

[0008] Other devices, apparatus, systems, methods, features and advantages of the present invention will or will become apparent to those skilled in the art upon reviewing the following drawings and detailed description. It is intended that all such additional devices, apparatus, systems, methods, features and advantages be included within this specification, be within the scope of the present invention, and be protected by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention may be better understood by referring to the following drawings. The components in the drawings are not necessarily drawn to scale, but emphasis is placed on illustrating the principles of the present invention. In the drawings, similar reference numerals indicate corresponding parts throughout the different views.

[0010] Figure 1 An exemplary flyback converter with primary-only output current regulation according to one aspect of the present disclosure is shown.

[0011] Figure 2 shows two consecutive cycles for the power switch transistor SW Figure 1 The primary current waveform and secondary current waveform of the flyback converter.

[0012] Figure 3 A controller for primary-only output current regulation according to one aspect of the present disclosure is shown.

[0013] Figure 4 Pulses of sense resistor voltage during a period of slope compensation are shown, wherein the peak sense resistor voltage is increased to account for slope compensation and still provide only primary output current regulation, according to one aspect of the present disclosure.

[0014] The drawings depict various embodiments for purposes of illustration only. One skilled in the art will readily recognize from the following discussion that alternative embodiments of the structures and methods shown herein may be employed without departing from the principles of the invention described herein. DETAILED DESCRIPTION

[0015] The present invention discloses universal primary-only output current sensing for a flyback converter that is effective in both CCM and DCM operation. This primary-only output current sense is considered "universal" because it is independent of the AC mains standard. For example, the AC mains voltage can be 120VAC or 240VAC, but the primary-only output current disclosed herein is not affected. Because the output current sensing is primary-only, efficiency is improved compared to direct sensing of the output current through a secondary-side sense resistor. In addition, no optocoupler or other type of ground-isolated communication channel is required to transmit the sensed output current value from the secondary side of the flyback converter to the primary side, thereby reducing manufacturing complexity and cost.

[0016] The primary-only output current sensing disclosed herein senses the average output current. After the off-time in a cycle of the power switch transistor, the output current surges high and ramps down before the next on-time in a subsequent cycle of the power switch transistor. The output current does not flow during the on-time of the power switch transistor. Therefore, the average output current takes into account the pulses and zero current periods of the output current in each cycle of the power switch transistor.

[0017] exist Figure 1 An exemplary primary-only output current sensing flyback converter 100 is shown in FIG. A rectifier (such as a diode bridge 112) rectifies the AC mains voltage VAC to provide a rectified input voltage Vin on an input rail 114 of the flyback converter 100. An input capacitor Cin is coupled between the input rail 114 and ground to filter and store the input voltage Vin. The input rail 114 is connected to a primary winding 108 of a transformer T1 having a secondary winding 110. The primary winding 108 is also connected to a power switch transistor SW, which in turn is coupled to ground through a sense resistor Rs. A controller 118 controls the cycling of the power switch transistor SW to regulate the output voltage Vout in a constant voltage mode and to regulate the output current in a constant current mode. When the controller 118 cycles on the power switch transistor SW, the primary winding current flows through the primary winding 108 and the power switch transistor SW to charge the sense resistor voltage on the sense resistor. Regardless of the mode, the controller 118 turns off the power switch transistor SW when the primary winding current reaches a desired peak current. The desired peak current drives the sense resistor voltage to be equal to the desired peak current voltage VIPK. Therefore, the controller 118 uses the sense resistor voltage as a proxy for the primary winding current and turns off the power switch transistor SW in response to the sense resistor voltage rising to be equal to the desired peak current voltage VIPK in each cycle.

[0018] When the primary winding current conducts in response to the power switch transistor SW being turned on, the output current is prevented from conducting (such as through the output diode D1). In other embodiments, the output diode D1 is replaced by a synchronous rectifier transistor. The output capacitor Co filters and stores the output voltage to the load 130. During periods where the load 130 is relatively high, the controller 18 may need to cycle the power switch transistor SW in a continuous conduction mode. Figure 2Some exemplary primary winding current (primary current) and output current (secondary current) waveforms of the flyback converter 100 are shown in FIG. 1 . The first switching cycle starts at time T0. Due to CCM operation, the primary current does not start from zero but starts with a value Imin_LIM. The power switch transistor SW remains on for an on-time equal to D*Tp, where Tp is the period of the cycle of the power switch transistor SW and D is the duty cycle of the on-time (the ratio of the on-time to the switching period Tp). The primary current continues to increase during the on-time until it reaches a peak value IPK at time T1, followed by turning off the power switch transistor SW. When the power switch transistor SW is turned on again, the secondary current pulses to a peak value Ipk_sec at time T1 and then drops to a minimum value Imin_sec at time T2. The time (T2–T1) that the secondary current flows is equal to (1–D)*Tp. Therefore, the switching period from T0 to T2 is equal to D*Tp+(1–D)*Tp, which is of course equal to Tp. Another switching cycle starts at time T2, where the power switch transistor SW is turned on. At time T3, the power switch transistor SW is turned off. The secondary current pulses to its peak value Ipk_sec again at time T3, and decreases to its minimum value Ipk_LIM at time T4 to end the second cycle.

[0019] During constant current mode, the controller 118 controls the cycle of the power switch transistor SW so that the average secondary current Io is equal to the desired value. However, due to the isolation through the transformer T1, the controller 118 cannot directly sense the output current. But the controller 118 can directly control the peak value IPK of the primary winding current. This control can be used to adjust the average output current Io as follows. It can then be seen that the average output current Io is equal to (1–D)*(Ipk_sec-ΔIsec / 2), where ΔIsec is the amount by which the secondary current drops from its peak value Ipk_sec to Imin_sec. Due to the turns ratio Nps in the transformer T1, the peak primary winding current forces the peak secondary current Ipk_sec to be equal to Nps*IPK. Therefore, the average output current Io becomes (1–D)*(Nps*IPK-ΔIsec / 2). The secondary current change ΔIsec is related to the primary current change ΔIL through the turns ratio Nps. The primary current change ΔIL is equal to (Vin*Ton) / Lm, where Vin is the input voltage of the flyback converter 100, Ton is the on-time of the power switch transistor SW in its previous switching cycle, and Lm is the magnetizing inductance of the transformer T1. Therefore, the average output current Io becomes equal to (1–D)*Nps*(IPK-1 / 2*(Vin*Ton) / Lm). It can be concluded that if the peak primary current IPK is set according to the following equation:

[0020] IPK=(Io / ((1–D)*Nps))+1 / 2*Vin*Ton / Lm Eq (1)

[0021] The desired average output current Io is achieved. This relationship is also true in discontinuous conduction mode. It should be noted that (1–D) is equal to (Tp–Ton) / Tp, which is equal to Toff / Ts, where Toff is the off time of the power switch transistor SW in its previous switching cycle. Therefore, equation (1) can be restated as:

[0022] IPK=(Io*Tp) / (Nps*Toff))+1 / 2*Vin*Ton / Lm Eq (2)

[0023] In discontinuous conduction mode, the off time of the previous switching cycle is replaced by the transformer reset time of the previous switching cycle. By Ohm's law, the peak sense resistor voltage VIPK is equal to Rs*IPK. Therefore, the peak sense resistor voltage VIPK corresponding to the peak primary current IPK can be expressed as:

[0024] VIPK=(Io*Tp*Rs) / (Nps*Toff))+1 / 2*Vin*Ton*Rs / Lm Eq (3)

[0025] Where Rs is the sense resistor resistance.

[0026] The parameters Lm and Nps are known in the manufacture of the flyback converter 118 and can be programmed into the controller 118, such as by burning fuses in a one-time programmable memory. The controller 118 can measure the input voltage Vin directly. Alternatively, as is known in the flyback field, the controller 118 can indirectly measure or monitor the input voltage. The switching cycle is also known. The controller 118 can also measure the on-time Ton of the previous cycle of the power switch transistor SW and use the on-time to calculate the peak primary current VIPK in the current cycle of the power switch transistor SW. Therefore, once the controller 118 senses that the sense resistor voltage is equal to the VIPK corresponding to the most recently calculated IPK and accordingly disconnects the power switch transistor SW, the output current is regulated to be equal to the desired average current value Io.

[0027] exist Figure 3An exemplary implementation of the controller 118 is shown in more detail in FIG. The controller 118 includes a logic circuit 300 (such as a microcontroller) for multiplying the parameters in equation (3) discussed above to calculate a digital value of VIPK (it should be noted that VIPK is equal to IPK*(resistance of the sense resistor Rs)). Therefore, the logic circuit 300 uses the measured on-time Ton, the desired average output current Io, the input voltage Vin, the switching period Ts, the magnetizing inductance Lm, the measured off-time, and the turns ratio Nps. For example, the logic circuit 300 can form the first value (the first half of equation (3)) using a first function of the following terms: the desired average output current Io, the switching period Tp, the measured off-time, the turns ratio Nps, and the sense resistor Rs. It should be noted that during the discontinuous conduction mode, the measured off-time is replaced by the transformer reset time Trst. The transformer reset time Trst is the delay from the off-time of the power switch transistor SW to the time when the secondary current ramps down to zero during the discontinuous conduction mode.

[0028] The logic circuit 300 may form a second value (the second half of equation (3)) using a second function of the following terms: input voltage Vin, measured on-time Ton, magnetizing inductance Lm, and sense resistor. By adding the first value and the second value, the logic circuit 300 forms a digital version of the peak sense resistor voltage. An analog-to-digital converter (ADC) converts the digital value of VIPK into an analog version, which is compared with the sense resistor voltage in a comparator. When the output signal of the comparator indicates that the sense resistor voltage has risen to equal VIPK, the switch driver turns off the power switch transistor SW. Parameters (such as magnetizing inductance Lm and turns ratio Nps of transformer T1) may be retrieved from a memory (e.g., a fuse programmable memory). A counter clocked by a clock signal from a clock may calculate the on-time Ton of a previous switching cycle determined from the switch driver output signal. Rather than calculating equation (1) digitally, it should be understood that the multiplication and summation for calculating VIPK may be performed in the analog domain, such as by using an operational amplifier.

[0029] It should be noted that if the on-time of the power switch transistor SW can be long enough, slope compensation is applied. Then, the resulting reduction in VIPK will cause the average output current to deviate from the desired average output current Io. For example, in Figure 4, a pulse of the sense resistor voltage during the on-time of the power switch transistor SW is shown. The pulse starts at time T0 and extends to time T2. But the delay from start time T0 to time T1 exceeds the slope compensation on-time threshold, causing slope compensation to begin. Therefore, slope compensation begins at time T1 until the on-time ends at time T2, causing the commanded VIPK to be reduced according to the slope compensation slope Se. But the controller 118 is configured to sense the application of slope compensation in the previous switching cycle and detect the amount of slope compensation or offset Vipk_cmp applied during the slope compensation period. Therefore, the controller 118 increases the commanded VIPK in the current switching cycle by the offset Vipk_cmp so that when the on-time period ends at time T2, the desired VIPK is achieved. In other words, in the absence of slope compensation, the controller 118 will command VIPK according to equation (3). But when slope compensation is detected, the controller 118 then commands VIPK+Vipk_cmp so that the desired value of VIPK is achieved when slope compensation reduces the command by the amount of Vipk_cmp.

[0030] It should be understood that various aspects or details of the present disclosure may be changed without departing from the scope of the present disclosure. The present disclosure is not exhaustive and does not limit the claimed disclosure to the precise form disclosed. In addition, the foregoing description is for illustrative purposes only and not for limiting purposes. Based on the above description, modifications and variations are possible or may be obtained from practicing the present disclosure. The claims and their equivalents define the scope of the present disclosure. In addition, although the technology has been described in a language specific to structural features and / or method actions, it should be understood that the appended claims are not necessarily limited to the described features or actions. Instead, features and actions are described as exemplary specific implementations of such technologies.

[0031] With respect to the use of the terms "include", "comprises", "has", "contains" and variations thereof herein, such terms are intended to be inclusive in a manner similar to the term "includes", thereby acting as an open transitional term without excluding any additional or other elements. In addition, unless otherwise specifically stated, conditional language such as "may", "can", "possibly" or "can" is understood within the context to present certain examples including certain features, elements and / or steps, while other examples do not include certain features, elements and / or steps. Therefore, such conditional language is generally not intended to imply that one or more examples require certain features, elements and / or steps in any way, or that one or more examples must include logic for determining whether certain features, elements and / or steps are included or will be performed in any particular example with or without user input or prompting. Unless otherwise explicitly stated, combination words such as phrases "at least one of X, Y or Z" should be understood to present items, terms, etc. that can be X, Y or Z, or a combination thereof.

[0032] In some alternative examples of specific implementation, one or more functions marked in the box may not occur in the order marked in the accompanying drawings. For example, in some cases, depending on the functions involved, two boxes shown in succession may be executed substantially simultaneously, or sometimes these boxes may be executed in the opposite order. In addition, in addition to the boxes shown in the flow chart or block diagram, other boxes may be added. In addition, the operation of the exemplary process is shown in a separate box and summarized with reference to those boxes. These processes are shown as a logical flow of blocks, each of which can represent one or more operations that can be implemented in hardware, software or a combination thereof. In the context of software, an operation represents a computer executable instruction stored on one or more computer-readable media, which enables one or more processing units to perform the referenced operation when executed by one or more processing units. Typically, computer executable instructions include routines, programs, objects, modules, components, data structures, etc. that perform specific functions or implement specific abstract data types. The order of describing the operations is not intended to be understood as a limitation, and any number of the operations may be performed in any order, combined in any order, subdivided into multiple sub-operations and / or performed in parallel to implement the process. The process may be performed by resources associated with one or more devices (such as one or more internal or external CPUs or GPUs) and / or one or more pieces of hardware logic (such as an FPGA, DSP, or other type of accelerator).

Claims

1. A flyback controller for a flyback converter, the flyback controller comprising: a logic circuit configured to calculate a peak sense resistor voltage for a present switching cycle of a power switch transistor in response to a desired average output current of the flyback converter during a continuous conduction mode of operation; a comparator configured to compare the peak sense resistor voltage to a sense resistor voltage; as well as a switch driver configured to turn off the power switch transistor in the current switching cycle in response to an output signal from the comparator indicating that the sense resistor voltage is equal to the peak sense resistor voltage to maintain an average output current of the flyback converter equal to the desired average output current.

2. The flyback controller of claim 1, wherein the logic circuit is a microcontroller. 3 . The flyback controller of claim 1 , wherein the logic circuit is further configured to calculate the peak sense resistor voltage in response to a turns ratio of a transformer in the flyback converter. 4 . The flyback controller of claim 1 , wherein the logic circuit is further configured to calculate the peak sense resistor voltage in response to an input voltage to the flyback converter. 5 . The flyback controller of claim 1 , wherein the logic circuit is further configured to calculate the peak sense resistor voltage in response to an on-time of the power switch transistor being a previous switching cycle. 6 . The flyback controller of claim 5 , wherein the logic circuit is further configured to increase the peak sense resistor voltage by a slope compensation offset.

7. The flyback controller according to claim 1, further comprising: an analog-to-digital converter configured to convert a digital peak sense resistor voltage from the logic circuit to provide an analog peak sense resistor voltage, and wherein the peak sense resistor voltage to the comparator is the analog peak sense resistor voltage. 8 . The flyback controller of claim 1 , wherein the logic circuit is further configured to calculate the peak sense resistor voltage in response to a period of the current switching cycle of the power switch transistor.

9. The flyback controller according to claim 3, further comprising: A memory is provided for storing the turns ratio and a magnetizing inductance of the transformer, wherein the logic circuit is further configured to calculate the peak sense resistor voltage in response to the magnetizing inductance of the transformer.

10. A method for operating a flyback converter during a continuous conduction mode, the method comprising: measuring an on-time of a power switch transistor in a previous switching cycle of the power switch transistor to provide a measured on-time; turning on the power switch transistor in a current switching cycle of the power switch transistor; calculating a peak sense resistor voltage in response to a desired average output current, the measured on-time, an input voltage to the flyback converter, a turns ratio of a transformer in the flyback converter, a magnetizing inductance of the transformer, and a period of the current switching cycle; as well as The power switch transistor is turned off in the current switching cycle in response to a sense resistor voltage being equal to the peak sense resistor voltage to maintain an average output current of the flyback converter equal to the desired average output current.

11. The method of claim 10, wherein calculating the peak sense resistor voltage comprises: forming a first function of: the desired average output current, the period, a difference between the period and the measured on-time, the turns ratio, and a sense resistor resistance to provide a first value; forming a second function of: the input voltage, the measured on-time, the magnetizing inductance, and the sense resistor resistance to provide a second value; as well as The first value and the second value are added to calculate the peak sense resistor voltage.

12. The method of claim 11, wherein the first function is a ratio of a first product of the desired average output current, the sense resistor resistance, and the period divided by a second product of the turns ratio and the difference between the period and the measured on-time.

13. The method of claim 11, wherein the second function is a ratio of a first product of the input voltage, the measured on-time, and the sense resistor resistance divided by two times the magnetizing inductance.

14. The method of claim 10, further comprising using the method during a discontinuous conduction mode.

15. A flyback converter, comprising: A transformer, the transformer comprising a primary winding; a power switch transistor connected to the primary winding; a sensing resistor connected in series with the power switch transistor; as well as a controller configured to control the cycling of the power switch transistor such that in a current cycle of the power switch transistor, a sense resistor voltage across the sense resistor is equal to a peak sense resistor voltage to control an average output current of the flyback converter to be equal to a desired average output current, the peak sense resistor voltage being a function of the desired average output current of the flyback converter, a period of the current cycle of the power switch transistor, an input voltage to the flyback converter, a measured on-time of the power switch transistor in a previous cycle of the power switch transistor, a magnetizing inductance of the transformer, and a turns ratio of the transformer.

16. The flyback converter of claim 15, wherein the controller comprises a logic circuit.

17. The flyback converter of claim 16, wherein the logic circuit is a microcontroller.

18. The flyback converter according to claim 15, wherein the controller further comprises: A counter is configured to count during the previous cycle of the power switch transistor to provide a measured on-time.

19. The flyback converter according to claim 18, wherein the controller further comprises: a comparator configured to compare the sense resistor voltage to the peak sense resistor voltage, wherein the controller is further configured to turn off the power switch transistor in the current cycle of the power switch transistor in response to an output signal from the comparator indicating that the sense resistor voltage is equal to the peak sense resistor voltage.

20. The flyback converter of claim 19, further comprising a switch driver for cycling the power switch transistor.

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