High frequency amplifier

Abstract

This invention provides a high-frequency amplifier. The high-frequency amplifier includes: an asymmetric Doherty amplifier comprising a carrier amplifier and a peak amplifier, amplifying an input high-frequency signal; a driver amplifier driving the asymmetric Doherty amplifier; a branching circuit branching the high-frequency signal amplified by the driver amplifier to an input path on the peak amplifier side and an input path on the carrier amplifier side; a phase adjustment circuit delaying at least one of the phase of the input signal of the peak amplifier and the phase of the input signal of the carrier amplifier; a first substrate; a second substrate; and a substrate member mounting the first substrate and the second substrate. When n is set to an integer greater than or equal to 0, the electrical length from the output terminal of the driver amplifier to the input terminal of the peak amplifier is set such that, when converted to the phase of the input high-frequency signal, it falls within the range of (2n+1)×π-π / 4 to (2n+1)×π+π / 4.

Description

Technical Field

[0001] This disclosure relates to high-frequency amplifiers. Background Technology

[0002] In recent years, broadband technology has been advancing in mobile communication systems such as mobile phones. Therefore, for power amplifiers used in base station devices and the like, high power efficiency over a wide bandwidth is desirable. As a power amplifier used to achieve this high power efficiency, a Doherty amplifier, which has a carrier amplifier (also called a main amplifier) ​​and a peak amplifier, is known. For example, the construction of a Doherty amplifier (Doherty-type amplifier) ​​is disclosed in Patent Document 1. Furthermore, Doherty amplifiers are typically used in conjunction with the subsequent stage of a drive amplifier.

[0003] Furthermore, when the driver amplifier and Doherty amplifier are mounted on a printed circuit board, a large printed circuit board is required if the driver amplifier, carrier amplifier, and peak amplifier are mounted on the same plane. Therefore, as a method for miniaturizing and saving area in the mounting of amplifiers, there exists a method that addresses this with three-dimensional mounting (Patent Document 2).

[0004] Patent Document 1: International Publication No. 2005 / 093948

[0005] Patent Document 2: Japanese Patent Application Publication No. 2008-305937

[0006] The high-frequency amplifier (high-frequency power amplifier) ​​that is the subject of this disclosure amplifies the input high-frequency signal to the necessary output, thus handling high power and consuming a large amount of current or electricity. As a result, it generates significant heat. Therefore, when arranging the aforementioned multiple high-frequency amplifiers in the above three-dimensional configuration, prioritizing heat dissipation efficiency, it is considered to place the driver amplifier, carrier amplifier, and peak amplifier on the lower layer, and other components on the upper layer. However, due to layout constraints, the driver amplifier and peak amplifier may be placed too close together, potentially leading to instability in the electrical characteristics of the peak amplifier. Summary of the Invention

[0007] The present invention was made in view of the actual situation described above, and its purpose is to provide a high-frequency amplifier with excellent heat dissipation and stability.

[0008] One aspect of the high-frequency amplifier disclosed herein includes: an asymmetric Doherty amplifier comprising a carrier amplifier and a peak amplifier, amplifying an input high-frequency signal, wherein the peak amplifier begins amplification operation when the output of the carrier amplifier reaches a saturation region and has a saturation output different from that of the carrier amplifier; a driver amplifier for driving the asymmetric Doherty amplifier; a branching circuit for branching the high-frequency signal amplified by the driver amplifier to an input path on the peak amplifier side and an input path on the carrier amplifier side; a phase adjustment circuit disposed on at least one of the input path on the peak amplifier side and the input path on the carrier amplifier side, and delaying at least one of the phase of the input signal of the peak amplifier and the phase of the input signal of the carrier amplifier; and a first substrate on which the driver amplifier, the carrier amplifier, and the peak amplifier are mounted. A second substrate, on which the branch circuit and the phase adjustment circuit are mounted; and a base member, on which the first substrate and the second substrate are mounted, wherein the drive amplifier, the carrier amplifier and the peak amplifier each have a front side on which a predetermined circuit is formed and a back side on the opposite side of the front side, and the back sides of the drive amplifier, the carrier amplifier and the peak amplifier are all in contact with the base member. In the state where the second substrate and the first substrate are stacked in an overlapping manner, the input terminal of the drive amplifier and the input terminal of the peak amplifier are located adjacent to each other. When n is set to an integer greater than or equal to 0, the electrical length from the output terminal of the drive amplifier to the input terminal of the peak amplifier is set to be in the range of (2n+1)×π-π / 4 to (2n+1)×π+π / 4 when converted into the phase of the input high-frequency signal.

[0009] Invention Effects

[0010] Based on the above, a high-frequency amplifier with excellent heat dissipation and stability can be provided. Attached Figure Description

[0011] Figure 1 This is a schematic cross-sectional view of a high-frequency amplifier according to one embodiment of the present disclosure.

[0012] Figure 2 This is an explanation Figure 1 Block diagram of a high-frequency amplifier.

[0013] Figure 3 yes Figure 1 A top-down view of the upper level.

[0014] Figure 4 yes Figure 1 The top view of the lower level.

[0015] Figure 5 yes Figure 1The circuit diagram of the driver amplifier.

[0016] Figure 6 It is an explanation and Figure 5 The circuit diagram corresponds to the upper-level diagram.

[0017] Figure 7 yes Figure 1 The circuit diagram of the Doherty amplifier.

[0018] Figure 8 It is an explanation and Figure 7 The circuit diagram corresponds to the lower-level diagram.

[0019] Figure 9 This is a schematic cross-sectional view of a high-frequency amplifier according to another embodiment of the present disclosure.

[0020] Label Explanation

[0021] 1…High-frequency amplifier, 10…Lower layer, 11…First dielectric layer, 12…Second dielectric layer, 13a, 13b, 13c, 14a, 15a, 15b, 16a, 17a…Signal vias, 20…Upper layer, 23…Third dielectric layer, 24…Fourth dielectric layer, 30…Input matching circuit, 40…Driver amplifier, 40a…Front side, 40b…Rear side, 41…Output matching circuit, 49…Curved pattern, 50…Doherty amplifier, 51…Branch circuit, 52…Phase adjustment circuit, 52a…via, 53…Input matching circuit, 54…Carrier amplifier, 54a…Front side, 54b…Rear side, 55…Output matching circuit, 56… 66… Doherty network, 56a… 90° transmission line, 61… Phase adjustment circuit, 61a… Via, 63… Input matching circuit, 64… Peak amplifier, 64a… Front side, 64b… Back side, 65… Output matching circuit, 100… Printed substrate, 101a, 101b… Wiring on printed substrate, La1… First wiring layer, La2… Second wiring layer, La3… Third wiring layer, La4… Substrate component, RFin… Input terminal, RFout… Output terminal, L, L1~L16… Inductors, C, C1~C32… Capacitors, R1, R3~R5… Resistors, TRL1~TRL4… Transmission lines, Vd, Vg… Power supply. Detailed Implementation

[0022] [Description of embodiments of this disclosure]

[0023] First, the contents of the embodiments disclosed herein will be listed for explanation.

[0024] (1) The high-frequency amplifier of the present invention comprises: an asymmetric Doherty amplifier, including a carrier amplifier and a peak amplifier, which amplifies an input high-frequency signal, wherein the peak amplifier begins amplification operation when the output of the carrier amplifier reaches the saturation region and has a saturation output different from that of the carrier amplifier; a driver amplifier that drives the asymmetric Doherty amplifier; a branching circuit that branches the high-frequency signal amplified by the driver amplifier to an input path on the peak amplifier side and an input path on the carrier amplifier side; a phase adjustment circuit disposed on at least one of the input path on the peak amplifier side and the input path on the carrier amplifier side, and delays at least one of the phase of the input signal of the peak amplifier and the phase of the input signal of the carrier amplifier; and a first substrate on which the driver amplifier, the carrier amplifier and the peak amplifier are mounted. The second substrate is equipped with the branch circuit and the phase adjustment circuit; and the base member is equipped with the first substrate and the second substrate. The drive amplifier, the carrier amplifier and the peak amplifier each have a front side with a defined circuit and a back side located on the opposite side of the front side. The back sides of the drive amplifier, the carrier amplifier and the peak amplifier are all in contact with the base member. When the second substrate and the first substrate are stacked in an overlapping manner, the input terminal of the drive amplifier and the input terminal of the peak amplifier are located adjacent to each other. When n is set to an integer greater than or equal to 0, the electrical length from the output terminal of the drive amplifier to the input terminal of the peak amplifier is set to be in the range of (2n+1)×π-π / 4 to (2n+1)×π+π / 4 when converted into the phase of the input high-frequency signal.

[0025] If the physical distance between the output terminals of the driver amplifier and the input terminals of the peak amplifier is very close, the phases of the output signals at these terminals will become the same or nearly the same, potentially leading to electrical instability such as oscillation. However, by adjusting the electrical length between these terminals to make the phases of the signals between the two close terminals (the output terminal of the driver amplifier and the input terminal of the peak amplifier) ​​opposite, the electrical characteristics of the peak amplifier will not become unstable even when the driver amplifier and the peak amplifier are configured close together. Therefore, even with a two-layer construction, the amplifier can be stabilized.

[0026] In addition, since the back sides of the drive amplifier, carrier amplifier, and peak amplifier are all in contact with the substrate components, a high-frequency amplifier with good heat dissipation can be provided.

[0027] (2) In one embodiment of the high-frequency amplifier disclosed herein, the phase difference between the high-frequency signal at the output terminal of the drive amplifier and the high-frequency signal at the input terminal of the peak amplifier is in the range of 11π / 4 to 13π / 4.

[0028] If the electrical length between two close terminals (the output terminal of the driver amplifier and the input terminal of the peak amplifier) ​​is converted into the phase of the signal, it becomes a phase difference of (2n+1)×π±π / 4. In particular, if the phase difference between the output signal of the driver amplifier and the input signal of the peak amplifier is in the range of 11π / 4 to 13π / 4, then electrical instability such as oscillation can be reliably eliminated.

[0029] (3) In one embodiment of the high-frequency amplifier disclosed herein, a grounded metal layer is disposed between the first substrate and the second substrate.

[0030] The grounded metal layer can shield electromagnetic waves. Therefore, the first substrate is not easily affected by electromagnetic waves generated on the second substrate side, and the second substrate is not easily affected by electromagnetic waves generated on the first substrate side.

[0031] (4) In one embodiment of the high-frequency amplifier disclosed herein, the peak amplifier is configured to have a larger saturation output than the carrier amplifier.

[0032] In peak amplifiers, the phase shift required to achieve optimal matching is greater than that required in carrier amplifiers.

[0033] [Details of the embodiments disclosed herein]

[0034] Hereinafter, specific examples of the high-frequency amplifier of this disclosure will be described with reference to the accompanying drawings. Figure 1 This is a schematic cross-sectional view of a high-frequency amplifier according to one embodiment of the present disclosure.

[0035] The high-frequency amplifier 1 is mounted on a communication device such as a base station device in a mobile communication system, for example, to amplify transmitted signals. The high-frequency amplifier 1 has a substrate member La4. The substrate member La4 is a metal (e.g., copper) plate that also serves as a heat sink and an external terminal, and is disposed on the printed circuit board 100 of the communication device.

[0036] A lower layer 10 and an upper layer 20 are mounted on a base member La4. The lower layer 10 corresponds to the first substrate of the present invention, and the upper layer 20 corresponds to the second substrate of the present invention.

[0037] The upper layer 20 is stacked overlapping the lower layer 10. The upper layer 20 is composed of a third dielectric layer 23 (e.g., with a thickness of 0.1 mm), a first wiring layer La1 (e.g., with a thickness of 10–35 μm), and a fourth dielectric layer 24 (e.g., with a thickness of 0.4 mm). A high-frequency circuit pattern is formed on the first wiring layer La1.

[0038] A second wiring layer La2 (e.g., with a thickness of 10–35 μm) is disposed between the fourth dielectric layer 24 and the lower layer 10 (second dielectric layer 12). The second wiring layer La2 is, for example, a full-coverage copper surface, which serves to shield electromagnetic waves generated between the first wiring layer La1 at the GND (ground) surface and between the upper layer 20 and the lower layer 10. The second wiring layer La2 is equivalent to the grounded metal layer of this disclosure.

[0039] The lower layer 10 is sandwiched between the substrate member La4 and the upper layer 20. The lower layer 10 is composed of a second dielectric layer 12 (e.g., with a thickness of 0.2 mm), a third wiring layer La3 (e.g., with a thickness of 10 to 35 μm), and a first dielectric layer 11 (e.g., with a thickness of 0.28 mm). A high-frequency circuit pattern with the substrate member La4 constituting the GND surface as the reference voltage is formed on the third wiring layer La3.

[0040] In manufacturing the high-frequency amplifier 1, firstly, a first wiring layer La1 is formed on one side (front) of the third dielectric layer 23. Next, after mounting an inductor L or capacitor C on one side of the first wiring layer La1, a fourth dielectric layer 24 is formed. Next, a second wiring layer La2 is formed on one side of the fourth dielectric layer 24. Next, after forming a second dielectric layer 12 on one side of the second wiring layer La2, a third wiring layer La3 is formed on one side of the second dielectric layer 12. Then, after mounting active components such as a driver amplifier 40, a carrier amplifier 54, and a peak amplifier 64, as well as an inductor L or capacitor C, on one side of the third wiring layer La3, a first dielectric layer 11 is formed.

[0041] The driver amplifier 40 has a front side 40a with defined circuitry and a back side 40b located opposite the front side 40a and, for example, without circuitry. The driver amplifier 40 is disposed on the first dielectric layer 11, facing upwards with the front side 40a opposite the upper layer 20, and mounted on one side of the third wiring layer La3. The back side 40b is disposed downwards away from the upper layer 20 and is fixed to a substrate member La4 coated with sintered silver paste or sintered copper paste.

[0042] The carrier amplifier 54 and the peak amplifier 64 are also disposed on the first dielectric layer 11, with the front side 54a and 64a facing upwards and mounted on one side of the third wiring layer La3. The back side 54b and 64b are disposed downwards in contact with the substrate component La4 and are fixed to the substrate component La4 coated with sintered silver paste or sintered copper paste.

[0043] A substrate member La4 (with a thickness of 0.15 to 0.25 mm) constituting the GND surface is disposed on one side of the first dielectric layer 11.

[0044] Additionally, the electrical path between the first wiring layer La1 of the upper layer 20 and the substrate member La4 is ensured, for example, using signal vias 13c, 13b, and 13a. Specifically, signal vias 13a to 13c penetrate the substrate member La4, the lower layer 10, and the fourth dielectric layer 24 of the upper layer 20. One end of signal via 13a is connected to the input terminal RFin, and the other end of signal via 13c is connected to the first wiring layer La1.

[0045] Furthermore, the electrical path between the first wiring layer La1 and the third wiring layer La3 of the lower layer 10 is ensured, for example, using signal vias 15a, 15b, and 14a. Specifically, firstly, signal vias 15a and 15b penetrate the fourth dielectric layer 24 of the upper layer 20 and the second dielectric layer 12 of the lower layer 10. One end of signal via 15a is connected to the first wiring layer La1, and the other end is connected to the third wiring layer La3 (the input of the driver amplifier 40). On the other hand, one end of signal via 15b is connected to the third wiring layer La3 (the output of the driver amplifier 40), and the other end is connected to the first wiring layer La1.

[0046] Furthermore, the signal via 14a also penetrates the fourth dielectric layer 24 of the upper layer 20 and the second dielectric layer 12 of the lower layer 10. One end of the signal via is connected to the first wiring layer La1, and the other end of the signal via is connected to the third wiring layer La3 (the input of the carrier amplifier 54 and the input of the peak amplifier 64).

[0047] Furthermore, the electrical path between the third wiring layer La3 and the substrate component La4 is ensured, for example, using signal vias 13a and 16a. Specifically, signal vias 13a and 16a penetrate the first dielectric layer 11 of the lower layer 10 and the substrate component La4. One end of signal via 16a is connected to the output of the Doherty amplifier 50 via the third wiring layer La3, and the other end of signal via 16a is connected to the output terminal RFout.

[0048] In this way, by stacking the upper layer 20 and the lower layer 10 in a superimposed manner, and installing the amplifier circuit containing the driver amplifier 40 and the Doherty amplifier 50 in three dimensions, it is possible to miniaturize the high-frequency amplifier 1, such as having a module size of 6mm square on the outermost contour and a thickness of 2.2mm.

[0049] Furthermore, no wire bonding connection is required in this high-frequency amplifier 1. Therefore, a large panel, for example, about 500 mm square, can be used in the manufacturing process, and for example, 6,000 6 mm square panels can be taken from that panel, thus achieving a significant cost reduction due to reduced processing and material costs.

[0050] Here, with the drive amplifier 40, carrier amplifier 54, and peak amplifier 64 all positioned on the lower layer 10, the physical distance between the output terminal of the drive amplifier 40 and the input terminal of the peak amplifier 64 can sometimes become very close because they are located adjacent to each other. In such a physical configuration, if the phases of the output signals and input signals from the aforementioned terminals become the same or nearly the same, it can lead to electrically unstable conditions such as oscillations.

[0051] Therefore, in the high-frequency amplifier 1, the electrical length from the output terminal of the driver amplifier 40 to the input terminal of the peak amplifier 64 is adjusted so that the phases of the signals at the output terminal of the driver amplifier 40 and the input terminal of the peak amplifier 64 are opposite. The electrical length from the output terminal of the driver amplifier 40 to the input terminal of the peak amplifier 64, or the delay time for the input signal with wavelength λ to travel from the output terminal of the driver amplifier 40 to the input terminal of the peak amplifier 64, is set to be within the range of (2n+1)×π-π / 4 to (2n+1)×π+π / 4 when converted to the phase of the input signal with wavelength λ. n is an integer greater than or equal to 0.

[0052] To achieve this, in the path from the drain output of the driver amplifier 40 to the branch circuit 51, for example, as Figure 3 As shown in the curve pattern 49, it detours sharply from the center of the upper layer 20 to the right half, or the phase adjustment circuit 61 is arranged between the branch circuit 51 and the peak amplifier 64, or... Figure 3 The phase adjustment circuit 61 is located near the curve pattern shown, and the path from the output of the branch circuit 51 to the via 61a is formed by a curve instead of a straight line, or the phase adjustment circuit 52 is arranged between the branch circuit 51 and the carrier amplifier 54.

[0053] In this way, since the electrical length between these terminals is adjusted so that the phases of the signals between two close terminals, such as the output terminal of the drive amplifier 40 and the input terminal of the peak amplifier 64, are opposite, the electrical characteristics of the peak amplifier 64 will not become unstable even when the drive amplifier 40 and the peak amplifier 64 are configured close to each other. Therefore, even with a two-layer construction, amplifier 1 can be stabilized.

[0054] More specifically, the phase difference between the high-frequency signal (hereinafter referred to as RF) at the output terminal of the drive amplifier 40 and the RF signal at the input terminal of the peak amplifier 64 is set to a range of 11π / 4 to 13π / 4. This reliably eliminates electrical instability conditions such as oscillations.

[0055] Furthermore, while the phase difference between the carrier amplifier and the peak amplifier is set to π / 2 in a typical Doherty amplifier, in the high-frequency amplifier 1, this phase difference is intentionally set to π. That is, the phase difference between the RF signal at the output terminal of the carrier amplifier 54 and the RF signal at the output terminal of the peak amplifier 64 is set to a range of π / 2 to 3π / 2. As a result, the electromagnetic waves emitted from the carrier amplifier 54 and the peak amplifier 64 cancel each other out in the vicinity, thus suppressing the electromagnetic waves emitted to the outside of the high-frequency amplifier 1 to a smaller extent.

[0056] Furthermore, the phase of the carrier amplifier 54 and the phase of the peak amplifier 64 are connected via... Figure 3 The phase adjustment circuits 52 and 61 shown are in Figure 7 , 8 The input matching circuits 53 and 63, the output matching circuits 55 and 65, and the transmission line TRL1 described herein are... Figure 4 The 90° transmission line 56a) described herein is synchronized at the output terminal RFout.

[0057] Figure 2 This is an explanation Figure 1 A block diagram of a high-frequency amplifier. Additionally, Figure 3 yes Figure 1 Top view of the upper level Figure 4 yes Figure 1 The top view of the lower level.

[0058] The high-frequency amplifier 1 has a driver amplifier 40 and a Doherty amplifier 50 disposed after the driver amplifier 40, and is configured to amplify signals in the frequency band of, for example, 5 GHz to 6 GHz.

[0059] In the circuit containing the driver amplifier 40, the Doherty amplifier 50 amplifies the RF signal, defined by wavelength λ, input to the input terminal RFin to a level that can amplify it to a specified transmission power.

[0060] The Doherty amplifier 50 is a circuit that includes a branch circuit 51, a phase adjustment circuit 52, 61, a carrier amplifier 54, a peak amplifier 64, and Doherty networks 56, 66. It further amplifies the RF signal obtained by the driver amplifier 40 and outputs it from the output terminal RFout.

[0061] The driver amplifier 40, carrier amplifier 54, and peak amplifier 64 are amplifiers that use, for example, GaN-HEMT (High Electron Mobility Transistor) as amplifying elements. Each of the driver amplifier 40, carrier amplifier 54, and peak amplifier 64 has a gate pad on one side of a rectangle and a drain pad on the opposite side.

[0062] Additionally, the drive amplifier 40, carrier amplifier 54, and peak amplifier 64 have source pads on both sides of their gate pads. The source pads of the drive amplifier 40, carrier amplifier 54, and peak amplifier 64 are connected via... Figure 1 The back side 40b, 54b, and 64b, as described, are connected to the base member La4. This ensures GND and forms a heat dissipation path from the drive amplifier 40, carrier amplifier 54, peak amplifier 64 to the base member La4.

[0063] Figure 3 The upper layer 20 and shown Figure 4 The lower layer 10 shown has planes of roughly similar shape, all formed, for example, 6 mm square.

[0064] like Figure 1 As shown, the RF signal input to the input terminal RFin (signal via 13a) via the signal wiring 101a provided on the printed circuit board 100 of the communication device originates from... Figure 1 The base member La4 described herein penetrates the lower layer 10 and passes through... Figure 1 The signal vias 13a, 13b, and 13c shown are input to the signal source without being connected to any part of the lower layer 10. Figure 3 The lower left corner portion of the upper layer 20 is observed in the image. The drive amplifier 40 is mounted on... Figure 4 Near the lower left of the lower layer 10, as observed in the image, the RF signal input to the upper layer 20 passes through signal via 15a towards the lower layer 10 and is input to the driver amplifier 40. The RF signal amplified by the driver amplifier 40 passes through signal via 15b towards the upper layer 20, such as... Figure 3The curve pattern 49 shows a large rotation. Specifically, in the direction of... Figure 3 After observing the upper edge of the upper layer 20, it turns right and moves to the right along the upper edge, then turns further right toward the lower edge of the upper layer 20, reaching the branch circuit 51 disposed on the upper layer 20.

[0065] Branch circuit 51 is disposed on the first wiring layer La1 of upper layer 20. Branch circuit 51 is, for example, a Wilkinson type splitter, which equally distributes the RF signal amplified by drive amplifier 40 to the input path on the peak amplifier side and the input path on the carrier amplifier side.

[0066] One side of the RF signal distributed by branch circuit 51 (the input path on the carrier amplifier side) reaches phase adjustment circuit 52 located on the first wiring layer La1 of upper layer 20. Phase adjustment circuit 52 adjusts the phase delay of the input signal of carrier amplifier 54 to correspond to a specified distribution constant. The RF signal after passing through phase adjustment circuit 52... Figure 3 The via 52a observed is formed near the lower edge of the upper layer 20 and faces the lower layer 10. It passes through, for example, and through... Figure 1 The signal path of the signal via 14a shown is the same.

[0067] Conversely, the other side of the RF signal distributed by branch circuit 51 (the input path on the peak amplifier side) reaches phase adjustment circuit 61 located on the first wiring layer La1 of upper layer 20. Phase adjustment circuit 61 adjusts the phase delay of the input signal of peak amplifier 64 by an amount corresponding to a specified distribution constant. The RF signal after passing through phase adjustment circuit 61... Figure 3 The via 61a observed is formed near the lower edge of the upper layer 20 and faces the lower layer 10. It also passes through... Figure 1 The signal path of the signal via 14a shown is the same.

[0068] Furthermore, in this embodiment, an example has been described where the phase adjustment circuit 52 is disposed between the branch circuit 51 and the carrier amplifier 54, and the phase adjustment circuit 61 is disposed between the branch circuit 51 and the peak amplifier 64. However, this disclosure is not limited to this example. For example, the phase adjustment circuit may be disposed between either the branch circuit 51 and the peak amplifier 64 or between the branch circuit 51 and the carrier amplifier 54 to delay the phase of the input signal.

[0069] The Doherty amplifier 50 in this embodiment is an asymmetric Doherty amplifier, where the peak amplifier 64 and the carrier amplifier 54 exhibit different maximum output strengths for the input RF signal. For example, the peak amplifier 64 has a saturation output (size) approximately twice that of the carrier amplifier 54, and the peak amplifier 64 begins amplification operation when the output of the carrier amplifier 54 reaches the saturation region. Specifically, the carrier amplifier 54 operates in class AB or class B, while the peak amplifier 64 operates in class C. When the instantaneous power is low, the carrier amplifier 54 operates, and the peak amplifier 64 does not operate, thus improving power efficiency. When the instantaneous power is high, both the carrier amplifier 54 and the peak amplifier 64 operate, thus maintaining high power efficiency and increasing saturation power.

[0070] As an example, the output of driver amplifier 40, carrier amplifier 54, and peak amplifier 64 is described. Driver amplifier 40 is used to output 10W, carrier amplifier 54 to output 15W, and peak amplifier 64 to output 30W. Here, the term "10W output" specifically refers to the size of the FET; it does not mean that it always outputs 10W, but rather that it has a size sufficient for 10W output.

[0071] The RF signal amplified by carrier amplifier 54 reaches the Doherty network 56 located on the carrier amplifier side of the lower layer 10. A 90° transmission line (also called a λ / 4 line) 56a is provided in this Doherty network 56. Therefore, the RF signal amplified by carrier amplifier 54 travels via the 90° transmission line 56a from the carrier amplifier 54 to the Doherty network 56. Figure 4 The output terminal RFout, located in the upper right corner of the lower layer 10, is combined with the output signal of the peak amplifier 64 described later and output.

[0072] On the other hand, the RF signal amplified by the peak amplifier 64 reaches the Doherty network 66 on the peak amplifier side of the lower layer 10, is combined with the output signal of the carrier amplifier 54, and then passes through... Figure 1 The signal path of the signal via 16a shown is output from the output terminal RFout. The signal output from the output terminal RFout is via, as shown... Figure 1 The signal wiring 101b, which is arranged on the printed circuit board 100 of the communication device as shown, is transmitted from the high-frequency amplifier 1 to the outside.

[0073] Figure 5 yes Figure 1 The driver amplifier circuit diagram, Figure 6 It is an explanation and Figure 5 The circuit diagram corresponds to the upper-level diagram. Additionally, Figure 7 yes Figure 1 Doherty amplifier circuit diagram. Figure 8It is an explanation and Figure 7 The circuit diagram corresponds to the lower-level diagram.

[0074] from Figure 5 The RF signal input at the shown input terminal RFin is input to the gate of the driver amplifier 40 (located on the lower layer 10) via the input matching circuit 30 (configured on the upper layer 20, consisting of inductors L1 and capacitors C1 to C4, a total of 5). The gate bias is supplied from the power supply Vg via inductor L2. Capacitor C5 is a bypass capacitor for the power supply Vg, and resistor R1 is an adjustment resistor.

[0075] The drain output of the driver amplifier 40 is supplied to the branch circuit 51 via the output matching circuit 41 (inductors L4 and L5, capacitors C7 to C9). A drain bias voltage is supplied from the power supply Vd via inductor L3. Capacitor C6 is a bypass capacitor for the power supply Vd.

[0076] Next, as Figure 7 As shown, in branch circuit 51, the RF signal from the driver amplifier 40 is equally distributed to the matching circuit composed of L11 and C24 and the matching circuit composed of C23, L12 and C29.

[0077] The RF signal, whose phase has been adjusted by the matching circuit consisting of L11 and C24, is further phase-adjusted by the phase adjustment circuit 52 (inductors L13, L14, and capacitor C30), and reaches the lower layer 10 via the via 52a, toward the carrier amplifier 54.

[0078] The RF signal arriving at the lower layer 10 is input to the gate of the carrier amplifier 54 via the input matching circuit 53 (capacitors C31, C11-14). The gate bias is supplied from the power supply Vg through the inductor L6. Capacitor C15 is a bypass capacitor for the power supply Vg, and resistor R4 is an adjustment resistor.

[0079] The drain output of carrier amplifier 54 is supplied to the Doherty network 56 on the carrier amplifier side via capacitor C26 for DC cutoff. Drain bias is supplied from power supply Vd via inductor L9. Capacitor C21 is a bypass capacitor for power supply Vd.

[0080] The Doherty network 56 on the carrier amplifier side consists of the output matching circuit 55 and the transmission line TRL1 (included in...). Figure 4 The 90° transmission line 56a) described herein is configured, and the output matching circuit 55 is composed of transmission line TRL2 and capacitor C25. The transmission line TRL1 is used to synthesize the output of carrier amplifier 54 and peak amplifier 64.

[0081] On the other hand, the RF signal, which is divided equally by the branch circuit 51 and whose phase is adjusted by the matching circuit composed of C23, L12 and C29, is further phase adjusted by the phase adjustment circuit 61 (inductors L15, L16 and capacitor C32), and reaches the lower layer 10 through the via 61a, toward the peak amplifier 64.

[0082] The RF signal arriving at the lower layer 10 is input to the gate of the peak amplifier 64 via the input matching circuit 63 (inductor L7, capacitors C16-19). A gate bias voltage is supplied from the power supply Vg via inductor L8. Capacitor C20 is a bypass capacitor for the power supply Vg, and resistor R5 is an adjustment resistor.

[0083] The drain output of peak amplifier 64 is supplied to the Doherty network 66 on the peak amplifier side via capacitor C28 for DC cutoff. Drain bias is supplied from power supply Vd via inductor L10. Capacitor C22 is a bypass capacitor for power supply Vd.

[0084] The Doherty network 66 on the peak amplifier side consists of an output matching circuit 65 and a transmission line TRL4. The output matching circuit 65 consists of a secondary structure of capacitors C27 and C10 and a transmission line TRL3.

[0085] Comparing the amplifier outputs described above, it is assumed that the current or power consumption, and the resulting heat generation, increase in the order of drive amplifier 40, carrier amplifier 54, and peak amplifier 64. In the high-frequency amplifier 1 of this embodiment, since drive amplifier 40, carrier amplifier 54, and peak amplifier 64 are all in contact with a metal (e.g., copper) substrate member La4, good heat dissipation can be achieved for drive amplifier 40, carrier amplifier 54, and peak amplifier 64. As a result, a compact and well-heat-dissipated high-frequency amplifier 1 can be provided.

[0086] In addition, as mentioned above Figure 1 In the case where the drive amplifier 40, carrier amplifier 54, and peak amplifier 64 are configured in the lower layer 10 as described above, for example, the input matching circuit 30 (inductor L1, capacitors C1 to C4) of the drive amplifier 40 can also be configured in the lower layer 10, and the input matching circuit 63 (inductor L7, capacitors C16 to C19) of the peak amplifier 64 can be configured in the upper layer 20.

[0087] Figure 9 This is a schematic cross-sectional view illustrating another embodiment of the high-frequency amplifier of this disclosure. Additionally, for those having... Figure 1 The high-frequency amplifier 1 has the same structure with the same designation and detailed descriptions are omitted.

[0088] Should Figure 9The high-frequency amplifier 1 shown also has a lower layer 10 and an upper layer 20 mounted on the substrate member La4. The drive amplifier 40, the carrier amplifier 54 and the peak amplifier 64 are all disposed on the first dielectric layer 11. The back surfaces 40b, 54b and 64b of the drive amplifier 40, the carrier amplifier 54 and the peak amplifier 64 are all arranged downward in a manner that contacts the substrate member La4 and are fixed to the substrate member La4.

[0089] Additionally, the electrical path between the third wiring layer La3 of the lower layer 10 and the substrate member La4 is ensured using a signal via 13a. The signal via 13a extends through the substrate member La4 and the first dielectric layer 11 of the lower layer 10, with one end connected to the input terminal RFin and the other end connected to the third wiring layer La3.

[0090] Furthermore, the electrical path between the third wiring layer La3 and the first dielectric layer 11 of the upper layer 20 is ensured using signal vias 15b and 14a. Specifically, the signal via 15b first penetrates the fourth dielectric layer 24 of the upper layer 20 and the second dielectric layer 12 of the lower layer 10. One end of the signal via 15b is connected to the output of the driver amplifier 40 via the third wiring layer La3, and the other end of the signal via 15b is connected to the first wiring layer La1.

[0091] In addition, the signal via 14a also penetrates the fourth dielectric layer 24 of the upper layer 20 and the second dielectric layer 12 of the lower layer 10. One end of the signal via is connected to the first wiring layer La1, and the other end of the signal via is connected to the input of the carrier amplifier 54 and the input of the peak amplifier 64 via the third wiring layer La3.

[0092] In addition, the electrical path between the third wiring layer La3 of the lower layer 10 and the substrate member La4 uses a signal via 17a that passes through the first dielectric layer 11.

[0093] Furthermore, the electrical path between the third wiring layer La3 and the substrate component La4 is ensured using signal vias 13a and 16a. Signal vias 13a and 16a penetrate the first dielectric layer 11 of the lower layer 10 and the substrate component La4. One end of signal via 16a is connected to the output of the Doherty amplifier 50 via the third wiring layer La3, and the other end of signal via 16a is connected to the output terminal RFout.

[0094] In addition, Figure 9 In the high-frequency amplifier 1 shown, the phase difference between the RF signal at the output terminal of the drive amplifier 40 and the RF signal at the input terminal of the peak amplifier 64 is set to the range of 11π / 2 to 13π / 2.

[0095] Furthermore, the RF signal input to the input terminal RFin (signal via 13a) via signal wiring 101a is input to the third wiring layer La3 of the lower layer 10, and then input to the driver amplifier 40 via the input matching circuit 30 provided on the lower layer 10. The RF signal amplified by the driver amplifier 40 is then transmitted to the branch circuit 51 provided on the upper layer 20 via the signal via 15b.

[0096] One side of the RF signal distributed by branch circuit 51 (the input path on the carrier amplifier side) reaches phase adjustment circuit 52, which adjusts the phase delay of the input signal of carrier amplifier 54 to correspond to a specified distribution constant. The RF signal after phase adjustment circuit 52 travels along the same path as the signal path through signal via 14a towards the lower layer 10 and is input to carrier amplifier 54. The RF signal amplified by carrier amplifier 54 reaches Doherty network 56 located on the carrier amplifier side of lower layer 10 and is combined with the output signal of peak amplifier 64 (described later).

[0097] On the other hand, the other side of the RF signal distributed by branch circuit 51 (the input path on the peak amplifier side) reaches phase adjustment circuit 61, which adjusts the phase delay of the input signal of peak amplifier 64 to correspond to a specified distribution constant. After passing through input matching circuit 63 on upper layer 20, the RF signal is input to peak amplifier 64 via the same path as the signal path through signal via 14a towards lower layer 10. The RF signal amplified by peak amplifier 64 reaches Doherty network 66 on peak amplifier side, is combined with the output signal of carrier amplifier 54, and is output from output terminal RFout via signal via 16a. The signal output from output terminal RFout is transmitted to the outside from high frequency amplifier 1 via signal wiring 101b.

[0098] The embodiments disclosed herein should be considered illustrative in all respects and not restrictive. The scope of this disclosure is not as defined above, but is indicated by the claims and is intended to include all changes within the meaning and scope equivalent to the claims.

Claims

1. A high-frequency amplifier, comprising: An asymmetric Doherty amplifier includes a carrier amplifier and a peak amplifier, which amplifies the input high-frequency signal. The peak amplifier begins amplification when the output of the carrier amplifier reaches the saturation region and has a different saturation output than the carrier amplifier. Drive the amplifier to drive the asymmetric Doherty amplifier; The branching circuit branches the high-frequency signal amplified by the drive amplifier to the input path on the peak amplifier side and the input path on the carrier amplifier side. A phase adjustment circuit is provided in at least one of the input path on the peak amplifier side and the input path on the carrier amplifier side, and delays at least one of the phase of the input signal of the peak amplifier and the phase of the input signal of the carrier amplifier. The first substrate is equipped with the drive amplifier, the carrier amplifier and the peak amplifier; The second substrate is equipped with the branch circuit and the phase adjustment circuit; and A base component, on which the first substrate and the second substrate are mounted, The drive amplifier, the carrier amplifier, and the peak amplifier each have a front side with defined circuitry formed thereon and a back side located opposite the front side. The back surfaces of the drive amplifier, the carrier amplifier, and the peak amplifier are all in contact with the substrate component. With the second substrate and the first substrate stacked together, the input terminals of the drive amplifier and the input terminals of the peak amplifier are located adjacent to each other. When n is set to an integer greater than or equal to 0, the electrical length from the output terminal of the drive amplifier to the input terminal of the peak amplifier is set to be in the range of (2n+1)×π-π / 4 to (2n+1)×π+π / 4 when converted into the phase of the input high-frequency signal.

2. The high-frequency amplifier according to claim 1, wherein, The phase difference between the high-frequency signal at the output terminal of the drive amplifier and the high-frequency signal at the input terminal of the peak amplifier is in the range of 11π / 4 to 13π / 4.

3. The high-frequency amplifier according to claim 1 or 2, wherein, A grounded metal layer is disposed between the first substrate and the second substrate.

4. The high-frequency amplifier according to any one of claims 1 to 3, wherein, The peak amplifier is configured to have a larger saturation output than the carrier amplifier.

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