A filter and its design method

Abstract

The present application is applicable to the field of digital signal processing technology, and particularly relates to a filter and a design method thereof, the method comprising: obtaining a first filter, calculating the zero points of the first filter; grouping the zero points of the first filter according to a preset cascade filter architecture, and obtaining a second filter according to the grouping result. The embodiment of the present application can reduce the chip area occupied and reduce power consumption.

Description

Technical Field

[0001] The present application relates to the technical field of digital signal processing, and in particular to a filter and a design method thereof. Background Art

[0002] In image processing, it is often necessary to filter the image. Filtering is usually implemented by two-dimensional (2D) image filters such as Gaussian filtering and mean filtering in application specific integrated circuit (ASIC) chips for image processing. When processing images of different resolutions, filters with different convolution kernel sizes are often required. For example, a 5×5 filter is used for video graphics adapter (VGA) images, a 3×3 filter is used for quarter VGA (QVGA) images, and a 9×9 filter is required for high definition (HD) images.

[0003] In ASIC chip design, in order to simultaneously meet the differences in image resolution, the first solution often requires the simultaneous implementation of filters with multiple convolution kernel sizes such as 3×3, 5×5, 7×7 and 9×9; the second solution, for example, designs a 9×9 filter and implements the filtering function of a 3×3, 5×5 or 7×7 filter by configuring the filter coefficients.

[0004] The first solution implements filters of several convolution kernel sizes at the same time, but the more types of convolution kernels are designed, the larger the chip area consumed. The second solution consumes less area, but the power consumption in the actual filtering process will be higher, especially when a large convolution kernel filter is used to complete the function of a small convolution kernel filter. For example, when a 9×9 filter is used to complete the function of a 3×3 filter, (9×9-3×3) / (9×9)=88.9% of the coefficients in its filter weights are zero, and the utilization rate of the multiply accumulate (MAC) unit is only 11.1%, which is inefficient and leads to increased power consumption. Summary of the invention

[0005] In view of this, an embodiment of the present application provides a filter and a design method thereof, which can reduce the chip area occupied and reduce power consumption.

[0006] In a first aspect, an embodiment of the present application provides a filter design method, comprising:

[0007] Acquire a first filter, and perform zero point calculation on the first filter;

[0008] The zero points of the first filter are grouped according to a preset cascade filter architecture, and the second filter is obtained according to the grouping result.

[0009] In this embodiment, based on the first filter (or original filter), a second filter (or target filter) having a filtering effect equivalent to that of the original filter is obtained in a preset cascade filter architecture, thereby reducing the chip area occupied and reducing power consumption.

[0010] As an implementation of the first aspect, the performing zero point calculation on the first filter includes:

[0011] If the first filter is a row-column separable filter, performing row-column separation on the first filter to obtain a column coefficient vector and a row coefficient vector;

[0012] The column coefficient vector and the row coefficient vector are used to construct a first sub-filter and a second sub-filter respectively, and zero point calculation is performed.

[0013] As an implementation manner of the first aspect, if the first filter is a row-column separable filter, grouping the zero points of the first filter according to a preset cascade filter architecture, and obtaining the second filter according to the grouping result, includes:

[0014] Grouping the zero points of the first sub-filter and the second sub-filter according to a preset cascade filter architecture to construct a third sub-filter and a fourth sub-filter;

[0015] The third sub-filter and the fourth sub-filter are recombined to obtain a second filter group.

[0016] As an implementation of the first aspect, using the column coefficient vector and the row coefficient vector to respectively construct a first sub-filter and a second sub-filter, and performing zero point calculation, includes:

[0017] Constructing a first sub-filter and a second sub-filter respectively using the column coefficient vector and the row coefficient vector;

[0018] Zero point calculation is performed on the first sub-filter and the second sub-filter respectively.

[0019] As an implementation of the first aspect, the performing zero point calculation on the first filter further includes:

[0020] If the first filter is a row-column non-separable filter, zero point calculation is performed on the first filter.

[0021] As an implementation of the first aspect, the preset cascade filter architecture includes three filtering units and a selection unit;

[0022] The three filtering units include a first 5×5 filtering unit, a first 3×3 filtering unit, and a second 3×3 filtering unit; the selection unit includes a first multi-way selection module and a second multi-way selection module;

[0023] The first multi-channel selection module includes a first signal and a second signal, and the second multi-channel selection module includes a third signal, a fourth signal and a fifth signal;

[0024] The input end of the first 5×5 filtering unit is connected to the first signal, the output end of the first 5×5 filtering unit is respectively connected to the input end of the first 3×3 filtering unit and the fifth signal, the output end of the first 3×3 filtering unit is connected to the second signal and the fourth signal, the input end of the second 3×3 filtering unit is connected to the first multi-channel selection module, and the output end of the second 3×3 filtering unit is connected to the third signal.

[0025] As an implementation of the first aspect, the preset cascade filter architecture includes four filtering units and a selection unit;

[0026] The four filtering units include a third 3×3 filtering unit, a fourth 3×3 filtering unit, a fifth 3×3 filtering unit and a sixth 3×3 filtering unit; the selection unit includes a third multi-way selection module;

[0027] The third multi-channel selection module includes a sixth channel signal, a seventh channel signal, an eighth channel signal and a ninth channel signal;

[0028] The output end of the third 3×3 filter unit is respectively connected to the input end of the fourth 3×3 filter unit and the ninth signal; the output end of the fourth 3×3 filter unit is respectively connected to the input end of the fifth 3×3 filter unit and the eighth signal; the output end of the fifth 3×3 filter unit is respectively connected to the input end of the sixth 3×3 filter unit and the seventh signal; the output end of the sixth 3×3 filter unit is connected to the sixth signal.

[0029] In a second aspect, an embodiment of the present application provides a filter, including a zero point calculation module, an acquisition module, and a cascade filtering module, wherein:

[0030] The zero point calculation module is used to obtain the first filter and perform zero point calculation on the first filter;

[0031] The acquisition module is used to group the zero points of the first filter according to the cascaded filtering module, and acquire the polynomial coefficient matrix corresponding to the cascaded second filter according to the grouping result.

[0032] The cascade filter module includes at least three filter units and a selection unit. The filter units are cascaded according to the corresponding polynomial coefficient matrix and through the selection unit to obtain the second filter, so that its filtering effect is equivalent to that of the first filter.

[0033] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it implements the filter design method as described in the first aspect or any implementation method of the first aspect.

[0034] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the filter design method as described in the first aspect or any implementation method of the first aspect is implemented.

[0035] In a fifth aspect, an embodiment of the present application provides a computer program product. When the computer program product runs on an electronic device, the electronic device executes the filter design method as described in the first aspect or any implementation of the first aspect.

[0036] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0038] Figure 1 It is a schematic diagram of an implementation flow of a filter design method provided by an embodiment of the present application;

[0039] Figure 2 This is a schematic diagram of a specific implementation flow of step S110 in a filter design method provided in an embodiment of the present application;

[0040] Figure 3 This is a schematic diagram of a specific implementation flow of step S113 in a filter design method provided in an embodiment of the present application;

[0041] Figure 4 This is a schematic diagram of a specific implementation flow of step S120 in a filter design method provided in an embodiment of the present application;

[0042] Figure 5 is a schematic diagram of a cascade connection of filters provided in an embodiment of the present application;

[0043] Figure 6 is a schematic structural diagram of a preset cascade filter architecture provided in an embodiment of the present application;

[0044] Figure 7 is a structural schematic diagram of another preset cascade filter architecture provided in an embodiment of the present application;

[0045] Figure 8 is a structural schematic diagram of a filter provided by an embodiment of the present application;

[0046] Fig. 9 It is a structural schematic diagram of a zero point calculation module in a filter provided in an embodiment of the present application;

[0047] Fig.10 It is a structural schematic diagram of a zero point calculation module in another filter provided in an embodiment of the present application;

[0048] Fig.11 It is a structural schematic diagram of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0049] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0050] The term "and / or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0051] "One embodiment" or "some embodiments" described in the specification of this application means that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the sentences "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0052] In addition, in the description of the present application, "plurality" means two or more. The terms "first", "second", "third", and "fourth" are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0053] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner, so the illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0054] Traditional filter design usually adopts two schemes. The first scheme is to design the filter according to the maximum convolution kernel of 9×9. For the filtering process of different convolution kernels, the number of MACs required by the filter to output one pixel is 9×9=81, and the area ratio coefficient is 9×9=81. The second scheme is to design multiple filters according to different convolution kernels. Assuming that 3×3, 5×5, 7×7 and 9×9 filters are designed respectively, the number of MACs required by the filter is different when performing different filtering. The area ratio coefficient is 3×3+5×5+7×7+9×9=164, which greatly increases the occupied area of ​​the chip. In fact, in the chip, the area ratio coefficient corresponds to the size of the area, the smaller the better; the number of MACs corresponds to the computing power consumption of the chip, the smaller the better.

[0055] Based on the above problems, the present application proposes a filter design method. Figure 1 A schematic diagram of the implementation flow of a filter design method provided in one embodiment of the present application. The filter design method in this embodiment can be executed by an electronic device. The electronic device includes but is not limited to a computer, a tablet computer, a server, a mobile phone, a camera or a wearable device. The server includes but is not limited to an independent server or a cloud server. The filter design method in this embodiment is suitable for situations where data needs to be filtered. Figure 1As shown, the filter design method may include steps S110 to S120.

[0056] S110, obtaining a first filter, and performing zero point calculation on the first filter.

[0057] In this embodiment, the first filter is an original filter, which is usually a filter to be used. The first filter is obtained, and zero point calculation is performed on the first filter.

[0058] As a non-limiting example, assume that the transfer function of the first filter is:

[0059]

[0060] By calculating and combining the zero points of the first filter, it is decomposed into a cascaded form of multiple low-order filters. In one embodiment, it is preferably:

[0061]

[0062] Its mathematical representation is:

[0063]

[0064] Furthermore, the zero point of the first filter can be obtained according to the above cascade form.

[0065] S120, grouping the zero points of the first filter according to a preset cascade filter architecture, and acquiring a second filter according to the grouping result.

[0066] In this embodiment, the electronic device is preset with a cascade filter architecture, and the preset cascade filter architecture can be pre-stored on the processor of the electronic device, and its expression is an integrated circuit, which can be called when used. The preset cascade filter architecture can be set by the system default or customized by the user, and this application is not limited to this. The preset cascade filter architecture includes multiple filter units and a selection unit, and the convolution kernel of the filter unit is usually smaller than the convolution kernel of the original filter. Multiple filter units can have different convolution kernel sizes or the same convolution kernel size. The selection unit is used to cascade the filter units.

[0067] As a non-limiting example, in some embodiments, the preset cascade filter architecture includes three filter units, namely, a first 5×5 filter unit, a first 3×3 filter unit, and a second 3×3 filter unit, and a selection unit. In some other embodiments, the preset cascade filter architecture includes four 3×3 filter units and a selection unit, and the four filter units are respectively a third 3×3 filter unit, a fourth 3×3 filter unit, a fifth 3×3 filter unit, and a sixth 3×3 filter unit.

[0068] In step S120, the zero points of the first filter can be grouped according to the preset cascade filter architecture, a polynomial coefficient matrix matching the preset cascade filter architecture is obtained, and the second filter is constructed using the polynomial coefficient matrix. It should be noted that the architecture of the second filter is the preset cascade filter architecture.

[0069] In some embodiments, zero-point grouping is performed according to the filter types included in a preset cascade filter architecture, and based on the cascade structure obtained after the zero-point grouping, coefficients corresponding to (or matching) the cascade structure are obtained in the preset cascade filter architecture to form a polynomial coefficient matrix, and the second filter is constructed using the polynomial coefficient matrix.

[0070] As a non-limiting example, assuming that the preset cascade filter architecture includes three types of filters, namely, a first 5×5 filtering unit, a first 3×3 filtering unit, and a second 3×3 filtering unit, zero point grouping is performed according to the three types of filters.

[0071] In this embodiment, according to the convolution kernel size and coefficient matrix of the original filter, a second filter (or target filter) having the same filtering effect as the original filter is obtained in a preset cascade filter architecture, thereby reducing the chip area occupied and reducing power consumption.

[0072] exist Figure 1 Based on the embodiment shown, in some other embodiments, specifically, as Figure 2 As shown, step S110 may include steps S111 to S113.

[0073] S111, obtain the first filter, and determine whether the first filter is row-column separable. If yes, that is, the first filter is a row-column separable filter, then continue to execute step S112 and subsequent steps; if no, that is, the first filter is a row-column non-separable filter, then perform zero point calculation on the first filter, and continue to execute step S120.

[0074] S112, performing row-column separation on the separable first filter to obtain a column coefficient vector and a row coefficient vector.

[0075] In some embodiments, it is assumed that the convolution kernel of the separable first filter is a two-dimensional Gaussian convolution kernel. More specifically, it is assumed that the two-dimensional Gaussian convolution kernel function is f[i, j] represents an image and performs a two-dimensional Gaussian filter on the image, that is:

[0076]

[0077]

[0078] in, m, n represent the order of the filter. Ignoring the influence of constant K, the above formula represents a two-dimensional Gaussian filter on an image, which is equivalent to a one-dimensional Gaussian filter on the columns first. c [j] is the column coefficient vector, and then a one-dimensional Gaussian filter is performed on the rows, g r [i] is a row coefficient vector, and the variance of the Gaussian kernel of each row and column is the same as the variance of the two-dimensional Gaussian kernel. It should be noted that in some other embodiments, the rows of the image can be first subjected to a one-dimensional Gaussian filter, and then the columns of the image can be subjected to a one-dimensional Gaussian filter. The present application does not limit the order of the rows and columns. The dimension of the coefficient matrix of the first filter can be set to (2M-1)×(2M-1), and the dimension of the coefficient matrix can also be expressed in other ways, which is not limited here.

[0079] It should be understood that in some other embodiments, the row-column separable two-dimensional filter may be a mean filter or other row-column separable filters in addition to a Gaussian filter, and the present application does not impose any specific limitation on the filter.

[0080] S113, constructing a first sub-filter and a second sub-filter respectively using the column coefficient vector and the row coefficient vector, and performing zero point calculation.

[0081] In some embodiments, more specifically, Figure 3 As shown, step S113 includes steps S1131 to S1132.

[0082] S1131 , construct a first sub-filter and a second sub-filter using the column coefficient vector and the row coefficient vector respectively.

[0083] In some embodiments, the first sub-filter and the second sub-filter can be constructed respectively using the column coefficient vector and the row coefficient vector obtained by performing row-column decomposition on the first filter based on step S112. More specifically, the first filter is a two-dimensional filter with a dimension of (2M-1)×(2M-1), then the dimension of the first sub-filter is 1×(2M-1), and its coefficient matrix is ​​a column coefficient vector; the dimension of the second sub-filter is (2M-1)×1, and its coefficient matrix is ​​a row coefficient vector. Furthermore, the first sub-filter and the second sub-filter can be cascaded to be equivalent to the first filter, that is, the filtering results of the cascaded first sub-filter and the second sub-filter are the same as those of the first filter.

[0084] It should be noted that, in some embodiments, the coefficient matrix of the first sub-filter may be a column coefficient vector, and the coefficient matrix of the second sub-filter may be a row coefficient vector; in some other embodiments, the coefficient matrix of the first sub-filter may be a row coefficient vector, and the coefficient matrix of the second sub-filter may be a column coefficient vector, and there is no limitation here.

[0085] S1132, perform zero point calculation on the first sub-filter and the second sub-filter respectively.

[0086] In some embodiments, based on the row coefficient vector of the first sub-filter and the column coefficient vector of the second sub-filter obtained in step S112, the transfer function G of the first sub-filter is r (Z) and the transfer function G of the second sub-filter c (Z) are:

[0087]

[0088]

[0089] Assuming that both the first sub-filter and the second sub-filter are Gaussian filters, and the Gaussian filter is a finite impulse response (FIR) filter, the first sub-filter and the second sub-filter can be decomposed into a cascade of multiple low-order filters by calculating and combining zero points. In one embodiment, it is preferred that:

[0090]

[0091]

[0092] More specifically, assuming that both the first sub-filter and the second sub-filter are high-order filters, they can be decomposed into a cascaded architecture of multiple second-order filters. The second-order cascade decomposes the above transfer function into a second-order polynomial multiplication form, which can be expressed as:

[0093]

[0094]

[0095] Each of the above second-order polynomials controls a pair of zero points. It should be noted that the transfer function can also be decomposed into a cascade form of multiple first-order polynomials and second-order polynomials, which is not limited here.

[0096] The first sub-filter and the second sub-filter may be decomposed according to a preset cascade filter architecture, and the zero points of the first sub-filter and the second sub-filter may be calculated according to the decomposed cascade structure (ie, polynomial).

[0097] exist Figure 3 Based on the embodiment shown, in some embodiments, if the first filter is a filter that can be separated into rows and columns, such as Figure 4 As shown, step S120 more specifically includes steps S121 to S122.

[0098] S121: Grouping the zero points of the first sub-filter and the second sub-filter according to a preset cascade filter architecture to construct a third sub-filter and a fourth sub-filter.

[0099] In some embodiments, if the dimensions of the first sub-filter and the second sub-filter are 1×(2M-1) and (2M-1)×1 respectively, by calculating the above zero points and grouping the zero points, the first sub-filter and the second sub-filter are reconstructed respectively to obtain the third sub-filter and the fourth sub-filter, and the dimensions of the third sub-filter and the fourth sub-filter can be transformed to M×M; further, the above method can be cyclically used to calculate the zero points of the third sub-filter and the fourth sub-filter and group them to further decompose them into two cascaded [(M+1) / 2]×[(M+1) / 2] filters, which are not limited here. As an example, the cascade structure of the filter can be as follows Figure 5 shown.

[0100] More specifically, if the zero point obtained by the same polynomial is a first-stage sub-filter, then the zero point obtained by multiple polynomials is a multi-stage sub-filter. The first sub-filter and the second sub-filter can be decomposed into a cascade of multiple polynomials, that is, the first sub-filter is divided into multiple polynomial cascades, and the zero point obtained by the same polynomial is a first-stage sub-filter, then a multi-stage third sub-filter can be obtained; the second sub-filter is the same as the first sub-filter, and a multi-stage fourth sub-filter can also be obtained, which will not be repeated here.

[0101] Based on the zero points in the polynomial calculated by the cascade architecture of decomposing the first sub-filter and the second sub-filter according to the preset cascade filter architecture in step S1132, and according to the positions of the zero points in the decomposed cascade architecture, the first sub-filter and the second sub-filter are reconstructed to obtain the third sub-filter and the fourth sub-filter; wherein, the preset cascade filter architecture needs to meet all filter combination requirements, if the preset filter architecture is preferably a cascade combination of a 5×5 filter and two 3×3 filters or a cascade combination of four 3×3 filters, then the corresponding third sub-filter and the fourth sub-filter are also decomposed into a cascade combination of a 5×5 filter unit and two 3×3 filter units or a cascade combination of four 3×3 filter units, and there is no limitation here.

[0102] S122: Recombine the third sub-filter and the fourth sub-filter to obtain a second filter group.

[0103] In some embodiments, the third sub-filter and the fourth sub-filter obtained in step S121 are decomposed from the first sub-filter and the second sub-filter, and the first sub-filter is composed of a row coefficient vector, and the second sub-filter is composed of a column coefficient vector. The reconstructed first sub-filter and the second sub-filter, that is, the third sub-filter and the fourth sub-filter are combined according to a preset cascade filter architecture, that is, the row coefficient vector and the column coefficient vector are multiplied to obtain multiple two-dimensional filters, and the multiple two-dimensional filters are combined to obtain a second filter group, whose filtering effect is equivalent to that of the first filter.

[0104] Based on the above filter cascade decomposition method, the two-dimensional (2M-1)×(2M-1) filter with separable rows and columns can be converted into two cascaded M×M sub-filters through the above method, and the filtering result is equivalent to the two-dimensional filter; further, the M×M filter can be further converted into two cascaded [(M+1) / 2]×[(M+1) / 2] filters to reduce the occupied area and reduce power consumption.

[0105] In this embodiment, according to the convolution kernel size and coefficient matrix of the original filter, filter units that meet the requirements of the original filter are selected in a preset cascade filter architecture for combination to obtain a target filter with a filtering effect equivalent to the original filter, thereby reducing the chip area occupied and reducing power consumption.

[0106] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0107] The beneficial effects of the filter design method provided by the embodiment of the present application are described below through specific application scenarios. It should be understood that the specific application scenarios cannot be interpreted as limiting the present application.

[0108] In some embodiments, the preset cascade filter architecture includes three filter units (or filters) and a selection unit. The three filter units are respectively a first 5×5 filter unit, a first 3×3 filter unit, and a second 3×3 filter unit. The selection unit includes a first multi-channel selection module and a second multi-channel selection module, wherein the first multi-channel selection module includes a first signal and a second signal, and the second multi-channel selection module includes a third signal, a fourth signal, and a fifth signal.

[0109] like Figure 6As shown, the three filter units are respectively a first 5×5 filter unit, a first 3×3 filter unit A and a second 3×3 filter unit B. The first multiplex selection module includes a first input selection pin Mux Sel0, and the first input selection pin MuxSel0 includes a first signal 0 and a second signal 1. The second multiplex selection module includes a second input selection pin MuxSel1, and the second input selection pin Mux Sel1 includes a third signal 0, a fourth signal 1 and a fifth signal 2.

[0110] Specifically, the input end of the first 5×5 filtering unit is connected to the first signal 0 in the first multi-way selection module Mux Sel0, and the output end of the first 5×5 filtering unit can be respectively connected to the input end of the first 3×3 filtering unit A and the fifth signal 2 of the second multi-way selection module Mux Sel1; the output end of the first 3×3 filtering unit A is connected to the second signal 1 in the first multi-way selection module Mux Sel0 and the fourth signal of the second multi-way selection module Mux Sel1; the input end of the second 3×3 filtering unit B is connected to the first multi-way selection module Mux Sel0, and the output end of the second 3×3 filtering unit B is connected to the third signal 0 of the second multi-way selection module Mux Sel1.

[0111] Based on the filter design method provided by the above embodiment, a second filter or a second filter group is determined in a preset cascade filter architecture, and the second filter or the second filter group is a filter or a filter combination equivalent to the original filter (or referred to as the first filter). The appropriate filter unit in the preset cascade filter architecture, that is, the second filter or the second filter group, can be cascaded by a selection unit to realize a filter equivalent to the original filter.

[0112] As an example, see Figure 6 As shown. If the convolution kernel of the original filter is 9×9, based on the filter design method provided in the above embodiment, the 9×9 filter can be decomposed into a combination of a 5×5 and two 3×3 filters. A 5×5 and two 3×3 filter units A and B are selected and combined through the second signal 1 of the first multi-way selection module Mux Sel0 and the third signal 0 of the second multi-way selection module Mux Sel1 to obtain a filter unit combination equivalent to the 9×9 original filter. If the convolution kernel of the original filter is 7×7, based on the filter design method provided in the above embodiment, the 7×7 filter can be decomposed into a combination of a 5×5 and a 3×3 filter. A 5×5 and a 3×3 filter unit A are selected and combined through the second signal 1 of the first multi-way selection module Mux Sel0 and the fourth signal 1 of the second multi-way selection module Mux Sel1 to obtain a filter unit combination equivalent to the 7×7 original filter.

[0113] It should be noted that in Figure 6 In the example shown, the original filter is a 9×9 filter. If the filter is designed with a filter convolution kernel of 9×9 using the traditional method, the number of MACs required to output one pixel is 81, and its area ratio coefficient is 81. However, by using the filter design method provided in an embodiment of the present application, the original filter is decomposed to obtain a filter combination equivalent to the original filter. The number of MACs required for the filter combination to output one pixel is 5×5+3×3+3×3=43, that is, the area ratio coefficient is 43. It can be seen that the filter design method provided in the embodiment of the present application reduces the chip area while also reducing power consumption.

[0114] As shown in Table 1 below, Figure 6 In the case where the preset cascade filter architecture shown, that is, the preset cascade filter architecture includes one 5×5 and two 3×3 filter units (Filter) A and B, the filter design method provided in an embodiment of the present application is used to implement the comparison of the results of 3×3Filter, 5×5Filter, 7×7Filter and 9×9Filter in the preset cascade filter architecture. Among them, ON represents the filter that needs to be cascaded, and OFF represents the filter that does not need to be cascaded. "-" indicates that the multi-way selection module does not select the signal.

[0115] Table 1

[0116]

[0117] It can be seen from Table 1 that after adopting the filtering solution of the embodiment of the present application, the number of MACs required for calculating one output pixel of the 9×9 filter is 5×5+3×3+3×3=43.

[0118] For the calculation of a pixel output by a 7×7 filter, the number of MACs required is 5×5+3×3=34.

[0119] For the calculation of a pixel output by a 5×5 filter, the number of MACs required is 5×5=25.

[0120] For the calculation of a pixel output by a 3×3 filter, the number of MACs required is 3×3=9.

[0121] Figure 6 The area ratio factor of the preset cascade filter architecture shown is 5×5+3×3+3×3=43.

[0122] In other embodiments, Figure 7As shown, the preset cascade filter architecture includes four filter units and a selection unit. The four filter units are four 3×3 filter units, namely the third 3×3 filter unit A, the fourth 3×3 filter unit B, the fifth 3×3 filter unit C and the sixth 3×3 filter unit D. The selection unit includes a third multi-way selection module, and the third multi-way selection module includes a third input selection pin Mux Sel. Among them, the third multi-way selection module includes the sixth signal 0, the seventh signal 1, the eighth signal 2 and the ninth signal 3. Preferably, the output end of the third 3×3 filter unit A is respectively connected to the input end of the fourth 3×3 filter unit B and the ninth signal 3 of the third multiplexer selection module Mux Sel, and a 3×3 filter combination can be output through the ninth signal 3; the output end of the fourth 3×3 filter unit B is respectively connected to the input end of the fifth 3×3 filter unit C and the eighth signal 2 of the third multiplexer selection module Mux Sel, and a 3×3+3×3 filter combination can be output through the eighth signal 2, that is, a 3×3 filter combination of two cascaded 3×3 filters, and its filtering effect is equivalent to a 5×5 filter; the output end of the fifth 3×3 filter unit C is respectively connected to the input end of the sixth 3×3 filter unit D and the seventh signal 1 of the third multiplexer selection module Mux Sel, and a 3×3×3 filter combination can be output through the seventh signal 1, that is, a 3×3 filter combination of three cascaded 3×3 filters, and its filtering effect is equivalent to a 7×7 filter; the output end of the sixth 3×3 filter unit D is connected to the third multiplexer selection module Mux The sixth signal 0 of Sel is connected, and a 4×3×3 filter combination, that is, a 4-cascaded 3×3 filter combination, can be output through the sixth signal 0, and its filtering effect is equivalent to a 9×9 filter.

[0123] As shown in Table 2 below, Figure 7 In the case where the preset cascade filter architecture shown, that is, the preset cascade filter architecture includes four 3×3 filter units (Filters) A, B, C and D, the filter design method provided by an embodiment of the present application is used to implement the comparison of the results of 3×3Filter, 5×5Filter, 7×7Filter and 9×9Filter in the preset cascade filter architecture. Among them, ON indicates that the filter needs to be cascaded, and OFF indicates that the filter does not need to be cascaded.

[0124] Table 2

[0125]

[0126] It can be seen from Table 2 that after adopting the filtering solution of the embodiment of the present application, the number of MACs required for calculating a pixel output by a 9×9 filter is 4×3×3=36.

[0127] For the calculation of one output pixel of a 7×7 filter, the number of MACs required is 3×3×3=27.

[0128] For the calculation of a pixel output by a 5×5 filter, the number of MACs required is 2×3×3=18.

[0129] For the calculation of a pixel output by a 3×3 filter, the number of MACs required is 3×3=9.

[0130] Figure 7 The area scaling factor of the preset cascade filter architecture shown is 4×3×3=36.

[0131] It should be understood that the preset cascade filter architecture may also adopt other forms, as long as it can basically meet all types of filter requirements, and there is no limitation here.

[0132] The first scheme in the traditional filter design is adopted, assuming that the filter is designed with a maximum convolution kernel of 9×9. For the calculation of a pixel output by a 9×9 filter, the number of MACs required is 9×9=81. For the calculation of a pixel output by a 7×7 filter, the number of MACs required is 9×9=81. For the calculation of a pixel output by a 5×5 filter, the number of MACs required is 9×9=81. For the calculation of a pixel output by a 3×3 filter, the number of MACs required is 9×9=81. The area ratio coefficient of this architecture is 9×9=81.

[0133] The second scheme in traditional filter design is adopted, and multiple filters of 3×3, 5×5, 7×7 and 9×9 are designed respectively. For the calculation of a pixel output by the 9×9 filter, the number of MACs required is 9×9=81. For the calculation of a pixel output by the 7×7 filter, the number of MACs required is 7×7=49. For the calculation of a pixel output by the 5×5 filter, the number of MACs required is 5×5=25. For the calculation of a pixel output by the 3×3 filter, the number of MACs required is 3×3=9. The area ratio coefficient of this architecture is 3×3+5×5+7×7+9×9=164.

[0134] Table 3 below is a comparison table of the number of MACs and area ratio coefficients required to implement 3×3Filter, 5×5Filter, 7×7Filter and 9×9Filter under four different implementation architectures.

[0135] Table 3

[0136]

[0137] It can be seen that compared with the traditional design method, the embodiment of the present application realizes a unified solution for multiple kernel sizes of row-column separable 2D filters, including a filter coefficient conversion algorithm and a chip hardware implementation architecture. While satisfying the flexibility and configurability of the filter kernel size, it ensures a small area and low power consumption. The effect is equivalent to designing multiple filters of different kernel sizes separately. For any M×M size of row-column separable 2D filter, as long as it is within the range supported by the design specifications and architecture, a cascade combination of multiple filters can be used for implementation, and the chip implementation area is small and the power consumption is low.

[0138] An embodiment of the present application also provides a filter design device. For details not described in detail in the filter design device, please refer to the description in the above method embodiment.

[0139] See also Figure 8 , Figure 8 7 is a schematic block diagram of a filter provided in an embodiment of the present application. The filter comprises: a zero point calculation module 71 , an acquisition module 72 and a cascade filter module 73 .

[0140] The zero point calculation module 71 is used to obtain a first filter and perform zero point calculation on the first filter.

[0141] The acquisition module 72 is used to group the zero points of the first filter according to the cascaded filtering module 73, and obtain the polynomial coefficient matrix corresponding to the cascaded second filter according to the grouping result.

[0142] The cascade filter module 73 includes at least three filter units and a selection unit. The filter units are cascaded according to corresponding polynomial coefficient matrices and through the selection unit to obtain a second filter, so that its filtering effect is equivalent to that of the first filter.

[0143] In some embodiments, Fig. 9 As shown, the zero point calculation module 71 includes a separation submodule 711 and a first calculation submodule 712 .

[0144] The separation submodule 711 is used for performing row-column separation on the first filter to obtain a column coefficient vector and a row coefficient vector if the first filter is a row-column separable filter;

[0145] The first calculation submodule 712 is used to construct a first sub-filter and a second sub-filter respectively using the column coefficient vector and the row coefficient vector, and perform zero point calculation.

[0146] In some embodiments, if the first filter is a row-column separable filter, the acquisition module 72 is specifically configured to:

[0147] Grouping the zero points of the first sub-filter and the second sub-filter according to a preset cascade filter architecture to construct a third sub-filter and a fourth sub-filter;

[0148] The third sub-filter and the fourth sub-filter are recombined to obtain a polynomial coefficient matrix corresponding to the cascaded second filter.

[0149] In some embodiments, the first calculation submodule 712 is specifically used to:

[0150] Constructing a first sub-filter and a second sub-filter respectively using the column coefficient vector and the row coefficient vector;

[0151] Zero point calculation is performed on the first sub-filter and the second sub-filter respectively.

[0152] In some embodiments, Fig.10 As shown, in Fig. 9 On the basis shown, the zero point calculation module 71 also includes a second calculation submodule 713 .

[0153] The second calculation submodule 713 is configured to perform zero point calculation on the first filter if the first filter is a row-column inseparable filter.

[0154] In some embodiments, the cascade filter module 73 includes three filter units and a selection unit;

[0155] The three filtering units include a first 5×5 filtering unit, a first 3×3 filtering unit, and a second 3×3 filtering unit; the selection unit includes a first multi-way selection module and a second multi-way selection module;

[0156] The first multi-channel selection module includes a first signal and a second signal, and the second multi-channel selection module includes a third signal, a fourth signal and a fifth signal;

[0157] The input end of the first 5×5 filtering unit is connected to the first signal, the output end of the first 5×5 filtering unit is respectively connected to the input end of the first 3×3 filtering unit and the fifth signal, the output end of the first 3×3 filtering unit is connected to the second signal and the fourth signal, the input end of the second 3×3 filtering unit is connected to the first multi-channel selection module, and the output end of the second 3×3 filtering unit is connected to the third signal.

[0158] In some embodiments, the cascade filter module 73 includes four filter units and a selection unit;

[0159] The four filtering units include a third 3×3 filtering unit, a fourth 3×3 filtering unit, a fifth 3×3 filtering unit and a sixth 3×3 filtering unit; the selection unit includes a third multi-way selection module;

[0160] The third multi-channel selection module includes a sixth channel signal, a seventh channel signal, an eighth channel signal and a ninth channel signal;

[0161] The output end of the third 3×3 filter unit is respectively connected to the input end of the fourth 3×3 filter unit and the ninth signal; the output end of the fourth 3×3 filter unit is respectively connected to the input end of the fifth 3×3 filter unit and the eighth signal; the output end of the fifth 3×3 filter unit is respectively connected to the input end of the sixth 3×3 filter unit and the seventh signal; the output end of the sixth 3×3 filter unit is connected to the sixth signal.

[0162] An embodiment of the present application also provides an electronic device, such as Fig.11 As shown, the electronic device may include one or more processors 90 ( Fig.11 The embodiment of the filter design method includes a memory 91 and a computer program 92, for example, a program for performing filtering processing, which is stored in the memory 91 and can be run on one or more processors 90. When the one or more processors 90 execute the computer program 92, the various steps in the filter design method embodiment can be implemented. Alternatively, when the one or more processors 90 execute the computer program 92, the functions of the various modules / units in the filter design device embodiment can be implemented, which is not limited here.

[0163] Those skilled in the art will understand that Fig.11 The electronic device is merely an example of an electronic device and does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, the electronic device may also include input and output devices, network access devices, buses, etc.

[0164] In one embodiment, the processor 90 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0165] In one embodiment, the memory 91 may be an internal storage unit of an electronic device, such as a hard disk or memory of the electronic device. The memory 91 may also be an external storage device of the electronic device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device. Further, the memory 91 may also include both an internal storage unit of the electronic device and an external storage device. The memory 91 is used to store computer programs and other programs and data required by the electronic device. The memory 91 may also be used to temporarily store data that has been output or is to be output.

[0166] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0167] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the embodiment of the filter design method can be implemented.

[0168] An embodiment of the present application provides a computer program product. When the computer program product is run on an electronic device, the electronic device can implement the steps in the filter design method embodiment.

[0169] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0170] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0171] In the embodiments provided in the present application, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0172] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0173] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0174] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above method embodiments, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electric carrier signals and telecommunication signals.

[0175] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A filter design method, characterized in that: include: Acquire a first filter, and perform zero point calculation on the first filter; Grouping the zero points of the first filter according to a preset cascade filter architecture, and obtaining a second filter according to the grouping result; The preset cascade filter architecture includes three filtering units and a selection unit; The three filtering units include a first 5×5 filtering unit, a first 3×3 filtering unit, and a second 3×3 filtering unit; the selection unit includes a first multi-way selection module and a second multi-way selection module; The first multi-channel selection module includes a first signal and a second signal, and the second multi-channel selection module includes a third signal, a fourth signal and a fifth signal; The input end of the first 5×5 filter unit is connected to the first signal, the output end of the first 5×5 filter unit is respectively connected to the input end of the first 3×3 filter unit and the fifth signal, the output end of the first 3×3 filter unit is connected to the second signal and the fourth signal, the input end of the second 3×3 filter unit is connected to the first multi-channel selection module, and the output end of the second 3×3 filter unit is connected to the third signal; or, The preset cascade filter architecture includes four filtering units and a selection unit; The four filtering units include a third 3×3 filtering unit, a fourth 3×3 filtering unit, a fifth 3×3 filtering unit and a sixth 3×3 filtering unit; the selection unit includes a third multi-way selection module; The third multi-channel selection module includes a sixth channel signal, a seventh channel signal, an eighth channel signal and a ninth channel signal; The output end of the third 3×3 filter unit is respectively connected to the input end of the fourth 3×3 filter unit and the ninth signal; the output end of the fourth 3×3 filter unit is respectively connected to the input end of the fifth 3×3 filter unit and the eighth signal; the output end of the fifth 3×3 filter unit is respectively connected to the input end of the sixth 3×3 filter unit and the seventh signal; the output end of the sixth 3×3 filter unit is connected to the sixth signal.

2. The filter design method according to claim 1, characterized in that: The performing zero point calculation on the first filter comprises: If the first filter is a row-column separable filter, performing row-column separation on the first filter to obtain a column coefficient vector and a row coefficient vector; The column coefficient vector and the row coefficient vector are used to construct a first sub-filter and a second sub-filter respectively, and zero point calculation is performed.

3. The filter design method according to claim 2, characterized in that: If the first filter is a row-column separable filter, the zero points of the first filter are grouped according to a preset cascade filter architecture, and the second filter is obtained according to the grouping result, including: Grouping the zero points of the first sub-filter and the second sub-filter according to a preset cascade filter architecture to construct a third sub-filter and a fourth sub-filter; The third sub-filter and the fourth sub-filter are recombined to obtain a second filter group.

4. The filter design method according to claim 2, characterized in that: The using the column coefficient vector and the row coefficient vector to respectively construct a first sub-filter and a second sub-filter, and performing zero point calculation, comprises: Constructing a first sub-filter and a second sub-filter respectively using the column coefficient vector and the row coefficient vector; Zero point calculation is performed on the first sub-filter and the second sub-filter respectively.

5. The filter design method according to claim 2, characterized in that: The performing zero point calculation on the first filter further includes: If the first filter is a row-column non-separable filter, zero point calculation is performed on the first filter.

6. A filter, characterized in that: It includes a zero point calculation module, an acquisition module, and a cascade filtering module, wherein: The zero point calculation module is used to obtain the first filter and perform zero point calculation on the first filter; The acquisition module is used to group the zero points of the first filter according to the cascaded filtering module, and acquire the polynomial coefficient matrix corresponding to the cascaded second filter according to the grouping result; The cascade filter module includes at least three filter units and a selection unit, wherein the filter units are cascaded according to the corresponding polynomial coefficient matrix and through the selection unit to obtain the second filter, so that the filtering effect thereof is equivalent to that of the first filter; The three filtering units include a first 5×5 filtering unit, a first 3×3 filtering unit, and a second 3×3 filtering unit; the selection unit includes a first multi-way selection module and a second multi-way selection module; The first multi-channel selection module includes a first signal and a second signal, and the second multi-channel selection module includes a third signal, a fourth signal and a fifth signal; The input end of the first 5×5 filter unit is connected to the first signal, the output end of the first 5×5 filter unit is respectively connected to the input end of the first 3×3 filter unit and the fifth signal, the output end of the first 3×3 filter unit is connected to the second signal and the fourth signal, the input end of the second 3×3 filter unit is connected to the first multi-channel selection module, and the output end of the second 3×3 filter unit is connected to the third signal; or, The cascade filter module includes four filter units and a selection unit; The four filtering units include a third 3×3 filtering unit, a fourth 3×3 filtering unit, a fifth 3×3 filtering unit and a sixth 3×3 filtering unit; the selection unit includes a third multi-way selection module; The third multi-channel selection module includes a sixth channel signal, a seventh channel signal, an eighth channel signal and a ninth channel signal; The output end of the third 3×3 filter unit is respectively connected to the input end of the fourth 3×3 filter unit and the ninth signal; the output end of the fourth 3×3 filter unit is respectively connected to the input end of the fifth 3×3 filter unit and the eighth signal; the output end of the fifth 3×3 filter unit is respectively connected to the input end of the sixth 3×3 filter unit and the seventh signal; the output end of the sixth 3×3 filter unit is connected to the sixth signal.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the filter design method according to any one of claims 1 to 5 are implemented.

8. A computer storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the filter design method according to any one of claims 1 to 5 are implemented.

Images