Interface power supply circuit and terminal

Abstract

This invention discloses an interface power supply circuit and a terminal. The circuit includes: a VBUS power network for a USB connector, a PMOS transistor VT2, an NMOS transistor Q3, an NMOS transistor Q1, and an NMOS transistor Q2. The VBUS power network is connected to the source of the PMOS transistor VT2. The control terminal of the PMOS transistor VT2 is connected to the drain of both the NMOS transistor Q3 and the NMOS transistor Q1. A resistor R1 is connected in parallel between the source and drain of the PMOS transistor VT2. The drain of the PMOS transistor VT2 is connected to the terminal's system power supply VDD_5V to supply power to the terminal's VCC_IN power supply. The drain of the NMOS transistor Q1 is connected to the VBUS power network via a pull-up resistor R1. The control terminal of the NMOS transistor Q1 is connected to the drain of the NMOS transistor Q2. The source of the NMOS transistor Q1 is connected to the GND ground terminal. This provides a more stable interface power supply solution, improving the operational stability of the terminal and enhancing the user experience.

Description

Technical Field

[0001] This invention relates to the field of mobile communications, and more particularly to an interface power supply circuit and terminal. Background Technology

[0002] Smart terminals generally adopt the classic computer architecture—the von Neumann architecture, which consists of five major components: the arithmetic logic unit (ALU), the controller, the memory, the input device, and the output device. The ALU and the controller constitute the core component of the computer—the central processing unit (CPU).

[0003] However, in the existing technology, the CPU of the smart terminal needs to download via USB. In order to ensure that the download is normal, the VBUS power network of the USB connector is required to power the entire system of the smart terminal. However, the power output capability of USB is limited. If USB power is used, the operation stability of the smart terminal is not good. Summary of the Invention

[0004] To address the aforementioned technical deficiencies in the prior art, this invention proposes an interface power supply circuit. The circuit includes: a VBUS power network for a USB connector, a PMOS transistor VT2, an NMOS transistor Q3, an NMOS transistor Q1, and an NMOS transistor Q2. The VBUS power network is connected to the source of the PMOS transistor VT2. The control terminal of the PMOS transistor VT2 is connected to the drain of both the NMOS transistor Q3 and the NMOS transistor Q1. A resistor R1 is connected in parallel between the source and drain of the PMOS transistor VT2. The drain of the PMOS transistor VT2 is connected to the system power supply VDD_5V of the terminal, thus supplying power to the terminal's VCC_IN power supply. The drain of the NMOS transistor Q1 is connected to the VBUS power network via a pull-up resistor R1. The control terminal of transistor Q1 is connected to the drain of NMOS transistor Q2, and the source of NMOS transistor Q1 is connected to GND. The drain of NMOS transistor Q2 is connected to the VBUS power network via pull-up resistor R2. The control terminal of NMOS transistor Q2 is connected to the UBOOT pin of the terminal's CPU, and the source of NMOS transistor Q2 is connected to GND. The drain of NMOS transistor Q3 is connected to the VBUS power network via pull-up resistor R1. The control terminal of NMOS transistor Q3 is connected to the terminal's main power supply VCC_CPU via pull-up resistor R3, and the source of NMOS transistor Q1 is connected to GND. The USB data D- port and D+ port are connected to the USB_DM signal port and USB_DP signal port of the terminal's CPU, respectively.

[0005] Optionally, when a download signal from the terminal's CPU is detected, the terminal's main power supply VCC_CPU is disconnected, and the terminal's PoE power supply and adapter power supply are removed.

[0006] Optionally, after removing the PoE power supply and adapter power supply from the terminal, the MCU_BOOT of the terminal's CPU is switched to a low level, a download USB cable is inserted, and a 5V power supply is available on the VBUS power network.

[0007] Optionally, when the CPU's Uboot is low, the control electrode of NMOS transistor Q2 is low. When the control electrode of NMOS transistor Q2 is low, NMOS transistor Q2 is in the off state, and its drain is connected to the VBUS power network by pull-up resistor R2, becoming high. The control electrode of NMOS transistor Q1 is high. When the control electrode of NMOS transistor Q1 is high, NMOS transistor Q1 is in the on state, and its drain is low. The control electrode of PMOS transistor VT2 becomes low, and PMOS transistor VT2 is in the on state. The VBUS power network outputs 5V power through PMOS transistor VT2 to VCC_CPU power supply to power the CPU's VCC_IN power supply. The CPU enters download mode and downloads software to the CPU through the USB D- and D+ ports.

[0008] Optionally, when the terminal's CPU enters download mode, the MCU_BOOT of the terminal's CPU is disconnected from the low level, and a 5V power supply is provided on the main power supply VCC_CPU power network.

[0009] Optionally, the control electrode of the NMOS transistor Q3 is connected to the main power supply VCC_CPU via a pull-up resistor R3 to present a high level.

[0010] Optionally, when the control electrode of the NMOS transistor Q3 is at a high level, the NMOS transistor Q3 is in the on state, and the drain electrode of the NMOS transistor Q3 is at a low level.

[0011] Optionally, the control electrode of the PMOS transistor VT2 remains at a low level, and the PMOS transistor VT2 remains in the on state.

[0012] Optionally, the VBUS power network outputs 5V power through the PMOS transistor VT2 to the main power supply VCC_CPU to power the CPU's VCC_IN power supply. The power supply on the main power supply VCC_CPU keeps the terminal's CPU in download mode, ensuring the normal progress of software download.

[0013] The present invention also proposes a terminal comprising an interface power supply circuit as described in any of the preceding claims.

[0014] The present invention relates to an interface power supply circuit and terminal. The interface power supply circuit includes: a VBUS power network for a USB connector, a PMOS transistor VT2, an NMOS transistor Q3, an NMOS transistor Q1, and an NMOS transistor Q2. The VBUS power network is connected to the source of the PMOS transistor VT2. The control terminal of the PMOS transistor VT2 is connected to the drain of the NMOS transistor Q3 and the drain of the NMOS transistor Q1. A resistor R1 is connected in parallel between the source and drain of the PMOS transistor VT2. The drain of the PMOS transistor VT2 is connected to the system power supply VDD_5V of the terminal to supply power to the terminal's VCC_IN power supply. The drain of the NMOS transistor Q1 is connected to the VBUS power network via a pull-up resistor R1. The control terminal of NMOS transistor Q1 is connected to the drain of NMOS transistor Q2, and the source of NMOS transistor Q2 is connected to GND. The drain of NMOS transistor Q2 is connected to the VBUS power network via pull-up resistor R2, the control terminal of NMOS transistor Q2 is connected to the U-Boot pin of the terminal's CPU, and the source of NMOS transistor Q2 is connected to GND. The drain of NMOS transistor Q3 is connected to the VBUS power network via pull-up resistor R1, and the control terminal of NMOS transistor Q3 is connected to the terminal's main power supply VCC_CPU via pull-up resistor R3. The source of NMOS transistor Q1 is connected to GND. The USB data D- port and D+ port are connected to the USB_DM signal port and USB_DP signal port of the terminal's CPU, respectively. This achieves a more stable interface power supply scheme, improving the operational stability of the terminal and enhancing the user experience. Attached Figure Description

[0015] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings:

[0016] Figure 1 This is a circuit diagram of the first embodiment of the interface power supply circuit of the present invention;

[0017] Figure 2 This is a circuit diagram of the second embodiment of the interface power supply circuit of the present invention;

[0018] Figure 3 This is a circuit diagram of the third embodiment of the interface power supply circuit of the present invention. Detailed Implementation

[0019] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0020] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0021] Example 1

[0022] Figure 1 This is a circuit diagram of the first embodiment of the interface power supply circuit of the present invention. This embodiment proposes an interface power supply circuit, which includes: a VBUS power network for a USB connector, a PMOS transistor VT2, an NMOS transistor Q3, an NMOS transistor Q1, and an NMOS transistor Q2. The VBUS power network is connected to the source of the PMOS transistor VT2. The control terminal of the PMOS transistor VT2 is connected to the drain of the NMOS transistor Q3 and the drain of the NMOS transistor Q1. A resistor R1 is connected in parallel between the source and drain of the PMOS transistor VT2. The drain of the PMOS transistor VT2 is connected to the system power supply VDD_5V of the terminal to supply power to the terminal's VCC_IN power supply. The drain of the NMOS transistor Q1 is connected to the VBUS power network through a pull-up resistor R1. The control terminal of the NMOS transistor Q1 is connected to... The drain of NMOS transistor Q2 and the source of NMOS transistor Q1 are connected to GND. The drain of NMOS transistor Q2 is connected to the VBUS power network via pull-up resistor R2. The control terminal of NMOS transistor Q2 is connected to the UBOOT pin of the terminal's CPU, and the source of NMOS transistor Q2 is connected to GND. The drain of NMOS transistor Q3 is connected to the VBUS power network via pull-up resistor R1. The control terminal of NMOS transistor Q3 is connected to the terminal's main power supply VCC_CPU via pull-up resistor R3, and the source of NMOS transistor Q1 is connected to GND. The USB data D- port and D+ port are connected to the USB_DM signal port and USB_DP signal port of the terminal's CPU, respectively.

[0023] As can be seen in this embodiment, when the terminal's UBOOT signal is low, it enters download mode. The USB VBUS power supply connects to the chip's VCC power supply network. Once in download mode, the power supply continues to control the USB VBUS power supply to the chip's VCC, maintaining the power supply network and ensuring normal download operation. This improves the stability of the smart terminal's power supply, thereby enhancing system stability and user experience.

[0024] The beneficial effect of this embodiment is that by proposing an interface power supply circuit, the circuit includes: a VBUS power network for a USB connector, a PMOS transistor VT2, an NMOS transistor Q3, an NMOS transistor Q1, and an NMOS transistor Q2. The VBUS power network is connected to the source of the PMOS transistor VT2, and the control terminal of the PMOS transistor VT2 is connected to the drain of the NMOS transistor Q3 and the drain of the NMOS transistor Q1. A resistor R1 is connected in parallel between the source and drain of the PMOS transistor VT2. The drain of the PMOS transistor VT2 is connected to the system power supply VDD_5V of the terminal to supply power to the terminal's VCC_IN power supply. The drain of the NMOS transistor Q1 is connected to the VBUS power network through a pull-up resistor R1. The control terminal of NMOS transistor Q2 is connected to the drain of NMOS transistor Q2, and the source of NMOS transistor Q1 is connected to GND. The drain of NMOS transistor Q2 is connected to the VBUS power network via pull-up resistor R2, and the control terminal of NMOS transistor Q2 is connected to the U-Boot pin of the terminal's CPU. The source of NMOS transistor Q2 is connected to GND. The drain of NMOS transistor Q3 is connected to the VBUS power network via pull-up resistor R1, and the control terminal of NMOS transistor Q3 is connected to the terminal's main power supply VCC_CPU via pull-up resistor R3. The source of NMOS transistor Q1 is connected to GND. The USB data D- and D+ ports are connected to the USB_DM and USB_DP signal ports of the terminal's CPU, respectively. This provides a more stable interface power supply scheme, improving the terminal's operational stability and enhancing the user experience.

[0025] Example 2

[0026] Figure 2 This is a circuit diagram of the second embodiment of the interface power supply circuit of the present invention. Based on the above embodiment, when the download signal of the terminal's CPU is detected, the terminal's main power supply VCC_CPU power supply is disconnected, and the terminal's POE power supply and adapter power supply are removed.

[0027] Optionally, after removing the PoE power supply and adapter power supply from the terminal, the MCU_BOOT of the terminal's CPU is switched to a low level, a download USB cable is inserted, and a 5V power supply is available on the VBUS power network.

[0028] Optionally, when the CPU's Uboot is low, the control electrode of the NMOS transistor Q2 is also low.

[0029] In this embodiment, when the control electrode of NMOS transistor Q2 is at a low level, NMOS transistor Q2 is in the off state, the drain of NMOS transistor Q2 is connected to the VBUS power network by the pull-up resistor R2 and becomes high level, and the control electrode of NMOS transistor Q1 is at a high level.

[0030] In this embodiment, when the control electrode of the NMOS transistor Q1 is at a high level, the NMOS transistor Q1 is in the on state, the drain electrode of the NMOS transistor Q1 is at a low level, the control electrode of the PMOS transistor VT2 becomes low, the PMOS transistor VT2 is in the on state, and the VBUS power network outputs 5V power through the PMOS transistor VT2 to supply power to the VCC_CPU power supply to the CPU's VCC_IN power supply.

[0031] In this embodiment, based on the above-described working method, the CPU enters download mode and downloads software to the CPU via the USB D- and D+ ports.

[0032] Example 3

[0033] Figure 3 This is a circuit diagram of the third embodiment of the interface power supply circuit of the present invention. Based on the above embodiment, when the CPU of the terminal enters the download mode, the MCU_BOOT of the CPU of the terminal is disconnected from the low level, and there is a 5V power supply on the power supply network of the main power supply VCC_CPU.

[0034] Optionally, the control electrode of the NMOS transistor Q3 is connected to the main power supply VCC_CPU via a pull-up resistor R3 to present a high level.

[0035] Optionally, when the control electrode of the NMOS transistor Q3 is at a high level, the NMOS transistor Q3 is in the on state, and the drain electrode of the NMOS transistor Q3 is at a low level.

[0036] Optionally, the control electrode of the PMOS transistor VT2 remains at a low level, and the PMOS transistor VT2 remains in the on state.

[0037] Optionally, the VBUS power network outputs 5V power through the PMOS transistor VT2 to the main power supply VCC_CPU to power the CPU's VCC_IN power supply. The power supply on the main power supply VCC_CPU keeps the terminal's CPU in download mode, ensuring the normal progress of software download.

[0038] Example 4

[0039] Based on the above embodiments, the present invention also proposes a terminal, which includes an interface power supply circuit as described in any of the preceding embodiments.

[0040] It should be noted that the above terminal embodiments and circuit embodiments belong to the same concept. The specific implementation process can be found in the circuit embodiments. Furthermore, the technical features in the circuit embodiments are also applicable to the terminal embodiments, and will not be repeated here.

[0041] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0042] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0043] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. An interface power supply circuit, characterized in that, The circuit includes: a VBUS power network for the USB connector, a PMOS transistor VT2, an NMOS transistor Q3, an NMOS transistor Q1, and an NMOS transistor Q2. The VBUS power network is connected to the source of the PMOS transistor VT2. The control terminal of the PMOS transistor VT2 is connected to the drain of both the NMOS transistor Q3 and the NMOS transistor Q1. A resistor R1 is connected in parallel between the source and drain of the PMOS transistor VT2. The drain of the PMOS transistor VT2 is connected to the system power supply VDD_5V of the terminal to supply power to the terminal's VCC_IN power supply. The drain of the NMOS transistor Q1 is connected to the VBUS power network through the resistor R1. The control terminal of the NMOS transistor Q1 is connected to the NMOS transistor Q2. The drain of transistor Q2 is connected to the source of NMOS transistor Q1, which is connected to the GND ground terminal. The drain of NMOS transistor Q2 is connected to the VBUS power network via pull-up resistor R2. The control terminal of NMOS transistor Q2 is connected to the UBOOT pin of the terminal's MCU, and the source of NMOS transistor Q2 is connected to the GND ground terminal. The drain of NMOS transistor Q3 is connected to the VBUS power network via resistor R1. The control terminal of NMOS transistor Q3 is connected to the terminal's main power supply VCC_MCU via pull-up resistor R3, and the source of NMOS transistor Q3 is connected to the GND ground terminal. The USB data D- port and D+ port are respectively connected to the USB_DM signal port and USB_DP signal port of the terminal's MCU.

2. The interface power supply circuit according to claim 1, characterized in that, When the MCU download signal of the terminal is detected, disconnect the main power supply VCC_MCU power supply of the terminal, and remove the POE power supply and adapter power supply of the terminal.

3. The interface power supply circuit according to claim 2, characterized in that, After removing the PoE power supply and adapter power supply from the terminal, switch the MCU_UBOOT of the terminal's MCU to low level, insert the download USB cable, and a 5V power supply is available on the VBUS power network.

4. The interface power supply circuit according to claim 3, characterized in that, When the U-Boot pin of the terminal's MCU is low, the control electrode of NMOS transistor Q2 is low. When the control electrode of NMOS transistor Q2 is low, NMOS transistor Q2 is in the off state. The drain of NMOS transistor Q2 is connected to the VBUS power network by the pull-up resistor R2 and becomes high. The control electrode of NMOS transistor Q1 is high. When the control electrode of NMOS transistor Q1 is high, NMOS transistor Q1 is in the on state. The drain of NMOS transistor Q1 is low. The control electrode of PMOS transistor VT2 becomes low, and PMOS transistor VT2 is in the on state. The VBUS power network outputs 5V power through PMOS transistor VT2 to VCC_MCU power supply to power the MCU's VCC_IN power supply. The MCU enters download mode and downloads software to the MCU through the USB D- and D+ ports.

5. The interface power supply circuit according to claim 1, characterized in that, When the terminal's MCU enters download mode, the terminal's MCU MCU_UBOOT is switched to low level, and a 5V power supply is available on the main power supply VCC_MCU power network.

6. The interface power supply circuit according to claim 5, characterized in that, The control electrode of the NMOS transistor Q3 is connected to the main power supply VCC_MCU through a pull-up resistor R3, thus presenting a high level.

7. The interface power supply circuit according to claim 6, characterized in that, When the control electrode of the NMOS transistor Q3 is at a high level, the NMOS transistor Q3 is in the on state, and the drain electrode of the NMOS transistor Q3 is at a low level.

8. The interface power supply circuit according to claim 7, characterized in that, The control electrode of the PMOS transistor VT2 remains at a low level, and the PMOS transistor VT2 is in the on state.

9. The interface power supply circuit according to claim 8, characterized in that, The VBUS power network outputs 5V power through the PMOS transistor VT2 to the main power supply VCC_MCU, which in turn supplies power to the MCU's VCC_IN power supply. The power supply on the main power supply VCC_MCU keeps the terminal's MCU in download mode, ensuring the normal progress of software download.

10. A terminal, characterized in that, The terminal includes an interface power supply circuit as described in any one of claims 1 to 9.

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