Acceleration circuit system for posit calculation

Abstract

Systems, devices, and methods related to acceleration circuitry for POSIT operations are described. A first operand formatted in a common digital or POSIT format may be received by a first buffer resident on the acceleration circuitry. A second operand formatted in a common digital or POSIT format may be received by a second buffer resident on the acceleration circuitry. An arithmetic operation, a logical operation, or both may be performed using processing circuitry resident on the acceleration circuitry using the first operand and the second operand. A result of the arithmetic operation, the logical operation, or both may be received by a third buffer resident on the acceleration circuitry.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor memories and methods, and more particularly to apparatus, systems, and methods for accelerating circuitry for POSIT operations. Background Art

[0002] Memory devices are typically provided as internal, semiconductor, integrated circuits within a computer or other electronic system. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory provides persistent data by retaining stored data when not powered, and may include NAND flash memory, NOR flash memory, and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

[0003] The memory device may be coupled to a host (e.g., a host computing device) to store data, commands, and / or instructions for use by the host while the computer or electronic system is in operation. For example, data, commands, and / or instructions may be transferred between the host and the memory device during operation of the computing or other electronic system. Summary of the Invention

[0004] According to aspects of the present application, a method for an acceleration circuit system for POSIT operation is provided. The method includes: receiving a first operand formatted in a universal number (UNUM) or POSIT format through a first buffer residing on the acceleration circuit system; receiving a second operand formatted in the UNUM or POSIT format through a second buffer residing on the acceleration circuit system; performing an arithmetic operation, a logical operation, or both using the first operand and the second operand using processing circuitry residing on the acceleration circuit system; and transmitting a result of the arithmetic operation, the logical operation, or both through a third buffer residing on the acceleration circuit system.

[0005] According to another aspect of the present application, an apparatus for accelerating circuitry for a POSIT operation is provided. The apparatus includes: a direct memory access (DMA) controller; a first buffer, couplable to the DMA controller and configured to store a first operand formatted in a universal number (UNUM) or POSIT format; a second buffer, couplable to the DMA controller and configured to store a second operand formatted in the UNUM or POSIT format; processing circuitry, couplable to the first and second buffers, wherein the processing circuitry is configured to perform an arithmetic operation, a logical operation, or both using the first and second operands; and a third buffer, couplable to the DMA controller and the processing circuitry, wherein the third buffer is configured to store a result of the arithmetic operation, the logical operation, or both.

[0006] According to another aspect of the present application, a system for accelerating circuitry for POSIT operations is provided. The system includes: a host; and a memory device, couplable to the host and comprising: a first memory configured to store operands formatted in a universal number (UNUM) or POSIT format and received from the host; a second memory configured to store instructions received from the host; and a processing device, couplable to the first memory and the second memory, configured to parse the instructions stored by the second memory into signals indicating the execution of an arithmetic operation, a logical operation, or both to be performed by computational circuitry couplable to the processing device, wherein the computational circuitry is configured to: receive the signal from the processing device; retrieve a specific one of the operands stored by the first memory based at least in part on the received signal; and perform the arithmetic operation, the logical operation, or both using the retrieved operand based at least in part on the received signal.

[0007] According to another aspect of the present application, a system for accelerating circuitry for POSIT operations is provided. The system includes: a host configured to: transfer a data vector formatted in a universal digital or POSIT format to a memory of a memory device; parse a higher-level instruction into lower-level instructions; and write a corresponding one of the lower-level instructions to a corresponding buffer of a corresponding computational circuit; and the memory device capable of being coupled to the host via a Peripheral Component Interconnect Express (PCIe) interface, wherein the memory device includes: the memory configured to store the data vector received from the host; and a plurality of computational circuits couplable to the memory, wherein each computational circuit is configured to: receive a corresponding lower-level instruction from the host; and perform an arithmetic operation, a logical operation, or both according to the corresponding lower-level instruction.

[0008] According to another aspect of the present application, a device for accelerating circuitry for posit operations is provided. The device includes: a direct memory access (DMA) block implemented in a field programmable gate array (FPGA), wherein the DMA block includes: a first first-in-first-out (FIFO) input buffer configured to receive a first bit string; a second FIFO input buffer (1046) configured to receive a second bit string; and a circuit system that can be coupled to the first FIFO buffer and the second FIFO buffer, wherein the circuit system is configured to unpack the first bit string and the second bit string; a first circuit system implemented in the FPGA and coupled to the DMA block, and configured to convert a data value formatted in a floating point format to a data value formatted in the unum or posit format. a second circuit system implemented in the FPGA and coupleable to the DMA block and configured to convert the data value formatted in the unum or posit format to a data value formatted in a floating-point format; a third circuit system implemented in the FPGA and coupleable to the DMA block and configured to perform an arithmetic operation, a logical operation, or both using the first bit string and the second bit string; a fourth circuit system implemented in the FPGA and coupleable to the first block, the second block, and the third block and configured to pack results of the arithmetic operation, the logical operation, or both; and a FIFO output buffer coupleable to the fourth circuit system.

[0009] According to another aspect of the present application, a method for accelerating a circuit system for a POSIT operation is provided, the method comprising: pre-calculating results of a plurality of arithmetic operations, a plurality of logical operations, or both using a plurality of operands formatted in a universal number (UNUM) or POSIT format; compiling the pre-calculated results into a lookup table (LUT); receiving an instruction from a processing device to perform a particular operation of the plurality of arithmetic operations or the plurality of logical operations using a particular set of the plurality of operands; and identifying, via the LUT, one of the pre-calculated results that corresponds to the particular operation and the particular set of the plurality of operands. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is another functional block diagram in the form of a computing system including an apparatus including a host and a memory device according to several embodiments of the present disclosure.

[0011] Figure 2A is a functional block diagram of a computing system including an apparatus including a host and a memory device according to several embodiments of the present disclosure.

[0012] Figure 2B is another functional block diagram in the form of a computing system including an apparatus including a host and a memory device according to several embodiments of the present disclosure.

[0013] Figure 3 is an instance of n-bit posit with es exponent bits.

[0014] Figure 4A is an example of a positive value for a 3-bit posit.

[0015] Figure 4B is an instance of the posit construct using two exponent bits.

[0016] Figure 5 is another functional block diagram in the form of a computing system including an apparatus including a host and a memory device according to several embodiments of the present disclosure.

[0017] Figure 6 is another functional block diagram in the form of a computing system including a device including a host and memory resources, according to several embodiments of the present disclosure.

[0018] Figure 7 is another functional block diagram in the form of a computing system including a device including a host and memory resources, according to several embodiments of the present disclosure.

[0019] Figure 8 is another functional block diagram in the form of a computing system including a device including a host and memory resources, according to several embodiments of the present disclosure.

[0020] Figure 9 is another functional block diagram in the form of a computing system including a device including a host and memory resources, according to several embodiments of the present disclosure.

[0021] Figure 10 is a functional block diagram of acceleration circuitry in accordance with several embodiments of the present disclosure.

[0022] Figure 11 is another functional block diagram in the form of a memory device according to several embodiments of the present disclosure.

[0023] Figure 12 is a flowchart illustrating an example method of an acceleration circuit system for POSIT operations according to several embodiments of the present disclosure.

[0024] Figure 13 is another flow chart illustrating an example method for an acceleration circuit system for POSIT operations according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] Systems, devices, and methods related to acceleration circuitry for POSIT operations are described. Universal numeric (UNUM) bit strings, such as POSIT bit string operands and POSIT bit strings representing results of arithmetic and / or logical operations performed using the POSIT bit string operands, may be stored in a memory resource, such as a memory array or other memory resource. Circuitry deployed in a memory device may access the memory resource to retrieve the UNUM bit string operands and / or results of arithmetic and / or logical operations performed using the UNUM bit string operands from the memory resource. For example, arithmetic and / or logical operations may be performed using a first UNUM bit string stored in the memory resource and a second UNUM bit string stored in the memory resource. The results of the arithmetic and / or logical operations may be stored in the memory resource and subsequently retrieved.

[0026] Computing systems can perform a wide range of operations that can include various calculations, which can require varying degrees of accuracy. However, computing systems have a limited amount of memory in which to store operands on which calculations are performed. To facilitate performing operations on operands stored by the computing system within the constraints imposed by limited memory resources, in some approaches, operands can be stored in a particular format. For simplicity, one such format is referred to as a "floating point" format or "float" (e.g., the IEEE 754 floating point format).

[0027] According to the floating-point standard, a bit string (e.g., a bit string that can represent a number), such as a binary number string, is represented in terms of three sets of integers or bits: one set of bits is called the "radix," one set of bits is called the "exponent," and one set of bits is called the "mantissa" (or significand). The sets of integers or bits define the format in which the binary number string is stored and, for simplicity, may be referred to herein as the "numeric format" or "format." For example, the three sets of integers (e.g., radix, exponent, and mantissa) that define the bits of a floating-point bit string described above may be referred to as the format (e.g., the first format). As described in more detail below, a posit bit string may include four sets of integers or bits (e.g., sign, scheme, exponent, and mantissa), which may also be referred to as the "numeric format" or "format" (e.g., the second format). Additionally, according to the floating-point standard, two infinite values ​​(e.g., +∞ and -∞) and / or two types of "not-a-number (NaN)" (quiet NaN and signaling NaN) may be included in the bit string.

[0028] Floating-point standards have been used in computing systems for several years and define arithmetic formats, interchange formats, rounding rules, operations, and exception handling for calculations performed by many computing systems. Arithmetic formats may include binary and / or decimal floating-point data, which may include finite numbers, no-number values, and / or special NaN values. Interchange formats may include encodings (e.g., bit strings) that can be used to exchange floating-point data. Rounding rules may include a set of properties that can be satisfied when rounding numbers during arithmetic operations and / or conversion operations. Floating-point operations may include arithmetic operations and / or other computational operations, such as trigonometric functions. Exception handling may include indications of exceptional conditions, such as division by zero, overflow, etc.

[0029] The alternative format of floating point is called "universal number" (UNUM) format. There are several forms of UNUM formats that can be called "posit" and / or "significant number (valid)", Type I UNUM, Type II UNUM and Type III UNUM. Type I UNUM is a superset of the IEEE 754 standard floating point format that uses "ubit" to indicate whether a real number is an accurate floating point number or whether it is between adjacent floating point numbers. The sign, exponent and fraction bits in Type I UNUM obtain their definitions from the IEEE 754 floating point format, but the length of the exponent and fraction fields of Type I UNUM can be significantly changed from a single bit to a maximum user-definable length. By obtaining sign, exponent and mantissa bits from the IEEE 754 standard floating point format, Type I UNUM can be expressed as similar to a floating point number, but the variable bit length displayed in the exponent and fraction bits of Type I UNUM may need additional management compared to a floating point number.

[0030] Type II unums are generally incompatible with floating point numbers, which allow for clean mathematical designs based on projected real numbers. A type II unum can contain n bits and can be described in terms of a "u-lattice" where the quadrants of a circular projection are filled with 2 n-3 -1 real number. The values ​​of a Type II unum can be reflected around an axis that bisects the circular projection so that positive values ​​are located in the upper right quadrant of the circular projection, while their negative counterparts are located in the upper left quadrant of the circular projection. The lower half of the circular projection representing a Type II unum can contain the reciprocal of the value located in the upper half of the circular projection. Type II unums typically rely on a lookup table (LUT) for most operations. For example, in some cases, the size of the lookup table may limit the effectiveness of a Type II unum. However, Type II unums can provide improved computational functionality compared to floating-point numbers based on some conditions.

[0031] The type III unum format is referred to herein as the "posit format" or, for simplicity, as "posit." Compared to floating-point bit strings, posit can, under certain conditions, allow for a wider dynamic range and higher accuracy (e.g., precision) than floating-point numbers with the same bit width. This can allow operations performed by a computing system to be performed at a higher rate (e.g., faster) than when using floating-point numbers when using posit, which in turn can improve the performance of the computing system by, for example, reducing the number of clock cycles used when performing operations and / or the power consumed when performing such operations. In addition, using posit in a computing system can achieve higher accuracy and / or precision than floating-point numbers, which can further improve the functionality of the computing system compared to certain methods (e.g., methods that rely on floating-point format bit strings).

[0032] posit can vary greatly in precision and accuracy based on the total bit quantity and / or the amount of integer sets or bit sets contained in posit. In addition, posit can produce a wide dynamic range. Depending on certain conditions, the accuracy, precision and / or dynamic range of posit can be greater than the accuracy, precision and / or dynamic range of floating or other digital formats, as described in more detail herein. The variable accuracy, precision and / or dynamic range of posit can be manipulated, for example, based on the application in which posit will be used. In addition, posit can reduce or eliminate overflow, underflow, NaN and / or other extreme cases associated with floating and other digital formats. In addition, compared with floating point numbers or other digital formats, using posit can allow the use of fewer bits to represent numerical values ​​(e.g., numbers).

[0033] In some embodiments, these features can allow for highly reconfigurable POSITs, which can provide improved application performance compared to approaches that rely on floating point or other numeric formats. Additionally, these features of POSITs can provide improved performance in machine learning applications compared to floating point or other numeric formats. For example, in machine learning applications where computational performance is crucial, POSITs can be used to train networks (e.g., neural networks) with the same or higher accuracy and / or precision as floating point or other numeric formats but using fewer bits than floating point or other numeric formats. Additionally, POSITs with fewer bits (e.g., smaller bit widths) than floating point or other numeric formats can be used to implement inference operations in machine learning scenarios. By achieving the same or enhanced results using fewer bits than floating point or other numeric formats, the use of POSITs can reduce the amount of time required to perform operations and / or reduce the amount of memory space required in applications, which can improve the overall functionality of computing systems in which POSITs are employed.

[0034] Embodiments herein are directed to an acceleration circuit system for POSIT operations. In some embodiments, the acceleration circuit system may be implemented on a field programmable gate array (FPGA). Control logic may be coupled to the acceleration circuit system or be a component of the acceleration circuit system. A Peripheral Component Interconnect Express (PCIe) interface may be coupled to the acceleration circuit system to communicate with a host. For example, the PCIe interface may be used to transfer data (e.g., a data array) to a local memory coupled to the acceleration circuit system. The local memory may be internal to a memory device containing the acceleration circuit system, external to a memory device containing the acceleration circuit system, or both. Commands from the host may be transferred to the acceleration circuit system via the PCIe interface. For example, commands from the host may control the processing of the data array (e.g., performing an arithmetic operation, a logical operation, or both). Results from processing the data array may be written to the local memory. Commands from the host may be interpreted by a processing device coupled to the acceleration circuit system. The processing device may be configured to control the retrieval of operands formatted, for example, in UNUM or POSIT format, and the transfer of results via a direct memory access (DMA) controller. The processing device may be configured to control processing of data by the acceleration circuitry. In some embodiments, the processing device may be a cache-coherent reduced instruction set computing device, such as a reduced instruction set computer (RISC) RISC-V device.

[0035] Commands from the host may be placed in a queue (e.g., a command buffer described further herein) of the processing device. Non-limiting examples of commands from the host to the processing device may include transferring a block of data from the host's memory to local memory, or vice versa, and processing the data in the local memory. The processing device may be configured to process data "in place."

[0036] In some embodiments, a first operand formatted in a unum or posit format may be received by a first buffer residing on the acceleration circuit system. As used herein, the term "residing on" refers to something being physically located on a particular component. For example, a processing unit "residing on" a memory device refers to a situation where the processing unit is physically located on the memory device. The term "residing on" may be used interchangeably herein with other terms such as "deployed on" or "located on." A second operand formatted in a unum or posit format may be received by a second buffer residing on the acceleration circuit system. An arithmetic operation, a logical operation, or both may be performed using the processing circuit system residing on the acceleration circuit system using the first operand and the second operand. The results of the arithmetic operation, the logical operation, or both may be transmitted by a third buffer residing on the acceleration circuit system.

[0037] In some embodiments, the acceleration circuitry may include a DMA controller. The acceleration circuitry may include a first buffer that may be coupled to the DMA controller and configured to store a first operand formatted in a unum or posit format. The acceleration circuitry may include a second buffer that may be coupled to the DMA controller and configured to store a second operand formatted in a unum or posit format. The acceleration circuitry may include processing circuitry that may be coupled to the first buffer and the second buffer. The processing circuitry may be configured to perform an arithmetic operation, a logical operation, or both using the first operand and the second operand. The acceleration circuitry may include a third buffer that may be coupled to the DMA controller and the computation circuitry. The third buffer may be configured to store a result of the arithmetic operation, the logical operation, or both.

[0038] In the following detailed description of the present disclosure, reference is made to the accompanying drawings which form a part hereof and in which is shown by way of illustration the manner in which one or more embodiments of the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one skilled in the art to practice the embodiments of the present disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and structural changes may be made without departing from the scope of the present disclosure.

[0039] As used herein, designators such as "X," "Y," "N," "J," "R," etc., specifically with respect to a figure numeral in the drawings, indicate that a plurality of the particular feature so designated may be included. It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" may include both singular and plural referents, unless the context clearly dictates otherwise. Additionally, "plurality," "at least one," and "one or more" (e.g., a plurality of memory banks) may refer to one or more memory banks, while "plurality" is intended to refer to more than one such thing. Furthermore, the words "may" and "can" are used throughout this application in a permissive sense (i.e., having the potential to, being able to), rather than in a mandatory sense (i.e., must).

[0040] The term "comprising" and its derivatives mean "including but not limited to". Depending on the context, the term "coupled" or "coupling" means physically connecting or accessing and moving (transmitting) commands and / or data, directly or indirectly. Depending on the context, the terms "bit string", "data" and "data value" are used interchangeably herein and may have the same meaning. The term "residing on" refers to the condition that one or more components are physically disposed on one or more different components. In addition, the terms "data", "plurality of bits" and "bit string" are used interchangeably herein, and the term "number" may refer to a bit string or a plurality of bits, depending on the context.

[0041] The figures herein follow a numbering convention in which the first one or more digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, 120 may refer to Figure 1 2 , and similar elements may be labeled 220 in FIG. 2 . A single reference numeral may generally be used herein to refer to a group or multiple similar elements or components. For example, multiple reference elements 433-1, 433-2, ..., 433-N may be collectively referred to as 433. As will be appreciated, elements shown in various embodiments herein may be added, exchanged, and / or eliminated to provide several additional embodiments of the present disclosure. In addition, the proportions and / or relative scales of the elements provided in the figures are intended to illustrate certain embodiments of the present disclosure and should not be construed as limiting.

[0042] Figure 1is another functional block diagram of a computing system in the form of an apparatus 100 including a host 102 and a memory device 104 according to several embodiments of the present disclosure. As used herein, "apparatus" may refer to, but is not limited to, any of a variety of structures or combinations of structures, such as a circuit or circuit system, one or more dies, one or more modules, one or more devices, or one or more systems. The acceleration circuit system 120 may be similar to Figure 2A and 2B Similarly, the host 102 may be similar to the acceleration circuit system 220 described in Figure 2A and 2B The host 202 described in FIG. 1 , the memory device 104 may be similar to Figure 2A and 2B , and the memory array 130 may be similar to the memory device 204 described in Figure 2A and 2B Each of the components (eg, host 102, acceleration circuitry 120, logic circuitry 122, memory resources 124, and / or memory array 130, etc.) may be individually referred to herein as a "device."

[0043] Host 102 may be communicatively coupled to memory device 104 via one or more channels 103, 105. Channels 103, 105 may be interfaces or other physical connections that allow bit strings, data, and / or commands to be transferred between host 102 and memory device 105. For example, a command to initiate an operation (e.g., an operation to convert a bit string in floating-point format to a bit string in posit format, and subsequent arithmetic and / or logical operations on the bit string in posit format) to be executed by acceleration circuitry 120 may be transmitted from the host via channels 103, 105. It should be noted that in some examples, acceleration circuitry 120 may execute an operation in response to a start command transmitted from host 102 via one or more of channels 103, 105 without an intervening command from host 102. That is, once acceleration circuitry 120 has received a command from host 102 to initiate execution of an operation, the operation may be executed by acceleration circuitry 120 without additional commands from host 102.

[0044] In some embodiments, a bit string (e.g., a posit bit string) can be generated and / or stored in memory array 130 without interfering with host 102. For example, a bit string can be generated and / or stored in memory array 130 without receiving multiple commands from host 102. In other words, in some embodiments, host 102 can send a single command to a memory device to request that an operation be performed using one or more bit strings. In response to receiving a command requesting the execution of an operation, memory device 104 (e.g., controller 110, acceleration circuitry 120, or other components of memory device 104) can execute the operation and / or retrieve the stored result of the operation without additional commands from host 102. This can reduce traffic across channels 103 / 105, which can increase the performance of computing devices associated with host 102 and / or memory device 104.

[0045] like Figure 1 As shown, the memory device 104 may include a register access component 106, a high-speed interface (HSI) 108, a controller 110, one or more extended row address (XRA) components 112, main memory input / output (I / O) circuitry 114, row address strobe (RAS) / column address strobe (CAS) chain control circuitry 116, a RAS / CAS chain component 118, an acceleration circuitry 120, and a memory array 130. Figure 1 As shown, the speed-up circuitry 120 is located in a physically distinct area of ​​the memory device 104 from the memory array 130. That is, in some embodiments, the speed-up circuitry 120 is located in a peripheral location of the memory array 130.

[0046] The register access component 106 can facilitate the transfer and retrieval of data from the host 102 to the memory device 104 and from the memory device 104 to the host 102. For example, the register access component 106 can store addresses (or facilitate the lookup of addresses), such as memory addresses, corresponding to bit strings to be transferred from the memory device 104 to the host 102 or from the host 102 to the memory device 104. In some embodiments, the register access component 106 can facilitate the transfer and retrieval of bit strings to be operated on by the acceleration circuitry 120, and / or the register access component 106 can facilitate the transfer and retrieval of bit strings that have already been operated on by the acceleration circuitry 120 for transfer to the host 102.

[0047] The HSI 108 may provide an interface between the host 102 and the memory device 104 for bit strings, commands, and / or data across the channel 105. The HSI 108 may be a double data rate (DDR) interface, such as a DDR3, DDR4, DDR5, etc. However, embodiments are not limited to a DDR interface, and the HSI 108 may be a quad data rate (QDR) interface, a peripheral component interconnect (PCI) interface (e.g., a peripheral component interconnect express (PCIe)) interface, or other suitable interface for transferring bit strings, commands, and / or data between the host 102 and the memory device 104.

[0048] Controller 110 may be responsible for executing instructions from host 102 and accessing acceleration circuitry 120 and / or memory array 130. Controller 110 may be a state machine, a sequencer, or some other type of controller. Controller 110 may receive commands from host 102 (e.g., via HSI 108) and, based on the received commands, control the operations of acceleration circuitry 120 and / or memory array 130. In some embodiments, controller 110 may receive commands from host 102 to cause an operation to be performed using acceleration circuitry 120. In response to receiving such commands, controller 110 may instruct acceleration circuitry 120 to begin executing the operation.

[0049] In a non-limiting example, the controller 110 may instruct the acceleration circuit system 120 to perform an operation to retrieve one or more bit strings stored in the memory array 130 and / or a resultant bit string stored in the memory array 130 that represents a result of an operation performed between the one or more bit strings. For example, the controller may receive a command from the host 104 requesting the execution of an operation between the one or more bit strings and send the command to the acceleration circuit system 120 to execute the operation. The acceleration circuit system 120 (e.g., a state machine resident on the acceleration circuit system 120, such as the state machine described herein) may be configured to execute an operation between the one or more bit strings. Figure 2B The state machine 223 (described in detail in FIG. 1 ) may determine whether the result of the requested operation is stored in the memory array 130, determine the address in the memory array 130 where the result of the requested operation is stored, and / or retrieve the result of the requested operation from the memory array 130. The acceleration circuitry 120 and / or the controller 110 may then cause the result of the requested operation to be transferred to the host 102 or other circuitry external to the memory array 130.

[0050] In some embodiments, the controller 110 may be a global processing controller and may provide power management functions to the memory device 104. The power management functions may include controlling the power consumed by the memory device 104 and / or the memory array 130. For example, the controller 110 may control the power provided to the various banks of the memory array 130 to control which banks of the memory array 130 are operated at different times during operation of the memory device 104. This may include shutting down certain banks of the memory array 130 while providing power to other banks of the memory array 130 to optimize the power consumption of the memory device 130. In some embodiments, the controller 110 controlling the power consumption of the memory device 104 may include controlling power to various cores of the memory device, such as to the acceleration circuitry 120.

[0051] The XRA component 112 is intended to provide additional functionality (e.g., peripheral amplifiers) that senses (e.g., reads, stores, caches) data values ​​of memory cells in the array and is distinct from the memory array 130. The XRA component 112 may include latches and / or registers. For example, additional latches may be included in "XRA component 112." The latches of the XRA component 112 may be located on the periphery of the memory array 130 of the memory device 104 (e.g., on the periphery of one or more banks of memory cells).

[0052] Main memory input / output (I / O) circuitry 114 may facilitate the transfer of bit strings, data, and / or commands to and from memory array 130. For example, main memory I / O circuitry 114 may facilitate the transfer of bit strings, data, and / or commands from host 102 and / or acceleration circuitry 120 to and from memory array 130. In some embodiments, main memory I / O circuitry 114 may include one or more direct memory access (DMA) components that may transfer bit strings, blocks of data, etc., from acceleration circuitry 120 to memory array 130 (and vice versa).

[0053] In some embodiments, main memory I / O circuitry 114 may facilitate transferring one or more bit strings from memory array 130 to acceleration circuitry 120 so that acceleration circuitry 120 can perform operations on the bit strings. Similarly, main memory I / O circuitry 114 may facilitate transferring bit strings on which one or more operations have been performed by acceleration circuitry 120 to memory array 130. As described in more detail herein, the operations may include operations to convert a bit string formatted according to a floating-point standard to a bit string formatted as posit (and vice versa), arithmetic operations performed on a bit string formatted as posit, logical operations performed on a bit string formatted as posit, and the like.

[0054] As described above, posit bit strings (e.g., data) may be stored and / or retrieved from memory array 130. In some embodiments, main memory I / O circuitry 114 may facilitate the storage and / or retrieval of posit bit strings to and / or from memory array 130. For example, main memory I / O circuitry 114 may be enabled to transfer a posit bit string to memory array 130 to be stored, and / or main memory I / O circuitry 114 may facilitate the retrieval of a posit bit string (e.g., a posit bit string representing an operation performed between one or more posit bit string operands) from memory array 130 in response to a command, for example, from controller 110 and / or acceleration circuitry 120.

[0055] The row address strobe (RAS) / column address strobe (CAS) chain control circuitry 116 and the RAS / CAS chain component 118 may be used in conjunction with the memory array 130 to latch row addresses and / or column addresses to initiate memory cycles. In some embodiments, the RAS / CAS chain control circuitry 116 and / or the RAS / CAS chain component 118 may resolve row addresses and / or column addresses of the memory array 130 at which read and write operations associated with the memory array 130 will begin or end. For example, after completing an operation using the acceleration circuitry 120, the RAS / CAS chain control circuitry 116 and / or the RAS / CAS chain component 118 may latch and / or resolve a specific location in the memory array 130 at which the bit string operated on by the acceleration circuitry 120 will be stored. Similarly, the RAS / CAS chain control circuitry 116 and / or the RAS / CAS chain component 118 may latch and / or resolve a specific location in the memory array 130 from which the bit string is to be transferred to the acceleration circuitry 120 before the acceleration circuitry 120 performs an operation on the bit string.

[0056] In some embodiments, RAS / CAS chain control circuitry 116 and RAS / CAS chain component 118 may be used in conjunction with memory array 130 to latch a row address and / or a column address to initiate an operation to retrieve one or more bit strings from memory array 130. For example, in response to acceleration circuitry 120 (e.g., Figure 2B In the embodiment of the present invention, a state machine 223 (described in detail and resident on the acceleration circuit system 220) requests a bit string stored at a specific address of the memory array 130, and the RAS / CAS chain control circuit system 116 and the RAS / CAS chain component 118 can latch the row address and / or column address corresponding to the bit string to facilitate retrieval of the requested bit string from the memory array 130.

[0057] If combined Figure 2A and 2B And the following combined Figure 5 Described in more detail, the acceleration circuit system 120 may be configured to receive a bit string having a first format (e.g., a bit string in a floating point format), convert the bit string to a second format (e.g., convert the bit string to a common digital format such as a posit format), and / or cause operations such as arithmetic and / or logical operations to be performed using the bit string having the second format. In some embodiments, the acceleration circuit system 120 may cause the bit string having the second format and / or the bit string containing the result of the arithmetic and / or logical operation to be stored in a data structure of the memory array 130 (e.g., herein in Figure 6 In the data structure 634 described in .

[0058] The acceleration circuitry 120 may include logic circuitry (e.g., Figure 2A and 2B 2) and memory resources (e.g., Figure 2A and 2B The bit string may be received by acceleration circuitry 120 from, for example, host 102 and / or memory array 130, and stored by acceleration circuitry 120 in, for example, a memory resource of acceleration circuitry 120. Acceleration circuitry (e.g., logic circuitry of acceleration circuitry 120) may perform operations on the bit string (or cause operations to be performed on it), as described herein in conjunction with Figure 5 Describe in more detail.

[0059] If combined Figure 3 and 4AAs described in more detail in FIG4B , POSIT can provide improved accuracy and may require less storage space (e.g., may contain a smaller number of bits) than a corresponding bit string represented in a floating-point format. Thus, by using acceleration circuitry 120 to convert a floating-point bit string into a POSIT bit string, the performance of memory device 102 can be improved compared to approaches that utilize only floating-point bit strings because operations can be performed more quickly on the POSIT bit string (e.g., because the data in the POSIT format is smaller and therefore requires less time and / or processing resources to perform the operation) and because less memory space is required in memory device 102 to store the bit string in the POSIT format, this can free up additional space in memory device 102 for other bit strings, data, and / or other operations to be performed. Additionally, by storing the bit string in a data structure in memory array 130 and subsequently retrieving it, the bit string can be quickly accessed for use in other operations and / or by, for example, an application running on host 102 in a more efficient manner than approaches that require performing arithmetic and / or logical operations each time the result of such an operation is requested. Furthermore, performing arithmetic and / or logical operations may require fewer clock cycles than some approaches because the results of arithmetic and / or logical operations between bit string operands may be retrieved from memory array 130, in contrast to approaches that perform operations between bit string operands whenever the results of such operations are requested.

[0060] The acceleration circuitry 120 may perform (or cause to be performed) arithmetic and / or logic operations on the resulting posit bit string. Arithmetic operations may include addition, subtraction, multiplication, division, fused multiply-add, multiply-accumulate, dot product unit, greater than or less than, absolute value (e.g., FABS()), fast Fourier transform, inverse fast Fourier transform, sigmoid function, convolution, square root, exponential and / or rectified linear unit (ReLu), as well as trigonometric operations such as sine, cosine, tangent, etc., while logic operations may include AND, OR, XOR, NOT, etc. As will be appreciated, the foregoing list of operations is not intended to be exhaustive, nor is it intended to be limiting, and the acceleration circuitry 120 may be configured to perform (or cause to be performed) other arithmetic and / or logic operations. As described herein, operands used in such operations (e.g., bit string operands) and / or results of such operations may be stored in memory array 130 and may subsequently be retrieved from memory array 130 in response to commands from acceleration circuitry 120.

[0061] In some embodiments, the acceleration circuitry 120 may perform the operations listed above in conjunction with the execution of one or more machine learning algorithms. For example, the acceleration circuitry 120 may perform operations associated with one or more neural networks. Neural networks may allow for the training of algorithms over time to determine output responses based on input signals. For example, over time, a neural network may essentially learn to better maximize the chances of achieving a specific objective. This can be advantageous in machine learning applications because the neural network can be trained with new data over time to better maximize the chances of achieving a specific objective. In many cases, a neural network can be trained over time to improve the performance of a specific task and / or a specific goal.

[0062] However, in some approaches, machine learning (e.g., neural network training) can be processing-intensive (e.g., can consume significant computer processing resources) and / or time-intensive (e.g., can require executing lengthy calculations that consume multiple cycles). In contrast, by using acceleration circuitry 120 to perform such operations, for example, by performing such operations on bit strings that have been converted to POSIT format by acceleration circuitry 120, the amount of processing resources and / or time consumed in performing the operations can be reduced compared to approaches that perform such operations using bit strings in floating-point format. Furthermore, by storing the results of operations on the bit strings converted to POSIT format in memory array 130 for subsequent retrieval, the amount of processing resources and / or time consumed in performing the operations can be even further reduced for subsequent requests for the results, since the operations have already been performed.

[0063] For example, the memory array 130 may be a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash array, and / or a NOR flash array, but the embodiments are not limited to these specific examples. The memory array 130 may serve as a Figure 1 In some embodiments, the memory array 130 may be configured to store bit strings operated on by the acceleration circuitry 120 (eg, resulting bit strings) and / or store bit strings to be transferred to the acceleration circuitry 120.

[0064] In some embodiments, memory array 130 is configured to store a plurality of bit strings to be used as operands in the execution of an arithmetic operation, a logical operation, or both. A controller 110 coupled to memory array 130 may be configured to receive a request to perform an arithmetic operation, a logical operation, or both using one or more bit strings. The request may be received from circuitry external to memory device 104 (e.g., host 102). Controller 110 may be configured to determine the bit size of the one or more bit strings to be used in the execution of the arithmetic operation, the logical operation, or both, and, in response to determining that the execution of the arithmetic operation, the logical operation, or both requires the bit size of the one or more bit strings to be less than the predetermined bit size, cause the arithmetic operation, the logical operation, or both to be performed using a bit string from the plurality of bit strings stored in memory array 130.

[0065] In some embodiments, the controller 110, coupled to the memory array 130 and the acceleration circuitry 120, may be configured to, in response to determining that execution of an arithmetic operation, a logical operation, or both requires one or more bit strings with a bit size less than a predetermined bit size, send a command to the acceleration circuitry to cause the acceleration circuitry to perform the arithmetic operation, the logical operation, or both. In some embodiments, the predetermined bit size may be 16 bits or less; however, embodiments are not limited to a particular bit size.

[0066] As described in more detail herein, the acceleration circuitry 120 may be configured to convert a bit string representing a result of an arithmetic operation or a logical operation, or both, into a format that is different from the format of the plurality of bit strings stored in the memory array 130. For example, the plurality of bit strings to be used as operands in performing the arithmetic operation or the logical operation, or both, are stored in a data structure in the memory array 130.

[0067] Figure 2A is a functional block diagram of a computing system 200 in the form of an apparatus including a host 202 and a memory device 204 according to several embodiments of the present disclosure. The memory device 204 may include one or more memory modules (e.g., a single in-line memory module, a dual in-line memory module, etc.). The memory device 204 may include volatile memory and / or non-volatile memory. In several embodiments, the memory device 204 may include a multi-chip device. The multi-chip device may include several different memory types and / or memory modules. For example, the memory system may include non-volatile or volatile memory on any type of module. In addition, each of the components (e.g., the host 202, the acceleration circuit system 220, the logic circuit system 222, the memory resources 224 and / or the memory array 230) may be referred to individually herein as a "device." Although Figure 2A Not explicitly shown in , the memory device 204 can be coupled to one or more media devices, such as a solid state drive, a flash media device, or the like.

[0068] Memory device 204 may provide main memory for computing system 200 or may be used as additional memory or storage throughout computing system 200. Memory device 204 may include one or more memory arrays 230 (e.g., an array of memory cells), which may include volatile and / or non-volatile memory cells. For example, memory array 230 may be a flash array having a NAND architecture. Embodiments are not limited to a particular type of memory device. For example, memory device 204 may include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, flash memory, and the like.

[0069] In embodiments where memory device 204 includes nonvolatile memory, memory device 204 may include a flash memory device, such as a NAND or NOR flash memory device. However, embodiments are not limited thereto, and memory device 204 may include other nonvolatile memory devices, such as nonvolatile random access memory devices (e.g., NVRAM, ReRAM, FeRAM, MRAM, PCM), "emerging" memory devices such as variable resistance (e.g., 3-D cross-point (3D XP) memory devices), memory devices including self-select memory (SSM) cell arrays, or the like, or combinations thereof. A variable resistance memory device may combine a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. Additionally, compared to many flash-based memories, variable resistance nonvolatile memories may perform write-in-place operations, where nonvolatile memory cells can be programmed without first erasing the nonvolatile memory cells. Compared to flash-based and variable resistance memories, self-select memory cells may include memory cells having a single chalcogenide material that serves as both the switch and the storage element of the memory cell.

[0070] like Figure 2A As illustrated in , host 202 may be coupled to memory device 204. In several embodiments, memory device 204 may be coupled to host 202 via one or more channels (e.g., channel 203). Figure 2A 2 , memory device 204 is coupled to host 202 via channel 203, and acceleration circuitry 220 of memory device 204 is coupled to memory array 230 via channel 207. Host 202 may be a host system, such as a personal laptop computer, desktop computer, digital camera, smartphone, memory card reader, and / or IoT-enabled device, among other types of hosts, and may include a memory access device, such as a processor (or processing device). Those skilled in the art will appreciate that a "processor" may be one or more processors, such as a parallel processing system, multiple coprocessors, and the like.

[0071] Host 202 may include a system motherboard and / or backplane, and may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry). System 200 may include separate integrated circuits, or host 202, memory device 204, and memory array 230 may be on the same integrated circuit. For example, system 200 may be a server system and / or a high performance computing (HPC) system and / or a portion thereof. Although Figure 2A The example shown in illustrates a system having a von Neumann architecture, but embodiments of the present disclosure may be implemented in a non-von Neumann architecture, which may not include one or more components typically associated with a von Neumann architecture (e.g., a central processing unit (CPU), an arithmetic logic unit (ALU), etc.).

[0072] Memory device 204 may include acceleration circuitry 220, which may include logic circuitry 222 and memory resources 224. Logic circuitry 222 may be provided in the form of an integrated circuit, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a system on a chip, or other combination of hardware and / or circuitry configured to perform the operations described in more detail herein. For example, logic circuitry 222 may be configured to receive one or more bit strings in a first format (e.g., a plurality of bits in a floating point format), convert the one or more bit strings into a second format (e.g., encode a plurality of bits in a posit format), and / or cause operations (e.g., arithmetic and / or logical operations) to be performed using the one or more bit strings in the second format. As used herein, a bit string in the second format (e.g., a bit string in a posit format) includes at least one bit called a "sign," a set of bits called a "scheme," a set of bits called an "exponent," and a set of bits called a "mantissa" (or significant digit). In conjunction with Figure 3 and 4A 4B describe examples of signs, schemes, exponent and mantissa bit sets in more detail.

[0073] The operations may include conversion operations to convert a floating-point bit string (e.g., a floating-point number) into a bit string in POSIT format, and vice versa. Once the floating-point bit string is converted into a bit string in POSIT format, the logic circuitry 222 may be configured to perform (or cause to be performed) arithmetic and / or logical operations using the POSIT bit string. Arithmetic operations may include addition, subtraction, multiplication, division, fused multiply-add, multiply-accumulate, dot product unit, greater than or less than, absolute value (e.g., FABS()), fast Fourier transform, inverse fast Fourier transform, sigmoid function, convolution, square root, exponential and / or rectified linear unit (ReLu), as well as trigonometric operations such as sine, cosine, tangent, etc., while logical operations may include logical operations such as AND, OR, XOR, NOT, etc. As will be appreciated, the foregoing list of operations is not intended to be exhaustive, nor is the foregoing list of operations intended to be limiting, and logic circuitry 222 may be configured to perform (or cause to be performed) other arithmetic and / or logic operations.

[0074] Logic circuitry 222 may include an ALU. The ALU may include circuitry (e.g., hardware, logic, one or more processing devices, etc.) to perform operations such as those described above (e.g., arithmetic operations, logical operations, bitwise operations, etc.) on integer binary bit strings (e.g., bit strings in posit format).

[0075] Acceleration circuitry 220 may further include memory resources 224 that may be communicatively coupled to logic circuitry 222. Memory resources 224 may include volatile memory resources, nonvolatile memory resources, or a combination of volatile and nonvolatile memory resources. In some embodiments, the memory resources may be random access memory (RAM), such as static random access memory (SRAM). However, embodiments are not limited thereto, and the memory resources may be a cache, one or more registers, NVRAM, ReRAM, FeRAM, MRAM, PCM), "emerging" memory devices such as the variable resistance memory devices described above, or a combination thereof.

[0076] The acceleration circuitry 220 may be communicatively coupled to a memory array 230 via one or more channels 207. The memory array 230 may be, for example, a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash array, and / or a NOR flash array. The array 230 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as data lines or digit lines). Although in Figure 2AA single array 230 is shown in FIG, but embodiments are not limited thereto. For example, the memory device 204 may include multiple memory arrays 230 (eg, multiple banks of DRAM cells, NAND flash cells, etc.).

[0077] Figure 2A 2. Embodiments of the present disclosure may include additional circuitry not described to avoid obscuring the present disclosure. For example, memory device 204 may include address circuitry to latch address signals provided on I / O connections via I / O circuitry. The address signals may be received and decoded by row and column decoders to access memory device 204 and / or memory array 230. Those skilled in the art will appreciate that the number of address input connections may depend on the density and architecture of memory device 204 and / or memory array 230.

[0078] Figure 2B 2 is another functional block diagram of a computing system in the form of an apparatus 200 including a host 202 and a memory device 204 according to several embodiments of the present disclosure. Figure 2B , apparatus 200 may include a host 202, which may be communicatively coupled to a memory device 204 via a communication path 203. Memory device 204 may include acceleration circuitry 220, which may include a state machine 223 and, optionally, memory resources 224. Acceleration circuitry 220 may be communicatively coupled to a memory array 230 via a communication path 207. Each of the components (e.g., host 202, acceleration circuitry 220, state machine 223, memory resources 224, and / or memory array 230) may be individually referred to herein as a "device."

[0079] exist Figure 2B In the embodiment shown in , where logic circuitry 222 includes a state machine 223, state machine 223 may be configured to execute a specified set of instructions to, for example, write, read, copy, and / or erase a bit string (e.g., data) stored in memory array 230. For example, as described in more detail herein, state machine 223 may execute instructions to read data from one or more rows and / or columns of memory array 230 to retrieve data stored in memory array 230. As described in conjunction with Figure 1 Describing in more detail, the data may include, among other things, one or more posit bit string operands and / or one or more operation (eg, arithmetic and / or logical operation) results.

[0080] By utilizing a state machine 223 configured to execute a specified set of instructions to write and / or retrieve posit bit strings from the memory array 230, improved performance of the memory device 204 may be achieved compared to some approaches because the amount of time-consuming and / or computationally resource-intensive process of performing operations between bit strings stored in the memory array 230 may be reduced by storing the results of such operations in the memory array 230 and retrieving the results of the operations directly from the memory array 230.

[0081] In some embodiments, the state machine 223 may determine an address in the memory array 230 where the relevant posit bit string is stored. For example, the state machine 223 may determine a row and / or column address in the memory array 230 where one or more posit bit string operands are stored and / or a row and / or column address where a resulting posit bit string representing the execution of an arithmetic and / or logical operation between the one or more posit bit string operands is stored. The state machine 223 may then send a command or request to retrieve the posit bit string stored at the address in the memory array 230 and / or cause the retrieved posit bit string to be transferred to the host 202, a media device coupled to the memory device 202 (e.g., a solid-state drive, a flash memory device, etc.), or other circuitry external to the memory array 230.

[0082] Figure 3 is an instance of an n-bit universal number or "unum" with es exponent bits. Figure 3 In the example of , the n-bit unum is the posit bit string 331. Figure 3 As shown in FIG, n-bit posit 331 may include a set of sign bits (e.g., sign bits 333), a set of scheme bits (e.g., scheme bits 335), a set of exponent bits (e.g., exponent bits 337), and a set of mantissa bits (e.g., mantissa bits 339). Mantissa bits 339 may alternatively be referred to as a "fractional portion" or "fraction bits" and may represent a portion of a bit string after a decimal point (e.g., a number).

[0083] The sign bit 333 can be zero (0) for positive numbers and one (1) for negative numbers. The scheme bits 335 are described below in conjunction with Table 1, which shows (binary) bit strings and their associated numerical meanings k. In Table 1, the numerical meaning k is determined by the run length of the bit string. The letter x in the binary part of Table 1 indicates that the bit value is not relevant for the determination of the scheme because the (binary) bit string terminates in response to successive bit flips or when the end of the bit string is reached. For example, in the (binary) bit string 0010, the bit string terminates in response to a zero flipping to a one and then back to zero. Therefore, the last zero is not relevant for the scheme and all that is considered for the scheme is the leading identical bit and the first relative bit of the terminating bit string (if the bit string contains such a bit).

[0084] Binary 0000 0001 001X 01XX 10XX 110X 1110 1111 Value (k) -4 -3 -2 -1 0 1 2 3

[0085] Table 1

[0086] exist Figure 3 In the scheme bit 335r corresponds to the same bit in the bit string, and the scheme bit 335 Corresponds to the relative position of the termination bit string. For example, for the value k of -2 shown in Table 1, the scheme bit r corresponds to the first two leading zeros, and the scheme bit Corresponds to one. As mentioned above, the final bit corresponding to the number k represented by X in Table 1 is irrelevant to the scheme.

[0087] If m corresponds to the number of identical bits in the bit string, then if the bit is zero, k = -m. If the bit is one, then k = m - 1. This is illustrated in Table 1, where for example the (binary) bit string 10XX has a single one, and k = m - 1 = 1 - 1 = 0. Similarly, the (binary) bit string 0001 contains three zeros, so k = -m = -3. This scheme can indicate used k The scaling factor of Table 2 below shows several example values ​​of used.

[0088] es 0 1 2 3 4 used 2 <![CDATA[2 2 =4]]> <![CDATA[4 2 =16]]> <![CDATA[16 2 =256]]> <![CDATA[256 2 =65536]]>

[0089] Table 2

[0090] The exponent bits 337 correspond to the exponent e as an unsigned number. In contrast to floating point numbers, the exponent bits 337 described herein may not have a bias associated with them. Thus, the exponent bits 337 described herein may represent the exponent e as a factor of 2. e Scaling. Figure 3 As shown in FIG, there may be up to es exponent bits (e1, e2, e3, ..., e es In some embodiments, this may allow for increasingly smaller accuracy of n-bit posit 331, where numbers closer to one in magnitude have higher accuracy than extremely large or small numbers. However, since extremely large or small numbers may be used less frequently in certain types of operations, Figure 3 The progressively less accurate performance of the n-bit posit 331 shown may be desirable in a wide range of situations.

[0091] Mantissa bits 339 (or fraction bits) represent any additional bits that may be part of n-bit posit 331 to the right of exponent bits 337. Similar to a floating point bit string, mantissa bits 339 represent a fraction f that may be similar to fraction 1.f, where f includes one or more bits to the right of the decimal point. However, in contrast to a floating point bit string, Figure 3In the illustrated n-bit posit 331 , the “hidden bit” (eg, one) may always be one (eg, unity), and the floating point bit string may include a subnormal number with a “hidden bit” of zero (eg, 0.f).

[0092] Figure 4A is an example of a positive value for a 3-bit posit. Figure 4A In , only the right half of the real numbers is projected. However, it should be understood that the corresponding Figure 4A The negative projection of the real numbers of their positive corresponding values ​​shown in may exist on the curve, which represents the real numbers around Figure 4A The transformation of the y-axis of the curve shown in .

[0093] exist Figure 4A In the example, es = 2, so The precision of posit 431-1 can be increased by appending bits to the bit string, e.g. Figure 4B For example, appending a bit with value one (1) to the bit string of posit 431-1 increases as shown by Figure 4B Similarly, a bit with a value of one is appended to Figure 4B The bit string of posit 431-2 in the example is increased by Figure 4B The following are methods that can be used to append bits to Figure 4A The bit string of posit 431-1 shown in Figure 4B An example of the interpolation rules of posit 431-2 and 431-3 described in .

[0094] If maxpos is the maximum positive value of the bit string of posit 431-1, 431-2, 431-3 and minpos is the minimum value of the bit string of posit 431-1, 431-2, 431-3, then maxpos may be equal to used and minpos may be equal to Between maxpos and ±∞, the new place value may be maxpos*used, and between zero and minpos, the new place value may be These new bit values ​​may correspond to the new scheme bits 335. At the existing value x=2 m and y = 2 n where m and n differ by more than one, the new place value is given by the geometric mean: This corresponds to the new exponent bit 337. If the new bit value is halfway between the existing x-value and y-value immediately adjacent to it, then the new bit value may represent the arithmetic mean. This corresponds to the new mantissa digit 339.

[0095] Figure 4B is an instance of the posit construct using two exponent bits. Figure 4B In , only the right half of the real numbers is projected. However, it should be understood that the corresponding Figure 4B The negative projection of the real numbers of their positive corresponding values ​​shown in may exist on the curve, which represents the real numbers around Figure 4B The transformation of the y-axis of the curve shown in . Figure 4B Each of posit 431-1, 431-2, 431-3 shown in FIG4 contains only two outlier values: zero (0) when all bits of the bit string are zero, and ±∞ when the bit string is one (1) followed by all zeros. It should be noted that the values ​​of posit 431-1, 431-2, 431-3 shown in FIG4 are precisely used k That is, the values ​​of posit 431-1, 431-2, 431-3 shown in FIG4 are exactly used by the multiplication scheme (for example, the above combined Figure 3 The scheme described is a power of k value represented by bit 335. Figure 4B In posit 431-1, es=2, so posit 431-2 has es=3, so And posit 431-3 has es=4, so

[0096] As bit is added to the 3-bit posit 431-1 to produce Figure 4B illustrative example of a 4-bit posit 431-2, used=256, so the bit string corresponding to used 256 has an extra scheme bit appended to it, and the previous used 16 has a terminating scheme bit appended to it As described above, between existing values, the corresponding bit string has an extra exponent bit appended to it. For example, the values ​​1 / 16, 1 / 4, 1, and 4 will have an exponent bit appended to them. That is, the last one corresponding to the value 4 is the exponent bit, the last zero corresponding to the value 1 is the exponent bit, and so on. This pattern can be further seen in posit 431-3, which is a 5-bit posit generated from the 4-bit posit 431-2 according to the above rules. If another bit is added to Figure 4B posit 431-3 in the number to produce a 6-digit posit, then the mantissa digit 339 will be appended to the value between 1 / 16 and 16.

[0097] The following is a non-limiting example of decoding a posit (e.g., posit 431) to obtain its digital equivalent. In some embodiments, the bit string corresponding to posit p is in the range -2n-1 to 2 n-1 , k is an integer corresponding to the scheme bits 335, and e is an unsigned integer corresponding to the exponent bits 337. If the set of mantissa bits 339 is represented by {f1f2…f fs} and f is composed of 1.f1 f2…f fs The value represented by (eg, by one after the decimal point after the mantissa digit 339), then p can be given by the following equation 1.

[0098]

[0099] Equation 1

[0100] Another illustrative example of decoding a posit bit string is provided below in conjunction with the posit bit string 0000110111011101 shown in Table 3 below.

[0101] symbol plan index mantissa 0 0001 101 11011101

[0102] Table 3

[0103] In Table 3, the posit bit string 0000110111011101 is broken down into its constituent bit sets (e.g., sign bit 333, scheme bits 335, exponent bits 337, and mantissa bits 339). Since es=3 in the posit bit string shown in Table 3 (e.g., because there are three exponent bits), used=256. Because the sign bit 333 is zero, the value of the numerical representation corresponding to the posit bit string shown in Table 3 is positive. The scheme bits 335 have a series of three consecutive zeros corresponding to the value -3 (as described above in conjunction with Table 1). Therefore, the scaling factor contributed by the scheme bits 335 is 256. -3 (For example, used k ). The exponent bits 337 represent five (5) as an unsigned integer and thus provide 2 e =2 5 = 32. Finally, the mantissa bits 339 given in Table 3 as 11011101 represent two hundred and twenty one (221) as an unsigned integer, so the mantissa bits 339 given above as f are Using these values ​​and Equation 1, the numerical value corresponding to the posit bit string given in Table 3 is

[0104] Figure 55 is another functional block diagram of a computing system including an apparatus 501 including a host 502 and a memory device 504, according to several embodiments of the present disclosure. Memory device 504 may include circuitry implemented on a field programmable gate array (FPGA). Components illustrated within dashed box 540 may be circuitry implemented on the FPGA. However, embodiments of the present disclosure are not limited in this regard.

[0105] Memory device 504 may include processing device 554. In at least one embodiment, processing device 554 may be a cache-coherent reduced instruction set computing (RISC) device. A non-limiting example of a cache-coherent reduced instruction set computing device is a 32-bit RISC-V device. Processing device 553 may be configured to receive commands from host 502. Processing device 553 may be configured to provide a signal to host 502 indicating completion and / or execution of a command from host 502. Processing device 553 may be configured to provide a signal to host 502 indicating an interrupt.

[0106] Memory device 504 may include logic circuitry 522. Logic circuitry 522 may be similar to a memory device 504 that incorporates Figure 2A The logic circuit system 522 described above can be coupled to the acceleration circuit system 520. However, the embodiments of the present disclosure are not limited thereto. For example, the logic circuit system 522 can be as follows: Figure 2A Illustrated components of acceleration circuitry 520. Acceleration circuitry 520 may be referred to as a posit arithmetic logic unit (PALU).

[0107] Acceleration circuitry 520 may include multiple buffers configured to receive data values ​​from logic circuitry 522. Buffers configured to receive data values ​​from logic circuitry 522 may be referred to as "input buffers" (e.g., input buffer 545). Each input buffer may be configured to store operands formatted in either unum or posit format. Operands may be represented by bit strings.

[0108] like Figure 5 As illustrated, input buffer A 545 may be configured to store "Operand A" and input buffer B 546 may be configured to store "Operand B." Operand A and / or operand B may be formatted in either unum or posit format. Although Figure 5 Two input buffers 545 and 546 are illustrated, but embodiments of the present disclosure are not limited thereto. For example, acceleration circuitry 520 may include a single input buffer or more than two input buffers. In at least one embodiment, at least one input buffer may be a first-in, first-out (FIFO) buffer.

[0109] Acceleration circuitry 520 may include circuitry (eg, processing circuitry) configured to perform at least one arithmetic operation, at least one logical operation, or both on at least one operand stored by at least one input buffer. Figure 5 As illustrated, the acceleration circuitry 520 may be configured to perform operations including, but not limited to, addition, subtraction, multiplication, division, fused multiply-add, multiply-accumulate, dot product unit, greater than or less than, absolute value (e.g., FABS()), fast Fourier transform, inverse fast Fourier transform, sigmoid function, convolution, square root, exponential, and trigonometric operations such as sine, cosine, tangent, AND, OR, XOR, NOT, and combinations thereof. In at least one embodiment, the acceleration circuitry 520 may include multiply-accumulate (MAC) circuitry 548.

[0110] The acceleration circuit system 520 may include at least one buffer configured to receive a data value resulting from at least one arithmetic operation, at least one logical operation, or both performed by the acceleration circuit system 520. A buffer configured to transmit the resulting data value may be referred to as an "output buffer" (e.g., output buffer 547). The output buffer may be configured to store the resulting data value formatted in unum or posit format. Although Figure 5 A single output buffer 547 is illustrated, but embodiments of the present disclosure are not limited thereto. For example, the acceleration circuitry 520 may include more than one output buffer. In at least one embodiment, at least one output buffer may be a FIFO buffer.

[0111] Logic circuitry 522 may include a direct memory access (DMA) controller 542. DMA controller 542 may be coupled to input buffers 545 and 546. DMA controller 542 may be coupled to at least one memory resource. Figure 5 As illustrated, the DMA controller 542 may be coupled to an interconnect 551, such as an Advanced eXtensible Interface (AXI) interconnect. The interconnect 551 may be coupled to a plurality of memory resources. At least one of the memory resources may be internal to the memory device 504, such as a scalable RAM 553 and a block RAM 555. As used herein, "scalable RAM" refers to a dual-port synchronous random access memory cell deployed within the FPGA that may be coupled to a plurality of dual-port synchronous random access memory cells to increase the amount of storage locations available for the scalable RAM 553. The interconnect 551 may be coupled to a memory resource 530 that is external to the memory device 504. The external memory resource 530 may be similar to a memory resource that is separately coupled to a scalable RAM 553. Figure 1 and 2A2B . Interconnect 551 can be coupled to external memory resources 530 via memory controller 550. External memory resources 530 can be main memory. Non-limiting examples of external memory resources 530 are double data rate (DDR) memory, such as DDR3 memory or DDR4 memory.

[0112] In at least one embodiment, the acceleration circuitry 520 may include a memory controller, such as a DMA controller 542. The memory controller may be coupled to a memory comprising at least two distinct memory components. The memory controller may be configured to retrieve a first operand, a second operand, or both from a specific one of the at least two distinct memory components of the memory based at least in part on signaling received by the memory controller. For example, the DMA controller 542 may be configured to retrieve at least one operand from any of the memory resources coupled thereto (e.g., scalable RAM 553, block RAM 555, external memory resources 530 (e.g., via memory controller 550), and combinations thereof) to input buffers 545 and 546. Additionally or alternatively, to retrieve operands from the memory resources, the DMA controller 542 may be configured to retrieve operands from the host 502.

[0113] The DMA controller 542 can be configured to communicate (e.g., transfer) the resulting data value from the output buffer 547 to at least one operand from any of the memory resources coupled thereto, such as the scalable RAM 553, the block RAM 555, the external memory resources 530 (e.g., via the memory controller 550), and combinations thereof. Additionally or alternatively, to communicating the resulting data value to the memory resource, the DMA controller 542 can be configured to communicate the resulting data value to the host 502.

[0114] The memory device 504 may be configured to communicate with the host 502 via a peripheral component interconnect express (PCIe) interface 552 .

[0115] In at least one embodiment, the logic circuitry 522 may include a microdecoding controller 544. Instead of using the acceleration circuitry 520 to perform arithmetic or logical operations, the microdecoding controller 544 may be used to identify precomputed results for the arithmetic or logical operations. The results of multiple arithmetic operations, multiple logical operations, or both may be precomputed using multiple operands formatted in unum or posit format. The precomputed results may be compiled into a lookup table (LUT). The LUT may be stored by the microdecoding controller 544 or other circuitry of the logic circuitry 522. The microdecoding controller 544 may receive an instruction from a processing device, such as the processing device 554 or the CPU of the host 502, to perform a specific operation from the multiple arithmetic operations or the multiple logical operations using a specific set of operands. The microdecoding controller 544 may identify, via the LUT, one of the precomputed results corresponding to the specific operation and the specific set of operands. The identified result may be used to perform additional arithmetic or logical operations.

[0116] Memory device 504 may include multiple instances of logic circuitry 522 and acceleration circuitry 520 as represented by the overlay representation of logic circuitry 522 and acceleration circuitry 520. However, the overlay representation is not intended to be a physical orientation and / or overlap of the multiple instances of logic circuitry 522 and acceleration circuitry 520.

[0117] Figure 6 is another functional block diagram of a computing system in the form of a device 607 including a host 602 and a memory resource 624 according to several embodiments of the present disclosure. The memory resource 624 may be similar to a device 607 in conjunction with a host 602. Figure 5 Scalable RAM 553, block RAM 555, and / or DDR3 memory 530 are depicted. Memory resources 624 may be configured to communicate with host 602 via PCIe interface 652.

[0118] A first buffer (e.g., data buffer 660) of host 602 may be configured to store data values ​​(e.g., data vectors). The data values ​​stored by data buffer 660 of host 602 may be communicated (e.g., transferred) to a second buffer, such as data buffer 662 of memory resource 624. The data values ​​stored by data buffer 662 of memory resource 624 may be communicated to data buffer 660 of host 602. A third buffer (command buffer 661) may be maintained by host 602. Command buffer 661 may be configured to store commands communicated from the CPU of host 602. Commands stored by command buffer 661 of host 602 may be copied (mirrored) to a fourth buffer (command buffer 663) of memory resource 624. Commands stored by command buffer 663 of memory resource 624 may be copied to command buffer 661 of host 602.

[0119] Depend on Figure 6 The processing device 654, illustrated as a RISC-V device, may be configured to monitor the command buffer 623 of the memory resource 624. The processing device 654 may be configured to parse instructions stored by the command buffer 663 of the memory resource 624 into signals indicating the execution of an arithmetic operation, a logical operation, or both to be performed by the computational circuitry 665. The computational circuitry 665 may include processing circuitry configured to perform the arithmetic operation, the logical operation, or both. For example, in response to a command being mirrored from the command buffer 661 of the host 602 to the command buffer 663 of the memory resource 624, the processing device 654 may be configured to parse the mirrored command (e.g., a host-level command) into one or more machine-level instructions (e.g., finite state machine commands). The processing device 654 may be configured to communicate data indicating completion of the host-level command to the command buffer 663 of the memory resource 624 in response to the state machine (e.g., state machine 623) executing the machine-level instruction parsed from the host-level command. Data indicating completion of the host-level command may be copied from the command buffer 663 of the memory resource 624 to the command buffer of the host 602 .

[0120] The computation circuitry 665 may be configured to receive a signal from the processing device 654, retrieve a specific one of the operands stored by the data buffer 662 of the memory resource 624 based at least in part on the received signal, and perform an arithmetic operation, a logical operation, or both using the retrieved operand based at least in part on the received signal. The processing device 654 may be configured to communicate the machine-level instruction to a buffer 664 of the computation circuitry 665. The buffer 664 may be a FIFO buffer. The buffer 664 may enable the storage of multiple machine-level instructions by the buffer 664 without having to wait for the completion of each individual machine-level instruction.

[0121] The computational circuitry 665 may include a state machine 623 (e.g., a finite state machine (FSM)). The state machine 623 may be similar to a state machine incorporating Figure 2B The state machine 223 is described. The state machine 623 can retrieve machine-level instructions from the buffer 664. The state machine 623 can be configured to direct the performance of arithmetic operations, logical operations, or both according to the machine-level instructions.

[0122] The computation circuitry 665 may include an acceleration circuitry 620 coupled to a state machine 623. The acceleration circuitry 620 may be similar to a state machine 623 coupled to a state machine 623. Figure 5 The acceleration circuit system 520 is described.

[0123] A non-limiting example of a host-level command is a general matrix multiplication (GEMM) command. An implementation of the GEMM command may include the host 602 transferring a bit string representing a matrix from a data buffer 660 to a data buffer 662 of the memory resource 624. An implementation of the GEMM command may include communicating command data associated with the GEMM command (e.g., the addresses and sizes of the two matrices) to a command buffer 661 of the host 602. The command data may be copied from the command buffer 661 of the host 602 to a command buffer 663 of the memory resource 624. The processing device 654 may detect the command data stored by the command buffer 663 of the memory resource 624 and parse the GEMM command into machine-level instructions, such as a plurality of dot product operations. The processing device 654 may parse each dot product operation into a plurality of FSM commands. The FSM commands may include, but are not limited to, clearing QUIRE, performing the dot product, transferring the result to a buffer of the acceleration circuit system 620 (e.g., in conjunction with Figure 5 64. The processing device 654 may store the GEMM command in the command buffer 663 of the memory resource 624 and write the result from the buffer to the result location. In response to completing all FSM commands for all dot product operations, the processing device 654 may communicate data indicating the completion of the GEMM command to the command buffer 663 of the memory resource 624. The data indicating the completion of the GEMM command may be copied from the command buffer 663 of the memory resource 624 to the command buffer 661 of the host 602.

[0124] PCIe interface 652 , memory resources 624 , processing device 654 , and / or computational circuitry 665 may be implemented on an FPGA.

[0125] Figure 7 is another functional block diagram of a computing system in the form of a device 709 including a host 702 and memory resources 724 according to several embodiments of the present disclosure. The host 702, PCIe interface 752, memory resources 724, processing device 754, and computing circuit system 765 may be similar to the combination of Figure 6 Depicted are host 602 , PCIe interface 652 , memory resources 624 , processing device 654 , and computing circuitry 665 .

[0126] and Figure 6Compared to the illustrated device 607, device 709 includes a plurality of computation circuits 766-0, 766-1, ..., 766-N (collectively, computation circuits 766). Similar to computation circuitry 765, each of computation circuits 766 may include a buffer 764 and a state machine 723 (e.g., an FSM). Buffer 766 may be configured to store machine-level instructions (e.g., FSM commands). However, each of computation circuits 766 includes a quire register 767 coupled to state machine 723. Require register 767 may be configured to store results (e.g., intermediate results) of iterations of recursive operations (e.g., arithmetic or logical operations) performed by the MAC. In some embodiments, each of computation circuits 766 may include a sense amplifier band, a string of flip-flops, or both, in addition to or in lieu of state machine 723.

[0127] like Figure 7 As illustrated, command buffer 761 of host 702 and command buffer 763 of memory resource 724 each include storage (e.g., command buffers) associated with each state machine of computation circuit 766 and computation circuitry 765. Command buffers 761 and 763 include storage for each of the state machines of N+1 computation circuits 766 and state machine 723 of computation circuitry 765.

[0128] If combined Figure 6 As described, the processing device 754 may parse a host-level command associated with a matrix multiplication (e.g., a GEMM command) into a plurality of machine-level instructions associated with a dot product operation. The dot product operation may be performed in parallel using the computational circuitry 766. The machine-level instructions for the corresponding dot product operation may be distributed among the computational circuitry 766. The PCIe interface 752, the memory resources 724, the processing device 754, the computational circuitry 765, and / or the computational circuitry 766 may be implemented on an FPGA. The acceleration circuitry 720 including a quire register 767 instead of a computational circuitry 765 in each of the computational circuits 766 may reduce the amount of resources of the FPGA implementing the computational circuitry 765. Compared to the device 709, the acceleration circuitry 520 may be implemented in a manner similar to that of the device 709. Figure 5 The acceleration circuitry 520 of the device 501 of the embodiment described can utilize a larger amount of FPGA resources. Including quire registers 767 in each of the computation circuits 766 can increase the amount of arithmetic and / or logical operations that can be performed in parallel while reducing the amount of FPGA resources to be implemented.

[0129] Figure 8is another functional block diagram of a computing system in the form of a device 811 including a host 802 and a memory resource 824 according to several embodiments of the present disclosure. The host 802, PCIe interface 852, memory resource 824, processing device 854, computing circuit system 865, and computing circuit 866 may be similar to the combination of Figure 7 Depicted are host 702 , PCIe interface 752 , memory resources 724 , processing device 754 , computing circuitry 765 , and computing circuitry 766 .

[0130] and Figure 7 Compared to the illustrated device 709, the device 811 includes an acceleration circuit system 868 coupled to the PCIe interface 852 in addition to the acceleration circuit system 820 of the computational circuit system 865. The acceleration circuit system 868 may have the same structure as the acceleration circuit system 820 of the computational circuit system 865 or a different structure. The acceleration circuit system 868 may be directly coupled to the PCIe interface 852. The acceleration circuit system may be mapped into a memory space associated with the PCIe interface 852 (e.g., indirect registers 870). The indirect registers 870 may be configured to store scalar operands, results of arithmetic or logical operations, or both. The output buffer of the acceleration circuit system 868 (e.g., in conjunction with Figure 5 The output buffer 547 described above may be combined with a busy flag so that read operations from the output buffer will not complete until the acceleration circuitry 868 has completed execution of the arithmetic or logical operation. A scalar multiplication operation performed using the apparatus 800 and the acceleration circuitry 868 may include writing a first scalar operand (operand A) to a first input buffer (e.g., input buffer 545) of the acceleration circuitry 868, writing a second scalar operand (operand B) to a second input buffer (e.g., input buffer 546) of the acceleration circuitry 868, and reading the result of the multiplication operation of the first and second scalar operands from a multiplication result register. Using the acceleration circuitry 868 to perform scalar operations may be more efficient than using the acceleration circuitry 820 of the computation circuitry 865.

[0131] In at least one embodiment, the device 800 can provide indirect access to operands stored by the memory resource 824. For example, if a combination of scalar and vector operations is to be performed, it may be more efficient to load the vector data into the memory resource 824 and maintain storage of the vector data by the memory resource 824 so that the computation circuitry 866 and the state machine 823 of the computation circuitry 865 can access the vector data without having to communicate the data to and from the host 802. If a scalar operation is to be performed on the vector data or the result from the vector operation, the scalar operation is performed on the memory resource 824. An indirect scalar multiplication operation may include writing the address of a first operand (operand A) stored in the memory resource 824 to the indirect register 870, writing the address of a second operand (operand B) stored in the memory resource 824 to the indirect register 870, and writing the address of the result of the scalar operation using the first and second operands stored in the memory resource 824 to the indirect register 870.

[0132] Figure 9 is another functional block diagram of a computing system in the form of a device 913 including a host 902 and memory resources 924 according to several embodiments of the present disclosure. The host 902, PCIe interface 952, memory resources 924, computing circuitry 965, and computing circuitry 966 may be similar to a combination of Figure 8 Depicted are host 802, PCIe interface 852, memory resources 824, computing circuitry 865, and computing circuitry 866.

[0133] and Figure 8 Compared to the illustrated device 811, the device 913 does not include a processing device coupled to the PCIe interface 952 and the memory resources 924. The buffer 964 of the computational circuitry 965 may be mapped to the memory space of the PCIe interface 952. Mapping the buffer 964 to the memory space of the PCIe interface 952 may enable a software driver of the host 902 to provide the memory resources provided by the processing device (e.g., in conjunction with the PCIe interface 952). Figure 8 The functionality provided by the embedded software of the processing device 854 described above. The software drivers of the host 902 can operate at a higher throughput than the embedded software of the processing device.

[0134] In at least one embodiment, the host 902 (e.g., via the CPU of the host 902) may parse a higher-level command, such as a GEMM command, into lower-level commands (e.g., machine-level instructions), such as state machine commands associated with a dot product operation of the GEMM command. The lower-level commands may be stored by a command buffer 961 of the host 902, which includes storage devices (e.g., registers) corresponding to each state machine 923 of the computation circuits 966 and the computation circuitry 965. The corresponding lower-level commands may be communicated (e.g., transferred) from the corresponding storage devices of the command buffer 961 of the state machine corresponding to one of the computation circuits 966-0, 966-1, ..., 966-N, or the computation circuitry 965 to the command buffer 964 of the computation circuit 966 or the computation circuitry 965. For example, the machine-level instructions may be transferred from the registers of the command buffer 961 of the state machine 923 corresponding to the computation circuit 966-1 to the command buffer 964 of the computation circuit 966-1.

[0135] Figure 10 is a functional block diagram of an acceleration circuit system 1020 in accordance with several embodiments of the present disclosure. The acceleration circuit system 1020 may be similar to a combination of Figures 5 to 9 Any of the described acceleration circuitry 520, 620, 720, 820, 868, 920, and 968. Acceleration circuitry 1020 may be implemented on an FPGA.

[0136] Acceleration circuitry 1020 may be able to store bursts of incoming data because arithmetic operations may be performed using two or more operands. Data values ​​corresponding to two operands may be supplied to acceleration circuitry 1020 during the same clock cycle. For example, if data is being read from an external memory resource (e.g., in conjunction with a 256-byte burst) in 256-byte bursts, the data values ​​may be supplied to the acceleration circuitry 1020. Figure 5 If the two operands are retrieved from the DDR3 memory 530 as described above, there is no guarantee that the data values ​​will arrive at the correct time. In at least one embodiment, the acceleration circuitry 1020 may include an AXI stream FIFO, such as input buffers 1046 and 1046. The acceleration circuitry 1020 may include an output buffer 1047, which may be configured to buffer data values ​​representing results from the arithmetic blocks before communicating the data values ​​from the acceleration circuitry 1020 to, for example, the DDR3 memory 530.

[0137] In at least one embodiment, acceleration circuitry 1020 may read sixty-four bits of data from input buffers 1045 and 1046 and convert the data into a format compatible with circuitry configured to perform arithmetic operations. For example, in an 8-bit posit environment, operands read from input buffers 1045, 1046, or both may be converted by circuitry 1072 into eight sequential inputs on a bus. Circuitry 1076 may include a multiplexer configured to select an output. Circuitry 1076 may include an ALU. The ALU may include circuitry (e.g., hardware, logic, one or more processing devices, etc.) that performs operations (e.g., arithmetic operations, logical operations, bitwise operations, etc.) on integer binary bit strings (e.g., bit strings in posit format). The results of the operations performed by circuitry 1076 corresponding to the eight sequential inputs may be filled into a 64-bit word by circuitry 1076, for example, and the 64-bit word is then written to output buffer 1047.

[0138] In at least one embodiment, input buffer 1045 , input buffer 1046 , output buffer 1047 , circuitry 1072 , and / or circuitry 1076 may be implemented in a DMA block.

[0139] In at least one embodiment, acceleration circuitry 1020 may include circuitry 1073 configured to convert data values ​​formatted in floating point format to unum or posit format. Acceleration circuitry 1020 may include circuitry 1074 configured to convert data values ​​formatted in unum or posit format to floating point format.

[0140] Figure 11 is another functional block diagram in the form of a memory device 1104 according to several embodiments of the present disclosure. PCIe interface 1152, memory resources 1124, and computing circuitry 1165 may be similar to a combination of Figure 6 The PCIe interface 652, memory resources 624, and computing circuitry 865 are depicted. Figure 11 Components of the state machine 1123 of the computational circuitry 1165 are illustrated.

[0141] The state machine 1123 may include multiple DMA controllers. Each corresponding DMA controller may be coupled to a corresponding buffer. Each buffer may be a FIFO buffer. Figure 11As illustrated, the state machine 1123 may include a first set 1171 of DMA controllers and FIFO buffers configured to retrieve (e.g., from memory resources 1124) and store a first operand (operand A (OPA)). The state machine 1123 may include a second set 1173 of DMA controllers and FIFO buffers configured to retrieve (e.g., from memory resources 1124) and store a second operand (operand B (OPB)). The state machine 1123 may include a third set 1175 of DMA controllers and FIFO buffers configured to retrieve (e.g., from memory resources 1124) and store a third operand (operand C (OPC)). The FIFO buffers of the sets 1171, 1173, and 1175 between the outputs of the respective DMA controllers and the acceleration circuitry 1120 may enable the acceleration circuitry 1120 to perform operations at a faster speed.

[0142] The acceleration circuitry 1120 of the computation circuitry 1165 may retrieve the first operand, the second operand, the third operand, or a combination thereof from the corresponding FIFO buffer of the state machine 1123. Figure 11 Three sets of DMA controllers and FIFO buffers 1171, 1173, and 1175 for retrieving and storing operands are illustrated, but the embodiment is not limited thereto. For example, the state machine 1123 may include fewer than three sets of DMA controllers and FIFO buffers or more than three sets of DMA controllers and FIFO buffers.

[0143] The state machine 1123 may include a DMA controller and a set of buffers 1177 configured to retrieve, store, and communicate results from the acceleration circuitry 1120. The buffers of the set 1177 may be FIFO buffers.

[0144] The processing device 1158 may communicate commands such as count, address, size, stride, and operation to be executed by the acceleration circuitry 1120 to the command buffer 1164. Figure 11 As illustrated, computational circuitry 1165 may include memory 1178 configured to store data indicating control signals, status, or both. The DMA controllers of sets 1171, 1173, and 1175 may retrieve the respective operands based at least in part on a command from processing device 1158 that includes a starting address, an amount of data to be retrieved (e.g., starting address + N * stride * operand size), and an operation count. As used herein, "stride" refers to the address increment between processed samples. For example, a stride of -1 may be used to read data from a buffer in reverse order. As another example, a stride of 2 may be used to read data from a buffer at address offsets of 0, 2, 4, 6, 8, and so on.

[0145] Figure 12is a flow chart illustrating an example method 1280 of an acceleration circuit system for POSIT operation according to several embodiments of the present disclosure. At block 1281, the method 1280 may include receiving a first operand by a first buffer residing on the acceleration circuit system. The first operand may be formatted in UNUM or POSIT format. The first buffer may be a FIFO buffer. The acceleration circuit system may be similar to Figure 1 , 2 and 5 to 11 describe the acceleration circuit systems 120, 220, 520, 620, 720, 820, 868, 920, 968, 1020 and 1120.

[0146] At block 1282, method 1280 may include receiving a second operand from a second buffer residing on the acceleration circuitry. The second operand may be formatted in a unum or posit format. The second buffer may be a FIFO buffer.

[0147] At block 1283, method 1280 may include performing an arithmetic operation, a logical operation, or both using the first operand and the second operand. As described above, the arithmetic operation may include the following arithmetic operations: addition, subtraction, multiplication, division, fused multiply-add, multiply-accumulate, dot product unit, greater than or less than, absolute value (e.g., FABS()), fast Fourier transform, inverse fast Fourier transform, sigmoid function, convolution, square root, exponential and / or rectified linear unit (ReLu), and trigonometric operations such as sine, cosine, tangent, etc., while the logical operation may include logical operations such as AND, OR, XOR, NOT, etc.

[0148] At block 1284, method 1280 may include transmitting the result of the arithmetic operation, the logical operation, or both through a third buffer residing on the acceleration circuitry. The result may be formatted in unum or posit format. The third buffer may be a FIFO buffer.

[0149] In some embodiments, the acceleration circuitry may be implemented on an FPGA. Method 1280 may further include retrieving the first operand, the second operand, or both from a memory residing on the FPGA. Method 1280 may further include retrieving the first operand, the second operand, or both from a main memory external to the acceleration circuitry. Method 1280 may further include retrieving the first operand, the second operand, or both via a DMA controller that may be coupled to the acceleration circuitry. Method 1280 may further include transferring the first operand, the second operand, or both from a host that may be coupled to the acceleration circuitry to at least one of a memory implemented on the FPGA and a main memory that may be coupled to the acceleration circuitry.

[0150] Figure 13is another flow chart illustrating an example method 1385 of an acceleration circuit system for posit operations according to several embodiments of the present disclosure. In at least one embodiment, the method 1385 may be at least partially implemented in conjunction with Figure 5 The method 1385 may be implemented as described in the microdecode controller 544. At block 1386, the method 1385 may include pre-calculating results of a plurality of arithmetic operations, a plurality of logical operations, or both using a plurality of operands formatted in the unum or posit format. In some embodiments, pre-calculating the results may include pre-calculating results of a plurality of arithmetic operations, a plurality of logical operations, or both using operands of a specific bit length.

[0151] At block 1387, the method 1385 may include compiling the pre-calculated results into the LUT. As described herein, the LUT may be used to identify the result of a particular arithmetic or logic operation within the LUT without performing the particular arithmetic or logic operation. For example, in response to an instruction to perform a particular arithmetic or logic operation, a microdecoding controller (e.g., microdecoding controller 544) may identify the result of the particular arithmetic or logic operation rather than performing the particular arithmetic or logic operation.

[0152] At block 1388, the method 1385 may include receiving an instruction from a processing device to perform a particular operation of a plurality of arithmetic operations or a plurality of logical operations using a particular set of a plurality of operands. In some embodiments, receiving the instruction from the processing device may include receiving the instruction from a host processing device.

[0153] At block 1389, the method 1385 may include identifying, via the LUT, one of the pre-computed results that corresponds to the particular operation and the particular set of operands. In some embodiments, identifying one of the pre-computed results may include determining an address of the LUT associated with the result of the particular operation and the particular set of operands. In some embodiments, the method 1385 may further include performing additional arithmetic or logical operations using the identified result.

[0154] Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover modifications or variations of one or more embodiments of the present disclosure. It should be understood that the above description has been made in an illustrative and not restrictive manner. Upon reviewing the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims together with the full scope of equivalents to which such claims are given.

[0155] In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure necessarily utilize more features than expressly recited in each claim. In fact, as reflected in the appended claims, the present subject matter lies in less than all of the features of a single disclosed embodiment. Thus, the appended claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. A method for accelerating a circuit system for POSIT operation, comprising: receiving, via a data buffer on a memory device, a first operand and a second operand formatted in a posit format; receiving commands from a host via a command buffer on the memory device; parsing, by a processing device, the instructions stored by the command buffer into signals indicating execution of an arithmetic operation or a logic operation; as well as performing the arithmetic operation or the logical operation by a computing circuit system, wherein the performing by the computing circuit system further comprises: receiving machine-level instructions from the processing device via a buffer; directing, through a state machine and according to the machine-level instruction, a multiply-accumulate MAC circuit system of the acceleration circuit system to perform the arithmetic operation or the logic operation using the first operand and the second operand; communicating, by the processing device, data indicating completion of the machine-level instruction to the command buffer of the memory device; and The data is copied from the command buffer of the memory device into a command buffer of the host.

2. The method according to claim 1, further comprising: determining whether the machine-level instruction has been executed by the state machine; as well as In response to determining that the machine-level instruction has been executed, the command buffer is caused to store the data indicative of the machine-level instruction executed.

3. The method of claim 1, further comprising retrieving the first operand, the second operand, or both from an external memory resource. 4 . The method of claim 3 , further comprising retrieving the first operand, the second operand, or both via a direct memory access (DMA) controller of the memory device.

5. The method of claim 4, wherein the acceleration circuitry is implemented in a field programmable gate array (FPGA) of the memory device.

6. A device for accelerating a circuit system for posit operation, comprising: Host; as well as a memory device coupled to the host and comprising: a data buffer configured to store a first operand and a second operand formatted in a posit format; a command buffer configured to store instructions received from the host; a processing device coupled to the data buffer and the command buffer, wherein the processing device is configured to parse instructions stored by the command buffer into signals indicating performance of arithmetic and logical operations; a computing circuit system configured to perform the arithmetic operation and the logical operation, wherein the computing circuit system further comprises: a buffer configured to store machine-level instructions; acceleration circuitry including multiply-accumulate MAC circuitry; and a state machine coupled to the buffer and the acceleration circuitry, the state machine configured to direct the MAC to perform the arithmetic operation and the logic operation using the first operand and the second operand according to the machine-level instruction, wherein in response to the state machine executing the machine-level instruction, the processing device communicates data indicating completion of the machine-level instruction to the command buffer.

7. The apparatus of claim 6, wherein the data buffer and the command buffer each comprise a first-in-first-out (FIFO) buffer.

8. The apparatus of claim 6, wherein the host is configured to mirror instructions stored in a command buffer of the host into the command buffer of the memory device.

9. The apparatus of claim 8, wherein the data indicating the completion of the machine-level instruction is copied into the command buffer of the host.

10. The apparatus of claim 6, wherein the apparatus is implemented in a field programmable gate array (FPGA) of the memory device.

11. The apparatus of claim 6, wherein the processing device is configured to: Parsing host-level instructions into machine-level instructions; and The machine-level instructions are communicated into the command buffer of the memory device.

12. The apparatus of claim 11, wherein the processing device comprises a cache coherent RISC device.

13. The apparatus of claim 11, wherein the apparatus is configured to communicate with an external host via a Peripheral Component Interconnect Express (PCIe) interface.

14. A system for accelerating a circuit system for POSIT operation, comprising: Host; as well as a memory device coupled to the host and comprising: a data buffer configured to store operands formatted in a posit format and received from the host; a command buffer configured to store instructions received from the host; and a processing device coupled to the data buffer and the command buffer, wherein the processing device is configured to parse instructions stored by the command buffer into signals indicating performance of an arithmetic operation or a logical operation; a computing circuit system configured to perform the arithmetic operation or the logical operation, wherein the computing circuit system further comprises: a buffer configured to store machine-level instructions; acceleration circuitry including multiply-accumulate MAC circuitry; and a state machine coupled to the buffer and the acceleration circuitry, the state machine configured to direct the MAC to perform the arithmetic operation or the logic operation using the stored operands according to the machine-level instructions, Wherein in response to the state machine executing the machine-level instruction, the processing device communicates data indicating completion of the machine-level instruction to the command buffer.

15. The system of claim 14, wherein the host is configured to mirror instructions stored in a command buffer of the host to the command buffer of the memory device.

16. The system of claim 15, wherein the data indicating the completion of the machine-level instruction is copied into the command buffer of the host.

17. The system of claim 14, wherein the state machine comprises: a plurality of direct memory access DMA controllers configured to retrieve stored operands; as well as A DMA controller is configured to write a result of the arithmetic operation or the logic operation into the data buffer.

18. The system of claim 17, wherein the state machine further comprises: a respective first-in-first-out FIFO buffer coupled to each of the plurality of DMAs; as well as A FIFO buffer is coupled to the DMA controller.

19. The system of claim 14, wherein the processing device is further configured to: determining whether the machine-level instruction has been executed by the state machine; and In response to determining that the machine-level instruction has been executed, the command buffer of the memory is caused to store data indicative of the machine-level instruction executed.

20. The system of claim 19, wherein the acceleration circuitry further comprises circuitry configured to convert data values ​​formatted in a floating point format to a posit format.

21. The system of claim 14, wherein the memory device is configured to communicate with the host via a Peripheral Component Interconnect Express (PCIe) interface.

22. The system of claim 14, wherein the processing device comprises a cache coherent RISC device.

23. The system of claim 14, wherein the computation circuitry is configured to receive a signal from the processing device and retrieve an operand stored in the data buffer based at least in part on the received signal.

24. The system of claim 14, wherein the computational circuitry is configured to perform a dot product operation of a matrix multiplication operation defined by the instruction stored by the command buffer.

25. The system according to claim 14, wherein the acceleration circuitry of the memory device is coupled to the data buffer, the command buffer, and a peripheral component interconnect express (PCIe) interface of the memory device, wherein the acceleration circuitry comprises: Direct memory access DMA controller; a first buffer coupled to the DMA controller and configured to store a first operand formatted in a posit format; a second buffer coupled to the DMA controller and configured to store a second operand formatted in a posit format; as well as Processing circuitry is coupled to the first buffer and the second buffer and is configured to perform a scalar operation using the first operand and the second operand.

26. The system of claim 25, further comprising a plurality of registers coupled to the PCIe and the acceleration circuitry, wherein the plurality of registers are configured to store at least one of the first operand, the second operand, and a result of the scalar operation.

27. A system for accelerating a circuit system for POSIT operation, comprising: Host; as well as A memory device coupled to the host via a Peripheral Component Interconnect Express (PCIe) interface, wherein the memory device comprises: a data buffer configured to store a first operand and a second operand formatted in a posit format received from the host; a command buffer configured to store instructions received from the host; a processing device coupled to the data buffer and the command buffer, wherein the processing device is configured to parse instructions stored by the command buffer into signals indicating performance of arithmetic and logical operations; and a plurality of computing circuits configured to perform the arithmetic operation and the logical operation, wherein each computing circuit further comprises: a buffer configured to store machine-level instructions; a quire register configured to store a result of an iteration of the recursive operation; and A state machine is coupled to the buffer and the acceleration circuit system, the state machine being configured to direct the execution of the arithmetic operation or the logic operation using the first operand and the second operand according to the machine-level instruction, wherein in response to the state machine executing the machine-level instruction, the processing device communicates data indicating completion of the machine-level instruction to the command buffer.

28. A device for accelerating a circuit system for posit operation, comprising: a memory device including a data buffer and a command buffer; a processing device coupled to the data buffer and the command buffer, wherein the processing device is configured to parse instructions stored by the command buffer into signals indicating performance of arithmetic and logical operations; A computing circuit system configured to perform the arithmetic and logical operations, wherein the computing circuit system comprises: a buffer configured to store machine-level instructions; acceleration circuitry including multiply-accumulate MAC circuitry; and a state machine coupled to the buffer and the acceleration circuitry, the state machine configured to direct the MAC to perform the arithmetic operation and the logic operation according to the machine-level instruction, wherein in response to the state machine executing the machine-level instruction, the processing device communicates data indicating completion of the machine-level instruction to the command buffer, The acceleration circuit system comprises: a first first-in first-out FIFO input buffer configured to receive a first bit string; a second FIFO input buffer configured to receive a second bit string; and circuitry couplable to the first FIFO buffer and the second FIFO buffer, wherein the circuitry is configured to unpack the first bit string and the second bit string; first circuitry configured to convert a data value formatted in a floating point format to a data value formatted in a unum or posit format; second circuitry configured to convert a data value formatted in the unum or posit format to a data value formatted in a floating point format; a third circuit system configured to perform an arithmetic operation, a logic operation, or both using the first bit string and the second bit string; fourth circuitry configured to pack results of the arithmetic operation, the logical operation, or both; and A FIFO output buffer may be coupled to the fourth circuitry.

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