CCFFET-embedded monolithic CCFFET

Abstract

Embodiments of the present disclosure relate to a monolithic charge-coupled field effect rectifier embedded with a charge-coupled field effect transistor. The integrated circuit includes a MOSFET device and a monolithic diode device, wherein the monolithic diode device is electrically connected in parallel with the body diode of the MOSFET device. The monolithic diode device is configured so that the forward voltage drop Vf of the monolithic diode device is D2 Smaller than the forward voltage drop Vf of the body diode of the MOSFET device D1 By controlling the gate oxide thickness, channel length and body doping concentration level, the forward voltage drop Vf D2 It is process-tunable. Forward voltage drop Vf D2 The tunability advantageously allows the design of integrated circuits to suit a wide range of applications based on switching speed and efficiency requirements.

Description

[0001] Cross-application of related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 014,973, filed on April 24, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates generally to monolithic integrated circuit devices, and in particular to monolithic integrated circuit field effect transistor devices. More particularly, the present invention contemplates the integration of a monolithic charge-coupled field effect rectifier device (e.g., a diode) embedded in a charge-coupled field effect transistor. The forward voltage drop of the charge-coupled field effect rectifier device is process tunable according to the requirements of switching speed and efficiency to meet a wide range of applications. Background Art

[0004] refer to Figure 1 , shows a circuit diagram of a power metal oxide semiconductor field effect transistor (MOSFET) device 10. The power MOSFET 10 includes a gate G, a source S, and a drain D. In this embodiment, the power MOSFET 10 is an n-channel device, and therefore the source S and the drain D are formed by n-type doped semiconductor regions, and the channel (and the body B) are formed by p-type doped semiconductor regions. The body B is electrically connected to the source S. The body diode D1 of the MOSFET 10 is formed by a pn junction having an anode formed by the p-type doped region of the body B and a cathode formed by the n-type region of the drain D.

[0005] In a switching circuit application, when the power MOSFET 10 is gate-controlled to be turned on, the body diode D1 is in reverse mode. When the power MOSFET 10 is subsequently turned off, the body diode D1 will be turned on in forward mode in its anti-parallel circuit configuration. The body diode D1 may, for example, have a forward voltage drop (Vf) of approximately 0.7V. However, this forward voltage drop is too high to support industry demands for faster switching speeds and higher efficiency.

[0006] Therefore, there is a need in the art to address the aforementioned problems. Summary of the invention

[0007] In an embodiment, an integrated circuit includes: a semiconductor layer doped with a first type of dopant, having a MOSFET device and a diode device monolithically integrated in the semiconductor layer, wherein the diode device is electrically connected in parallel with the body diode of the MOSFET device. The MOSFET device includes: a first trench in the semiconductor layer; a first region of the semiconductor layer doped with a first type of dopant at a top surface of the semiconductor layer; a third region of the semiconductor layer doped with a second type of dopant opposite to the first type and placed between the first region and a first drift region formed by the semiconductor layer; and a first gate electrode located in the first trench and separated from the first region and the third region by a first gate oxide layer having a first thickness. The diode device includes: a second trench in the semiconductor layer; a second region of the semiconductor layer doped with a first type of dopant at a top surface of the semiconductor layer, wherein the first region and the second region are separated from each other; a fourth region doped with a second type of dopant and placed between the second region and a second drift region formed by the semiconductor layer; and a second gate electrode located in the second trench and separated from the second region and the fourth region by a second gate oxide layer having a second thickness less than the first thickness.

[0008] In an embodiment, an integrated circuit includes: a semiconductor layer doped with a first type of dopant, having a MOSFET device and a diode device monolithically integrated in the semiconductor layer. The MOSFET device includes: a drain region formed by the semiconductor layer; a body region within the semiconductor layer; a source region within the semiconductor layer; and a first insulating trench extending through the source region and the body region, and including a first gate. The diode device includes: a cathode region formed by the semiconductor layer; an anode region within the semiconductor layer; and a second insulating trench extending through the anode region and including a second gate. The first metal layer is electrically in contact with the semiconductor layer to form a drain electrode for the MOSFET device and a cathode electrode for the diode device. The second metal layer is electrically in contact with the first gate to form a gate electrode for the MOSFET device. The third metal layer is electrically in contact with the source region to form a source electrode for the MOSFET device. The fourth metal layer is electrically in contact with the anode region and the second gate to form an anode electrode for the anode device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0010] Figure 1 is a circuit diagram of a power metal oxide semiconductor field effect transistor (MOSFET) device;

[0011] Figure 2is a circuit diagram of a power MOSFET device with an embedded rectifier diode;

[0012] Figure 3A , Figure 3B and Figure 3C shows a parallel cross section of a power MOSFET fabricated as a vertical conduction transistor;

[0013] Figure 4A , Figure 4B and Figure 4C Shows the embedding FIG. 3A to FIG. 3C Parallel cross section of the rectifier diode of the power MOSFET;

[0014] Figure 5 A top view (plan view) showing the layout of a monolithic integrated circuit of a power MOSFET device with an embedded rectifier diode;

[0015] Figure 6 A top view (plan view) showing the layout of a monolithic integrated circuit of a power MOSFET device with an embedded rectifier diode;

[0016] Fig. 7A Shows Figure 3A TEM image of cross section;

[0017] Figure 7B Shows Figure 4A TEM images of cross sections; and

[0018] FIG. 8A to FIG. 8H The process steps for the fabrication of a monolithic semiconductor integrated circuit device are shown. DETAILED DESCRIPTION

[0019] refer to Figure 2 , shows a circuit diagram of a power metal oxide semiconductor field effect transistor (MOSFET) device 12 with an embedded rectifying diode D2. The power MOSFET 12 includes a gate G, a source S, and a drain D. In this example, the power MOSFET 12 is an n-channel device, and therefore the source S and the drain D are formed by an n-type doped semiconductor region, and the channel (and the body B) are formed by a p-type doped semiconductor region. The body B is electrically connected to the source S. The body diode D1 of the MOSFET 12 is formed by a pn junction, having an anode formed by the p-type doped region of the body B and a cathode formed by the n-type region of the drain D. An additional rectifying diode D2 is electrically coupled in parallel with the body diode D1 between the body B (source S) and the drain D. The rectifying diode D2 has a forward voltage drop Vf that is smaller than that of the body diode D1. D1 Forward voltage drop Vf D2 As a result, relative to Figure 1The switching speed and efficiency of the MOSFET 10 are improved. In the manner described herein, the forward voltage drop Vf D2 The value of can be process tunable.

[0020] In a preferred embodiment, the power MOSFET 12 is manufactured as a monolithic integrated circuit device having a rectifier diode D2, which is embedded in the structure of a field effect transistor having a body diode D1. In other words, the MOSFET 12 and the diode D2 share a common semiconductor substrate. In addition, as will be described in more detail herein, the transistor and rectifier diode devices can share certain common structures.

[0021] Figure 3AA first cross-section of a power MOSFET 12 fabricated as a vertical conduction transistor is shown. A semiconductor substrate 20 (e.g., silicon) doped n-type includes a back surface. A first metal layer 22 at the back surface of the substrate 20 provides a drain electrode for the transistor 12. An n-type doped epitaxial layer 24, for example made of silicon, is formed from the upper surface of the substrate 20. The epitaxial layer 24 is more lightly doped than the semiconductor substrate 20 and forms an n-type drift region 30 for the drain of the transistor. A more heavily n-type doped region 26 at the front surface of the epitaxial layer 24 provides a source region for the transistor 12. The bottom of the n-type doped region 26 is spaced from the front surface of the epitaxial layer 24 to a depth t4 (wherein the depth t4 is approximately 0.2 μm, for example in the range of 0.15 μm to 0.25 μm). A p-type doped region 28 buried in the epitaxial layer 24 provides a body region of the transistor 12 between the doped region for the source and the n-type drift region 30. The bottom of the p-type doped region 28 is spaced from the front surface of the epitaxial layer 24 to a depth t2 (wherein the depth t2 is about 1 μm, for example in the range of 0.9 μm to 1.1 μm). A trench 32 is formed in the epitaxial layer 24 on either side of the n-type drift region 30. The trench 32 extends from the front surface of the epitaxial layer 24 completely through the regions 26 and 28, reaching a depth deeper than the bottom of the buried p-type doped region 28, but not reaching the top of the n-type doped substrate 20. The trench is filled with an insulating material 34 (such as a dielectric material in the form of an oxide). A field plate electrode 36 is located in each trench 32. The field plate electrode 36 can be made of, for example, a polysilicon material that is deposited in the sub-trench 38 (formed in (or formed by) the insulating material 34) and insulated from the epitaxial layer 24 by the insulating material 34. A gate electrode 40 is also located in each trench 32 on the opposite side of the field plate electrode 36. Each gate electrode 40 may be made, for example, of polysilicon material deposited within the sub-trench. The gate electrode 40 is insulated from the field plate electrode 36 by an intervening (i.e., inter-poly) oxide layer 42a. The gate electrode 40 is also insulated from the semiconductor regions 26, 28, and 30 (of the epitaxial layer 24) by a gate oxide layer 42b having a thickness t1 (wherein the thickness t1 is approximately For example, to ). The thickness of the inter-poly oxide layer 42a and the gate oxide layer 42b will typically be different, with thickness t1 being thinner. The gate electrode 40 extends from the front surface of the epitaxial layer 24 to a depth t3 (wherein depth t3 is greater than depth t2; where depth t3 is approximately 1.3 μm, for example in the range of 1.2 μm to 1.4 μm), and has a width w in the plane of the cross section (wherein width w is approximately 0.45 μm, for example in the range of 0.4 μm to 0.5 μm). At a location between two adjacent trenches 32, a more heavily p-doped region 44 is buried within the buried p-doped region 28 to provide contact to the p-doped region 28. An insulating layer 46 extends over the top surface of the epitaxial layer 24 (it will be noted that layer 46 may be fabricated from a stack of insulating layers). A first opening 48 extends through the insulating layer 46 at a location aligned with the more heavily p-doped region 44. The first opening 48 also extends through the more heavily n-doped region 26 at the front surface of the epitaxial layer (and depending on the positioning of the heavily p-doped region 44, may also extend partially through the p-doped region 28 for the body of the transistor). The first opening 48 is filled with a metallic material that forms a portion 50 of the source S electrode of the transistor. It will be noted that the metallic material of the portion 50 is in direct physical and electrical contact with both the more heavily n-doped region 26, which forms the source region, and the heavily p-doped region 44, which forms contact to the p-doped region 28 for the body of the transistor. A second metallic layer 52 at the top surface of the insulating layer 46 provides another portion for the source S electrode of the transistor.

[0022] Figure 3A TEM images of the cross section Fig. 7A Shown in.

[0023] Figure 3B A second cross-section of power MOSFET 12 is shown. Figure 3B The second cross section is at Figure 3A The first cross-sectional plane is made in a plane parallel to but offset from the plane of the first cross-section. Like reference numerals refer to the same components. Figure 3A and Figure 3B The offset between the cross sections is in a direction orthogonal to the parallel planes of those cross sections (i.e., in the direction into / out of the page of the drawing). A second opening 54 extends through the insulating layer 46 at a location aligned with each gate click 40. The second opening 54 is filled with a metallic material that forms a portion 56 of the gate click of the transistor. It will be noted that the metal of portion 56 is in electrical contact with the polysilicon material of the gate click 40. A third metal layer 58 at the top surface of the insulating layer 46 provides another portion for the transistor gate G electrode.

[0024] Figure 3CA third cross section of power MOSFET 12 is shown. Figure 3C The third cross section is at Figure 3A The first cross-section and the second cross-section are made in planes that are parallel but offset from each other. Like reference numerals refer to the same components. Figure 3A , Figure 3B and Figure 3C The offset between the cross sections is in a direction orthogonal to the parallel planes of those cross sections (i.e., in the direction into / out of the page of the drawing). A third opening 60 extends through the insulating layer 46 at a location aligned with each field plate electrode 36. The third opening 60 is filled with a metal material that forms another portion 62 of the source S electrode of the transistor. It will be noted that the metal of portion 62 is in electrical contact with the polysilicon material of the field plate electrode 36. The second metal layer 52 at the top surface of the insulating layer 46 provides another portion of the source S electrode for the transistor.

[0025] Figure 4A Shown is embedded FIG. 3A to FIG. 3C A first cross-section of a monolithic rectifier diode of a power MOSFET 12 of FIG. Similar reference numerals refer to the same components. The structure of the rectifier diode may share the following common parts with the structure of the power MOSFET 12: a substrate 20 (where the cathode region of the diode D2 is formed), a first metal layer 22 (where the cathode electrode is provided), a lightly doped epitaxial layer 24 having an n-type drift region 30, a trench 32, an insulating material 34, a field plate electrode 36, a sub-trench 38, and an insulating layer 46. A more heavily n-type doped region 26' at the front surface of the epitaxial layer 24 provides a source region. The bottom of the n-type doped region 26' is spaced apart from the front surface of the epitaxial layer 24 to a depth t4' (wherein the depth t4' is approximately 0.15 μm, for example in the range of 0.1 μm to 0.2 μm). A p-type doped region 28' buried in the epitaxial layer 24 provides a body region between the doped region for the source and the n-type drift region 30. Combined with the forward voltage drop Vf of the tuning diode D2 D2 , the doping concentration level of the p-type dopant for region 28' is selected. The bottom of p-type doped region 28' is spaced apart from the front surface of epitaxial layer 24 to a depth t2' (wherein depth t2' is less than depth t2; where depth t2' is about 0.6 μm, for example, in the range of 0.5 μm to 0.7 μm). Combined with the forward voltage drop Vf of tuning diode D2 D2, the depth t2' of the p-type doped region 28' that defines the channel length is selected. The trenches 32 extend completely through the regions 26' and 28' and terminate in the epitaxial layer 24. A gate electrode 40' is also located in each trench 32 on the opposite side of the field plate electrode 36. Each gate electrode 40' can be made of, for example, a polysilicon material. The gate electrode 40' is insulated from the field plate electrode 36 by an intervening (i.e., inter-poly) oxide layer 42a'. The gate electrode is also insulated from the semiconductor regions 26', 28' and 30 (of the epitaxial layer 24) by a gate oxide layer 42b', which has a thickness t1' (wherein the thickness t1' is less than the thickness t1; where the thickness t1' is approximately For example, to In the range of ). Combined with the forward voltage drop Vf of the tuning diode D2 D2 , the thickness t1' of the gate oxide layer 42b' is selected. The gate electrode 40' extends from the front surface of the epitaxial layer 24 to a depth t3' (wherein the depth t3' is greater than the depth t2', and wherein the depth t3' is less than the depth t3; wherein the depth t3' is approximately 0.9μm, for example in the range of 0.8μm to 1.0μm), and has a width w' in the plane of the cross section (wherein the width w is less than the width w'; wherein the width w' is approximately 0.6μm, for example in the range of 0.55μm to 0.65μm). At a position between two adjacent trenches 32, a more heavily p-type doped region 44' is buried within the buried p-type doped region 28' to provide a contact for the body region. The fourth opening 70 extends through the insulating layer 46 at a position aligned with the more heavily p-type doped region 44'. The fourth opening 70 also extends through the more heavily n-type doped region 26' at the front surface of the epitaxial layer (and, depending on the positioning of the heavily p-type doped region 44', also partially extends through the p-type doped region 28' for the body of the transistor). The fourth opening 70 is filled with a metallic material that forms a portion 72 of the anode A electrode of the rectifier diode D2. It will be noted that the metallic material of portion 72 is in direct physical and electrical contact with both the more heavily n-type doped region 26', which forms the source region, and the heavily p-type doped region 44', which forms a contact to the p-type doped region 28' for the body. The fourth metal layer 74 at the top surface of the insulating layer 46 provides another portion of the anode A electrode. The fourth metal layer 74 is electrically connected (short-circuited) to the second metal layer 52 (and in an embodiment, layers 52 and 74 may include the same metal layer). It will be noted that the metal layer 22 also presents and forms a portion of the cathode C electrode.

[0026] Figure 4A A cross-sectional TEM image is shown in Figure 7B middle.

[0027] In an embodiment, Figure 4A The first cross section is in accordance with the power MOSFET 12 Figure 3A , Figure 3B and Figure 3C The first cross-section, the second cross-section, and the third cross-section are made in planes that are parallel but offset from the planes of the first cross-section, the second cross-section, and the third cross-section. Figure 3A , Figure 3B , Figure 3C and Figure 4A The offset between the cross sections is in a direction orthogonal to the parallel planes of those cross sections (ie, in the direction of entering / leaving the page of the drawing).

[0028] Figure 4B A second cross section of a rectifier diode is shown. Figure 4B The second cross section is at Figure 4A The first cross-sectional plane is made in a plane parallel to but offset from the plane of the first cross-section. Like reference numerals refer to the same components. Figure 4A and Figure 4B The offset between the cross sections is in a direction orthogonal to the parallel planes of those cross sections (i.e., in the direction into / out of the page of the drawing). A fifth opening 76 extends through the insulating layer 46 at a location aligned with each gate electrode 40'. The fifth opening 76 is filled with a metallic material forming a portion 78 of the anode electrode. It will be noted that the metal of portion 78 is in electrical contact with the polysilicon material of the gate electrode 40'. A fourth metallic layer 74 at the top surface of the insulating layer 46 provides another portion of the anode A electrode.

[0029] Figure 4C A third cross section of a rectifier diode is shown. Figure 4C The third cross section is at Figure 4A and Figure 4B The first cross-section and the second cross-section are made in planes that are parallel but offset. Like reference numerals refer to the same components. Figure 4A , Figure 4B and Figure 4C The offset between the cross sections is in a direction orthogonal to the parallel planes of those cross sections (i.e., in the direction into / out of the page of the drawing). A sixth opening 80 extends through the insulating layer 46 at a location aligned with each field plate electrode 36. The sixth opening 80 is filled with a metallic material that forms a portion 82 of the anode A electrode. It will be noted that the metal of portion 82 is in electrical contact with the polysilicon material of the field plate electrode 36. The fourth metal layer 74 at the top surface of the insulating layer 46 provides another portion of the anode A electrode.

[0030] Reference now Figure 5, a top view (plan view) of the layout of a monolithic integrated circuit for a power metal oxide semiconductor field effect transistor (MOSFET) device 12 with an embedded rectifier diode D2 is shown. The plan view is illustrated at the level of the upper surface of the epitaxial layer 24 corresponding to regions 26 and 26'. The relative positions of regions 44 and 44' are shown by dotted lines because these regions are buried below regions 26 and 26'. Regions 28 and 28' are not shown, but generally have the same planar layout as regions 26 and 26'. Electrode portions 50, 56, 62, 72, 78 and 82 are shown, and it should be understood that the number of included portions and their positions are shown only as examples, and in an embodiment, each portion provided is likely to have multiple. In addition, the illustration of only one pair of grooves is only by way of example, and in a preferred embodiment, its layout will include multiple groove pairs arranged parallel to each other (e.g., parallel to the left and right sides of a pair of grooves shown in the illustration). In this example, trench 32 and its field plate electrode 36 are shared structures between MOSFET 12 at the top and diode D2 at the bottom. In alternative embodiments, MOSFET 12 and diode D2 may alternatively have separate trench 32 and field plate electrode 36 structures.

[0031] Reference now Figure 6 , shows a top view (plan view) of a layout for a monolithic integrated circuit of a power metal oxide semiconductor field effect transistor (MOSFET) device 12 with an embedded rectifying diode. The plan view is illustrated at a level corresponding to the upper surface of the epitaxial layer 24 of the regions 26 and 26'. In this layout, the structures for the MOSFET device 12 with the embedded rectifying diode D2 are arranged side by side (as shown in FIG. Figure 5 It will be appreciated that, as with respect to the aligned layout shown in Figure 6 The layout of the embedded rectifier diode D2 shown on the left side of the layout of the MOSFET device 12 in FIG. 1 can be copied to the right side of the layout for the MOSFET device 12. In addition, as shown above in conjunction with Figure 5 It is noted that the illustration of only one pair of trenches is by way of example only, and in a preferred embodiment, the layout of each of the MOSFET device 12 and the embedded rectifier diode D2 will include multiple trench pairs.

[0032] Figure 5 to Figure 6 The plan view is only an example of a layout configuration. The illustration is not drawn to scale. In addition, the illustration does not show the layout for a complete monolithic device. As is known to those skilled in the art, the illustrated layout structure can be repeated multiple times and arranged in a tiled or unit manner.

[0033] FIG. 8A to FIG. 8H1 shows the process steps for the manufacture of the gate 40, 40' and gate oxide layer 42, 42' of the MOSFET device 12 with an embedded rectifier diode D2. It will be noted that FIG. 8A to FIG. 8H The left side of each of the figures in FIG. 1 shows the positioning of a MOSFET device 12 (having D1) being manufactured, and FIG. 8A to FIG. 8H The right side of each of the figures shows the positioning of the embedded rectifier diode D2 being manufactured. FIG. 8A to FIG. 8H The steps are illustrative only and do not show all structures or all individual process steps. The figures are not presented to scale.

[0034] exist Fig. 8A In the embodiment of the present invention, standard manufacturing processes known to those skilled in the art have been performed to produce trenches 32, insulating material 34, sub-trench 38 and field plate electrode 36. As an example of the process: trenches 32 are produced in epitaxial layer 24 by an etching process. A conformal insulating material layer is deposited to line each trench and define sub-trench 38; then polysilicon material is deposited to fill each sub-trench; polishing operation is performed to remove excess polysilicon material and define field plate electrode 36.

[0035] exist Figure 8B In the embodiment, a mask 100 is provided at the location where the MOSFET device 12 is being manufactured. Then etching is performed to remove the portion of the insulating material 34 at the upper portion of the trench, which is at the location where the embedded rectifier diode D2 is being manufactured. Here etching is performed to a depth t3'.

[0036] exist Figure 8C In the process, thermal oxidation is performed to Figure 8B A gate oxide 42b' having a thickness t1' is grown on the surface of the epitaxial layer 24 (at regions 26', 28' and 30) exposed by etching in the process, and the forward voltage drop Vf of the tuning diode D2 is adjusted by controlling the parameters of the thermal oxidation. D2 , the thickness t1' may be selected. It will be noted that this thermal oxidation step will also produce an inter-poly oxide layer 42a'.

[0037] exist Fig.8D In the process, polysilicon material is deposited to fill the opening and form gate 40'.

[0038] exist Fig. 8E In the embodiment, a mask 102 is provided at the location where the embedded rectifier diode D2 is being manufactured. Then etching is performed to remove the portion of the insulating material 34 at the upper portion of the trench, which is in the location where the MOSFET device 12 is being manufactured. Here etching is performed to a depth t3.

[0039] exist Fig.8F In the process, thermal oxidation is performed to Fig. 8E A gate oxide 42b having a thickness t1 is grown on the surface of epitaxial layer 24 (at regions 26', 28' and 30) exposed by the etching in . It will be noted that this thermal oxidation step will also produce an inter-poly oxide layer 42a.

[0040] exist Figure 8G In the process, polysilicon material is deposited to fill the opening and form gate 40 .

[0041] The fabrication process continues with the use of known masking and dopant implantation steps to form regions 26 and 28 for transistor 12 (left side) and regions 26' and 28' for rectifier diode D2 (right side). Figure 8H By controlling the parameters of the implantation process and combining the forward voltage drop Vf of the tuning diode D2 D2 , the thickness t2' and the dopant concentration in region 28' may be selected.

[0042] Although the invention has been illustrated and described in detail in the drawings and the foregoing description, the illustration and description are to be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments may be understood and effected by those skilled in the art in practicing the claimed invention through study of the drawings, the disclosure, and the appended claims.

Claims

1. An integrated circuit, comprising: a semiconductor layer doped with a first type of dopant; MOSFET devices, including: a first trench in the semiconductor layer; a first region of the semiconductor layer, doped with the first type of dopant at a top surface of the semiconductor layer; a third region of the semiconductor layer doped with a second type of dopant opposite to the first type and positioned between the first region and a first drift region formed by the semiconductor layer; and a first gate disposed in the first trench and separated from the first region and the third region by a first gate oxide layer having a first thickness; Diode devices, including: a second trench in the semiconductor layer; a second region of the semiconductor layer, doped with the first type of dopant at a top surface of the semiconductor layer, wherein the first region and the second region are separated from each other; a fourth region doped with the second type of dopant and positioned between the second region and a second drift region formed by the semiconductor layer; and a second gate disposed in the second trench and separated from the second region and the fourth region by a second gate oxide layer having a second thickness smaller than the first thickness; The diode device is electrically connected in parallel with the body diode of the MOSFET device. 2 . The integrated circuit of claim 1 , wherein the first trench and the second trench are the same trench. 3 . The integrated circuit of claim 1 , wherein the first trench and the second trench are different trenches.

4. The integrated circuit of claim 1, wherein the semiconductor layer is an epitaxial layer supported by a semiconductor substrate.

5. The integrated circuit according to claim 1: The MOSFET device further comprises a first field plate, which is located in the first trench and is separated from the first gate by a first inserted oxide layer; and The diode device further includes a second field plate, which is located in the second trench and is separated from the second gate by a second inserted oxide layer.

6. The integrated circuit according to claim 5: wherein the MOSFET device further comprises a source electrode, the source electrode being electrically connected to the first region and the first field plate; wherein the diode device further comprises an anode electrode electrically connected to the second region and the second field plate; and The source electrode and the anode electrode are electrically connected to each other.

7. The integrated circuit of claim 6, further comprising: a gate electrode for the MOSFET device, electrically connected to the first gate; as well as The anode electrode is also electrically connected to the second grid electrode.

8. The integrated circuit of claim 1 , wherein the MOSFET device further comprises: a fifth region within the third region, the fifth region being more heavily doped with the second type of dopant than the third region; A source electrode is electrically connected to the first region and the fifth region.

9. The integrated circuit of claim 1 , wherein the diode device comprises: a sixth region within the fourth region, the sixth region being more heavily doped with the second type of dopant than the fourth region; as well as An anode electrode is electrically connected to the second region and the sixth doped region.

10. The integrated circuit of claim 9, wherein the anode electrode is also electrically connected to the second gate.

11. The integrated circuit of claim 1, wherein a forward voltage drop of the diode device is less than a forward voltage drop of the body diode of the MOSFET device.

12. The integrated circuit of claim 1 , further comprising: The drain electrode of the MOSFET device is electrically connected to the semiconductor layer; as well as The cathode electrode of the diode device is electrically connected to the semiconductor layer. 13 . The integrated circuit according to claim 12 , wherein the semiconductor layer is an epitaxial layer supported by a semiconductor substrate, and wherein the drain electrode and the cathode electrode are located at a back surface of the semiconductor substrate.

14. The integrated circuit of claim 1, wherein a thickness of the first region is greater than a thickness of the second region. 15 . The integrated circuit according to claim 1 , wherein a depth of a bottom of the third region is greater than a depth of a bottom of the fourth region.

16. The integrated circuit of claim 1, wherein a width of the first gate is smaller than a width of the second gate.

17. The integrated circuit of claim 1, wherein a depth of the first gate is greater than a depth of the second gate.

18. The integrated circuit of claim 1, wherein the second thickness and the depth and doping level of the fourth region are process tuned to set a forward voltage drop of the diode device to be less than a forward voltage drop of the body diode of the MOSFET device.

19. An integrated circuit comprising: a semiconductor layer doped with a first type of dopant; MOSFET devices, including: a drain region formed by the semiconductor layer; a body region within the semiconductor layer; a source region in the semiconductor layer; and a first insulating trench extending through the source region and the body region and including a first gate; Diode devices, including: a cathode region formed by the semiconductor layer; an anode region within the semiconductor layer; and a second insulating trench extending through the anode region and including a second gate; a first metal layer in electrical contact with the semiconductor layer to form a drain electrode for the MOSFET device and a cathode electrode for the diode device; a second metal layer in electrical contact with the first gate to form a gate electrode for the MOSFET device; a third metal layer in electrical contact with the source region to form a source electrode for the MOSFET device; and A fourth metal layer is electrically contacted with the anode region and the second gate to form an anode electrode for the anode device.

20. The integrated circuit of claim 19, wherein the third metal layer is electrically connected to the fourth metal layer such that the diode device is electrically connected in parallel with a body diode of the MOSFET device.

21. The integrated circuit of claim 20, wherein a forward voltage drop of the diode device is less than a forward voltage drop of the body diode of the MOSFET device.

22. The integrated circuit of claim 19, wherein the first isolation trench and the second isolation trench are the same isolation trench.

23. The integrated circuit of claim 19, wherein the first isolation trench and the second isolation trench are different isolation trenches.

24. The integrated circuit of claim 19, wherein the first gate of the first insulating trench is separated from the source region and the body region by a first gate oxide layer having a first thickness, and wherein the second gate of the second insulating trench is separated from the anode region by a second gate oxide layer having a second thickness less than the first thickness.

25. The integrated circuit according to claim 24: The MOSFET device further comprises a first field plate, which is located in the first insulating trench and is separated from the first gate by a first inserted oxide layer; and The diode device further includes a second field plate, which is located in the second insulating trench and is separated from the second gate by a second inserted oxide layer.

26. The integrated circuit according to claim 25: wherein the third metal layer is also in electrical contact with the first field plate; and The fourth metal layer is also in electrical contact with the second field plate.

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