Pixel

Abstract

The present disclosure relates to a pixel, the pixel comprising: a switching transistor, transmitting a data voltage to a first node; a storage capacitor, electrically connected between a first power supply line and the first node and storing the data voltage; a first driving transistor and a second driving transistor, electrically connected to the first power supply line, the first node and the second node; and a first light-emitting element and a second light-emitting element, electrically connected between the second node and the second power supply line. The anode of the first light-emitting element and the cathode of the second light-emitting element are electrically connected to the second node, the cathode of the first light-emitting element and the anode of the second light-emitting element are electrically connected to the second power supply line, the first driving transistor is a P-type transistor, and the second driving transistor is an N-type transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is the national phase of International Application No. PCT / KR2020 / 002700 filed on February 25, 2020, which claims priority to and the benefit of Korean Patent Application No. 10-2019-0024668 filed on March 4, 2019 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to pixels capable of improving the efficiency of a display device and methods for driving the pixels. Background Art

[0004] Light-emitting elements (e.g., light-emitting diodes) have high light conversion efficiency, significantly low energy consumption, and semi-permanent lifespan, and are environmentally friendly. Therefore, light-emitting elements can be used in many fields, such as traffic lights, mobile phones, car headlights, outdoor electronic signs, backlights, and indoor and outdoor lighting.

[0005] Recently, research and development have been conducted on display devices using ultra-small light-emitting elements of a nanometer size as light-emitting elements.

[0006] Nano-light-emitting elements are usually deposited on a substrate by an ink printing method. With this technology, it is difficult to deposit nano-light-emitting elements biased in the same direction in each pixel. Therefore, there is a problem that nano-light-emitting elements biased in the reverse direction may not emit light by the direct current drive of the pixel, thereby reducing the luminous efficiency.

[0007] It should be understood that this background technology section is intended, in part, to provide a useful background for understanding the technology. However, this background technology section may also include ideas, concepts or understandings of a part that was not known or understood by a person skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0008] Embodiments of the present disclosure may relate to a pixel capable of improving light emission efficiency and a method of driving the pixel.

[0009] According to an embodiment of the present disclosure, a pixel may include: a switching transistor, which transmits a data voltage to a first node; a storage capacitor, which is electrically connected between a first power supply line and a first node, and the storage capacitor stores the data voltage; a first driving transistor, which is electrically connected to the first power supply line, the first node, and the second node; a second driving transistor, which is electrically connected to the first power supply line, the first node, and the second node; a first light-emitting element, which is electrically connected between the second node and the second power supply line; and a second light-emitting element, which is electrically connected between the second node and the second power supply line, wherein an anode of the first light-emitting element and a cathode of the second light-emitting element may be electrically connected to the second node, a cathode of the first light-emitting element and an anode of the second light-emitting element may be electrically connected to the second power supply line, the first driving transistor may be a P-type transistor, the second driving transistor may be an N-type transistor, a gate of the first driving transistor and a gate of the second driving transistor may be electrically connected to the first node, a source of the first driving transistor and a source of the second driving transistor may be electrically connected to the first power supply line, and a drain of the first driving transistor and a drain of the second driving transistor may be electrically connected to the second node.

[0010] In an embodiment, the gate of the switching transistor can be electrically connected to a scan line to which a scan signal is applied, one of the source and the drain of the switching transistor can be electrically connected to a data line to which a data voltage is applied, and the other of the source and the drain of the switching transistor can be electrically connected to the first node.

[0011] In an embodiment, each of the first light emitting element and the second light emitting element may include a light emitting diode having a nano-size.

[0012] In an implementation, the first driving transistor may be a PMOS, and the second driving transistor may be an NMOS.

[0013] In an embodiment, in the first period, the first driving voltage applied to the first power line may be higher than the second driving voltage applied to the second power line, and in the second period, the first driving voltage applied to the first power line may be lower than the second driving voltage applied to the second power line.

[0014] In an embodiment, the first period and the second period may be repeated alternately.

[0015] In an embodiment, in a first period, the first driving transistor may be turned on and the second driving transistor may be turned off, and in a second period, the first driving transistor may be turned off and the second driving transistor may be turned on.

[0016] In an embodiment, one of a first driving voltage applied to the first power supply line and a second driving voltage applied to the second power supply line may maintain a constant value during a first period and a second period.

[0017] In an embodiment, each of the first period and the second period may correspond to a portion of one frame.

[0018] In an embodiment, each of the first period and the second period may correspond to at least one frame.

[0019] In an embodiment, a ratio of the second period to the first period may be substantially equal to a ratio of the number of the second light emitting elements to the number of the first light emitting elements.

[0020] In an embodiment, the pixel may further include an initialization transistor electrically connected to the second node, wherein a gate of the initialization transistor may be electrically connected to a scan line to which a scan signal is applied, one of a source and a drain of the initialization transistor may be electrically connected to the second node, and the other of the source and the drain of the initialization transistor may be electrically connected to an initialization power line.

[0021] In an embodiment, the pixel may further include an initialization transistor electrically connected to the second node, wherein a gate of the initialization transistor may be electrically connected to a scan line to which a scan signal is applied, one of a source and a drain of the initialization transistor may be electrically connected to the second node, and the other of the source and the drain of the initialization transistor may be electrically connected to a second power supply line.

[0022] According to an embodiment of the present disclosure, a pixel may include: a switching transistor, transmitting a data voltage to a first node; a first storage capacitor, electrically connected between a (1-1)th power supply line and the first node, the first storage capacitor storing the data voltage; a second storage capacitor, electrically connected between a (1-2)th power supply line and the first node, the second storage capacitor storing the data voltage; a first driving transistor, electrically connected to the (1-1)th power supply line, the first node, and the second node; a second driving transistor, electrically connected to the (1-2)th power supply line, the first node, and the second node, a first light-emitting element, electrically connected between the second node and the second power supply line; and a second light-emitting element, electrically connected to the (1-2)th power supply line. The first light emitting element and the second light emitting element are connected between a first node and a second power supply line, wherein the anode of the first light emitting element and the cathode of the second light emitting element can be electrically connected to the second node, the cathode of the first light emitting element and the anode of the second light emitting element can be electrically connected to the second power supply line, the first driving transistor can be a P-type transistor, the second driving transistor can be an N-type transistor, the gate of the first driving transistor and the gate of the second driving transistor can be electrically connected to the first node, the source of the first driving transistor can be electrically connected to the (1-1)th power supply line, the source of the second driving transistor can be electrically connected to the (1-2)th power supply line, and the drain of the first driving transistor and the drain of the second driving transistor can be electrically connected to the second node.

[0023] In an embodiment, the gate of the switching transistor can be electrically connected to a scan line to which a scan signal is applied, one of the source and the drain of the switching transistor can be electrically connected to a data line to which a data voltage is applied, and the other of the source and the drain of the switching transistor can be electrically connected to the first node.

[0024] In an embodiment, each of the first light emitting element and the second light emitting element may include a light emitting diode having a nano-size.

[0025] In an implementation, the first driving transistor may be a PMOS, and the second driving transistor may be an NMOS.

[0026] In an embodiment, in a first period, the first driving transistor may be turned on or off and the second driving transistor may be turned off, in a second period, the first driving transistor may be turned off and the second driving transistor may be turned on or off, and the first period and the second period may be repeated alternately.

[0027] In an embodiment, in the first time period and the second time period, the (1-1)th driving voltage applied to the (1-1)th power supply line may be higher than the second driving voltage applied to the second power supply line, and the (1-2)th driving voltage applied to the (1-2)th power supply line may be lower than the second driving voltage applied to the second power supply line.

[0028] In an embodiment, in the first period, the data voltage may be lower than a value obtained by adding the threshold voltage of the second driving transistor to the (1-2)th driving voltage, and in the second period, the data voltage may be higher than a value obtained by subtracting the threshold voltage of the second driving transistor from the (1-1)th driving voltage.

[0029] In an embodiment, each of the first period and the second period may correspond to a portion of one frame.

[0030] In an embodiment, each of the first period and the second period may correspond to at least one frame.

[0031] In an embodiment, a ratio of the second period to the first period may be substantially equal to a ratio of the number of the second light emitting elements to the number of the first light emitting elements.

[0032] In an embodiment, in a first time period, a (1-1)th driving voltage applied to a (1-1)th power supply line may be higher than a second driving voltage applied to a second power supply line, and in a second time period, the (1-1)th power supply line may float, and in the second time period, a (1-2)th driving voltage applied to a (1-2)th power supply line may be lower than a second driving voltage applied to the second power supply line, and in the first time period, the (1-2)th power supply line may float.

[0033] In an embodiment, in a first time period, a (1-1)th driving voltage applied to a (1-1)th power supply line may be higher than a second driving voltage applied to a second power supply line, in a second time period, a (1-2)th driving voltage applied to a (1-2)th power supply line may be lower than the second driving voltage applied to the second power supply line, the (1-1)th driving voltage applied to the (1-1)th power supply line in at least a portion of the second time period may be substantially equal to the (1-2)th driving voltage applied to the (1-2)th power supply line in the second time period, and the (1-2)th driving voltage applied to the (1-2)th power supply line in at least a portion of the first time period may be substantially equal to the (1-1)th driving voltage applied to the (1-1)th power supply line in the first time period.

[0034] In an embodiment, the pixel may further include an initialization transistor connected to the second node, wherein a gate of the initialization transistor may be electrically connected to a scan line to which a scan signal is applied, one of a source and a drain of the initialization transistor may be electrically connected to the second node, and the other of the source and the drain of the initialization transistor may be electrically connected to an initialization power line.

[0035] In an embodiment, the pixel may further include an initialization transistor electrically connected to the second node, wherein a gate of the initialization transistor may be electrically connected to a scan line to which a scan signal is applied, one of a source and a drain of the initialization transistor may be electrically connected to the second node, and the other of the source and the drain of the initialization transistor may be electrically connected to a second power supply line.

[0036] In an embodiment, the pixel may further include an initialization transistor electrically connected to the first node, wherein a gate of the initialization transistor may be electrically connected to a scan line to which a previous scan signal is applied, one of a source and a drain of the initialization transistor may be electrically connected to the first node, and the other of the source and the drain of the initialization transistor may be electrically connected to an initialization power line.

[0037] In an embodiment, the pixel may further include an initialization transistor electrically connected to the first node, wherein the gate of the initialization transistor may be electrically connected to a scan line to which a previous scan signal is applied, one of the source and the drain of the initialization transistor may be electrically connected to the first node, and the other of the source and the drain of the initialization transistor may be electrically connected to an initialization power line, and when the previous scan signal is applied in the second period, an initialization voltage substantially equal to the (1-1)th drive voltage may be applied to the initialization power line, and when the previous scan signal is applied in the first period, an initialization voltage substantially equal to the (1-2)th drive voltage may be applied to the initialization power line.

[0038] According to one or more embodiments of the present disclosure, a pixel and a method of driving the pixel may provide the following and other effects.

[0039] According to an embodiment, light emitting elements that can be biased in opposite directions in a pixel can emit light alternately. Therefore, the light emitting efficiency of a display device including the pixel can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic diagram showing a display device according to an embodiment.

[0041] Figure 2 is a schematic circuit diagram showing a circuit arranged as a pixel according to an embodiment.

[0042] Figure 3 It is shown Figure 1 Schematic plan view of three adjacent pixels.

[0043] Figure 4 is along Figure 3 A schematic cross-sectional view taken along line II'.

[0044] Figure 5 It is shown Figure 3 A schematic detailed view of any one light emitting element.

[0045] Figure 6 It is shown Figure 2 A schematic diagram of an implementation of a timing diagram of a circuit diagram.

[0046] Figure 7 It is shown Figure 2 A schematic diagram of another embodiment of a timing diagram of a circuit diagram.

[0047] Figure 8 It is shown that during the first period Figure 2 A schematic circuit diagram of the equivalent circuit of the circuit diagram.

[0048] Fig. 9 It is shown that during the second period Figure 2 A schematic circuit diagram of the equivalent circuit of the circuit diagram.

[0049] Fig.10 is a schematic circuit diagram showing a circuit further including a light emitting element initialization circuit according to an embodiment.

[0050] Fig.11 is a schematic circuit diagram showing a circuit further including a light emitting element initialization circuit according to another embodiment.

[0051] Fig.12 is a schematic circuit diagram showing a circuit arranged as a pixel according to another embodiment.

[0052] Fig.13 It is shown Fig.12 A schematic diagram of an implementation of a timing diagram of a circuit diagram.

[0053] Fig.14 It is shown that during the first period Fig.12 A schematic circuit diagram of the equivalent circuit of the circuit diagram.

[0054] Fig.15 It is shown that during the second period Fig.12 A schematic circuit diagram of the equivalent circuit of the circuit diagram.

[0055] Fig.16 It is shown Fig.12 A schematic diagram of an implementation of a timing diagram of a circuit diagram.

[0056] Fig.17 It is shown Fig.12 A schematic diagram of another embodiment of a timing diagram of a circuit diagram.

[0057] Fig.18 is a schematic circuit diagram showing a circuit further including a light emitting element initialization circuit according to an embodiment.

[0058] Fig.19 is a schematic circuit diagram showing a circuit further including a light emitting element initialization circuit according to another embodiment.

[0059] Fig. 20 is a schematic circuit diagram illustrating a circuit further including a storage capacitor initialization circuit according to an embodiment of the present disclosure.

[0060] Fig.21 It is shown Fig. 20 A schematic diagram of an implementation of a timing diagram of a circuit diagram. DETAILED DESCRIPTION

[0061] From the embodiments described in detail below with reference to the accompanying drawings, it will be clear that the advantages and features of the present disclosure and the methods for realizing them. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. The elements, operations, and techniques that will be understood by those of ordinary skill in the art may not be described in detail in the embodiments to prevent the present disclosure from being obscured. Throughout the specification, the same reference numerals represent the same elements.

[0062] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well (and conversely, the plural forms are intended to include forms as well), unless the context clearly indicates otherwise. The terms "overlapping" or "overlapping" mean that a first object can be above or below a second object or on one side of the second object, and conversely, a second object can be above or below a first object or on one side of the first object. Additionally, the term "overlapping" may include layer, stack, facing or facing, extending throughout, covering or partially covering, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art.

[0063] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or". In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0064] It should be understood that the term "connected to" or "coupled to" may include a physical connection or an electrical connection or a physical connection or an electrical connection. When an element is referred to as being "connected" to another element, the element may be "directly connected" to the other element, or "electrically connected" to the other element, with one or more intervening elements interposed therebetween. It should also be understood that terms such as "comprises", "including", "includes", "have", "has" and / or "having" used in this specification specify the presence of the features, wholes, steps, operations, elements and / or components set forth, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0065] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings herein, the "first element" discussed below may be referred to as the "second element" or the "third element", and the "second element" and the "third element" may also be referred to as the "third element".

[0066] As used herein, "about," "approximately," and "substantially" are inclusive of the stated values ​​and mean values ​​within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0067] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal meaning unless explicitly defined in the specification.

[0068] In the following, reference will be made to Figures 1 to 21 A display device according to an embodiment of the present disclosure is described.

[0069] Figure 1 is a schematic diagram showing a display device according to an embodiment.

[0070] like Figure 1 As shown in , the display device according to the embodiment may include a display panel 111 , a scan driver 151 , a data driver 153 , a timing controller 122 , a lookup table LUT, and a power supply part 123 .

[0071] The display panel 111 may include pixels PX and scan lines SL1 to SLi, data lines DL1 to DLj, and power supply lines VL for transmitting various signals required for the pixels PX to display images. In such an embodiment, i may be a natural number greater than 2, and j may be a natural number greater than 3. According to an embodiment, the power supply line VL may include a first power supply line VDL and a second power supply line VSL that may be electrically separated from each other. According to an embodiment, the first power supply line VDL may include a (1-1)th power supply line VDL1 and a (1-2)th power supply line VDL2 that may be electrically separated from each other.

[0072] The pixels PX may be arranged in a matrix form at the display panel 111 .

[0073] Each pixel PX may include at least one light emitting element (eg, a light emitting diode). At least some of the pixels PX may include light emitting elements LEDs connected in parallel and biased in opposite directions (see Figure 2 ).

[0074] At least two pixels PX among all pixels PX (eg, i×j pixels PX) may include different numbers of light emitting elements LED. For example, if one pixel PX includes five light emitting elements LED connected in parallel, another pixel PX may include one light emitting element LED.

[0075] At least one pixel PX among all the pixels PX may include at least one first light emitting element LED1 that may be arranged (biased) in a forward direction and at least one second light emitting element LED2 that may be arranged (biased) in a reverse direction. For example, if the pixel PX includes five light emitting elements LED, three first light emitting elements LED1 may be arranged in a forward direction, and the other two second light emitting elements LED2 may be arranged in a reverse direction. The first light emitting element LED1 refers to an element that emits light by a positive current flowing from a first power supply line VDL to a second power supply line VSL (hereinafter, the direction of the current may be referred to as a forward direction, and the opposite direction may be referred to as a reverse direction), and the second light emitting element LED2 refers to an element that emits light by a current flowing from the second power supply line VSL to the first power supply line VDL.

[0076] At least two pixels PX among all the pixels PX may include different numbers of first light emitting elements LED1. At least two pixels PX among all the pixels PX may include different numbers of second light emitting elements LED2. The ratio of the first light emitting element LED1 to the second light emitting element LED2 included in one pixel PX may be equal to or different from the ratio of the first light emitting element LED1 to the second light emitting element LED2 included in another pixel PX.

[0077] The pixels PX may include a red pixel PX displaying red, a green pixel PX displaying green, and a blue pixel PX displaying blue.

[0078] The red pixel PX may include at least one red light emitting element emitting red light, the green pixel PX may include at least one green light emitting element emitting green light, and the blue pixel PX may include at least one blue light emitting element emitting blue light.

[0079] Information about the number of first light-emitting elements LED1 and the number of second light-emitting elements LED2 included in each pixel PX may be pre-stored in the lookup table LUT. For example, information about the number of first light-emitting elements LED1 and the number of second light-emitting elements LED2 included in each of i×j pixels PX and their ratio may be pre-stored in the lookup table LUT. For example, in this lookup table LUT, information about the number of first light-emitting elements LED1 and the number of second light-emitting elements LED2 included in all i×j pixels PX and their ratio may be pre-stored.

[0080] Information about the number of first light-emitting elements LED1 and the number of second light-emitting elements LED2 included in each pixel PX (or the ratio between the numbers) or the number of first light-emitting elements LED1 and the number of second light-emitting elements LED2 included in all pixels PX (or the ratio between the numbers) can be obtained through a photo taken by a camera or the magnitude and direction of the current detected from each pixel PX of the display panel 111. For example, as the number of first light-emitting elements LED1 in the pixel PX or all pixels PX increases, the forward current detected from the pixel PX or all pixels PX may increase. Similarly, as the number of second light-emitting elements LED2 increases, the reverse current may increase.

[0081] A system (not shown) positioned outside the display panel 111 may output a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, a power signal VCC, and an image data voltage DATA through a low voltage differential signaling (LVDS) transmitter of a graphic controller. The vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the clock signal DCLK, and the power signal VCC output from the system may be applied to the timing controller 122. The image data voltage DATA sequentially output from the system may be applied to the timing controller 122.

[0082] The timing controller 122 may correct each of the image data voltages DATA of the pixel PX applied from the above system to generate a corrected image data voltage DATA', and apply the corrected image data voltage DATA' to the data driver 153. In such an embodiment, the timing controller 122 may correct the image data voltage DATA of the corresponding pixel PX based on the number of the first light emitting elements LED1 and the number of the second light emitting elements LED2 included in the corresponding pixel PX and the ratio between the numbers. For example, the timing controller 122 may identify the number of the first light emitting elements LED1 and the number of the second light emitting elements LED2 of the corresponding pixel PX and the ratio therebetween based on the information provided from the lookup table LUT, and may correct the image data voltage DATA of the corresponding pixel PX based on the identified number of the light emitting elements LED1 and LED2 and the ratio therebetween.

[0083] The timing controller 122 may generate a data control signal DCS and a scan control signal SCS by using a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal DCLK input to the timing controller 122, and provide them to the data driver 153 and the scan driver 151. The data control signal DCS may be applied to the data driver 153, and the scan control signal SCS may be applied to the scan driver 151.

[0084] The data control signal DCS may include a dot clock signal, a source shift clock signal, a source enable signal, and a polarity inversion signal.

[0085] The scan control signal SCS may include a gate start pulse signal, a gate shift clock signal, and a gate output enable signal.

[0086] After sampling the corrected image data voltage DATA' according to the data control signal DCS from the timing controller 122, the data driver 153 may sample the analog data voltage Vdata of one horizontal line for each horizontal period (horizontal time 1H, 2H, ...), and apply the latched analog data voltage Vdata to the data lines DL1 to DLj. For example, the data driver 153 may convert the corrected image data voltage DATA' from the timing controller 122 into the analog data voltage Vdata using the gamma voltage input from the power supply unit 123, and apply the converted analog data voltage Vdata to the data lines DL1 to DLj. The analog data voltages Vdata respectively applied to the data lines DL1 to DLj will be referred to as data voltages Vdata hereinafter.

[0087] The scan driver 151 may include a shift register for generating a scan signal in response to a gate start pulse signal from the timing controller 122, and a level shifter for shifting the scan signal to a voltage level suitable for driving the pixel PX. The scan driver 151 may provide the first to i-th scan signals Scan to the scan lines SL1 to SLi, respectively, in response to a scan control signal SCS from the timing controller 122.

[0088] The power supply unit 123 may generate a gamma voltage, a first driving voltage VDD, and a second driving voltage VSS by using a power signal VCC. The power supply unit 123 may provide the gamma voltage to the data driver 153, provide the first driving voltage VDD to the first power supply line VDL, and provide the second driving voltage VSS to the second power supply line VSL. The power supply unit 123 may include a first power supply unit that provides the first driving voltage VDD and a second power supply unit that provides the second driving voltage VSS. The power supply unit 123 may provide the (1-1)th driving voltage VDD1 to the (1-1)th power supply line VDL1, and provide the (1-2)th driving voltage VDD2 to the (1-2)th power supply line VDL2. The power supply unit 123 may include a (1-1)th power supply unit that provides the (1-1)th driving voltage VDD1 and a (1-2)th power supply unit that provides the (1-2)th driving voltage VDD2.

[0089] Figure 2 is a schematic circuit diagram showing a circuit arranged as a pixel according to an embodiment.

[0090] refer to Figure 2 , the pixel PX may include a first light emitting element LED1 and a second light emitting element LED2 and a pixel circuit that may selectively apply a driving current to the first light emitting element LED1 and the second light emitting element LED2.

[0091] The pixel circuit may include a switching circuit transmitting a data voltage Vdata applied to a data line (eg, an mth data line DLm), a storage circuit storing the transmitted data voltage Vdata, and a driving circuit controlling the first and second light emitting elements LED1 and LED2 according to the stored data voltage Vdata.

[0092] The switching circuit may include a switching transistor ST connected to a data line (e.g., an mth data line DLm), a scan line (e.g., an nth scan line SLn), and a first node N1. The storage circuit may include a storage capacitor Cst connected to the first node N1 and a first power supply line VDL. The driving circuit may be connected to each of the first node N1, the first power supply line VDL, and the second node N2, respectively, and include a first driving transistor DT1 and a second driving transistor DT2 that may be complementary types to each other.

[0093] The light emitting element LED may include Figure 5 The nano-sized ultra-small light-emitting diode shown in . The light-emitting element LED may include at least two light-emitting elements LED1 and LED2, each of which may be connected to a second node N2 and a second power supply line VSL, and may be biased opposite to each other. The light-emitting element LED may include a first light-emitting element LED1 and a second light-emitting element LED2. The anode of the first light-emitting element LED1 and the cathode of the second light-emitting element LED2 may be connected to the second node N2, and the cathode of the first light-emitting element LED1 and the anode of the second light-emitting element LED2 may be connected to the second power supply line VSL.

[0094] The first light emitting element LED1 and the second light emitting element LED2 may alternately emit light according to the first driving voltage VDD, the second driving voltage VSS, and the data voltage Vdata of the first node N1.

[0095] In the following, reference will be made to Figure 2 Describe in detail the connection relationship between each transistor and the light-emitting element.

[0096] The switching transistor ST may include a first gate electrode connected to the nth scan line SLn, and may be connected between the mth data line DLm and the first node N1. One of the first source electrode and the first drain electrode of the switching transistor ST may be connected to the mth data line DLm, and the other of the first source electrode and the first drain electrode may be connected to the first node N1. For example, the first source electrode of the switching transistor ST may be connected to the mth data line DLm, and the first drain electrode of the switching transistor ST may be connected to the first node N1. In such an embodiment, m may be a natural number. The switching transistor ST may be a P-type or N-type transistor. The switching transistor ST may be a PMOS or NMOS transistor.

[0097] The first drive transistor DT1 includes a second gate electrode connected to the first node N1, and may be connected between the first power supply line VDL and the second node N2. In an embodiment, the first drive transistor DT1 may be a P-type transistor or a PMOS transistor. One of the second source electrode and the second drain electrode of the first drive transistor DT1 may be connected to the first power supply line VDL, and the other of the second source electrode and the second drain electrode may be connected to the second node N2. For example, the second source electrode of the first drive transistor DT1 may be connected to the first power supply line VDL, and the second drain electrode of the first drive transistor DT1 may be connected to the second node N2. The first drive transistor DT1 may control the magnitude of the current flowing from the first power supply line VDL to the second node N2 (the current flowing from the second source electrode to the second drain electrode) according to the data voltage Vdata applied to the second gate electrode.

[0098] The second drive transistor DT2 may include a third gate electrode connected to the first node N1, and may be connected between the first power supply line VDL and the second node N2. In an embodiment, the second drive transistor DT2 may be an N-type transistor or an NMOS transistor. In an embodiment, the first drive transistor DT1 and the second drive transistor DT2 may be mutually complementary transistors, such as CMOS transistors. One of the third source electrode and the third drain electrode of the second drive transistor DT2 may be connected to the first power supply line VDL, and the other of the third source electrode and the third drain electrode may be connected to the second node N2. For example, the third source electrode of the second drive transistor DT2 may be connected to the first power supply line VDL, and the third drain electrode of the second drive transistor DT2 may be connected to the second node N2. The second drive transistor DT2 may control the magnitude of the current (current flowing from the third drain electrode to the third source electrode) flowing from the second node N2 to the first power supply line VDL according to the data voltage Vdata applied to the third gate electrode.

[0099] The storage capacitor Cst may be connected between the first node N1 and the first power supply line VDL. The storage capacitor Cst may store the data voltage Vdata applied to the first node N1, that is, the data voltage Vdata applied to the second gate electrode of the first driving transistor DT1 and the third gate electrode of the second driving transistor DT2, within one frame or a partial period of one frame.

[0100] Figure 3 It is shown Figure 1 A schematic plan view of three adjacent pixels of Figure 4 is along Figure 3 A schematic cross-sectional view taken along line II'.

[0101] like Figure 3 and Figure 4 As shown in FIG. 1 , the display device may include a substrate 301, a buffer layer 302, a first gate insulating film 303a, a second gate insulating film 303b, an insulating interlayer 304, a planarizing layer 305, a switching transistor ST, a first driving transistor DT1 (P-type transistor, PMOS transistor), a second driving transistor DT2 (although in FIG. Figure 4 Not shown in the figure, but except that the second driving transistor DT2 can be an N-type transistor, an NMOS transistor, the second driving transistor DT2 has the same structure and connection relationship with other elements as the first driving transistor DT1) and the dummy layer 320.

[0102] The switching transistor ST may include a first semiconductor layer 321 , a first gate electrode GE1 , a first source electrode SE1 , and a first drain electrode DE1 .

[0103] The first driving transistor DT1 may include a second semiconductor layer 322 , a second gate electrode GE2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0104] The second driving transistor DT2 may include a third semiconductor layer (not shown), a third gate electrode (not shown), a third source electrode (not shown), and a third drain electrode (not shown).

[0105] The buffer layer 302 may be positioned on the substrate 301. The buffer layer 302 may overlap the entire surface of the substrate 301.

[0106] The first semiconductor layer 321 , the second semiconductor layer 322 , a third semiconductor layer (not shown), and the dummy layer 320 may be positioned on the buffer layer 302 .

[0107] The first gate insulating film 303a may be disposed (ie, positioned) on the first semiconductor layer 321, the second semiconductor layer 322, the third semiconductor layer (not shown), and the buffer layer 302. The first gate insulating film 303a may overlap the entire surface of the substrate 301.

[0108] The first gate electrode GE1, the second gate electrode GE2, the third gate electrode (not shown), and the second power supply line VSL may be positioned on the first gate insulating film 303a. In such an embodiment, the first gate electrode GE1 may be positioned on the first gate insulating film 303a to overlap with the channel region C1 of the first semiconductor layer 321, the second gate electrode GE2 may be positioned on the first gate insulating film 303a to overlap with the channel region C2 of the second semiconductor layer 322, the third gate electrode (not shown) may be positioned on the first gate insulating film 303a to overlap with the channel region (not shown) of the third semiconductor layer (not shown), and the second power supply line VSL may be positioned on the first gate insulating film 303a to overlap with the dummy layer 320.

[0109] The second gate insulating film 303 b may be positioned on the first gate electrode GE1 , the second gate electrode GE2 , the third gate electrode (not shown), the second power supply line VSL, and the first gate insulating film 303 a . The second gate insulating film 303 b may overlap the entire surface of the substrate 301 .

[0110] The first power supply line VDL may be positioned on the second gate insulating film 303b. The first power supply line VDL may be positioned on the second gate insulating film 303b to overlap with the second gate electrode GE2 and the third gate electrode (not shown). The storage capacitor Cst may be positioned between the first power supply line VDL and the second gate electrode GE2 and between the first power supply line VDL and the third gate electrode (not shown).

[0111] The insulating interlayer 304 may be positioned on the first power supply line VDL and the second gate insulating film 303 b . The insulating interlayer 304 may overlap the entire surface of the substrate 301 .

[0112] The first source electrode SE1 , the first drain electrode DE1 , the second source electrode SE2 , the second drain electrode DE2 , the third source electrode (not shown), the third drain electrode (not shown), and the connection electrode 340 may be positioned on the insulating interlayer 304 .

[0113] The first source electrode SE1 may be connected to the first source region S1 of the first semiconductor layer 321 through a first source contact hole defined through the insulating interlayer 304 , the second gate insulating film 303 b , and the first gate insulating film 303 a .

[0114] The first drain electrode DE1 may be connected to the first drain region D1 of the first semiconductor layer 321 through a first drain contact hole defined through the insulating interlayer 304, the second gate insulating film 303b, and the first gate insulating film 303a. Although not shown, the first drain electrode DE1 may be connected to the second gate electrode GE2 and the third gate electrode (not shown) through corresponding contact holes defined through the insulating interlayer 304 and the second gate insulating film 303b.

[0115] The second source electrode SE2 may be connected to the second source region S2 of the second semiconductor layer 322 through a second source contact hole defined through the insulating interlayer 304, the second gate insulating film 303b, and the first gate insulating film 303a. Although not shown, the second source electrode SE2 may be connected to the first power supply line VDL through a contact hole defined through the insulating interlayer 304.

[0116] The second drain electrode DE2 may be connected to the second drain region D2 of the second semiconductor layer 322 through a second drain contact hole defined through the insulating interlayer 304 , the second gate insulating film 303 b , and the first gate insulating film 303 a .

[0117] The third source electrode (not shown) may be connected to a third source region (not shown) of the third semiconductor layer (not shown) through a third source contact hole defined through the insulating interlayer 304, the second gate insulating film 303b, and the first gate insulating film 303a. The third source electrode (not shown) may be connected to the first power supply line VDL through a contact hole defined through the insulating interlayer 304.

[0118] The third drain electrode (not shown) may be connected to a third drain region (not shown) of the third semiconductor layer (not shown) through a third drain contact hole defined through the insulating interlayer 304 , the second gate insulating film 303 b , and the first gate insulating film 303 a .

[0119] The connection electrode 340 may be connected to the second power supply line VSL through a contact hole defined through the insulating interlayer 304 and the second gate insulating film 303 b .

[0120] The planarization layer 305 may be positioned on the first source electrode SE1 , the first drain electrode DE1 , the second source electrode SE2 , the second drain electrode DE2 , the third source electrode (not shown), the third drain electrode (not shown), the connection electrode 340 , and the insulating interlayer 304 .

[0121] A first electrode portion 351 and a second electrode portion 352 may be positioned on the planarization layer 305 .

[0122] The first electrode portion 351 may be connected to the second drain electrode DE2 and the third drain electrode (not shown) through a first contact hole defined through the planarization layer 305 .

[0123] The second electrode portion 352 may be connected to the connection electrode 340 through a second contact hole defined through the planarization layer 305. The second electrode portion 352 may be connected to the second power supply line VSL through the connection electrode 340.

[0124] The light emitting element LED may be positioned on the first electrode portion 351, the second electrode portion 352, and the planarization layer 305. For example, an anode electrode of the first light emitting element LED1 may be connected to the first electrode portion 351, and a cathode electrode of the first light emitting element LED1 may be connected to the second electrode portion 352. A cathode electrode of the second light emitting element LED2 may be connected to the first electrode portion 351, and an anode electrode of the second light emitting element LED2 may be connected to the second electrode portion 352.

[0125] The first pixel PX1, the second pixel PX2, and the third pixel PX3 may include light emitting elements LED emitting light of different colors. For example, the light emitting element LED of the first pixel PX1 may be a red light emitting element emitting red light, the light emitting element LED of the second pixel PX2 may be a green light emitting element emitting green light, and the light emitting element LED of the third pixel PX3 may be a blue light emitting element emitting blue light.

[0126] like Figure 3 As shown in , the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include different numbers of light-emitting elements LED. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may include different numbers of first light-emitting elements LED1. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may include different numbers of second light-emitting elements LED2. The ratio of the first light-emitting element LED1 to the second light-emitting element LED2 of one pixel PX may be substantially the same as or different from the ratio of the first light-emitting element LED1 to the second light-emitting element LED2 of another pixel PX. For example, the first pixel PX1 may include three first light-emitting elements LED1 and two second light-emitting elements LED2, the second pixel PX2 may include two first light-emitting elements LED1 and two second light-emitting elements LED2, and the third pixel PX3 may include one first light-emitting element LED1 and two second light-emitting elements LED2.

[0127] The first contact electrode 371 may connect the first electrode portion 351 and the anode ANO of the first light emitting element LED1 to each other, and connect the first electrode portion 351 and the cathode CAT of the second light emitting element LED2 to each other. The second contact electrode 372 may connect the second electrode portion 352 and the anode ANO of the second light emitting element LED2 to each other, and connect the second electrode portion 352 and the cathode CAT of the first light emitting element LED1 to each other. The light blocking film 306 may be positioned on the planarization layer 305. The light blocking film 306 may have an opening 355 defining the region of the pixel PX. The light emitting element LED described above may be positioned in the region of the pixel PX.

[0128] A spacer 307 may be positioned on the light blocking film 306. The width of the spacer 307 may be smaller than the width of the light blocking film 306, and the thickness of the spacer 307 may be greater than the thickness of the light blocking film 306. The width of the spacer 307 and the width of the light blocking film 306 refer to dimensions in the X-axis direction, and the thickness of the spacer 307 and the thickness of the light blocking film 306 refer to dimensions in the Z-axis direction.

[0129] A passivation film 308 may be positioned on the light blocking film 306 , the light emitting element LED, the first electrode portion 351 , the second electrode portion 352 , the first contact electrode 371 , the second contact electrode 372 , and the planarization layer 305 .

[0130] An anti-reflection film 309 may be positioned on the passivation film 308 and the spacer 307. The anti-reflection film 309 prevents reflection of light incident on the display device from the outside.

[0131] The first pixel PX1, the second pixel PX2, and the third pixel PX3 may include anti-reflection films 309 of different colors. For example, the anti-reflection film 309 of the first pixel PX1 may be a red anti-reflection film that prevents red light from being reflected, the anti-reflection film 309 of the second pixel PX2 may be a green anti-reflection film that prevents green light from being reflected, and the anti-reflection film 309 of the third pixel PX3 may be a blue anti-reflection film that prevents blue light from being reflected.

[0132] An encapsulation layer 310 may be positioned on the anti-reflection film 309 and the spacer 307. The encapsulation layer 310 may overlap the entire surface of the substrate 301.

[0133] Figure 5 It is shown Figure 3 A schematic detailed view of any one light emitting element.

[0134] The light emitting element LED may be, for example, an ultra-small light emitting diode of nanometer size and may have a Figure 5Although not shown, the light emitting element LED may have a quadrilateral parallelepiped shape or various other shapes.

[0135] The light emitting element LED may include a first electrode 411, a second electrode 412, a first semiconductor layer 431, a second semiconductor layer 432, and an active layer 450. In an implementation, the light emitting element LED may further include an insulating film 470 in addition to the aforementioned components 411, 412, 431, 432, and 450.

[0136] The first semiconductor layer 431 may be positioned between the first electrode 411 and the active layer 450 .

[0137] The active layer 450 may be positioned between the first semiconductor layer 431 and the second semiconductor layer 432 .

[0138] The second semiconductor layer 432 may be positioned between the active layer 450 and the second electrode 412 .

[0139] The insulating film 470 may have a ring shape surrounding a portion of the first electrode 411, a portion of the second electrode 412, the first semiconductor layer 431, the active layer 450, and the second semiconductor layer 432. As another example, the insulating film 470 may have a ring shape surrounding only the active layer 450. The insulating film 470 may prevent contact between the active layer 450 and the first electrode portion 351, and prevent contact between the active layer 450 and the second electrode portion 352. The insulating film 470 may protect the outer surface including the active layer 450 to prevent the light emitting efficiency of the light emitting element LED from being reduced.

[0140] The first electrode 411, the first semiconductor layer 431, the active layer 450, the second semiconductor layer 432, and the second electrode 412 may be sequentially stacked on each other in the length direction of the light emitting element LED. In such an embodiment, the length of the light emitting element LED may refer to the dimension in the X-axis direction. For example, the length L of the light emitting element LED may be in the range of about 2 μm to about 5 μm.

[0141] The first electrode 411 and the second electrode 412 may be ohmic contact electrodes, but the first electrode 411 and the second electrode 412 are not limited thereto and may be Schottky contact electrodes.

[0142] The first electrode 411 and the second electrode 412 may include a conductive metal. For example, the first electrode 411 and the second electrode 412 may include one or more metal materials of aluminum, titanium, indium, gold, and silver. The first electrode 411 and the second electrode 412 may include the same material. In other embodiments, the first electrode 411 and the second electrode 412 may include different materials.

[0143] The first semiconductor layer 431 may include, for example, an n-type semiconductor layer. For example, in the case where the light emitting element LED is a blue light emitting element, the n-type semiconductor layer may include a semiconductor layer having an empirical formula of In x Al y Ga 1-x-y The n-type semiconductor material may be doped with a first conductive dopant (eg, Si, Ge, Sn, etc.).

[0144] A light emitting element LED of a different color than the blue light emitting element described above may include a different type of Group III-V semiconductor material as the n-type semiconductor layer.

[0145] The first electrode 411 may be omitted. In the absence of the first electrode 411, the first semiconductor layer 431 may be connected to the first electrode portion 351. One side of the first semiconductor layer 431 including the n-type semiconductor layer may be referred to as a cathode, and the first electrode 411 contacting the first semiconductor layer 431 may be referred to as a cathode electrode.

[0146] The second semiconductor layer 432 may include, for example, a p-type semiconductor layer. For example, in the case where the light emitting element LED is a blue light emitting element, the p-type semiconductor layer may include a semiconductor layer having an empirical formula of In x Al y Ga 1-x-y The p-type semiconductor material may be doped with a second conductive dopant (eg, Mg).

[0147] The second electrode 412 may be omitted. In the absence of the second electrode 412, the second semiconductor layer 432 may be connected to the second electrode portion 352. One side of the second semiconductor layer 432 including the p-type semiconductor layer may be referred to as an anode, and the second electrode 412 contacting the second semiconductor layer 432 may be referred to as an anode electrode.

[0148] The active layer 450 may have a single quantum well structure or a multi-quantum well structure. For example, a cladding layer (not shown) doped with a conductive dopant may be disposed above or below the active layer 450, and the cladding layer (i.e., the cladding layer including the conductive dopant) may be an AlGaN layer or an InAlGaN layer. Materials such as AlGaN or AlInGaN may be used as the active layer 450. When an electric field is applied to the active layer 450 described above, light may be generated by the recombination of electron-hole pairs. The position of the active layer 450 may be changed differently depending on the type of the light emitting element LED.

[0149] The active layer of a light emitting element LED having a different color than the blue light emitting element described above may include a different type of Group III-V semiconductor material.

[0150] In an implementation, although not shown, the light emitting element LED may further include at least one of a phosphor layer, an active layer, a semiconductor layer, and electrodes above or below the first and second semiconductor layers 431 and 432 .

[0151] The anode of the first light-emitting element LED1 (i.e., the second electrode 412 or the second semiconductor layer 432 including a p-type semiconductor layer) can be connected to the second drain electrode of the first driving transistor DT1 and the third drain electrode of the second driving transistor DT2, i.e., connected to the second node N2, through the first electrode portion 351 and the first contact electrode 371, and the cathode of the first light-emitting element LED1 (i.e., the first electrode 411 or the first semiconductor layer 431 including an n-type semiconductor layer) can be connected to the second power supply line VSL through the connecting electrode 340, the second electrode portion 352 and the second contact electrode 372.

[0152] The anode of the second light-emitting element LED2 (i.e., the second electrode 412 or the second semiconductor layer 432 including a p-type semiconductor layer) can be connected to the second power supply line VSL through the connecting electrode 340, the second electrode portion 352 and the second contact electrode 372, and the cathode of the second light-emitting element LED2 (i.e., the first electrode 411 or the first semiconductor layer 431 including an n-type semiconductor layer) can be connected to the second drain electrode of the first driving transistor DT1 and the third drain electrode of the second driving transistor DT2, i.e., to the second node N2, through the first electrode portion 351 and the first contact electrode 371.

[0153] In the following, reference will be made to Figure 6 , Figure 7 , Figure 8 and Fig. 9 A method of driving a pixel PX according to an embodiment is described in detail.

[0154] Figure 6 It is shown Figure 2A schematic diagram of an implementation of a timing diagram of a circuit diagram. Figure 7 It is shown Figure 2 A schematic diagram of another embodiment of a timing diagram of a circuit diagram. Figure 8 It is shown that during the first period Figure 2 A schematic circuit diagram of the equivalent circuit of the circuit diagram. Fig. 9 It is shown that during the second period Figure 2 A schematic circuit diagram of the equivalent circuit of the circuit diagram.

[0155] The method of driving the pixel PX according to the embodiment may include a first period P1 in which the first light emitting element LED1 emits light and a second period P2 in which the second light emitting element LED2 emits light, and the first period P1 and the second period P2 may be repeated alternately.

[0156] Each of the first period P1 and the second period P2 may correspond to at least one frame period. For example, the first period P1 and the second period P2 may correspond to 4 frame periods and 2 frame periods, respectively. Each of the first period P1 and the second period P2 may correspond to a partial period of a frame. For example, the first period P1 and the second period P2 may correspond to 2 / 3 frame periods and 1 / 3 frame periods, respectively.

[0157] The first period P1 and the second period P2 may be the same as or different from each other. The ratio of the first period P1 to the second period P2 may correspond to the ratio of the number of the first light-emitting elements LED1 to the number of the second light-emitting elements LED2. For example, in the case where the number of the first light-emitting elements LED1 included in the pixel PX is n times the number of the second light-emitting elements LED2 included in the pixel PX, the first period P1 may be n times the second period P2. For example, if the number of the first light-emitting elements LED1 included in all pixels PX is n times the number of the second light-emitting elements LED2 included in all pixels PX, the first period P1 may be n times the second period P2.

[0158] During the first period P1, the first driving voltage VDD applied to the first power line VDL may be greater than the second driving voltage VSS applied to the second power line VSL, and during the second period P2, the first driving voltage VDD applied to the first power line VDL may be less than the second driving voltage VSS applied to the second power line VSL.

[0159] refer to Figure 6, in the case of entering the first period P1 from the second period P2, the first driving voltage VDD may be changed from the low level voltage VL to the high level voltage VH, and the second driving voltage VSS may be changed from the high level voltage VH to the low level voltage VL. During the first period P1, the first driving voltage VDD may be maintained as the high level voltage VH, and the second driving voltage VSS may be maintained as the low level voltage VL.

[0160] In the case of entering the second period P2 from the first period P1, the first driving voltage VDD may be changed from the high level voltage VH to the low level voltage VL, and the second driving voltage VSS may be changed from the low level voltage VL to the high level voltage VH. During the second period P2, the first driving voltage VDD may be maintained as the low level voltage VL, and the second driving voltage VSS may be maintained as the high level voltage VH. The low level voltage VL may be less than the high level voltage VH.

[0161] The timing of entering the second period P2 from the first period P1 and the timing of entering the first period P1 from the second period P2 may be synchronized with the timing when the current scan signal Scan[n] (eg, the scan signal at the current time) is applied.

[0162] refer to Figure 7 , the second driving voltage VSS may be fixed to the intermediate level voltage VM, and the first driving voltage VDD may alternate between the low level voltage VL and the high level voltage VH. The low level voltage VL may be less than the intermediate level voltage VM, and the intermediate level voltage VM may be less than the high level voltage VH. For example, in the case of entering the first period P1 from the second period P2, the first driving voltage VDD may change from the low level voltage VL to the high level voltage VH, and in the case of entering the second period P2 from the first period P1, the first driving voltage VDD may change from the high level voltage VH to the low level voltage VL. The second driving voltage VSS may maintain the intermediate level voltage VM during the first period P1 and the second period P2.

[0163] However, embodiments of the present disclosure are not limited thereto, and the first driving voltage VDD may be fixed to the middle-level voltage VM, and the second driving voltage VSS may alternate between the low-level voltage VL and the high-level voltage VH.

[0164] In the following, reference will be made to Figure 6 and Figure 8 The operation of the pixel PX during the first period P1 is described.

[0165] refer to Figure 6, the current scan signal Scan[n] applied to the corresponding scan line (e.g., the nth scan line SLn) among the scan lines SL1-SLi may be applied to the gate of the switching transistor ST, and the data voltage Vdata applied to the corresponding data line (e.g., the mth data line DLm) among the data lines DL1 to DLj may be applied to the source of the switching transistor ST. The switching transistor ST may be a P-type or N-type transistor. Hereinafter, the switching transistor ST will be described with respect to a P-type transistor.

[0166] The scan line to be driven at the current time (for example, the nth scan line SLn) may be the nth scan line SLn, and the scan signal applied to the nth scan line SLn is the scan signal Scan[n] (also referred to as the "current scan signal Scan[n]"), and the scan line driven before the current scan line may be the (n-1)th scan line SLn-1, and the scan signal applied to the (n-1)th scan line SLn-1 may be the scan signal Scan[n-1] (also referred to as the "previous scan signal Scan[n-1]").

[0167] First, when the current scan signal Scan[n] is applied (i.e., when the current scan signal Scan[n] is applied at a low level), the switching transistor ST, which may be a P-type transistor, can be turned on, and the data voltage Vdata applied to the data line (e.g., the mth data line DLm) can be transmitted to the first node N1 (the gate of the first drive transistor DT1, the gate of the second drive transistor DT2, and one end of the storage capacitor Cst) through the switching transistor ST.

[0168] The storage capacitor Cst may be charged according to the data voltage Vdata transmitted to the first node N1, and may store the charged data voltage Vdata during the first period P1. Therefore, the first node N1 (the gate of the first driving transistor DT1 and the gate of the second driving transistor DT2) may maintain the transmitted data voltage Vdata during the first period P1.

[0169] The data voltage Vdata stored in the storage capacitor Cst may be applied to the gates of the first and second drive transistors DT1 and DT2. As described above, in an embodiment, the first drive transistor DT1 may be a P-type transistor, and the second drive transistor DT2 may be an N-type transistor.

[0170] The voltage VCst stored in the storage capacitor Cst (i.e., the voltage difference Vgs1 between the gate voltage Vg1 and the source voltage Vs1 of the first driving transistor DT1) can be substantially equal to the difference between the data voltage Vdata (which can be the voltage of the first node N1 connected to the gate of the first driving transistor DT1) and the first driving voltage VDD applied to the first power supply line VDL (which is connected to the source of the first driving transistor DT1). During the first period P1, the first driving voltage VDD can be a high-level voltage VH. In order to turn on the first driving transistor DT1, the voltage difference Vgs1 between the gate voltage Vg1 and the source voltage Vs1 of the first driving transistor DT1 can be less than the threshold voltage -Vth1 (Vth1 is a positive value) of the first driving transistor DT1 which is a P-type transistor.

[0171] VCst = Vgs1 = Vg1 - Vs1 = Vdata - VH < -Vth1

[0172] Vdata < -Vth1 + VH (conditional expression 1)

[0173] In an embodiment, the first driving transistor DT1 can operate in the saturation region. Therefore, the voltage Vd1 of the drain of the first driving transistor DT1 connected to the second node N2 (i.e., the drain voltage Vd1) can be less than the voltage that is Vth1 greater than the gate voltage Vg1.

[0174] Vd1 < Vg1 + Vth1 = Vdata + Vth1

[0175] -Vth1 + V1L < Vdata (conditional expression 2)

[0176] However, the embodiments of the present disclosure are not limited thereto, and the first driving transistor DT1 can operate in the triode region.

[0177] Since the second node N2 can be connected to the second power supply line VSL through the first light-emitting element LED1 connected in the forward direction, the drain voltage Vd1 of the first driving transistor DT1 connected to the second node N2 can have a level (e.g., voltage level, magnitude, etc.) approximately equal to the low-level voltage VL. More precisely, the voltage of the second node N2 can be greater than the low-level voltage VL of the second power supply line VSL by the voltage drop VLED (VLED is a positive value) of the first light-emitting element LED1.

[0178] -Vth1 + (VL + VLED) < Vdata (conditional expression 3)

[0179] Thus, in an embodiment, in order for the first driving transistor DT1 to turn on and operate in the saturation region, the data voltage Vdata transmitted to the gate of the first driving transistor DT1 may have a voltage level satisfying the following range.

[0180] -Vth1+(VL+VLED)<Vdata<-Vth1+VH (Conditional Expression 4)

[0181] In an embodiment, as described above, the data voltage Vdata stored in the storage capacitor Cst may also be applied to the gate of the N-type second driving transistor DT2. Compared with a P-type transistor, in an N-type transistor, the terminal to which a high-level voltage can be applied may be referred to as the drain, and the terminal to which a low-level voltage can be applied may be referred to as the source. And in the case of the second driving transistor DT2 in the first period P1, the terminal connected to the first power supply line VDL may be referred to as the drain, and the terminal connected to the second node N2 may be referred to as the source.

[0182] In an embodiment, in the first period P1, the second driving transistor DT2 may be turned off. Therefore, the voltage difference Vgs2 between the gate voltage Vg2 and the source voltage Vs2 of the second driving transistor DT2 may be less than the threshold voltage Vth2 (Vth2 is a positive value) of the second driving transistor DT2, which may be an N-type transistor.

[0183] Vgs2=Vg2-Vs2=Vdata-(VL+VLED)<Vth2

[0184] Vdata<Vth2+(VL+VLED) (Conditional Expression 5)

[0185] Thus, in order for the first driving transistor DT1 to turn on in the saturation region and the second driving transistor DT2 to be turned off during the first period P1, the data voltage Vdata transmitted to the first node N1 may have a range that satisfies both Conditional Expression 3 and Conditional Expression 4.

[0186] In order for both the first driving transistor DT1 and the second driving transistor DT2 to be turned off during the first period P1, the data voltage Vdata transmitted to the first node N1 may have the following range.

[0187] -Vth1+VH<Vdata<Vth2+(VL+VLED) (Conditional Expression 6)

[0188] Thus, in order for both the first driving transistor DT1 and the second driving transistor DT2 to be turned off, the following condition may need to be satisfied.

[0189] -Vth1+VH<Vth2+(VL+VLED)

[0190] refer to Figure 8 During the first period P1, the driving current Id may flow from the source to the drain of the first driving transistor DT1, and the magnitude of the driving current Id may be determined based on the data voltage Vdata applied to the gate of the first driving transistor DT1. The driving current Id may flow through one or more first light-emitting elements LED1 that may be forward biased among the light-emitting elements LED connected in parallel between the second node N2 and the second power supply line VSL. Therefore, the first light-emitting element LED1 may emit light by the driving current Id, and the reverse-biased second light-emitting element LED2 may not emit light.

[0191] In an embodiment, if Figure 7 As shown in the timing diagram shown in , in the first period P1, the high level voltage VH can be applied to the first power supply line VDL, and the intermediate level voltage VM can be applied to the second power supply line VSL. In such an embodiment, except that the second driving voltage VSS applied to the second power supply line VSL in Conditional Formulas 1 to 6 can be replaced with VM instead of VL, the operation of the pixel PX can be substantially the same as those described above.

[0192] In the following, reference will be made to Figure 6 and Fig. 9 The operation of the pixel PX during the second period P2 is described.

[0193] For example, in the first period P1, when the current scan signal Scan[n] is applied (i.e., when the current scan signal Scan[n] is applied at a low level), the switching transistor ST, which may be a P-type transistor, can be turned on, and the data voltage Vdata applied to the data line (e.g., the mth data line DLm) can be transmitted to the first node N1 through the switching transistor ST.

[0194] The data voltage Vdata stored in the storage capacitor Cst may be applied to the gates of the first and second driving transistors DT1 and DT2. In an embodiment, in contrast to the first period P1, in the second period P2, a low level voltage VL may be applied to the first power supply line VDL, and a high level voltage VH may be applied to the second power supply line VSL.

[0195] In the case of the second driving transistor DT2 which may be an N-type, in the second period P2, the terminal connected to the first power supply line VDL to which a low-level voltage VL may be applied may be referred to as a source, and the terminal connected to the second node N2 to which a high-level voltage VH (more accurately, VH-VLED) may be applied may be referred to as a drain.

[0196] The voltage VCst stored in the storage capacitor Cst (i.e., the voltage difference Vg2 between the gate voltage Vg2 and the source voltage Vs2 of the second drive transistor DT2) may be substantially equal to the difference between the data voltage Vdata (which may be the voltage of the first node N1 connected to the gate of the second drive transistor DT2) and the first drive voltage VDD applied to the first power supply line VDL (which is connected to the source of the second drive transistor DT2). During the second period P2, the first drive voltage VDD may be a low level voltage VL. In an embodiment, the voltage difference Vgs2 between the gate voltage Vg2 and the source voltage Vs2 of the second drive transistor DT2 may be greater than the threshold voltage Vth2 (Vth2 is a positive value) of the second drive transistor DT2, which may be an N-type transistor.

[0197] VCst=Vgs2=Vg2-Vs2=Vdata-VL>Vth2

[0198] Vdata>Vth2+VL (Conditional formula 7)

[0199] In an embodiment, the second driving transistor DT2 may operate in a saturation region. Therefore, a drain voltage Vd2 of the second driving transistor DT2 connected to the second node N2 may be greater than a voltage that is Vth2 less than the gate voltage Vg2.

[0200] Vd2>Vg2-Vth2=Vdata-Vth2

[0201] Vth2+Vd2>Vdata (Conditional formula 8)

[0202] However, the embodiments of the present disclosure are not limited thereto, and the first driving transistor DT1 may operate in a triode region.

[0203] Since the second node N2 may be connected to the second power supply line VSL through the second light emitting element LED2 connected in the reverse direction, the drain voltage Vd2 of the second driving transistor DT2 connected to the second node N2 may have a level approximately equal to the high level voltage VH. More specifically, the voltage of the second node N2 may be lower than the high level voltage VH of the second power supply line VSL by a voltage drop VLED of the second light emitting element LED2 (VLED is a positive value).

[0204] Vth1+(VH-VLED)>Vdata (Conditional formula 9)

[0205] Therefore, in an embodiment, in order to turn on and operate the second driving transistor DT2 in the saturation region, the data voltage Vdata transmitted to the gate of the second driving transistor DT2 may have a voltage level satisfying the following range.

[0206] Vth2+(VH-VLED)>Vdata>Vth2+VL (Conditional formula 10)

[0207] In an embodiment, as described above, the data voltage Vdata stored in the storage capacitor Cst may also be applied to the gate of the P-type first driving transistor DT1. In contrast to the N-type transistor, in the P-type transistor, a terminal to which a high-level voltage may be applied may be referred to as a source, and a terminal to which a low-level voltage may be applied may be referred to as a drain, and in the case of the first driving transistor DT1 in the second period P2, a terminal connected to the first power supply line VDL may be referred to as a drain, and a terminal connected to the second node N2 may be referred to as a source.

[0208] In an embodiment, the first driving transistor DT1 may be turned on in the second period P2. Therefore, a voltage difference Vgs1 between a gate voltage Vg1 and a source voltage Vs1 of the first driving transistor DT1 may be greater than a threshold voltage -Vth1 (Vth1 is a positive value) of the first driving transistor DT1 which may be a P-type transistor.

[0209] Vgs1=Vg1-Vs1=Vdata-(VH-VLED)>-Vth1

[0210] Vdata>-Vth1+(VH-VLED) (Conditional formula 11)

[0211] Therefore, in order to turn on the second driving transistor DT2 in the saturation region and turn off the first driving transistor DT1 during the second period P2 , the data voltage Vdata transmitted to the first node N1 may have a range satisfying both Conditional Expression 9 and Conditional Expression 10.

[0212] In order to turn off the first and second driving transistors DT1 and DT2 during the second period P2 , the data voltage Vdata transmitted to the first node N1 may have the following range.

[0213] Vth2+VL>Vdata>-Vth1+(VH-VLED) (Conditional formula 12)

[0214] Therefore, in order to turn off both the first driving transistor DT1 and the second driving transistor DT2 , the following conditions may need to be satisfied.

[0215] Vth2+VL>-Vth1+(VH-VLED)

[0216] During the second period P2, the driving current Id may flow in a direction from the drain to the source of the second driving transistor DT2, and the magnitude of the driving current Id may be determined based on the data voltage Vdata applied to the gate of the second driving transistor DT2. The driving current Id may flow through one or more second light-emitting elements LED2 that may be forward biased among the light-emitting elements LED connected in parallel between the second node N2 and the second power supply line VSL. Therefore, the second light-emitting element LED2 emits light by the driving current Id, and the reverse-biased first light-emitting element LED1 may not emit light.

[0217] In an embodiment, if Figure 7 As shown in the timing diagram shown in , in the second period P2, the low level voltage VL can be applied to the first power supply line VDL, and the intermediate level voltage VM can be applied to the second power supply line VSL. In such an embodiment, except that the second driving voltage VSS applied to the second power supply line VSL in Conditional Formulas 7 to 12 can be replaced with VM instead of VH, the operation of the pixel PX can be substantially the same as described above.

[0218] Fig.10 is a schematic circuit diagram showing a circuit further including a light emitting element initialization circuit according to an embodiment.

[0219] Fig.10 The pixel circuit may further include a light emitting element initialization circuit connected to the second node N2. Since the configuration other than the light emitting element initialization circuit may be connected to the reference Figure 2 The circuits of the described pixels PX are substantially the same, and thus a detailed description thereof will be omitted.

[0220] The light emitting element initialization circuit may include an initialization transistor IT1 connected to an initialization power line IL1 , a scan line (eg, an nth scan line SLn), and a second node N2 .

[0221] The initialization transistor IT1 may include a gate electrode connected to the nth scan line SLn, and may be connected between the initialization power line IL1 and the second node N2. One of the source electrode and the drain electrode of the initialization transistor IT1 may be connected to the initialization power line IL1, and the other of the source electrode and the drain electrode may be connected to the second node N2. For example, the source electrode of the initialization transistor IT1 may be connected to the initialization power line IL1, and the drain electrode of the initialization transistor IT1 may be connected to the second node N2. The initialization transistor IT1 may be a P-type or N-type transistor. Power supply unit ( Figure 1123) shown in FIG. 123) may apply an initialization voltage VI1 to the initialization power line IL1. The initialization voltage VI1 may be substantially equal to the second driving voltage VSS applied to the second power line VSL. The initialization voltage VI1 may be different from the second driving voltage VSS applied to the second power line VSL.

[0222] In the following, the following will describe Fig.10 The operation of the pixel PX shown in FIG.

[0223] As described above, the anode ANO of the first light emitting element LED1 and the cathode CAT of the second light emitting element LED2 may be connected to the second node N2, and the cathode CAT of the first light emitting element LED1 and the anode ANO of the second light emitting element LED2 may be connected to the second power supply line VSL. Therefore, during the first period P1, the first light emitting element LED1 may be forward biased to emit light, and the second light emitting element LED2 may be reverse biased so that charges may be accumulated at opposite ends of the diode as in a capacitor. Conversely, during the second period P2, the second light emitting element LED2 may be forward biased to emit light, and the first light emitting element LED1 may be reverse biased so that charges may be accumulated at opposite ends of the diode as in a capacitor.

[0224] First, during the second period P2 , the second light emitting element LED2 may be forward biased to emit light, and the first light emitting element LED1 may be reverse biased so that charges may be accumulated at opposite ends of the diode like in a capacitor.

[0225] When a low-level current scan signal Scan[n] is applied to the gate of the switching transistor ST at the beginning of the first period P1 , the switching transistor ST may be turned on and the data voltage Vdata may be transmitted to the storage capacitor Cst.

[0226] At substantially the same time as above, in the case where the current scan signal Scan[n] of a low level may be applied to the gate of the initialization transistor IT1, the initialization transistor IT1 may be turned on, and the initialization voltage VI1 applied to the initialization power line IL1 may be applied to the second node N2 through the initialization transistor IT1. Therefore, the charge accumulated in the first light emitting element LED1 may be discharged through the initialization transistor IT1. In such an embodiment, the initialization voltage VI1 applied to the initialization power line IL1 may be substantially equal to or higher than the second driving voltage VSS applied to the second power supply line VSL. For example, the initialization voltage VI1 may be higher than the low level voltage VL.

[0227] When the current scan signal Scan[n] changes to a high level again, the initialization transistor IT1 can be turned off during the remaining first period P1, and the first light emitting element LED1 can be driven by the driving current Id output from the first driving transistor DT1. During the remaining first period P1, the second light emitting element LED2 can be reverse biased so that charges can be accumulated at opposite ends thereof.

[0228] Similarly, when a low-level current scan signal Scan[n] is applied to the gate of the switching transistor ST at the beginning of the second period P2 , the switching transistor ST may be turned on and the data voltage Vdata may be applied to the storage capacitor Cst.

[0229] At substantially the same time as above, the initialization transistor IT1 may be turned on, and the initialization voltage VI1 applied to the initialization power line IL1 may be transmitted to the second node N2 through the initialization transistor IT1. Therefore, at the beginning of the second period P2, the charge accumulated in the second light emitting element LED2 may be discharged through the initialization transistor IT1. In such an embodiment, the initialization voltage VI1 applied to the initialization power line IL1 may be substantially equal to or lower than the second driving voltage VSS applied to the second power supply line VSL. For example, the initialization voltage VI1 may be lower than the high level voltage VH.

[0230] When the current scan signal Scan[n] changes to a high level again, the initialization transistor IT1 can be turned off during the remaining second period P2, and the second light emitting element LED2 can be driven by the drive current Id output from the second drive transistor DT2. During the remaining second period P2, the first light emitting element LED1 can be reverse biased so that charges can be accumulated at its opposite ends.

[0231] In the embodiment, although it has been described that both the initialization transistor IT1 and the switching transistor ST can be turned on by the same current scan signal Scan[n], the embodiments of the present disclosure are not limited thereto. The initialization transistor IT1 can be turned on before the switching transistor ST can be turned on, and can be turned off at the same time or before the switching transistor ST is turned on. For example, the gate of the initialization transistor IT1 can be connected to the (n-1)th scan line SLn-1, and the previous scan signal Scan[n-1] can be applied thereto.

[0232] Fig.11 is a schematic circuit diagram showing a circuit further including a light emitting element initialization circuit according to another embodiment.

[0233] In addition to the initialization transistor IT1 being connected to the second power supply line VSL, according to Fig.11The pixel PX can have a Fig.10 The pixels PX described have substantially the same configuration.

[0234] The light emitting element initialization circuit may include an initialization transistor IT1 connected to the second power supply line VSL, a scan line (eg, an nth scan line SLn), and a second node N2.

[0235] The initialization transistor IT1 may include a gate electrode connected to the nth scan line SLn, and may be connected between the second power supply line VSL and the second node N2. One of the source electrode and the drain electrode of the initialization transistor IT1 may be connected to the second power supply line VSL, and the other of the source electrode and the drain electrode may be connected to the second node N2. For example, the source electrode of the initialization transistor IT1 may be connected to the second power supply line VSL, and the drain electrode of the initialization transistor IT1 may be connected to the second node N2.

[0236] In the case where the initialization transistor IT1 is turned on according to the current scan signal Scan[n] at the beginning of the first period P1, the second driving voltage VSS applied to the second power supply line VSL can be transmitted to the second node N2 through the initialization transistor IT1. Therefore, substantially the same voltage can be applied to the opposite ends of the first light emitting element LED1, so that the charges accumulated in the first light emitting element LED1 during the second period P2 can be discharged.

[0237] Similarly, when the initialization transistor IT1 is turned on according to the current scan signal Scan[n] at the beginning of the second period P2, substantially the same voltage can be applied to the opposite ends of the second light emitting element LED2 so that the charge accumulated in the second light emitting element LED2 during the first period P1 can be discharged.

[0238] Fig.12 is a schematic circuit diagram showing a circuit arranged as a pixel according to another embodiment.

[0239] The pixel circuit may include a switching circuit that transmits a data voltage Vdata applied to a data line (e.g., the mth data line DLm), a storage circuit that stores the transmitted data voltage Vdata, and a driving circuit that controls a current for driving a light emitting element LED according to the stored data voltage Vdata.

[0240] The switching circuit may include a switching transistor ST connected to a data line (e.g., an mth data line DLm), a scan line (e.g., an nth scan line SLn), and a first node N1. The storage circuit may include a first storage capacitor Cst1 connected to the first node N1 and the (1-1)th power supply line VDL1, and a second storage capacitor Cst2 connected to the first node N1 and the (1-2)th power supply line VDL2. The driving circuit may include a first driving transistor DT1 connected to the first node N1, the (1-1)th power supply line VDL1, and a second node N2, and a second driving transistor DT2 connected to the first node N1, the (1-2)th power supply line VDL2, and a second node N2. The first driving transistor DT1 and the second driving transistor DT2 may be complementary to each other.

[0241] The light emitting element LED may include an ultra-small light emitting diode of nanometer size. The light emitting element LED may include at least two light emitting element LEDs that may be respectively connected to the second node N2 and the second power supply line VSL and biased in opposite directions. The light emitting element LED may include a first light emitting element LED1 and a second light emitting element LED2. The anode of the first light emitting element LED1 and the cathode of the second light emitting element LED2 may be connected to the second node N2, and the cathode of the first light emitting element LED1 and the anode of the second light emitting element LED2 may be connected to the second power supply line VSL.

[0242] Power Supply Department Figure 1 123) shown in may include: a (1-1)th power supply unit, providing a (1-1)th driving voltage VDD1 to a (1-1)th power supply line VDL1; a (1-2)th power supply unit, providing a (1-2)th driving voltage VDD2 to a (1-2)th power supply line VDL2; and a second power supply unit, providing a second driving voltage VSS to a second power supply line VSL.

[0243] The first and second light emitting elements LED1 and LED2 may alternately emit light according to the (1-1)th driving voltage VDD1, the (1-2)th driving voltage VDD2, the second driving voltage VSS, and the data voltage Vdata of the first node N1.

[0244] In the following, reference will be made to Fig.12 Describe the connection relationship between each transistor and each light emitting element in detail.

[0245] The switching transistor ST may include a first gate electrode connected to the nth scan line SLn, and may be connected between the mth data line DLm and the first node N1. One of the first source electrode and the first drain electrode of the switching transistor ST may be connected to the mth data line DLm, and the other of the first source electrode and the first drain electrode may be connected to the first node N1. For example, the first source electrode of the switching transistor ST may be connected to the mth data line DLm, and the first drain electrode of the switching transistor ST may be connected to the first node N1. The switching transistor ST may be a P-type or N-type transistor. The switching transistor ST may be a PMOS or NMOS transistor.

[0246] The first drive transistor DT1 may include a second gate electrode connected to the first node N1, and may be connected between the (1-1)th power supply line VDL1 and the second node N2. In an embodiment, the first drive transistor DT1 may be a P-type transistor or a PMOS transistor. One of the second source electrode and the second drain electrode of the first drive transistor DT1 may be connected to the (1-1)th power supply line VDL1, and the other of the second source electrode and the second drain electrode may be connected to the second node N2. For example, the second source electrode of the first drive transistor DT1 may be connected to the (1-1)th power supply line VDL1, and the second drain electrode of the first drive transistor DT1 may be connected to the second node N2. The first drive transistor DT1 may control the magnitude of a current (current flowing from the second source electrode to the second drain electrode) flowing from the (1-1)th power supply line VDL1 to the second node N2 according to the data voltage Vdata applied to the second gate electrode.

[0247] The second drive transistor DT2 may include a third gate electrode connected to the first node N1, and may be connected between the (1-2)th power supply line VDL2 and the second node N2. In an embodiment, the second drive transistor DT2 may be an N-type transistor or an NMOS transistor. In an embodiment, the first drive transistor DT1 and the second drive transistor DT2 may be mutually complementary transistors, such as CMOS transistors. One of the third source electrode and the third drain electrode of the second drive transistor DT2 may be connected to the (1-2)th power supply line VDL2, and the other of the third source electrode and the third drain electrode may be connected to the second node N2. For example, the third source electrode of the second drive transistor DT2 may be connected to the (1-2)th power supply line VDL2, and the third drain electrode of the second drive transistor DT2 may be connected to the second node N2. The second drive transistor DT2 controls the magnitude of the current (current flowing from the third drain electrode to the third source electrode) flowing from the second node N2 to the (1-2)th power supply line VDL2 according to the data voltage Vdata applied to the third gate electrode.

[0248] The first storage capacitor Cst1 may be connected between the first node N1 and the (1-1)th power supply line VDL1. The second storage capacitor Cst2 may be connected between the first node N1 and the (1-2)th power supply line VDL2. The first storage capacitor Cst1 and the second storage capacitor Cst2 may store the data voltage Vdata applied to the first node N1 during one frame or a partial period of one frame.

[0249] In the following, reference will be made to Fig.12 , Fig.13 , Fig.14 and Fig.15 A method of driving a pixel PX according to an embodiment is described in detail.

[0250] Fig.13 It is shown Fig.12 A schematic diagram of an implementation of a timing diagram of a circuit diagram. Fig.14 It is shown that during the first period Fig.12 A schematic circuit diagram of the equivalent circuit of the circuit diagram. Fig.15 It is shown that during the second period Fig.12 A schematic circuit diagram of the equivalent circuit of the circuit diagram.

[0251] As described above, according to the method of driving the pixel PX according to the embodiment, the first period P1 in which the first light emitting element LED1 emits light and the second period P2 in which the second light emitting element LED2 emits light may be included and the first period P1 and the second period P2 may be repeated alternately.

[0252] During the first period P1 and the second period P2, the (1-1)th driving voltage VDD1 applied to the (1-1)th power supply line VDL1, the (1-2)th driving voltage VDD2 applied to the (1-2)th power supply line VDL2, and the second driving voltage VSS applied to the second power supply line VSL may have substantially the same value. For example, the (1-1)th driving voltage VDD1 may be higher than the second driving voltage VSS, and the (1-2)th driving voltage VDD2 may be lower than the second driving voltage VSS. For example, the (1-1)th driving voltage VDD1 may be a high level voltage VH, the (1-2)th driving voltage VDD2 may be a low level voltage VL, and the second driving voltage VSS may be an intermediate level voltage VM.

[0253] In the following, reference will be made to Fig.12 , Fig.13 and Fig.14 The operation of the pixel PX during the first period P1 is described.

[0254] refer to Fig.12, the current scan signal Scan[n] applied to the corresponding scan line (e.g., the nth scan line SLn) among the scan lines SL1-SLi may be applied to the gate of the switching transistor ST, and the data voltage Vdata applied to the corresponding data line (e.g., the mth data line DLm) among the data lines DL1 to DLj may be applied to the source of the switching transistor ST. The switching transistor ST may be a P-type or N-type transistor. Hereinafter, the switching transistor ST will be described with respect to a P-type transistor.

[0255] First, when the current scan signal Scan[n] is applied (i.e., when the current scan signal Scan[n] is applied at a low level), the switching transistor ST, which may be a P-type transistor, can be turned on, and the data voltage Vdata applied to the data line (e.g., the mth data line DLm) can be transmitted to the first node N1 (the gate of the first driving transistor DT1, the gate of the second driving transistor DT2, one end of the first storage capacitor Cst1, and one end of the second storage capacitor Cst2) through the switching transistor ST.

[0256] The first storage capacitor Cst1 and the second storage capacitor Cst2 may be charged according to the data voltage Vdata transmitted to the first node N1 and store the data voltage Vdata during the first period P1. Therefore, the first node N1 maintains the transmitted data voltage Vdata during the first period P1.

[0257] The data voltage Vdata stored in the storage capacitor Cst may be applied to the gates of the first and second drive transistors DT1 and DT2. As described above, in an embodiment, the first drive transistor DT1 may be a P-type transistor, and the second drive transistor DT2 may be an N-type transistor.

[0258] The voltage VCst1 stored in the first storage capacitor Cst1 (i.e., the voltage difference Vgs1 between the gate voltage Vg1 and the source voltage Vs1 of the first drive transistor DT1) may be substantially equal to the difference between the data voltage Vdata (which may be the voltage of the first node N1 connected to the gate of the first drive transistor DT1) and the (1-1)th drive voltage VDD1 applied to the (1-1)th power supply line VDL1 (which is connected to the source of the first drive transistor DT1).

[0259] During the first period P1 , the first driving transistor DT1 may be turned on, and the second driving transistor DT2 may be turned off.

[0260] To turn on the first driving transistor DT1, the voltage difference Vgs1 between the gate voltage Vg1 and the source voltage Vs1 of the first driving transistor DT1 can be less than the threshold voltage -Vth1 (Vth1 is a positive value) of the first driving transistor DT1, which can be a P-type transistor.

[0261] VCst1 = Vgs1 = Vg1 - Vs1 = Vdata - VH < -Vth1

[0262] Vdata < -Vth1 + VH (conditional expression 13)

[0263] To turn off the second driving transistor DT2, the voltage difference Vgs2 between the gate voltage Vg2 and the source voltage Vs2 of the second driving transistor DT2 can be less than the threshold voltage Vth2 (Vth2 is a positive value) of the second driving transistor DT2, which can be an N-type transistor.

[0264] Vgs2 = Vg2 - Vg2 = Vdata - VL < Vth2

[0265] Vdata < Vth2 + VL (conditional expression 14)

[0266] Therefore, to turn on the first driving transistor DT1 and turn off the second driving transistor DT2 during the first period P1, the data voltage Vdata transmitted to the first node N1 can have a range that satisfies both conditional expression 13 and conditional expression 14.

[0267] During the first period P1, the driving current Id can flow in the direction from the source to the drain of the first driving transistor DT1, and the magnitude of the driving current Id can be determined based on the voltage stored in the first storage capacitor Cst1. The driving current Id can flow through one or more first light-emitting elements LED1 that can be forward-biased among the light-emitting elements LED connected in parallel between the second node N2 and the second power supply line VSL. Therefore, the first light-emitting element LED1 can emit light through the driving current Id, and the reversely biased second light-emitting element LED2 can not emit light.

[0268] Hereinafter, reference will be made to Fig.12 、 Fig.13 and Fig.15 to describe the operation of the pixel PX during the second period P2.

[0269] During the second period P2, the first driving transistor DT1 can be turned off and the second driving transistor DT2 can be turned on.

[0270] To turn on the second driving transistor DT2, the voltage difference Vgs2 between the gate voltage Vg2 and the source voltage Vs2 of the second driving transistor DT2 (i.e., the voltage VCst2 stored in the second storage capacitor Cst2) can be higher than the threshold voltage Vth2 of the second driving transistor DT2 which can be an N-type transistor (Vth2 is a positive value).

[0271] VCst2 = Vgs2 = Vg2 - Vs2 = Vdata - VL > Vth2

[0272] Vdata > Vth2 + VL (conditional expression 15)

[0273] To turn off the first driving transistor DT1, the voltage difference Vgs1 between the gate voltage Vg1 and the source voltage Vs1 of the first driving transistor DT1 can be higher than the threshold voltage -Vth1 of the first driving transistor DT1 which can be a P-type transistor (Vth1 is a positive value).

[0274] Vgs1 = Vg1 - Vs1 = Vdata - VH > -Vth1

[0275] Vdata > -Vth1 + VH (conditional expression 16)

[0276] Therefore, to turn on the second driving transistor DT2 and turn off the first driving transistor DT1 during the second period P2, the data voltage Vdata transmitted to the first node N1 can have a range that satisfies both conditional expression 15 and conditional expression 16.

[0277] During the second period P2, the driving current Id flows in the direction from the drain to the source of the second driving transistor DT2, and the magnitude of the driving current Id can be determined according to the voltage stored in the second storage capacitor Cst2. The driving current Id flows through one or more second light-emitting elements LED2 that can be forward-biased among the light-emitting elements LED connected in parallel between the second node N2 and the second power supply line VSL. Therefore, the second light-emitting elements LED2 can emit light through the driving current Id, and the reverse-biased first light-emitting element LED1 can not emit light.

[0278] To turn off the first driving transistor DT1 and the second driving transistor DT2, the data voltage Vdata transmitted to the first node N1 can have the following range.

[0279] -Vth1 + VH < Vdata < Vth2 + VL (conditional expression 17)

[0280] Therefore, to turn off both the first driving transistor DT1 and the second driving transistor DT2, the following conditions may need to be satisfied.

[0281] -Vth1+VH <Vth2+VL

[0282] Therefore, under such conditions, in the range where the data voltage Vdata can be lower than -Vth1+VH, only the first driving transistor DT1 can be turned on, so that the first light-emitting element LED1 emits light, in the range where the data voltage Vdata can be between -Vth1+VH and Vth2+VL, both the first driving transistor DT1 and the second driving transistor DT2 can be turned off, so that the first light-emitting element LED1 and the second light-emitting element LED2 can neither emit light, and in the range where the data voltage Vdata can be higher than Vth2+VL, only the second driving transistor DT2 can be turned on, so that the second light-emitting element LED2 can emit light.

[0283] Fig.16 It is shown Fig.12 A schematic diagram of an implementation of a timing diagram of a circuit diagram.

[0284] As described above, according to the method of driving the pixel PX according to the embodiment, the first period P1 in which the first light emitting element LED1 emits light and the second period P2 in which the second light emitting element LED2 emits light may be included and the first period P1 and the second period P2 may be repeated alternately.

[0285] The (1-1)th driving voltage VDD1 applied to the (1-1)th power supply line VDL1 may be maintained at the high level voltage VH during the first period P1, and the (1-1)th power supply line VDL1 may be floated during the second period P2. For example, the (1-1)th power supply line VDL1 may be disconnected from the power supply unit 123 during the second period P2.

[0286] The (1-2)th driving voltage VDD2 applied to the (1-2)th power supply line VDL2 may be maintained at the low level voltage VL during the second period P2, and the (1-2)th power supply line VDL2 may be floated during the first period P1. For example, during the first period P1, the (1-2)th power supply line VDL2 may be disconnected from the power supply unit 123.

[0287] During the first period P1 and the second period P2 , the second driving voltage VSS applied to the second power supply line VSL may be maintained at the middle level voltage VM.

[0288] Fig.17 It is shown Fig.12 A schematic diagram of another embodiment of a timing diagram of a circuit diagram.

[0289] As described above, according to the method of driving the pixel PX according to the embodiment, the first period P1 in which the first light emitting element LED1 emits light and the second period P2 in which the second light emitting element LED2 emits light may be included and the first period P1 and the second period P2 may be repeated alternately.

[0290] During the first period P1, the (1-1)th driving voltage VDD1 applied to the (1-1)th power supply line VDL1 may be maintained at a high level voltage VH. In a second period P2 immediately before entering the first period P1 (e.g., during a period in which the previous scan signal Scan[n-1] may be applied), a voltage having substantially the same level as the (1-2)th driving voltage VDD2 applied to the (1-2)th power supply line VDL2 (i.e., a low level voltage VL) may be applied to the (1-1)th power supply line VDL1. During the rest of the second period P2, the (1-1)th driving voltage VDD1 applied to the (1-1)th power supply line VDL1 may be maintained at a high level voltage VH.

[0291] Therefore, the charges charged in the first storage capacitor Cst1 may be discharged immediately before the first period P1 starts, so that the first storage capacitor Cst1 may be initialized.

[0292] In the second period P2, the (1-2) driving voltage VDD2 applied to the (1-2) power supply line VDL2 may be maintained at the low level voltage VL. In the first period P1 immediately before entering the second period P2 (e.g., during the period in which the previous scan signal Scan[n-1] may be applied), a voltage having substantially the same level as the (1-1) driving voltage VDD1 applied to the (1-1) power supply line VDL1 (i.e., the high level voltage VH) may be applied to the (1-2) power supply line VDL2. During the remaining first period P1, the (1-2) driving voltage VDD2 applied to the (1-2) power supply line VDL2 may be maintained at the low level voltage VL.

[0293] Therefore, the charges charged in the second storage capacitor Cst2 may be discharged immediately before the second period P2 starts, so that the second storage capacitor Cst2 may be initialized.

[0294] Fig.18 and Fig.19 is a circuit diagram showing a circuit further including a light emitting element initialization circuit according to an embodiment of the present disclosure.

[0295] Fig.18 The light emitting element initialization circuit may include Fig.10The initialization transistor IT1 shown in FIG. 1 is connected to the initialization power line IL1 , the scan line (eg, the nth scan line SLn), and the second node N2 . Fig.19 The light emitting element initialization circuit may include an initialization transistor IT1 connected to the second power supply line VSL, a scan line (eg, the nth scan line SLn), and a second node N2. Fig.18 and Fig.19 The connection and operation of the light emitting element initialization circuit can be compared with the reference Fig.10 and Fig.11 Those described are substantially the same, so a detailed description thereof will be omitted.

[0296] Fig. 20 is a schematic circuit diagram illustrating a circuit further including a storage capacitor initialization circuit according to an embodiment of the present disclosure. Fig.21 It is shown Fig. 20 A schematic diagram of an implementation of a timing diagram of a circuit diagram.

[0297] Fig. 20 The pixel PX of FIG. 1 may include a storage capacitor initialization circuit connected to the first node N1. Since the configuration other than the storage capacitor initialization circuit may be connected to the reference node N1, Fig.12 The configurations of the described pixels PX are substantially the same, and thus a detailed description thereof will be omitted.

[0298] The storage capacitor initialization circuit may include an initialization transistor IT2 connected to the initialization power line IL2, the (n-1)th scan line SLn-1, and the first node N1.

[0299] The initialization transistor IT2 may include a gate electrode connected to the (n-1)th scan line SLn-1, and may be connected between the initialization power line IL2 and the first node N1. One of the source electrode and the drain electrode of the initialization transistor IT2 may be connected to the initialization power line IL2, and the other of the source electrode and the drain electrode of the initialization transistor IT2 may be connected to the first node N1. For example, the source electrode of the initialization transistor IT2 may be connected to the initialization power line IL2, and the drain electrode of the initialization transistor IT2 may be connected to the first node N1. The initialization transistor IT2 may be a P-type or N-type transistor. Power supply unit ( Figure 1 123) shown in FIG. 1 can apply the initialization voltage VI2 to the initialization power line IL2.

[0300] In the following, reference will be made to Fig. 20 and Fig.21 An initialization operation of the storage capacitors Cst1 and Cst2 of the pixel PX is described.

[0301] As described above, the first storage capacitor Cst1 may be connected between the (1-1)th power supply line VDL1 and the first node N1, and the second storage capacitor Cst2 may be connected between the (1-2)th power supply line VDL2 and the first node N1.

[0302] First, charges may be accumulated and maintained at opposite ends of the first storage capacitor Cst1 and the second storage capacitor Cst2 according to the data voltage Vdata transmitted to the first node N1 during the second period P2.

[0303] In the case where the previous scan signal Scan[n-1] of a low level is applied to the gate of the initialization transistor IT2 just before entering the first period P1, the initialization transistor IT2 can be turned on, and the initialization voltage VI2 applied to the initialization power line IL2 can be transmitted to the first node N1 through the initialization transistor IT2. For example, in such an embodiment, the initialization voltage VI2 transmitted by the previous scan signal Scan[n-1] can be substantially equal to the (1-1)th driving voltage VDD1 that can be applied to the (1-1)th power supply line VDL1 during the first period P1. Therefore, the charge stored in the first storage capacitor Cst1 can be discharged through the initialization transistor IT2 just before entering the first period P1, so that the first storage capacitor Cst1 can be initialized.

[0304] When the previous scan signal Scan[n-1] changes to a high level again, the initialization transistor IT2 can be turned off at the beginning of the second period P2, and at the same time, when the low level current scan signal Scan[n] can be applied to the gate of the switching transistor ST, the switching transistor ST can be turned on and the data voltage Vdata can be transmitted to the storage capacitor Cst.

[0305] In the case where the low-level previous scan signal Scan[n-1] is applied to the gate of the initialization transistor IT2 just before entering the second period P2, the initialization transistor IT2 can be turned on, and the initialization voltage VI2 applied to the initialization power line IL2 can be transmitted to the first node N1 through the initialization transistor IT2. For example, in such an embodiment, the initialization voltage VI2 transmitted by the previous scan signal Scan[n-1] can be substantially equal to the low-level voltage VL, which can be the (1-2)th driving voltage VDD2 applied to the (1-2)th power supply line VDL2 during the second period P2. Therefore, the charge stored in the second storage capacitor Cst2 can be discharged through the initialization transistor IT2 just before entering the second period P2, so that the second storage capacitor Cst2 can be initialized.

[0306] When the previous scan signal Scan[n-1] changes to a high level again, the initialization transistor IT2 can be turned off at the beginning of the second period P2, and at the same time, when the low level current scan signal Scan[n] is applied to the gate of the switching transistor ST, the switching transistor ST can be turned on and the data voltage Vdata can be transmitted to the storage capacitor Cst.

[0307] While the present disclosure has been shown and described with reference to the embodiments thereof and the drawings, it will be apparent to those skilled in the art that various substitutions, modifications and variations may be made without departing from the spirit and scope of the present disclosure.

Claims

1. Pixels, including: a switch transistor, transmitting the data voltage to the first node; a storage capacitor electrically connected between the first power supply line and the first node, the storage capacitor storing the data voltage; a first driving transistor electrically connected to the first power supply line, the first node and a second node; a second driving transistor electrically connected to the first power supply line, the first node and the second node; a first light emitting element, electrically connected between the second node and a second power supply line; as well as A second light emitting element is electrically connected between the second node and the second power supply line; wherein: The anode of the first light emitting element and the cathode of the second light emitting element are electrically connected to the second node, The cathode of the first light emitting element and the anode of the second light emitting element are electrically connected to the second power supply line, The first driving transistor is a P-type transistor, The second driving transistor is an N-type transistor, A gate of the first driving transistor and a gate of the second driving transistor are electrically connected to the first node, A source of the first driving transistor and a source of the second driving transistor are electrically connected to the first power supply line, and A drain of the first driving transistor and a drain of the second driving transistor are electrically connected to the second node, and in, In a first period, a first driving voltage applied to the first power supply line is higher than a second driving voltage applied to the second power supply line, and In a second period, the first driving voltage applied to the first power supply line is lower than the second driving voltage applied to the second power supply line.

2. The pixel according to claim 1, wherein: The gate of the switching transistor is electrically connected to a scanning line to which a scanning signal is applied, One of a source and a drain of the switching transistor is electrically connected to a data line to which the data voltage is applied, and The other of the source and the drain of the switch transistor is electrically connected to the first node.

3. The pixel according to claim 1, wherein: Each of the first light emitting element and the second light emitting element includes a light emitting diode having a nanometer size.

4. The pixel according to claim 1, wherein: The first drive transistor is a PMOS, and the second drive transistor is an NMOS.

5. The pixel according to claim 1, wherein: The first period and the second period are repeated alternately.

6. The pixel of claim 1, wherein: In the first period, the first driving transistor is turned on, and the second driving transistor is turned off, and In the second period, the first driving transistor is turned off, and the second driving transistor is turned on.

7. The pixel according to claim 1, wherein: One of the first driving voltage applied to the first power supply line and the second driving voltage applied to the second power supply line maintains a constant value during the first period and the second period.

8. The pixel according to claim 1, wherein: Each of the first period and the second period corresponds to a portion of one frame.

9. The pixel according to claim 1, wherein: Each of the first period and the second period corresponds to at least one frame.

10. The pixel according to claim 1, wherein: The ratio of the second period to the first period is equal to the ratio of the number of the second light-emitting elements to the number of the first light-emitting elements.

11. The pixel according to claim 1, further comprising an initialization transistor electrically connected to the second node, in: The gate of the initialization transistor is electrically connected to a scan line to which a scan signal is applied, One of the source and the drain of the initialization transistor is electrically connected to the second node, and The other of the source and the drain of the initialization transistor is electrically connected to an initialization power line.

12. The pixel according to claim 1, further comprising an initialization transistor electrically connected to the second node, in: The gate of the initialization transistor is electrically connected to a scan line to which a scan signal is applied, One of the source and the drain of the initialization transistor is electrically connected to the second node, and The other of the source and the drain of the initialization transistor is electrically connected to the second power supply line.

13. Pixels, including: a switch transistor, transmitting the data voltage to the first node; a first storage capacitor electrically connected between a 1-1 power supply line and the first node, the first storage capacitor storing the data voltage; a second storage capacitor electrically connected between the 1-2 power supply line and the first node, the second storage capacitor storing the data voltage; a first driving transistor electrically connected to the 1-1th power supply line, the first node and the second node; a second driving transistor electrically connected to the 1-2 power supply line, the first node and the second node; a first light emitting element, electrically connected between the second node and a second power supply line; as well as A second light emitting element is electrically connected between the second node and the second power supply line, wherein: The anode of the first light emitting element and the cathode of the second light emitting element are electrically connected to the second node, The cathode of the first light emitting element and the anode of the second light emitting element are electrically connected to the second power supply line, The first driving transistor is a P-type transistor, The second driving transistor is an N-type transistor, A gate of the first driving transistor and a gate of the second driving transistor are electrically connected to the first node, The source of the first driving transistor is electrically connected to the 1-1th power supply line, The source of the second driving transistor is electrically connected to the 1-2nd power supply line, and A drain of the first driving transistor and a drain of the second driving transistor are electrically connected to the second node, and in, In a first period, the first driving transistor is turned on or off, and the second driving transistor is turned off, In a second period, the first driving transistor is turned off, and the second driving transistor is turned on or off, and The first period and the second period are repeated alternately.

14. The pixel of claim 13, wherein: The gate of the switching transistor is electrically connected to a scanning line to which a scanning signal is applied, One of a source and a drain of the switching transistor is electrically connected to a data line to which the data voltage is applied, and The other of the source and the drain of the switch transistor is electrically connected to the first node.

15. The pixel according to claim 13, wherein: Each of the first light emitting element and the second light emitting element includes a light emitting diode having a nanometer size.

16. The pixel according to claim 13, wherein: The first drive transistor is a PMOS, and the second drive transistor is an NMOS.

17. The pixel according to claim 13, wherein: In the first period and the second period, The 1-1 driving voltage applied to the 1-1 power supply line is higher than the second driving voltage applied to the second power supply line, and The 1-2 driving voltage applied to the 1-2 power supply line is lower than the second driving voltage applied to the second power supply line.

18. The pixel of claim 17, wherein: In the first period, the data voltage is lower than a value obtained by adding a threshold voltage of the second driving transistor to the 1-2nd driving voltage, and In the second period, the data voltage is higher than a value obtained by subtracting the threshold voltage of the second driving transistor from the 1-1th driving voltage.

19. The pixel according to claim 13, wherein: Each of the first period and the second period corresponds to a portion of one frame.

20. The pixel according to claim 13, wherein: Each of the first period and the second period corresponds to at least one frame.

21. The pixel according to claim 13, wherein: The ratio of the second period to the first period is equal to the ratio of the number of the second light-emitting elements to the number of the first light-emitting elements.

22. The pixel of claim 13, wherein: In the first period, the 1-1 driving voltage applied to the 1-1 power supply line is higher than the second driving voltage applied to the second power supply line, In the second period, the 1-1th power supply line is floating, In the second period, the 1-2 driving voltage applied to the 1-2 power supply line is lower than the second driving voltage applied to the second power supply line, and In the first period, the 1-2 th power supply line is floating.

23. The pixel of claim 13, wherein: In the first period, the 1-1 driving voltage applied to the 1-1 power supply line is higher than the second driving voltage applied to the second power supply line, In the second period, the 1-2 driving voltage applied to the 1-2 power supply line is lower than the second driving voltage applied to the second power supply line, the 1-1st driving voltage applied to the 1-1st power supply line in at least a portion of the second period is equal to the 1-2nd driving voltage applied to the 1-2nd power supply line in the second period, and The 1-2 driving voltage applied to the 1-2 power supply line in at least a portion of the first period is equal to the 1-1 driving voltage applied to the 1-1 power supply line in the first period.

24. The pixel of claim 13, further comprising an initialization transistor connected to the second node, in: The gate of the initialization transistor is electrically connected to a scan line to which a scan signal is applied, One of the source and the drain of the initialization transistor is electrically connected to the second node, and The other of the source and the drain of the initialization transistor is electrically connected to an initialization power line.

25. The pixel of claim 13, further comprising an initialization transistor electrically connected to the second node, in: The gate of the initialization transistor is electrically connected to a scan line to which a scan signal is applied, One of the source and the drain of the initialization transistor is electrically connected to the second node, and The other of the source and the drain of the initialization transistor is electrically connected to the second power supply line.

26. The pixel of claim 13, further comprising an initialization transistor electrically connected to the first node, in: The gate of the initialization transistor is electrically connected to the scan line to which the previous scan signal is applied, One of a source and a drain of the initialization transistor is electrically connected to the first node, and The other of the source and the drain of the initialization transistor is electrically connected to an initialization power line.

27. The pixel of claim 17, further comprising an initialization transistor electrically connected to the first node, in: The gate of the initialization transistor is electrically connected to the scan line to which the previous scan signal is applied, One of a source and a drain of the initialization transistor is electrically connected to the first node, and the other of the source and the drain of the initialization transistor is electrically connected to an initialization power line, In the case where the previous scan signal is applied in the second period, applying an initialization voltage equal to the 1-1th driving voltage to the initialization power line, and In the case where the previous scan signal is applied in the first period, the initialization voltage equal to the 1-2 th driving voltage is applied to the initialization power line.

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