Power conversion system and virtual DC voltage generator circuit

Abstract

The present disclosure solves the problem of connecting multiple circuits on the DC side without using a smoothing capacitor. The power conversion system (10) according to the present disclosure includes a first circuit (1), a second circuit (2) and a third circuit (3). The first internal terminal (111, 112), the second internal terminal (211, 212) and the third internal terminal (341, 342) are electrically connected to the same connection unit (7). The third circuit (3) provides an output voltage (VT) between the two ends of the secondary winding (332) of the transformer (33) via a switching element (Q31-Q34) and a transformer (33). The secondary winding (332) is electrically connected to the third internal terminal (341, 342). The waveform of the output voltage (VT) includes: a rising range, in which the output voltage (VT) changes from a first potential to a second potential; a falling range, in which the output voltage (VT) changes from the second potential to the first potential; and a flat range, in which the output voltage (VT) is maintained at the first potential or the second potential.

Description

Technical Field

[0001] The present disclosure generally relates to a power conversion system and a virtual DC voltage generator circuit, and more particularly to a power conversion system and a virtual DC voltage generator circuit that convert power unidirectionally or bidirectionally. Background Art

[0002] Patent document 1 discloses a power converter (power conversion system) that can be connected to a solar power generation panel. The power converter of patent document 1 is configured to convert DC power into AC power, and includes a DC / DC converter and a DC / AC converter. The DC / AC converter is connected to the DC / DC converter via an intermediate bus. An intermediate capacitor is connected to the intermediate bus.

[0003] The power converter of Patent Document 1 requires a smoothing capacitor (as an intermediate capacitor) to connect the DC / DC converter and the DC / AC converter on the DC side.

[0004] Reference List

[0005] Patent Literature

[0006] Patent Document 1: WO 2017 / 068814 A1 Summary of the invention

[0007] An object of the present disclosure is to provide a power conversion system and a virtual DC voltage generator circuit, both of which allow a plurality of circuits to be connected on the DC side without using a smoothing capacitor.

[0008] A power conversion system according to one aspect of the present disclosure includes a first circuit and a second circuit, and power is transmitted between a first internal terminal of the first circuit and a second internal terminal of the second circuit. The first circuit includes a first internal terminal and a first external terminal, and the first external terminal is electrically connected to an AC power source or an AC load. The second circuit includes at least a second internal terminal. The power conversion system also includes a third circuit. The third circuit includes a third internal terminal and a third external terminal. In the power conversion system, the first internal terminal, the second internal terminal, and the third internal terminal are electrically connected to the same connection unit. The third circuit includes a switching element and a transformer electrically connected to the switching element. The third circuit is configured to provide an output voltage between both ends of a secondary winding of the transformer via the switching element and the transformer. The secondary winding is electrically connected to the third internal terminal. The output voltage has a waveform including a rising range, a falling range, and a flat range. In the rising range, the output voltage changes from a first potential to a second potential higher than the first potential. In the falling range, the output voltage changes from the second potential to the first potential. In the flat range, the output voltage remains at the first potential or the second potential.

[0009] A virtual DC voltage generator circuit according to another aspect of the present disclosure is used as a third circuit in a power conversion system. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a circuit diagram of a virtual DC voltage generator circuit and a power conversion system according to a first embodiment of the present disclosure;

[0011] Figure 2 is a waveform diagram illustrating operation of a power conversion system in an inverter mode;

[0012] Figure 3 is a waveform diagram showing another operation of the power conversion system in the inverter mode;

[0013] Figure 4 Shows Figure 3 A waveform diagram of a first and second time period is specified;

[0014] FIG. 5A to FIG. 5C is a waveform diagram showing simulation results of a power conversion system;

[0015] FIG. 6A to FIG. 6C is another waveform diagram showing simulation results of the power conversion system;

[0016] Figure 7 It shows that FIG. 8A to FIG. 8C An enlarged waveform diagram of a portion of the operation of the power conversion system in inverter mode is shown;

[0017] FIG. 8A to FIG. 8C is another waveform diagram showing simulation results of the power conversion system;

[0018] Fig. 9A and Fig. 9B is a circuit diagram showing an exemplary structure of a primary side circuit of a virtual DC voltage generator circuit according to a first modification of the first embodiment of the present disclosure;

[0019] Fig.10 is a circuit diagram showing an exemplary structure of a secondary side circuit of a virtual DC voltage generator circuit;

[0020] FIG. 11A to FIG. 11D is a circuit diagram showing an exemplary structure of a snubber circuit for use in a power conversion system according to a second modification of the first embodiment of the present disclosure;

[0021] Fig.12 is a block diagram showing the structure of a power conversion system according to a second embodiment of the present disclosure; and

[0022] Fig.13 is a circuit diagram showing the structure of a power conversion system. DETAILED DESCRIPTION

[0023] (First embodiment)

[0024] (1) Overview

[0025] Reference Figure 1 An overview of a power conversion system 10 according to an exemplary embodiment is described.

[0026] like Figure 1 As shown, the power conversion system 10 according to this embodiment is a system that performs power conversion between the first DC terminals T11, T12, the second DC terminals T21, T22 and the AC terminals T31, T32, T33. The solar cell 70 is electrically connected to the first DC terminals T11, T12. The storage battery 80 is electrically connected to the second DC terminals T21, T22. The power grid 90 is electrically connected to the AC terminals T31, T32, T33. As used herein, the "power grid" refers to an overall system that allows a power supplier such as a power company to supply power to a customer's power receiving device.

[0027] The power conversion system 10 according to this embodiment converts the DC power supplied from at least one of the solar cell 70 or the storage battery 80 into AC power having three phases (i.e., U phase, V phase, and W phase), and outputs (transmits) the AC power to the grid 90. In addition, the power conversion system 10 also converts the AC power supplied from the grid 90 into DC power, and outputs the DC power to the storage battery 80.

[0028] In other words, when the solar cell 70 generates electricity or the storage battery 80 discharges electricity, the power conversion system 10 converts the DC power supplied from the solar cell 70 or the storage battery 80 into AC power, and outputs the AC power to the grid 90. In this case, each of the solar cell 70 and the storage battery 80 functions as a "DC power source", and the grid 90 functions as a "three-phase AC load (AC load)" having a U phase, a V phase, and a W phase. In other words, when the storage battery 80 is charging, the power conversion system 10 converts the AC power supplied from the grid 90 into DC power, and outputs the DC power to the storage battery 80. In this case, the storage battery 80 functions as a "DC load", and the grid 90 functions as a "three-phase AC power source (AC power source)" having a U phase, a V phase, and a W phase.

[0029] like Figure 1As shown, the power conversion system 10 according to this embodiment includes a first circuit 1 and a second circuit 2, and transmits power between first internal terminals 111, 112 of the first circuit 1 and second internal terminals 211, 212 of the second circuit 2. The first circuit 1 includes first internal terminals 111, 112 and first external terminals 113-115, and the first external terminals 113-115 are electrically connected to the power grid 90. The second circuit 2 includes at least second internal terminals 211, 212. In this embodiment, the second circuit 2 includes second internal terminals 211, 212 and second external terminals 213, 214.

[0030] The power conversion system 10 also includes a third circuit 3. The third circuit 3 includes third internal terminals 341, 342 and third external terminals 343, 344. In the power conversion system 10, the first internal terminals 111, 112, the second internal terminals 211, 212 and the third internal terminals 341, 342 are electrically connected to the same connection unit 7. The third circuit 3 includes switching elements Q31-Q34 and a transformer 33 electrically connected to the switching elements Q31-Q34. The third circuit 3 provides an output voltage VT between both ends of a secondary winding 332 of the transformer 33 via the switching elements Q31-Q34 and the transformer 33. The secondary winding 332 is electrically connected to the third internal terminals 341, 342. The output voltage VT has a rise range W11 (see Figure 2 ), falling range W13 (see Figure 2 ) and flat range W12 (see Figure 2 ) of the waveform W1 (see Figure 2 In the rising range W11, the output voltage VT increases from the first potential VT1 (see Figure 2 ) becomes a second potential VT2 higher than the first potential VT1 (see Figure 2 ). In the falling range W13, the output voltage VT changes from the second potential VT2 to the first potential VT1. In the flat range W12, the output voltage VT remains at the first potential VT1 or the second potential VT2. As used herein, if the waveform range is "flat", the entire waveform range may naturally be flat, but may also have slight changes at least partially. Therefore, even if the flat range W12 of the waveform W1 of the output voltage VT has some slight changes, the flat range W12 may be considered to be flat herein.

[0031] Furthermore, the virtual DC voltage generator circuit 3 according to the embodiment may be used as the third circuit 3 in the power conversion system 10 .

[0032] As described above, in the power conversion system 10 according to the embodiment, the third circuit 3 provides the output voltage VT between both ends of the secondary winding 332 of the transformer 33. This allows a DC voltage corresponding to the flat range W12 of the output voltage VT to be generated in the connection unit 7. Therefore, the first circuit 1 and the second circuit 2 can be connected on the DC side without using a smoothing capacitor.

[0033] Furthermore, in the known power conversion system, in order to smooth the ripples generated on the DC side by the AC component having, for example, a commercial frequency of the power supply or load on the AC side, a capacitor having a large capacity is provided for the connection unit 7. In contrast, in the power conversion system 10 according to this embodiment, the effect of smoothing the above ripples can be achieved by the capacitors C1, C2 or the battery 80, so there is no need to provide a smoothing capacitor for the connection unit 7.

[0034] In the following description of the exemplary embodiments, the power conversion system 10 will be described as being introduced into a non-residential facility, such as an office building, a hospital, a commercial facility, or a school.

[0035] In particular, in recent years, there has been an increasing trend for companies or individuals to "sell electricity" by causing the power obtained from a distributed power source (e.g., a solar cell 70, a storage battery 80, or a fuel cell) to flow back to a commercial power grid. The sale of electricity is achieved by connecting the distributed power source to the commercial power grid. When the grid connection is made, the power generated by the distributed power source is converted into power suitable for the commercial power grid by using a power conversion system 10 called a "power conditioner." The power conversion system 10 according to this embodiment can be used, for example, as a power conditioner to convert DC power into three-phase AC power between the solar cell 70 and the storage battery 80 as a distributed power source and the power grid 90, and vice versa.

[0036] (2) Structure

[0037] Next, we will refer to Figure 1 The structure of the power conversion system 10 according to this embodiment is described.

[0038] like Figure 1As shown, the power conversion system 10 according to this embodiment includes a first circuit 1, a second circuit 2 and a third circuit 3. The power conversion system 10 performs power conversion between two first DC terminals T11, T12, two second DC terminals T21, T22 and three AC terminals T31, T32, T33. Electrically connected to the first DC terminals T11, T12 is a solar cell 70 used as a DC power source. Electrically connected to the second DC terminals T21, T22 is a storage battery 80 used as a DC power source or a DC load. Electrically connected to the AC terminals T31, T32, T33 is a power grid 90 as a three-phase AC power source or a three-phase AC load having a U phase, a V phase and a W phase, respectively.

[0039] The power conversion system 10 also includes a filter circuit 4, a buffer circuit 5, a control circuit 6, and a connection unit 7. The power conversion system 10 may also include two first DC terminals T11, T12, two second DC terminals T21, T22, and three AC terminals T31, T32, T33. Alternatively, the two first DC terminals T11, T12, the two second DC terminals T21, T22, and the three AC terminals T31, T32, T33 do not necessarily belong to the constituent elements of the power conversion system 10. In addition, as used herein, a "terminal" is not necessarily a component that connects, for example, an electric wire, but may also be, for example, a lead of an electronic component or a part of a conductor included in a circuit board.

[0040] (2.1) First Circuit

[0041] The first circuit 1 may be, for example, a DC / AC converter. Specifically, the first circuit 1 may be a three-phase inverter circuit for converting a DC voltage between terminals P1 and N1 (described later) into an AC voltage having a rectangular waveform. Figure 1 As shown, the first circuit 1 includes six first switch elements Q11-Q16 connected together in a bridge. In addition, the first circuit 1 also includes two first internal terminals 111, 112 and three first external terminals 113-115.

[0042] Each of the first switching elements Q11-Q16 can be, for example, a depletion-type n-channel metal oxide semiconductor field effect transistor (MOSFET). The first switching element Q11 having a higher potential is electrically connected in series with the first switching element Q12 having a lower potential between the terminals P1 and N1. The first switching element Q13 having a higher potential is electrically connected in series with the first switching element Q14 having a lower potential between the terminals P1 and N1. The first switching element Q15 having a higher potential is electrically connected in series with the first switching element Q16 having a lower potential between the terminals P1 and N1. That is, between the terminals P1 and N1, the series circuit of the first switching elements Q11 and Q12, the series circuit of the first switching elements Q13 and Q14, and the series circuit of the first switching elements Q15 and Q16 are electrically connected in parallel with each other.

[0043] Each of the first switching elements Q11-Q16 includes a parasitic diode having an anode electrically connected to a source of an associated one of the first switching elements Q11-Q16 and a cathode electrically connected to a drain of an associated one of the first switching elements Q11-Q16.

[0044] The drain of each of the first switching elements Q11, Q13, Q15 having a higher potential is electrically connected to the terminal P1 via the first internal terminal 111. The source of each of the first switching elements Q12, Q14, Q16 having a lower potential is electrically connected to the terminal N1 via the first internal terminal 112. In addition, the source of the first switching element Q11 having a higher potential is electrically connected to the drain of the first switching element Q12 having a lower potential. Similarly, the source of the first switching element Q13 having a higher potential is electrically connected to the drain of the first switching element Q14 having a lower potential. Similarly, the source of the first switching element Q15 having a higher potential is electrically connected to the drain of the first switching element Q16 having a lower potential.

[0045] The first switching elements Q11 - Q16 are turned on and off in response to first drive signals Sig5 - Sig10 supplied from the control circuit 6 , respectively.

[0046] (2.2) Second Circuit

[0047] The second circuit 2 may be, for example, a DC / DC converter. Specifically, the second circuit 2 may be a boost chopper circuit for boosting the DC voltage provided from the solar cell 70. Figure 1 As shown, the second circuit 2 includes a capacitor C2, an inductor L1 and two second switch elements Q21, Q22. In addition, the second circuit 2 also includes two second internal terminals 211, 212 and two second external terminals 213, 214.

[0048] The capacitor C2 is electrically connected between the two first DC terminals T11 and T12 via the two second external terminals 213 and 214. In other words, the capacitor C2 is connected to the solar cell 70 via the two second external terminals 213 and 214 and the two first DC terminals T11 and T12. The capacitor C2 may be, for example, an electrolytic capacitor. The capacitor C2 has the ability to stabilize the voltage between the first DC terminals T11 and T12. Alternatively, the capacitor C2 does not have to be one of the constituent elements of the second circuit 2.

[0049] Each of the second switching elements Q21, Q22 may be, for example, a depletion-type n-channel MOSFET. The second switching element Q21 having a higher potential is electrically connected in series with the second switching element Q22 having a lower potential between the terminals P1 and N1. That is, the series circuit of the second switching elements Q21, Q22 is electrically connected between the terminals P1 and N1.

[0050] Each of the second switching elements Q21, Q22 includes a parasitic diode having an anode electrically connected to a source of an associated one of the second switching elements Q21, Q22 and a cathode electrically connected to a drain of an associated one of the second switching elements Q21, Q22.

[0051] The drain of the second switching element Q21 having a higher potential is electrically connected to the terminal P1 via the second internal terminal 211. The source of the second switching element Q22 having a lower potential is electrically connected to the terminal N1 via the second internal terminal 212. In addition, the source of the second switching element Q21 having a higher potential is electrically connected to the drain of the second switching element Q22 having a lower potential.

[0052] The second switching elements Q21 , Q22 are turned on and off in response to second drive signals Sig11 , Sig12 supplied from the control circuit 6 , respectively.

[0053] A first terminal of the inductor L1 is electrically connected to the second external terminal 213. A second terminal of the inductor L1 is electrically connected to a connection node between the second switching elements Q21, Q22.

[0054] (2.3) Third Circuit

[0055] The third circuit (virtual DC power supply generator circuit) 3 may be, for example, a DC / DC converter. Figure 1 As shown, the third circuit 3 includes a capacitor C1, a transformer 33 and four third switching elements Q31-Q34. The third circuit 3 also includes two third internal terminals 341, 342 and two third external terminals 343, 344.

[0056] The capacitor C1 is electrically connected between the two second DC terminals T21 and T22 via the two third external terminals 343 and 344. In other words, the capacitor C1 is connected to the battery 80 via the two third external terminals 343 and 344 and the two second DC terminals T21 and T22. The capacitor C1 may be, for example, an electrolytic capacitor. The capacitor C1 has the ability to stabilize the voltage between the second DC terminals T21 and T22. Alternatively, the capacitor C1 does not have to be one of the constituent elements of the third circuit 3.

[0057] Each of the third switching elements Q31-Q34 may be, for example, a depletion-type n-channel MOSFET. Each of the third switching elements Q31-Q34 includes a parasitic diode. The anode of the parasitic diode of each of the third switching elements Q31-Q34 is electrically connected to the source of the associated one of the third switching elements Q31-Q34, and the cathode thereof is electrically connected to the drain of the associated one of the third switching elements Q31-Q34.

[0058] The third switching elements Q31-Q34 are turned on and off respectively in response to the third drive signals Sig1-Sig4 provided from the control circuit 6. Note that in the following description, when there is no need to particularly distinguish the first drive signals Sig5-Sig10, the second drive signals Sig11, Sig12, and the third drive signals Sig1-Sig4 from each other, these drive signals will be collectively referred to as "drive signals Sig1-Sig12" hereinafter.

[0059] The transformer 33 includes a primary winding 331 and a secondary winding 332 that are magnetically coupled together. The primary winding 331 is electrically connected to the capacitor C1 via the third switching elements Q31, Q32. The secondary winding 332 is electrically connected between the third internal terminals 341, 342 via the third switching elements Q33, Q34.

[0060] The transformer 33 can be, for example, an RF isolation transformer with a center tap. The primary winding 331 of the transformer 33 can be implemented as, for example, a series circuit of two windings L31 and L32, whose connection node is the primary side center tap CT1. Similarly, the secondary winding 332 of the transformer 33 can be implemented as, for example, a series circuit of two windings L33 and L34, whose connection node is the secondary side center tap CT2. That is, the two windings L31 and L32 are electrically connected in series to form the primary winding 331. Similarly, the two windings L33 and L34 are electrically connected in series to form the secondary winding 332. The primary side center tap CT1 is electrically connected to the positive terminal of the capacitor C1 (i.e., close to the second DC terminal T21). The secondary side center tap CT2 is electrically connected to a third internal terminal 341. The turns ratio of the windings L31, L32, L33, and L34 can be, for example, 1:1:1:1. For example, the turns ratio of the windings L31, L32, L33, L34 may be arbitrarily changed according to the specifications of the power conversion system 10. In the following description, a circuit including the third switching elements Q31, Q32 and the primary winding 331 of the transformer 33 will hereinafter be referred to as a "primary side circuit 31", and a circuit including the third switching elements Q33, Q34 and the secondary winding 332 of the transformer 33 will hereinafter be referred to as a "secondary side circuit 32".

[0061] The third circuit 3 receives the voltage across the battery 80 as an input voltage via the second DC terminals T21 , T22 .

[0062] In the third circuit 3, the third switching elements Q31, Q32 of the primary side circuit 31 are turned on and off, thereby converting the input voltage into a radio frequency AC voltage having a rectangular waveform of, for example, 20kHz, and applying (providing) the AC voltage to the primary winding 331 (including windings L31, L32).

[0063] The third switching element Q31 is electrically connected in series with the winding L31 between the two ends of the capacitor C1. The third switching element Q32 is electrically connected in series with the winding L32 between the two ends of the capacitor C1. In other words, the series circuit of the third switching element Q31 and the winding L31 and the series circuit of the third switching element Q32 and the winding L32 are electrically connected in parallel between the second DC terminals T21 and T22.

[0064] The drain of the third switching element Q31 is electrically connected to the primary side center tap CT1 via the winding L31. The drain of the third switching element Q32 is electrically connected to the primary side center tap CT1 via the winding L32. The sources of the third switching elements Q31 and Q32 are electrically connected to the second DC terminal T22 having a low potential (i.e., a negative side).

[0065] In the third circuit 3, the third switching elements Q33, Q34 of the secondary side circuit 32 are turned on and off, thereby converting the AC voltage having positive and negative polarities and a rectangular waveform and generated on the secondary winding 332 (including the windings L33, L34) into a DC voltage having a positive polarity, and outputting the DC voltage between the two terminals P1, N1 of the connection unit 7. In this case, a voltage is provided between the terminals P1, N1 so that, of the two terminals P1, N1, the terminal P1 has a higher potential (positive pole), and the terminal N1 has a lower potential (negative pole).

[0066] The third switch element Q33 is electrically connected in series with the winding L33 between the terminals P1 and N1. The third switch element Q34 is electrically connected in series with the winding L34 between the terminals P1 and N1. That is, the series circuit of the third switch element Q33 and the winding L33 and the series circuit of the third switch element Q34 and the winding L34 are electrically connected in parallel between the terminals P1 and N1.

[0067] The drain of the third switching element Q33 is electrically connected to the secondary side center tap CT2 via the winding L33. The drain of the third switching element Q34 is electrically connected to the secondary side center tap CT2 via the winding L34. The sources of the third switching elements Q33 and Q34 are electrically connected to the terminal N1 with a lower potential (i.e., the negative side).

[0068] Alternatively, a capacitor may be electrically connected between the drain and source of each of the third switching elements Q31, Q32. In this case, the capacitor resonates with the primary winding 331, thereby achieving soft switching of the third switching elements Q31-Q34. Alternatively, the capacitor may be electrically connected between the drains of the third switching elements Q31, Q32, or may be electrically connected in parallel to each of the windings L31, L32.

[0069] (2.4) Filter circuit

[0070] The filter circuit 4 smoothes the AC voltage having a rectangular waveform and supplied from the first circuit 1. Thus, the AC voltage having a rectangular waveform and supplied from the first circuit 1 is converted into an AC voltage having a sinusoidal waveform and an amplitude corresponding to its pulse width.

[0071] Specifically, the filter circuit 4 includes a plurality of (for example, Figure 1 In the example shown, there are three inductors L41, L42, L43 and a plurality of (for example, Figure 1In the example shown, there are three capacitors C41, C42, and C43. The first terminal of the inductor L41 is electrically connected to the connection node between the first switching elements Q11 and Q12 via the first external terminal 113, and the second terminal thereof is electrically connected to the AC terminal T31. The first terminal of the inductor L42 is electrically connected to the connection node between the first switching elements Q13 and Q14 via the first external terminal 114, and the second terminal thereof is electrically connected to the AC terminal T32. The first terminal of the inductor L43 is electrically connected to the connection node between the first switching elements Q15 and Q16 via the first external terminal 115, and the second terminal thereof is electrically connected to the AC terminal T33. The capacitor C41 is electrically connected between the AC terminals T31 and T32. The capacitor C42 is electrically connected between the AC terminals T32 and T33. The capacitor C43 is electrically connected between the AC terminals T31 and T33.

[0072] In other words, the connection node between the first switching elements Q11 and Q12 is electrically connected to the AC terminal T31 corresponding to the U phase via the inductor L41. The connection node between the first switching elements Q13 and Q14 is electrically connected to the AC terminal T32 corresponding to the V phase via the inductor L42. The connection node between the first switching elements Q15 and Q16 is electrically connected to the AC terminal T33 corresponding to the W phase via the inductor L43.

[0073] (2.5) Buffer circuit

[0074] The snubber circuit 5 is electrically connected to the terminals P1 , N1 . That is, the snubber circuit 5 is electrically connected to the transformer 33 of the third circuit 3 .

[0075] The buffer circuit 5 is a regenerative buffer circuit for absorbing electric energy from the terminals P1 and N1 of the connection unit 7 and injecting (regenerating) the electric energy into the terminals P1 and N1. Figure 2 ), the buffer circuit 5 absorbs part of the electric energy exceeding the first clamp value Vclp1 through the terminals P1 and N1, thereby clamping the upper limit value of the bus voltage Vbus at the first clamp value Vclp1. In addition, if the bus voltage Vbus becomes lower than the second clamp value Vclp2 (<Vclp1), the buffer circuit 5 injects (regenerates) electric energy into the terminals P1 and N1, thereby clamping the lower limit value of the bus voltage Vbus at the second clamp value Vclp2.

[0076] like Figure 1 As shown, the buffer circuit 5 includes a plurality of (for example, Figure 1 In the example shown, two) diodes D1, D2, a resistor R1 and a plurality of (eg, Figure 1In the example shown, there are two) capacitors C51 and C52. Diode D1 is electrically connected in series with capacitor C51 between terminals P1 and N1. Diode D2 is electrically connected in series with capacitor C52 between terminals P1 and N1. The anode of diode D1 is electrically connected to terminal P1, and its cathode is electrically connected to terminal N1 via capacitor C51. The anode of diode D2 is electrically connected to terminal N1 via capacitor C52, and its cathode is electrically connected to terminal P1. That is, diodes D1 and D2 are connected in opposite directions between terminals P1 and N1. Resistor R1 is electrically connected between the connection node of diode D1 and capacitor C51 and the connection node of diode D2 and capacitor C52.

[0077] In the buffer circuit 5, when the bus voltage Vbus exceeds the first clamping value Vclp1, the electric energy absorbed from the terminals P1 and N1 is stored in the capacitor C51. The electric energy stored in the capacitor C51 is transmitted to the capacitor C52 via the resistor R1. If the bus voltage Vbus is lower than the second clamping value Vclp2, the electric energy stored in the capacitor C52 is regenerated at the terminals P1 and N1 via the diode D2.

[0078] (2.6) Control circuit

[0079] The control circuit 6 is implemented as, for example, a microcomputer including a processor and a memory. That is, the control circuit 6 is implemented as a computer system including a processor and a memory. The computer system performs the functions of the control circuit 6 by causing the processor to execute an appropriate program. The program may be pre-stored in the memory. Alternatively, the program may also be downloaded via a telecommunication line such as the Internet, or distributed after being stored in a non-transitory storage medium such as a memory card.

[0080] The control circuit 6 is configured to control each of the first circuit 1, the second circuit 2, and the third circuit 3. The control circuit 6 outputs first drive signals Sig5-Sig10 for driving the first switching elements Q11-Q16, respectively, to the first circuit 1. The control circuit 6 outputs second drive signals Sig11, Sig12 for driving the second switching elements Q21, Q22, respectively, to the second circuit 2. The control circuit 6 outputs third drive signals Sig1-Sig4 for driving the third switching elements Q31-Q34, respectively, to the third circuit 3. Each of the drive signals Sig1-Sig12 is a PWM signal, which is a binary signal that switches between a high level (exemplary effective value) and a low level (exemplary invalid value).

[0081] (2.7) Connection unit

[0082] like Figure 1As shown, the first circuit 1 is electrically connected to the connection unit 7 via the first internal terminals 111, 112. In addition, the second circuit 2 is also electrically connected to the connection unit 7 via the second internal terminals 211, 212. In addition, the third circuit 3 is also electrically connected to the connection unit 7 via the third internal terminals 341, 342. In other words, the first internal terminals 111, 112 of the first circuit 1, the second internal terminals 211, 212 of the second circuit 2, and the third internal terminals 341, 342 of the third circuit 3 are all electrically connected to the same connection unit 7. That is, in the power conversion system 10 according to the present embodiment, the first circuit 1, the second circuit 2, and the third circuit 3 are electrically connected together on the DC side.

[0083] like Figure 1 As shown, the connection unit 7 includes terminals P1 and N1. In addition, the secondary side circuit 32 of the third circuit 3 operates so that the voltage at the terminal P1 is positive relative to the terminal N1 (i.e., the terminal P1 is allowed to have a higher potential than the terminal N1). Electrically connected to the connection unit 7 is the above-mentioned buffer circuit 5.

[0084] (3) Operation

[0085] (3.1) Operation of power conversion system

[0086] Next, we will refer to Figure 2-Figure 4 The operation of the power conversion system 10 according to this embodiment is described.

[0087] The power conversion system 10 according to the present embodiment converts (transmits) power bidirectionally between the first DC terminal T11, T12, the second DC terminal T21, T22 and the AC terminal T31, T32, T33. That is, the power conversion system 10 has an inverter mode and a converter mode as its two operating modes. As used herein, the inverter mode refers to a mode in which the DC power supplied to the first DC terminal T11, T12 and the second DC terminal T21, T22 is converted into three-phase AC power, and then the three-phase AC power is output through the AC terminals T31, T32, T33. The converter mode in this article refers to a mode in which the three-phase AC power supplied to the AC terminals T31, T32, T33 is converted into DC power, and then the DC power is output through the second DC terminals T21, T22.

[0088] In other words, the inverter mode herein refers to a mode in which a voltage drop is caused between the AC terminals T31, T32, and T33 in the same direction as the direction in which the current flows through the grid 90, that is, a mode in which voltages and currents of the same polarity are generated. On the other hand, the converter mode herein refers to a mode in which a voltage drop is caused between the AC terminals T31, T32, and T33 in the opposite direction to the direction in which the current flows through the grid 90, that is, a mode in which voltages and currents of opposite polarities are generated.

[0089] In the following description, the case where the power conversion system 10 operates in the inverter mode to convert DC power into three-phase AC power with a frequency of 50 Hz or 60 Hz is described as an example. In addition, in the following description, the case where the driving frequency of the second switching elements Q21, Q22 is 40 kHz and the driving frequency of the third switching elements Q31-Q34 is 20 kHz is described as an example.

[0090] Figure 2 is a waveform diagram showing the operation of the power conversion system 10 according to the present embodiment in the inverter mode. Figure 2 In the figure, the horizontal axis indicates time. Figure 2 , the waveforms of the third drive signal Sig1-Sig4, the first drive signal Sig5, Sig6, the first drive signal Sig7, Sig8, the first drive signal Sig9, Sig10, and the second drive signal Sig11, Sig12 are shown in this order from top to bottom. Figure 2 Also shown are the output voltage VT and the third output current I3, the voltage Vo between the two ends of the second switching element Q22 and the second output current I2, the first output current I1, the currents Id1 and Id2 flowing through the diodes D1 and D2, the bus voltage Vbus, and the first clamp value Vclp1 and the second clamp value Vclp2.

[0091] For the drive signals Sig1-Sig12, Figure 2 In the figure, their high level is represented by "H", and their low level is represented by "L". Each of the first switching elements Q11-Q16, the second switching elements Q21, Q22, and the third switching elements Q31-Q34 is turned on when its associated drive signal Sig1-Sig12 is at a high level, and is turned off when its associated drive signal Sig1-Sig12 is at a low level.

[0092] In addition, the output voltage VT is a voltage generated between both ends of the secondary winding 332. The third output current I3 is a current flowing from the secondary side center tap CT2 to the terminal P1. In addition, the voltage Vo is a voltage between both ends of the second switching element Q22. The second output current I2 is a current flowing to the terminal P1 through the second switching element Q21. The first output current I1 is a current flowing from the first circuit 1 to the terminal P1. In the inverter mode, the first output current I1 flows from the terminal P1 to the first circuit 1, and is therefore represented by "-I1".

[0093] The control circuit 6 controls the second circuit 2 so that its second switching elements Q21, Q22 are alternately turned on and off. When the second switching element Q21 is turned on and the second switching element Q22 is turned off, a voltage with a positive polarity is applied (supplied) to the terminals P1, N1. On the other hand, when the second switching element Q21 is turned off and the second switching element Q22 is turned on, the electric energy generated by the solar cell 70 is stored in the inductor L1 via the second switching element Q22.

[0094] The control circuit 6 controls the third switching elements Q31, Q32 of the third circuit 3 so that positive and negative voltages are alternately applied to the primary winding 331. In addition, the control circuit 6 controls the third switching elements Q33, Q34 so that the voltage at the terminal P1 is positive relative to the terminal N1.

[0095] Specifically, the control circuit 6 turns off the third switch elements Q32 and Q34 when turning on the third switch elements Q31 and Q33. The control circuit 6 turns on the third switch elements Q32 and Q34 when turning off the third switch elements Q31 and Q33. In this case, the control circuit 6 controls the third switch elements Q31-Q34 with the same duty ratio. In this embodiment, the duty ratio of the third switch elements Q31-Q34 is set to 0.5 (substantially 50%).

[0096] In addition, the control circuit 6 controls the third switching elements Q31 , Q32 so that a radio frequency AC voltage is supplied to the primary winding 331 and the secondary winding 332 , and also controls the third switching elements Q33 , Q34 so that a voltage having a positive polarity is supplied to the terminals P1 , N1 .

[0097] For the first circuit 1 , the control circuit 6 controls the amplitude or phase of at least one of the voltage or current output through the AC terminals T31 , T32 , T33 by turning each of the first switching elements Q11 - Q16 on or off.

[0098] The control circuit 6 controls the first circuit 1 so that in a period T1a including an inversion period Td1 in which the polarity of the voltage applied to the primary winding 331 is inverted, power is not transmitted between the first circuit 1 and the third circuit 3. In addition, the control circuit 6 controls the second circuit 2 so that in a period T1b including the inversion period Td1, power is not transmitted between the second circuit 2 and the third circuit 3. Furthermore, the control circuit 6 controls the first circuit 1 so that power is transmitted between the first circuit 1 and the third circuit 3 in a period T2a different from the period T1a. Likewise, the control circuit 6 controls the second circuit 2 so that power is transmitted between the second circuit 2 and the third circuit 3 in a period T2b different from the period T1b.

[0099] Specifically, the control circuit 6 operates to repeatedly go through a series of first to fifth modes to be described below.

[0100] In the first mode, the control circuit 6 outputs the first drive signals Sig5-Sig10 to the first circuit 1, so that the first switch elements Q11, Q13, Q15 with higher potentials are turned on, or the first switch elements Q12, Q14, Q16 with lower potentials are turned on. This changes the operation mode to the first cycle mode in which the current circulates in the first circuit 1 (hereinafter referred to as the "first cycle period").

[0101] In the second mode, the control circuit 6 outputs the second drive signal Sig11, Sig12 to the second circuit 2, so that the second switch element Q21 with a higher potential is turned off, and the second switch element Q22 with a lower potential is turned on, wherein the first circuit 1 is allowed to operate in the first mode. This changes the operation mode to a second cycle mode in which the current circulates in the second circuit 2 (hereinafter referred to as a "second cycle period"). Optionally, the first mode and the second mode may appear in reverse order.

[0102] In the third mode, the control circuit 6 outputs the third drive signals Sig1-Sig4 to the third circuit 3, so that the four third switch elements Q31-Q34 are turned off, wherein the first circuit 1 is allowed to operate in the first mode, and the second circuit 2 is allowed to operate in the second mode. At this time, the output voltage VT rises or falls with the excitation current generated by the transformer 33 (see Figure 2 ). In addition, since the first output current I1 becomes zero in this case, the third switching elements Q31-Q34 can perform zero current switching (soft switching), which allows stable switching at all times (corresponding to the inversion period) regardless of the load current.

[0103] In the fourth mode, the control circuit 6 outputs the third drive signal Sig1-Sig4 to the third circuit 3, so that the third switching elements Q31, Q33 are turned on, or the third switching elements Q32, Q34 are turned on. Therefore, a voltage with a positive polarity is applied (or provided) between the terminals P1 and N1. In addition, in the fourth mode, the control circuit 6 outputs the first drive signal Sig5-Sig10 to the first circuit 1, so that the first switching element Q11 with a higher potential is turned on and the first switching elements Q14, Q16 with a lower potential are turned on, or the first switching elements Q11, Q15 with a higher potential are turned on and the first switching element Q14 with a lower potential is turned on. In this way, power is transmitted between the first circuit 1 and the third circuit 3 (corresponding to the transmission period). Although referring to Figure 2 The example shown describes the (on / off) state of each switching element, but Figure 2 The (on / off) states of the third switching elements Q31 - Q34 shown should not be construed as limiting but may be modified in various ways as long as the exclusive relationship between the first circuit 1 and the first mode is satisfied.

[0104] In the fifth mode, the control circuit 6 outputs the third drive signal Sig1-Sig4 to the third circuit 3, so that the third switch elements Q31, Q33 are turned on, or the third switch elements Q32, Q34 are turned on. Therefore, a voltage with a positive polarity is applied (or provided) between the terminals P1 and N1. In addition, in the fourth mode, the control circuit 6 outputs the second drive signal Sig11, Sig12 to the second circuit 2, so that the second switch element Q21 with a higher potential is turned on, and the second switch element Q22 with a lower potential is turned off. In this way, power is converted between the second circuit 2 and the third circuit 3 (corresponding to the transmission period). Optionally, the fourth mode and the fifth mode may appear in reverse order.

[0105] The first circuit 1 repeatedly passes through the first mode and the fourth mode, and the second circuit 2 repeatedly passes through the second mode and the fifth mode. When the first circuit 1 operates in the first mode, and the second circuit 2 operates in the second mode, the third circuit 3 operates in the third mode.

[0106] In this case, the inversion period Td1 in which all four third switch elements Q31-Q34 of the third circuit 3 are turned off needs to be synchronized with the first mode of the first circuit 1. Therefore, the first circuit 1 needs to be synchronized with the carrier of the third circuit 3. In addition, the inversion period Td1 in which all four third switch elements Q31-Q34 of the third circuit 3 are turned off needs to be synchronized with the second mode of the second circuit 2. Therefore, the second circuit 2 needs to be synchronized at a frequency twice the carrier frequency of the third circuit 3. In other words, synchronizing the carrier of the third circuit 3 with the carriers of the first circuit 1 and the second circuit 2 can make the inversion period Td1 in which all four third switch elements Q31-Q34 of the third circuit 3 are turned off synchronized with the first mode and the second mode.

[0107] like Figure 2 As shown, the waveform W1 of the output voltage VT generated between the two ends of the secondary winding 332 of the transformer 33 of the third circuit 3 has a rectangular waveform. Specifically, the waveform W1 of the output voltage VT includes a rising range W11, a falling range W13, and a flat range W12. Figure 2 As shown, in the rising range W11, the output voltage VT increases (changes) proportionally from the first potential VT1 to the second potential VT2 (>VT1) higher than the first potential VT1. Figure 2 As shown, in the falling range W13, the output voltage VT decreases (changes) proportionally from the second potential VT2 to the first potential VT1. Figure 2 As shown, in the flat range W12, the output voltage VT is maintained at the first potential VT1 or the second potential VT2. In addition, in the power conversion system 10 according to this embodiment, a DC voltage corresponding to the flat range W12 of the output voltage VT generated between both ends of the secondary winding 332 is applied (supplied) to the terminals P1, N1 of the connection unit 7. That is, the power conversion system 10 according to this embodiment allows a DC voltage corresponding to the flat range W12 of the output voltage VT to be generated in the connection unit 7, thereby enabling the first circuit 1 and the second circuit 2 to be connected on the DC side.

[0108] In addition, on the path from the capacitor C1 of the third circuit 3 to the connection unit 7, an inductor (except the transformer 33) is not connected appropriately. For example, if the second switching element Q21 with a higher potential in the second circuit 2 is turned on, and the second switching element Q22 with a lower potential is turned off, the capacitor C2 with a low impedance and the connection unit 7 are connected via the inductor L1, so that the impedance is relatively high. On the other hand, if the second switching element Q21 with a higher potential in the second circuit 2 is turned off, and the second switching element Q22 with a lower potential is turned on, the path from the capacitor C2 to the connection unit 7 is cut off, so that the impedance is higher. In this case, the load current causes the voltage change in the connection unit 7 to be too large to perform AC conversion.

[0109] In contrast, in the power conversion system 10 according to the embodiment, in the period in which any one of the four third switching elements Q31-Q34 of the third circuit 3 is turned on, the impedance between the terminals P1 and N1 becomes a low impedance equivalent to the capacitor C1. Therefore, even if a smoothing capacitor is not used in the connection unit 7, the impedance between the terminals P1 and N1 becomes low.

[0110] In this case, the third circuit 3 acts as a voltage source only when the third circuit 3 has a low impedance. Therefore, the third circuit 3 appropriately has a low impedance. In other words, an inductor (except the transformer 33) is appropriately not connected on the path from the capacitor C1 of the third circuit 3 to the connection unit 7. Even so, a high impedance may be caused at a frequency sufficiently higher than the carrier frequency (for example, in the case of ringing). However, since the frequency component can be removed by the buffer circuit 5, the low impedance can still be maintained.

[0111] In addition, if the time ratio (i.e., the ratio of the conduction period of the switching element to its cycle) is low, the voltage utilization rate decreases, and therefore, it is necessary to increase the voltage value of the output voltage from the third circuit 3 to the connection unit 7. Therefore, in the period in which any one of the four third switching elements Q31-Q34 of the third circuit 3 is turned on, the time ratio is appropriately equal to or greater than 50%. The time ratio of this period is more appropriately equal to or greater than 90%. The power conversion system 10 according to this embodiment can increase the time ratio to 50% or more by shortening the reversal period Td1 of the transformer 33 of the third circuit 3.

[0112] exist Figure 2 In the example shown, for example, there is a time difference between the moment when the first switch element Q11 is turned on and the moment when the second switch element Q21 is turned on. Therefore, when the second switch element Q21 is turned on, the rate of change (dI3 / dt) of the third output current I3 increases. Figure 2In the example shown, for example, there is a time difference between the moment when the first switch element Q13 is turned on and the moment when the second switch element Q22 is turned on. Therefore, when the second switch element Q22 is turned on, the rate of change of the third output current I3 also increases. In addition, as the change of the third output current I3 becomes larger, the ringing voltage caused by the leakage inductance of the transformer 33 also increases. Therefore, in order to reduce the ringing voltage, the amplitude of the change of the third output current I3 is appropriately reduced. Specifically, in order to reduce the amplitude of the change of the third output current I3, the moment when the first switch element Q11-Q16 is turned on or the moment when the first switch element Q11-Q16 is turned off is appropriately consistent with the moment when the second switch element Q21, Q22 is turned on or the moment when the second switch element Q21, Q22 is turned off (i.e., synchronized).

[0113] exist Figure 3 In the example shown, the first switching element Q11 and the second switching element Q21 are turned on at respective times synchronized with each other. Figure 3 In the example shown, the first switching element Q13 and the second switching element Q22 are also turned on at the same time. Figure 3 In the example shown, the first switching element Q14 and the second switching element Q21 are turned on at respective times synchronized with each other. Figure 3 In the example shown, the respective moments at which the first switching element Q12 and the second switching element Q22 are turned on are synchronized with each other. This allows reducing the amplitude of variation caused in the third output current I3 at each of these moments, thereby also reducing the effective value of the third output current I3. In addition, reducing the amplitude of variation of the third output current I3 can also reduce the ringing voltage. Furthermore, as the ringing voltage decreases, the first clamping value Vclp1 and the second clamping value Vclp2 of the buffer circuit 5 also decrease (see Figure 2 and Figure 3 ).

[0114] In addition, Figure 2 In contrast, the current amounts Id1 and Id2 flowing through the diodes D1 and D2 of the snubber circuit 5 also decrease, resulting in a decrease in input power of the snubber circuit 5. Therefore, the output power of the snubber circuit 5 decreases, thereby enabling the energy causing ringing to also be reduced.

[0115] exist Figure 3In the example shown, the various moments when the first switch element Q11 and the second switch element Q21 are turned on are synchronized with each other, the various moments when the first switch element Q13 and the second switch element Q22 are turned on are also synchronized with each other, the moments when the first switch element Q14 and the second switch element Q21 are turned on are also synchronized with each other, and the moments when the first switch element Q12 and the second switch element Q22 are turned on are also synchronized with each other. However, since I3=-I1-I2, it is necessary to reduce d(I1+I2) / dt to reduce dI3 / dt. Therefore, in order to reduce d(I1+I2) / dt, the turn-on moment or turn-off moment of at least one of the first switch elements Q11-Q16 of the first circuit 1 and the turn-on moment or turn-off moment of at least one of the second switch elements Q21, Q22 of the second circuit 2 need to be synchronized with each other. For example, the turn-off moment of at least one of the first switch elements Q11-Q16 and the turn-off moment of at least one of the second switch elements Q21, Q22 can be synchronized with each other. Alternatively, the turn-on timing of at least one of the first switching elements Q11 - Q16 and the turn-off timing of at least one of the second switching elements Q21 , Q22 may be synchronized with each other, or vice versa.

[0116] In the first period T1 (see FIG. 1 ) including the reversal period Td1 in which the voltage applied to the primary winding 331 of the transformer 33 is reversed Figure 4 ), the control circuit 6 controls the first circuit 1 so that no power is transmitted between the first circuit 1 and the third circuit 3, and also controls the second circuit 2 so that no power is transmitted between the second circuit 2 and the third circuit 3. In addition, in the second time period T2 (see Figure 4 ), the control circuit 6 controls the first circuit 1 so that power is transmitted between the first circuit 1 and the third circuit 3, and also controls the second circuit 2 so that power is transmitted between the second circuit 2 and the third circuit 3.

[0117] More specifically, in the power conversion system 10, as Figure 4 As shown, the first period T1 and the second period T2 are allocated in the unit time corresponding to the half carrier of the PWM signal. In addition, the reversal period Td1 and the cycle period are allocated to the first period T1, and the supply period is allocated to the second period T2. Note that if the power conversion system 10 operates in the inverter mode, the supply period is allocated to the second period T2. On the other hand, if the power conversion system 10 operates in the converter mode, the regeneration period is allocated to the second period T2.

[0118] Then, the control circuit 6 generates a target voltage or current by performing PWM control on the first circuit 1 to change the ratio of the second period T2 to each unit period (half carrier). As used herein, the target voltage or current may be, for example, a voltage or current having the same waveform as the modulation signal used for PWM control.

[0119] As used herein, the first time length (i.e., the length of the time period T4 from the start of the first time period T1 to the start of the inversion time period Td1) is equal to or longer than the second time length (i.e., the length of the time period T3 from the end of the inversion time period Td1 to the end of the first time period T1). That is, by comparing the respective time lengths of the time periods T4 and T3 respectively set before and after the inversion time period Td1 within the first time period T1, it can be seen that the time length of the time period T4 before the inversion time period Td1 is equal to or longer than the time length of the time period T3 after the inversion time period Td1. Figure 4 In the illustrated example, the time length of the period T4 (first time length) is longer than the time length of the period T3 (second time length).

[0120] In this embodiment, specifically, even when at least the DC voltage applied to the second DC terminals T21, T22 is a maximum value within the rated operating range, the first time length (i.e., the time length of period T4) is equal to or longer than the second time length (i.e., the time length of period T3).

[0121] Specifically, the voltage applied to the power grid 90 has a value defined by the specification, while the voltage of the battery 80 has a range of a specific width defined by the specification. For example, as the voltage of the battery 80 rises, the excitation current of the transformer 33 rises, but its voltage utilization rate decreases. That is, the extra time is increased. Therefore, even if an overcurrent that cannot be caused in a stable state is generated, making the first time length (i.e., the time length of the period T4) longer than the second time length (i.e., the time length of the period T3) allows the residual current to have more time to decay. This reduces the possibility of the residual current (tail current) falling on the reversal period Td1, thereby reducing the bias of the transformer 33. As used herein, "residual current" refers to the current left due to the leakage inductance of the transformer 33 of the third circuit 3 even after the first circuit 1 and the second circuit 2 have been cut off.

[0122] On the contrary, if the voltage of the storage battery 80 is relatively low, the voltage utilization rate increases and the extra time decreases. In this case, even if the first time length (i.e., the time length of the period T4) is longer than the second time length (i.e., the time length of the period T3), the residual current may not have enough time to decay. In this case, the voltage of the transformer 33 may suddenly reverse, which may cause bias magnetism. Usually, when bias magnetism occurs, the excitation current of the transformer 33 increases, so better DC superposition characteristics are required. In this embodiment, if the voltage of the storage battery 80 is low, bias magnetism may occur. However, this rarely causes problems because the excitation current is originally low.

[0123] In this case, the second time length (ie, the time length of the period T3) is appropriately set to the minimum required value, and the first time length (ie, the time length of the period T4) is appropriately set to the maximum value falling within the allowable range.

[0124] Alternatively, the time periods T3 and T4 may also be defined as follows. Specifically, when the power conversion system 10 is operated in the inverter mode, the time period T4 may be defined as the time period from the end of the second time period T2 as the supply period to the start of the reversal period Td1, and the time period T3 may be defined as the time period from the end of the reversal period Td1 to the start of the second time period T2 as the supply period. Similarly, when the power conversion system 10 is operated in the converter mode, the time period T4 may be defined as the time period from the end of the second time period T2 as the regeneration period to the start of the reversal period Td1, and the time period T3 may be defined as the time period from the end of the reversal period Td1 to the start of the second time period T2 as the regeneration period.

[0125] The control circuit 6 suitably includes a detection unit for detecting an abnormality, for example, an overcurrent or an overvoltage, in each of the first circuit 1 and the second circuit 2. When the detection unit detects any abnormality in the first circuit 1 or the second circuit 2, the control circuit 6 suitably makes the turn-off timing of at least one of the first switching elements Q11-Q16 or the second switching elements Q21, Q22 different from the turn-off timing of the third switching elements Q31-Q34.

[0126] Specifically, for example, when the detection unit detects an overcurrent or overvoltage in the first circuit 1, the control circuit 6 turns off the first switch elements Q11-Q16. At this time, the control circuit 6 can turn off or not turn off the second switch elements Q21, Q22 of the second circuit 2. In addition, at this time, the control circuit 6 continues to perform PWM control on the third switch elements Q31-Q34 of the third circuit 3.

[0127] In addition, for example, when the detection unit detects an overcurrent or overvoltage in the second circuit 2, the control circuit 6 turns off the second switch elements Q21 and Q22. At this time, the control circuit 6 can turn off or not turn off the first switch elements Q11-Q16 of the first circuit 1. In addition, at this time, the control circuit 6 continues to perform PWM control on the third switch elements Q31-Q34 of the third circuit 3.

[0128] Then, when a predetermined period of time has elapsed since at least one of the first switching elements Q11 - Q16 or the second switching elements Q21 , Q22 has been turned off, the control circuit 6 turns off the third switching elements Q31 - Q34 .

[0129] This allows the regenerative energy supplied from the first circuit 1 or the second circuit 2 to be regenerated in the capacitor C1 , thereby allowing the stress applied to the third switching elements Q31 - Q34 to be reduced by the regenerative energy.

[0130] (3.2) Simulation results

[0131] Next, we will refer to Figures 5A-8C The simulation results of the power conversion system 10 according to this embodiment are described.

[0132] Figure 5A-5C The simulation results performed with the output power of the second circuit 2 set to 5 kW, the output power (discharge power) of the third circuit 3 set to 5 kW, and the output power (discharge power) of the first circuit 1 set to 10 kW are shown. Figure 5A shows the waveform of the current, Figure 5B shows the waveform of the voltage, and Figure 5C The waveform of the power is shown. In this example, the voltage Vbat between the two ends of the storage battery 80 is 320V, the voltage Vpv between the two ends of the solar cell 70 is 300V, and the voltage Vlink between the terminals P1 and N1 is 380V. In addition, the primary winding 331 and the secondary winding 332 of the transformer 33 have a turns ratio of 1:1.2. Please note that Figure 5B The voltage Vlink between the terminals P1 and N1 shown is an average value. Figure 5C The data shown, the output power (discharge power) of the first circuit 1 is 10kW, the output power of the second circuit 2 is 5kW, and the output power (discharge power) of the third circuit 3 is 5kW. It can be seen that the power is transmitted as designed.

[0133] Figure 6A-6C The simulation results performed with the output power of the second circuit 2 set to 5 kW, the output power (charging power) of the third circuit 3 set to -10 kW, and the output power (charging power) of the first circuit 1 set to -5 kW are shown. Fig. 6Ashows the waveform of the current, Figure 6B shows the waveform of the voltage, and Figure 6C The waveform of the power is shown. In this example, the voltage Vbat between the two ends of the storage battery 80 is 320V, the voltage Vpv between the two ends of the solar cell 70 is 300V, and the voltage Vlink between the terminals P1 and N1 is 380V. In addition, the primary winding 331 and the secondary winding 332 of the transformer 33 have a turns ratio of 1:1.2. Please note that Figure 6B The voltage Vlink between the terminals P1 and N1 shown is an average value. Figure 6C The data shown, the output power (charging power) of the first circuit 1 is -5kW, the output power of the second circuit 2 is 5kW, and the output power (charging power) of the third circuit 3 is -10kW. It can be seen that the power is transmitted as designed.

[0134] Figure 7 It shows that according to Figure 8A-8C An enlarged waveform diagram of a portion of the operation in the inverter mode of the power conversion system 10 of this embodiment is shown. Figure 8A-8C is another waveform diagram showing the simulation results performed by the power conversion system when the output power of the second circuit 2 is set to 10 kW, the output power of the third circuit 3 is set to 0 kW, and the output power (discharge power) of the first circuit 1 is set to 10 kW. Fig. 8A shows the waveform of the current, Figure 8B shows the waveform of the voltage, and Figure 8C The waveform of the power is shown. In this example, the voltage Vbat between the two ends of the storage battery 80 is 320V, the voltage Vpv between the two ends of the solar cell 70 is 300V, and the voltage Vlink between the terminals P1 and N1 is 380V. In addition, the primary winding 331 and the secondary winding 332 of the transformer 33 have a turns ratio of 1:1.2. Please note that Figure 8B The voltage Vlink between the terminals P1 and N1 shown is an average value. Figure 8C The data shown, the output power (discharge power) of the first circuit 1 is 10kW, the output power of the second circuit 2 is 10kW, and the output power of the third circuit 3 is 0kW. It can be seen that the power is transmitted as designed. In these results, it should be noted that according to Figure 7 According to the data shown, the time average value of the output current I3 of the third circuit 3 is 0A, and the output power of the third circuit 3 is 0kW. It can be seen that even if the output of the third circuit 3 is 0kW, it is still possible to output the output voltage VT having a rectangular waveform. In addition, even if the connection unit 7 is not provided with a smoothing capacitor, power can still be transmitted between the first circuit 1 and the second circuit 2.

[0135] (4) Variant

[0136] Please note that the first embodiment described above is only one of the exemplary embodiments of the various embodiments of the present disclosure and should not be interpreted as limiting. On the contrary, the first embodiment can be easily modified in various ways depending on design choices or any other factors without departing from the scope of the present disclosure. Next, the variations of the first embodiment will be listed one by one.

[0137] In the power conversion system 10 according to the present disclosure, its control circuit 6, for example, includes a computer system. The computer system may include a processor and a memory as main hardware components. The functions of the power conversion system 10 according to the present disclosure can be performed by causing the processor to execute a program stored in the memory of the computer system. The program may be pre-stored in the memory of the computer system. Alternatively, the program may also be downloaded via a telecommunications line, or distributed after being recorded in some non-temporary storage media such as a memory card, an optical disk, or a hard disk drive (any of which is readable by a computer system). The processor of the computer system may be implemented as a single or multiple electronic circuits, including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). These electronic circuits may be integrated on a single chip or distributed on multiple chips, as appropriate. These multiple chips may be integrated in a single device or distributed in multiple devices without restriction.

[0138] In addition, in the above-described embodiment, a plurality of constituent elements of the power conversion system 10 are housed in a single housing. However, this is not a necessary structure of the power conversion system 10. Alternatively, these constituent elements of the power conversion system 10 may be distributed in a plurality of different housings. Still alternatively, at least some functions of the power conversion system 10 (e.g., functions of the control circuit 6) may also be implemented as a server system or a cloud computing system.

[0139] (4.1) First variant

[0140] In the first embodiment described above, the third circuit 3 is implemented as a center-tap type converter circuit. Fig. 9A and Fig. 9B As shown, the third circuit 3 may include a primary side circuit 31A or a primary side circuit 31B instead of the primary side circuit 31. Fig.10 As shown, the third circuit 3 may include a secondary side circuit 32A instead of the secondary side circuit 32. That is, the third circuit 3 may include one of the primary side circuits 31, 31A, 31B and one of the secondary side circuits 32, 32A. In other words, the third circuit 3 may be a combination of one of the primary side circuits 31, 31A, 31B and one of the secondary side circuits 32, 32A. Fig. 9A , Fig. 9B and Fig.10 A power conversion system 10 according to a first modification is described. Note that the power conversion system 10 according to the first modification has the same structure as the power conversion system 10 according to the first embodiment except for the third circuit 3. Therefore, any constituent elements of the first modification having the same functions as their counterparts in the above-described first embodiment will be denoted by the same reference numerals as the counterparts, and descriptions thereof will be omitted herein.

[0141] The power conversion system 10 according to the first modification includes a first circuit 1, a second circuit 2, and a third circuit 3. In addition, the power conversion system 10 also includes a filter circuit 4, a buffer circuit 5, a control circuit 6, and a connection unit 7. In addition, the power conversion system 10 also includes two first DC terminals T11, T12, two second DC terminals T21, T22, and three AC terminals T31, T32, T33.

[0142] like Fig. 9A As shown, the primary side circuit 31A of the third circuit 3 includes four third switching elements Q35-Q38 and a winding L35.

[0143] Each of the third switching elements Q35-Q38 may be, for example, a depletion-type n-channel MOSFET. The third switching element Q35 having a higher potential is electrically connected in series with the third switching element Q36 having a lower potential between both ends of the capacitor C1. The third switching element Q37 having a higher potential is electrically connected in series with the third switching element Q38 having a lower potential between both ends of the capacitor C1. That is, the series circuit of the third switching elements Q35 and Q36 and the series circuit of the third switching elements Q37 and Q38 are electrically connected in parallel between both ends of the capacitor C1.

[0144] Each of the third switching elements Q35-Q38 includes a parasitic diode having an anode electrically connected to a source of an associated one of the third switching elements Q35-Q38 and a cathode electrically connected to a drain of an associated one of the third switching elements Q35-Q38.

[0145] The drain of each of the third switching elements Q35, Q37 having a higher potential is electrically connected to the second DC terminal T21 having a higher potential. The source of each of the third switching elements Q36, Q38 having a lower potential is electrically connected to the second DC terminal T22 having a lower potential. In addition, the source of the third switching element Q35 having a higher potential is electrically connected to the drain of the third switching element Q36 having a lower potential. Similarly, the source of the third switching element Q37 having a higher potential is electrically connected to the drain of the third switching element Q38 having a lower potential.

[0146] A first terminal of the winding L35 is electrically connected to a connection node between the third switching elements Q35 and Q36. A second terminal of the winding L35 is electrically connected to a connection node between the third switching elements Q37 and Q38.

[0147] At the same time, if Fig. 9B As shown, the primary side circuit 31B of the third circuit 3 includes two third switching elements Q39 and Q40, a capacitor C31 and a winding L35.

[0148] Each of the third switching elements Q39, Q40 may be, for example, a depletion-type n-channel MOSFET. The third switching element Q39 having a higher potential is electrically connected in series with the third switching element Q40 having a lower potential between both ends of the capacitor C1. That is, the series circuit of the third switching elements Q39, Q40 is electrically connected between both ends of the capacitor C1.

[0149] Each of the third switching elements Q39, Q40 includes a parasitic diode, the anode of which is electrically connected to the source of the associated one of the third switching elements Q39, Q40, and the cathode of which is electrically connected to the drain of the associated one of the third switching elements Q39, Q40.

[0150] The drain of the third switching element Q39 having a higher potential is electrically connected to the second DC terminal T21 having a higher potential. The source of the third switching element Q40 having a lower potential is electrically connected to the second DC terminal T22 having a lower potential. In addition, the source of the third switching element Q39 having a higher potential is electrically connected to the drain of the third switching element Q40 having a lower potential.

[0151] A first terminal of the winding L35 is electrically connected to a connection node between the third switching elements Q39, Q40. A second terminal of the winding L35 is electrically connected to a second DC terminal T22 having a lower potential via a capacitor C31.

[0152] like Fig.10 As shown, the secondary side circuit 32A of the third circuit 3 includes four third switching elements Q41 - Q44 and a winding L36 .

[0153] Each of the third switch elements Q41-Q44 may be, for example, a depletion-type n-channel MOSFET. The third switch element Q41 having a higher potential is electrically connected in series with the third switch element Q42 having a lower potential between the terminals P1 and N1. The third switch element Q43 having a higher potential is electrically connected in series with the third switch element Q44 having a lower potential between the terminals P1 and N1. That is, the series circuit of the third switch elements Q41 and Q42 and the series circuit of the third switch elements Q43 and Q44 are electrically connected in parallel between the terminals P1 and N1.

[0154] Each of the third switching elements Q41-Q44 includes a parasitic diode having an anode electrically connected to a source of an associated one of the third switching elements Q41-Q44 and a cathode electrically connected to a drain of an associated one of the third switching elements Q41-Q44.

[0155] The drain of each of the third switching elements Q41, Q43 having a higher potential is electrically connected to the terminal P1 having a higher potential. The source of each of the third switching elements Q42, Q44 having a lower potential is electrically connected to the terminal N1 having a lower potential. In addition, the source of the third switching element Q41 having a higher potential is electrically connected to the drain of the third switching element Q42 having a lower potential. Similarly, the source of the third switching element Q43 having a higher potential is electrically connected to the drain of the third switching element Q44 having a lower potential.

[0156] A first terminal of the winding L36 is electrically connected to a connection node between the third switching elements Q41 and Q42. A second terminal of the winding L36 is electrically connected to a connection node between the third switching elements Q43 and Q44.

[0157] Even when these primary side circuits 31A, 31B and secondary side circuit 32A are used, a DC voltage corresponding to the flat range W12 can be generated between the terminals P1, N1. Therefore, even in this modification, the first circuit 1 and the second circuit 2 can be electrically connected on the DC side without using a smoothing capacitor.

[0158] (4.2) Second variant

[0159] The power conversion system 10 may include any one of the snubber circuits 5A-5D instead of the snubber circuit 5. Figures 11A-11DA power conversion system 10 according to a second modification is described. Note that the power conversion system 10 according to the second modification has the same structure as the power conversion system 10 according to the first embodiment, except for the snubber circuits 5A-5D. Therefore, any constituent elements of the second modification having the same functions as the counterparts of the above-described first embodiment will be denoted by the same reference numerals as the counterparts, and descriptions thereof will be omitted herein.

[0160] The power conversion system 10 according to the second modification includes a first circuit 1, a second circuit 2, and a third circuit 3. In addition, the power conversion system 10 further includes a filter circuit 4, any one of the buffer circuits 5A-5D, a control circuit 6, and a connection unit 7. Furthermore, the power conversion system 10 further includes two first DC terminals T11, T12, two second DC terminals T21, T22, and three AC terminals T31, T32, T33.

[0161] like Fig.11A As shown, the buffer circuit 5A includes a diode D1, a resistor R1 and a capacitor C51. The diode D1 is electrically connected in series with the capacitor C51 between the terminals P1 and N1. The anode of the diode D1 is electrically connected to the terminal P1, and the cathode thereof is electrically connected to the terminal N1 via the capacitor C51. The resistor R1 is electrically connected between the anode and cathode of the diode D1. In the buffer circuit 5A, the electric energy stored in the capacitor C51 is consumed by the resistor R1.

[0162] like Fig. 11B As shown, the buffer circuit 5B includes a diode D1, a resistor R1, a capacitor C51 and a switching element Q51. The diode D1 is electrically connected in series with the capacitor C51 between the terminals P1 and N1. The anode of the diode D1 is electrically connected to the terminal P1, and the cathode thereof is electrically connected to the terminal N1 via the capacitor C51. The first terminal of the resistor R1 is electrically connected to the connection node between the diode D1 and the capacitor C51, and the second terminal thereof is electrically connected to the terminal N1 via the switching element Q51. In the buffer circuit 5B, when the switching element Q51 is turned on, the electric energy stored in the capacitor C51 is consumed by the resistor R1.

[0163] like Fig. 11C As shown, the buffer circuit 5C includes a plurality of (for example, Fig. 11C In the example shown, two) diodes D1, D2, an inductor L51, a plurality of (for example, Fig. 11C In the example shown, two) capacitors C51, C52, and a plurality of (eg, Fig. 11CIn the example shown, there are two) switching elements Q51 and Q52. The diode D1 is electrically connected in series with the capacitor C51 between the terminals P1 and N1. The diode D2 is electrically connected in series with the capacitor C52 between the terminals P1 and N1. The anode of the diode D1 is electrically connected to the terminal P1, and its cathode is electrically connected to the terminal N1 via the capacitor C51. The anode of the diode D2 is electrically connected to the terminal N1 via the capacitor C52, and its cathode is electrically connected to the terminal P1. That is, the diodes D1 and D2 are connected in mutually opposite directions between the terminals P1 and N1. The first terminal of the inductor L51 is electrically connected to the connection node between the diode D1 and the capacitor C51 via the switching element Q51, and the second terminal thereof is electrically connected to the connection node between the diode D2 and the capacitor C52. The switching element Q52 is electrically connected between the terminal N1 and the connection node between the switching element Q51 and the inductor L51. In this buffer circuit 5C, a step-down chopper circuit is formed by the switching elements Q51, Q52 and the inductor L51. In this snubber circuit 5C, the voltage between both ends of the capacitor C1 is lowered by turning on and off the switching elements Q51, Q52, and electric energy corresponding to the lowered voltage between both ends of the capacitor C51 is stored in the capacitor C52.

[0164] like Fig.11D As shown, the buffer circuit 5D includes a plurality of (eg, Fig.11D In the example shown, two) diodes D1, D2, a resistor R1, a plurality of (e.g., Fig.11D In the example shown, there are two) capacitors C51, C52 and a switching element Q51. A diode D1 is electrically connected in series with the capacitor C51 between the terminals P1 and N1. A diode D2 is electrically connected in series with the capacitor C52 between the terminals P1 and N1. The anode of the diode D1 is electrically connected to the terminal P1, and its cathode is electrically connected to the terminal N1 via the capacitor C51. The anode of the diode D2 is electrically connected to the terminal N1 via the capacitor C52, and its cathode is electrically connected to the terminal P1. That is, the diodes D1 and D2 are connected in opposite directions between the terminals P1 and N1. The first terminal of the resistor R1 is electrically connected to the connection node between the diode D1 and the capacitor C51, and the second terminal thereof is electrically connected to the connection node between the diode D2 and the capacitor C52 via the switching element Q51. In this buffer circuit 5D, when the switching element Q51 is turned on, the electric energy stored in the capacitor C51 is stored in the capacitor C52 via the resistor R1.

[0165] Even in the buffer circuits 5A to 5D, when the bus voltage Vbus between the terminals P1 and N1 exceeds the first clamp value Vclp1, a portion of the electric energy exceeding the first clamp value Vclp1 is absorbed by the terminals P1 and N1, thereby clamping the upper limit value of the bus voltage Vbus at the first clamp value Vclp1. In addition, in the buffer circuits 5C and 5D, if the bus voltage Vbus becomes lower than the second clamp value Vclp2 (<Vclp1), electric energy is injected (regenerated) into the terminals P1 and N1, thereby clamping the lower limit value of the bus voltage Vbus at the second clamp value Vclp2.

[0166] Therefore, providing power conversion system 10 with any of snubber circuits 5A- 5D (rather than snubber circuit 5 ) may reduce the possibility of generating ringing or surge voltage in power conversion system 10 .

[0167] (4.3) Third variant

[0168] Other modifications of the first embodiment will be listed one by one.

[0169] The first embodiment mainly describes the operation in the inverter mode. However, almost the same description also applies to the operation in the converter mode.

[0170] In addition, in the above-mentioned first embodiment, the power conversion system 10 has two operation modes, that is, the inverter mode and the converter mode. However, this is not an essential feature of the power conversion system 10. Alternatively, the power conversion system 10 may have only the inverter mode as its operation mode, or only the converter mode as its operation mode. In other words, the power conversion system 10 does not have to be configured to convert power bidirectionally, but may also be configured to convert power only unidirectionally.

[0171] Alternatively, an external diode (rather than a parasitic diode) may be connected to each of the first switching elements Q11-Q16, the second switching elements Q21, Q22, and the third switching elements Q31-Q34. In addition, each of the first switching elements Q11-Q16, the second switching elements Q21, Q22, and the third switching elements Q31-Q34 does not have to be a MOSFET, but may be, for example, an npn-type insulated gate bipolar transistor. In this case, the diode is electrically connected between the emitter and the collector of the bipolar transistor in such a direction that a current is allowed to flow in a direction opposite to the current flowing through the switching element in the on state.

[0172] Furthermore, the control circuit 6 is not necessarily a microcomputer, and may be implemented as, for example, a central processing unit (CPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or any other appropriate type of circuit.

[0173] Alternatively, the first time length (ie, the length of period T4 from the start of the first period T1 to the start of the inversion period Td1) may be equal to the second time length (ie, the length of period T3 from the end of the inversion period Td1 to the end of the first period T1).

[0174] Optionally, the buffer circuits 5, 5A, 5B, 5C, 5D may be omitted. In addition, in the first embodiment, the buffer circuit 5 is connected between the terminals P1, N1 and the first circuit 1. Alternatively, the buffer circuits 5, 5A, 5B, 5C, 5D may also be connected, for example, between the second circuit 2 and the terminals P1, N1 or between the third circuit 3 and the terminals P1, N1.

[0175] In addition, in the above-mentioned first embodiment, the second circuit 2 is a synchronous rectification boost chopper circuit. Alternatively, the second circuit 2 may also be an asynchronous rectification boost chopper circuit. Still alternatively, the second circuit 2 may also be an isolation boost chopper circuit.

[0176] Optionally, the connection unit 7 may include a smoothing capacitor.

[0177] Furthermore, the AC power source or the AC load electrically connected to the first external terminal of the first circuit 1 may have a single phase. In this case, the first circuit 1 is implemented as four first switching elements bridged together.

[0178] (Second embodiment)

[0179] In the power conversion system 10 according to the first embodiment, the single third circuit 3 is connected to the single first circuit 1 and the single second circuit 2. Alternatively, as Fig.12 and Fig.13 As shown, a single third circuit 3 can be connected to two first circuits 1A, 1B and two second circuits 2A, 2B. Fig.12 and Fig.13 A power conversion system 10A according to a second embodiment is described. Note that each of the first circuit 1A, 1B, the second circuit 2A, 2B, and the third circuit 3 of the power conversion system 10A according to the second embodiment is the same as a corresponding one of the first circuit 1, the second circuit 2, and the third circuit 3 of the power conversion system 10 according to the first embodiment described above. Therefore, in the following description, any constituent element of the second embodiment having the same function as the counterpart of the first embodiment described above will be denoted by the same reference numeral as the counterpart, and its description will be omitted herein. In addition, in Fig.12 and Fig.13 In the figure, for the sake of simplicity, the buffer circuit 5 and the control circuit 6 are omitted.

[0180] like Fig.12 and Fig.13As shown, the power conversion system 10A according to the second embodiment includes a plurality of (for example, two in this embodiment) first circuits 1A, 1B, a plurality of (for example, two in this embodiment) second circuits 2A, 2B, and a single third circuit 3. In addition, the power conversion system 10A further includes a plurality of (for example, two in this embodiment) filter circuits 4A, 4B, a plurality of buffer circuits 5, a control circuit 6, and a connection unit 7. The plurality of first circuits 1A, 1B, the plurality of second circuits 2A, 2B, the plurality of filter circuits 4A, 4B, and the plurality of buffer circuits 5 correspond one to one.

[0181] One end of each of the plurality of second circuits 2 is electrically connected to the first device 71 or the second device 72. Each of the first device 71 and the second device 72 may be any one of a solar cell, a battery, or a fuel cell. Alternatively, each of the first device 71 and the second device 72 may also be implemented as, for example, a converter circuit that may be used as a DC power supply. Still alternatively, each of the first device 71 and the second device 72 may also be, for example, a circuit that receives a DC voltage as an input voltage, a load device, or a motor.

[0182] The other end of each of the plurality of second circuits 2 is electrically connected to an associated one of the plurality of first circuits 1 via a connection unit 7. That is, in the power conversion system 10A according to the second embodiment, the plurality of second circuits 2 and the plurality of first circuits 1 are electrically connected to the same connection unit 7. The other end of each of the plurality of first circuits 1 opposite to the second circuit 2 is electrically connected to the plurality of filter circuits 4. Each of the plurality of filter circuits 4 is electrically connected to the third device 91 or the fourth device 92. For example, each of the third device 91 and the fourth device 92 may be an AC power grid. Alternatively, each of the third device 91 and the fourth device 92 may also be, for example, a circuit, a load device, or a motor that receives an AC voltage as an input voltage.

[0183] One end of the third circuit 3 is electrically connected to a DC power supply 81. The DC power supply 81 may be any one of a solar cell, a storage battery, or a fuel cell. Alternatively, the DC power supply 81 may also be implemented as, for example, a converter circuit that can be used as a DC power supply. The other end of the third circuit 3 is electrically connected to a connection unit 7. That is, in the power conversion system 10A according to the second embodiment, a plurality of first circuits 1, a plurality of second circuits 2, and a single third circuit 3 are electrically connected to the same connection unit 7.

[0184] In the power conversion system 10A according to the second embodiment, two first circuits 1A, 1B, two second circuits 2A, 2B and a single third circuit 3 are electrically connected to the same connection unit 7. The third circuit 3 allows the connection unit 7 (terminals P1, N1) to generate a DC voltage corresponding to the flat range W12 of the output voltage VT. This allows a plurality of first circuits 1A, 1B and a plurality of second circuits 2A, 2B to be electrically connected on the DC side without using a smoothing capacitor.

[0185] In the second embodiment, the number of the first circuits 1A, 1B provided and the number of the second circuits 2A, 2B provided are both two. However, this is merely an example of the present disclosure and should not be construed as limiting. Alternatively, the number of the first circuits provided and the number of the second circuits provided may be three or more, respectively.

[0186] (Summary)

[0187] As can be seen from the foregoing description, the power conversion system (10; 10A) according to the first aspect includes a first circuit (1) and a second circuit (2), and transmits DC power between a first internal terminal (111, 112) of the first circuit (1) and a second internal terminal (211, 212) of the second circuit (2). The first circuit (1) includes a first internal terminal (111, 112) and a first external terminal (113-115), and the first external terminal (113-115) is electrically connected to an AC power source or an AC load. The second circuit (2) includes at least a second internal terminal (211, 212). The power conversion system (10; 10A) also includes a third circuit (3). The third circuit (3) includes a third internal terminal (341, 342) and a third external terminal (343, 344). In a power conversion system (10; 10A), first internal terminals (111, 112), second internal terminals (211, 212) and third internal terminals (341, 342) are electrically connected to the same connection unit (7). A third circuit (3) includes a switching element (Q31-Q34) and a transformer (33) electrically connected to the switching element (Q31-Q34). The third circuit (3) provides an output voltage (VT) between both ends of a secondary winding (332) of the transformer (33) via the switching element (Q31-Q34) and the transformer (33). The secondary winding (332) is electrically connected to the third internal terminals (341, 342). The output voltage (VT) has a waveform (W1) including a rising range (W11), a falling range (W13) and a flat range (W12). In the rising range (W11), the output voltage (VT) changes from a first potential (VT1) to a second potential (VT2) higher than the first potential (VT1). In the falling range (W13), the output voltage (VT) changes from the second potential (VT2) to the first potential (VT1). In the flat range (W12), the output voltage (VT) remains at the first potential (VT1) or the second potential (VT2).

[0188] This aspect allows a DC voltage corresponding to a flat range (W12) of an output voltage (VT) generated between both ends of a secondary winding (332) of a transformer (33) of a third circuit (3) to be generated in a connection unit (7). Thus, a plurality of circuits (i.e., a first circuit 1 and a second circuit 2) can be connected on the DC side without using a smoothing capacitor.

[0189] In the power conversion system (10; 10A) according to the second aspect which can be implemented in combination with the first aspect, the connection unit (7) does not include a smoothing capacitor.

[0190] This aspect allows the overall size of the power conversion system (10; 10A) to be reduced compared to a case where the connection unit (7) includes a smoothing capacitor.

[0191] A power conversion system (10; 10A) according to a third aspect which can be implemented in combination with the first or second aspect further includes a snubber circuit (5; 5A; 5B; 5C; 5D) electrically connected to the connection unit (7).

[0192] This aspect can reduce ringing or surge voltage generated in the power conversion system (10; 10A).

[0193] In a power conversion system (10; 10A) according to a fourth aspect that can be implemented in combination with any one of the first to third aspects, a first circuit (1) includes a first switching element (Q11-Q16) different from a third switching element (Q31-Q34) used as a switching element. A second circuit (2) includes a second switching element (Q21, Q22) different from the first switching element (Q11-Q16) and the third switching element (Q31-Q34). The first circuit (1) is configured to provide a first output current (I1) having a rectangular waveform to a first internal terminal (111) by controlling the on / off state of the first switching element (Q11-Q16). The second circuit (2) is configured to provide a second output current (I2) having a rectangular waveform to a second internal terminal (211) by controlling the on / off state of the second switching element (Q21, Q22).

[0194] This aspect can reduce the residual current caused by the leakage inductance of the transformer (33).

[0195] In a power conversion system (10; 10A) according to a fifth aspect that can be implemented in combination with the fourth aspect, a first drive signal (Sig5-Sig10), a second drive signal (Sig11, Sig12) and a third drive signal (Sig1-Sig4) are synchronized with each other. The first drive signal (Sig5-Sig10) is a signal for turning on or off the first switching element (Q11-Q16). The second drive signal (Sig11, Sig12) is a signal for turning on or off the second switching element (Q21, Q22). The third drive signal (Sig1-Sig4) is a signal for turning on or off the third switching element (Q31-Q34).

[0196] This aspect allows the third switching elements Q31-Q34 to perform zero current switching (soft switching) which is always stable regardless of the load current.

[0197] In an electric power conversion system (10; 10A) according to the sixth aspect which can be implemented in combination with the fifth aspect, the turn-on moment of the first switching element (Q11-Q16) or the turn-off moment of the first switching element (Q11-Q16) is synchronized with the turn-on moment of the second switching element (Q21, Q22) or the turn-off moment of the second switching element (Q21, Q22).

[0198] This aspect can reduce the ringing voltage generated by the leakage inductance of the transformer (33), thereby reducing power loss.

[0199] In a power conversion system (10; 10A) according to the seventh aspect which can be implemented in combination with any one of the fourth to sixth aspects, each of the first circuit (1) and the second circuit (2) is configured not to transmit power to the third circuit (3) during a first time period (T1; T1a; T1b) including a reversal period (Td1), wherein the polarity of the voltage applied to the primary winding (331) of the transformer (33) is reversed during the reversal period (Td1).

[0200] This aspect allows the third circuit (3) to perform zero current switching (which is always stable and independent of the load current), thereby reducing switching losses.

[0201] In the power conversion system (10; 10A) according to the eighth aspect which can be implemented in combination with the seventh aspect, the first time length is equal to or greater than the second time length. The first time length defines the length of a period from the start of the first period (T1) to the start of the inversion period (Td1). The second time length defines the length of a period from the end of the inversion period (Td1) to the end of the first period (T1).

[0202] This aspect can increase the first time length, thereby reducing the possibility of residual current (tail current) falling on the reversal period (Td1), thereby reducing the possibility of the transformer (33) having bias magnetism.

[0203] The power conversion system (10; 10A) according to the ninth aspect which can be implemented in combination with any one of the fourth to eighth aspects further includes a control circuit (6). The control circuit (6) turns off the third switching element (Q31-Q34) when a predetermined period of time has passed since at least one of the first switching element (Q11-Q16) or the second switching element (Q21, Q22) has been turned off, upon detecting any abnormality in one of the first circuit (2) or the second circuit (2).

[0204] This aspect allows the stress on the third switching element (Q31-Q34) to be reduced by regenerative energy, compared to the case where the third switching element (Q31-Q34) is turned off at the turn-off timing of the first switching element (Q11-Q16) and the second switching element (Q21, Q22).

[0205] A power conversion system (10A) according to a tenth aspect that can be implemented in combination with any one of the first to ninth aspects includes: a plurality of first circuits (1A, 1B); and a plurality of second circuits (2A, 2B). A first internal terminal (111, 112) of each of the plurality of first circuits (1A, 1B), a second internal terminal (211, 212) of each of the plurality of second circuits (2A, 2B), and a third internal terminal (341, 342) of the third circuit (3) are electrically connected to a connection unit (7).

[0206] This aspect allows a plurality of first circuits (1A, 1B) and a plurality of second circuits (2A, 2B) to be electrically connected on the DC side without using a smoothing capacitor.

[0207] The virtual DC voltage generator circuit (3) according to the eleventh aspect is used as the third circuit (3) in the power conversion system (10; 10A) according to any one of the first to tenth aspects.

[0208] This aspect allows a DC voltage corresponding to a flat range (W12) of an output voltage (VT) generated between both ends of a secondary winding (332) of a transformer (33) of a virtual DC voltage generator circuit (3) to be generated in a connection unit (7). Therefore, a plurality of circuits (i.e., a first circuit 1 and a second circuit 2) can be connected on the DC side without using a smoothing capacitor.

[0209] Note that the constituent elements according to the second to tenth aspects are not essential constituent elements of the power conversion system (10; 10A) but may be appropriately omitted.

[0210] Reference numerals list

[0211] 1 First Circuit

[0212] 111, 112 First internal terminal

[0213] 113-115 First external terminal

[0214] Q11-Q16 First switching element

[0215] 2 Second Circuit

[0216] 211, 212 Second internal terminal

[0217] 213, 214 Second external terminal

[0218] Q21, Q22 Second switch element

[0219] 3 Third circuit (DC voltage generator circuit)

[0220] 33 Transformer

[0221] 341, 342 Third internal terminal

[0222] 343, 344 Third external terminal

[0223] Q31-Q34 Third switch element (switching element)

[0224] 5.5A, 5B, 5C, 5D Buffer Circuit

[0225] 6 Control Circuit

[0226] 7 Connection unit

[0227] 10. 10A power conversion system

[0228] I1 First output current

[0229] I2 Second output current

[0230] T1 First period

[0231] Td1 Reversal period

[0232] VT Output voltage

[0233] VT1 first potential

[0234] VT2 Second potential

[0235] W1 Output voltage waveform

[0236] W11 Rising Range

[0237] W12 Flat Range

[0238] W13 descent range.

Claims

1. A power conversion system, comprising: A first circuit includes a first internal terminal and a first external terminal, and the first external terminal is electrically connected to an AC power source or an AC load; as well as a second circuit including at least a second internal terminal, The power conversion system is configured to transfer power between the first internal terminal of the first circuit and the second internal terminal of the second circuit, The power conversion system further includes a third circuit including a third internal terminal and two third external terminals. The first internal terminal, the second internal terminal and the third internal terminal are electrically connected to the same connection unit, The third circuit includes a switching element and a transformer electrically connected to the switching element, the third circuit being configured to provide an output voltage between both ends of a secondary winding of the transformer via the switching element and the transformer, The secondary winding is electrically connected to the third internal terminal, at least one element including a primary-side switching element as the switching element is electrically connected in series between at least one of the two third external terminals and at least one of the two ends of the primary winding of the transformer, and the at least one element is an element other than a coil and a capacitor, at least one element including a secondary-side switching element as the switching element is electrically connected in series between the same connection unit and at least one of the two ends of the secondary winding of the transformer, and the at least one element is an element other than a coil and a capacitor, The waveform of the output voltage includes: a rising range, wherein the output voltage changes from a first potential to a second potential higher than the first potential; a falling range, wherein the output voltage changes from the second potential to the first potential; and A flat range, wherein the output voltage is maintained at the first potential or the second potential.

2. The power conversion system according to claim 1, wherein The connection unit does not include a smoothing capacitor. 3 . The power conversion system according to claim 1 , further comprising a snubber circuit electrically connected to the connection unit.

4. The power conversion system according to claim 1 or 2, wherein The first circuit includes a first switching element that is different from a third switching element used as the switching element, The second circuit includes a second switching element, the second switching element is different from the first switching element and the third switching element, The first circuit is configured to supply a first output current having a rectangular waveform to the first internal terminal by controlling an on / off state of the first switching element, and The second circuit is configured to supply a second output current having a rectangular waveform to the second internal terminal by controlling an on / off state of the second switching element.

5. The power conversion system according to claim 4, wherein A first drive signal for turning on or off the first switching element, a second drive signal for turning on or off the second switching element, and a third drive signal for turning on or off the third switching element are synchronized with each other.

6. The power conversion system according to claim 5, wherein The time when the first switching element is turned on or the time when the first switching element is turned off is synchronized with the time when the second switching element is turned on or the time when the second switching element is turned off.

7. The power conversion system according to claim 4, wherein Each of the first circuit and the second circuit is configured not to transmit power to the third circuit during a first period including an inversion period in which a polarity of a voltage applied to a primary winding of the transformer is reversed.

8. The power conversion system according to claim 7, wherein The first time length is equal to or greater than a second time length, the first time length defining the length of a period from the start of the first period to the start of the inversion period, and the second time length defining the length of a period from the end of the inversion period to the end of the first period.

9. The power conversion system according to claim 4 further includes a control circuit, which is configured to: when any abnormality in one of the first circuit or the second circuit is detected, turn off the third switching element when a predetermined time period has passed since at least one of the first switching element or the second switching element has been turned off.

10. The power conversion system according to claim 1 or 2, wherein The power conversion system comprises: a plurality of first circuits, one of the plurality of first circuits being the first circuit; and a plurality of second circuits, one of the plurality of second circuits being the second circuit, and A first internal terminal of each of the plurality of first circuits, a second internal terminal of each of the plurality of second circuits, and a third internal terminal of the third circuit are electrically connected to the connection unit.

11. A virtual DC voltage generator circuit, included in a power conversion system, the power conversion system comprising: A first circuit includes a first internal terminal and a first external terminal, and the first external terminal is electrically connected to an AC power source or an AC load; as well as a second circuit including at least a second internal terminal, The power conversion system is configured to transfer power between the first internal terminal of the first circuit and the second internal terminal of the second circuit, The power conversion system further includes the virtual DC voltage generator circuit, the virtual DC voltage generator circuit including a third internal terminal and two third external terminals, The first internal terminal, the second internal terminal and the third internal terminal are electrically connected to the same connection unit, The virtual DC voltage generator circuit includes a switching element and a transformer electrically connected to the switching element, the virtual DC voltage generator circuit being configured to provide an output voltage between both ends of a secondary winding of the transformer via the switching element and the transformer, The secondary winding is electrically connected to the third internal terminal, at least one element including a primary-side switching element as the switching element is electrically connected in series between at least one of the two third external terminals and at least one of the two ends of the primary winding of the transformer, and the at least one element is an element other than a coil and a capacitor, at least one element including a secondary-side switching element as the switching element is electrically connected in series between the same connection unit and at least one of the two ends of the secondary winding of the transformer, and the at least one element is an element other than a coil and a capacitor, The waveform of the output voltage includes: a rising range, wherein the output voltage changes from a first potential to a second potential higher than the first potential; a falling range, wherein the output voltage changes from the second potential to the first potential; and A flat range, wherein the output voltage is maintained at the first potential or the second potential.

12. The virtual DC voltage generator circuit according to claim 11, wherein The connection unit does not include a smoothing capacitor.

13. The virtual DC voltage generator circuit according to claim 11 or 12, wherein: The power conversion system further includes a snubber circuit electrically connected to the connection unit.

14. The virtual DC voltage generator circuit according to claim 11 or 12, wherein The first circuit includes a first switching element that is different from a third switching element used as the switching element, The second circuit includes a second switching element, the second switching element is different from the first switching element and the third switching element, The first circuit is configured to supply a first output current having a rectangular waveform to the first internal terminal by controlling an on / off state of the first switching element, and The second circuit is configured to supply a second output current having a rectangular waveform to the second internal terminal by controlling an on / off state of the second switching element.

15. The virtual DC voltage generator circuit according to claim 14, wherein A first drive signal for turning on or off the first switching element, a second drive signal for turning on or off the second switching element, and a third drive signal for turning on or off the third switching element are synchronized with each other.

16. The virtual DC voltage generator circuit according to claim 15, wherein The time when the first switching element is turned on or the time when the first switching element is turned off is synchronized with the time when the second switching element is turned on or the time when the second switching element is turned off.

17. The virtual DC voltage generator circuit of claim 14, wherein Each of the first circuit and the second circuit is configured not to transmit power to the virtual DC voltage generator circuit during a first period including an inversion period in which a polarity of a voltage applied to a primary winding of the transformer is reversed.

18. The virtual DC voltage generator circuit of claim 17, wherein The first time length is equal to or greater than a second time length, the first time length defining the length of a period from the start of the first period to the start of the inversion period, and the second time length defining the length of a period from the end of the inversion period to the end of the first period.

19. The virtual DC voltage generator circuit according to claim 14, wherein: The power conversion system also includes a control circuit, which is configured to: when any abnormality in one of the first circuit or the second circuit is detected, turn off the third switching element when a predetermined time period has passed since at least one of the first switching element or the second switching element has been turned off.

20. The virtual DC voltage generator circuit according to claim 11 or 12, wherein The power conversion system comprises: a plurality of first circuits, one of the plurality of first circuits being the first circuit; and a plurality of second circuits, one of the plurality of second circuits being the second circuit, and A first internal terminal of each of the plurality of first circuits, a second internal terminal of each of the plurality of second circuits, and a third internal terminal of the virtual DC voltage generator circuit are electrically connected to the connection unit.

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