Analog-to-digital (A / D) converter with internal diagnostic circuitry

Abstract

An analog-to-digital (A / D) converter (200) includes a capacitor array (204) having respective first terminals (206) selectively coupled to a reference voltage or ground via a plurality of switches and having respective second terminals (208) coupled to a sample-and-hold (S / H) output (212). The A / D converter also includes a voltage comparator (230) having a first input coupled to the S / H output (212) and a second input coupled to a bias voltage. The voltage comparator is configured to output a comparison voltage in response to the bias voltage and a sampled charge at the S / H output. The A / D converter also includes a successive approximation register (240) coupled to receive the comparison voltage and configured to output an approximate digital code in response to the comparison voltage, wherein the approximate digital code is varied by controlling the equivalent capacitance of the capacitor array.

Description

Technical Field

[0001] The present disclosure generally relates to analog-to-digital (A / D) converters with internal diagnostic circuitry. Background Art

[0002] In safety / critical applications, analog input (AI) modules are used to measure parameters such as temperature, pressure, voltage levels, and air quality. The AI ​​module outputs a control signal in response to the input parameter, and this control signal is converted into a digital code via an analog-to-digital (A / D) converter. Because fault detection in the AI ​​module is desirable in safety / critical applications, it is crucial to ensure that the A / D converter's output bits toggle independently of adjacent bits. If one or more of the A / D converter's output bits fail to toggle independently of adjacent bits, the A / D converter is unsuitable for use.

[0003] Figure 1 An external test circuit 100 for testing the A / D converter 104 is shown. During normal operating mode, the analog signal generated by the AI ​​module 108 is multiplexed by a 2:1 multiplexer 112 to the A / D converter 104, which generates a digital code representing the analog signal. During test mode, a digital-to-analog (D / A) converter 116 generates a test signal in response to the digital code. Noise generated by the generator 120 can be added to the test signal at an adder 124. The test signal with the added noise is multiplexed by the multiplexer 112 to the A / D converter 104. The test signal is varied by varying the digital code, and the output of the A / D converter 104 is checked to ensure that all output bits of the A / D converter 104 toggle independently of adjacent bits.

[0004] External test circuit 100 has several disadvantages. It requires PCB area and increases failure modes in safety / critical systems. Furthermore, because AI modules for safety / critical applications are typically designed with isolated input channels to improve reliability, multiple instances of the external test circuit are required for the isolated input channels. Summary of the Invention

[0005] Various aspects of the present invention relate to an analog-to-digital (A / D) converter with internal diagnostic circuitry. In one aspect, the A / D converter includes a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of first switches, and having respective second terminals coupled to a sample-and-hold (S / H) output, wherein the S / H output is selectively coupled to a bias voltage via a second switch. The A / D converter also includes a voltage comparator having a first input coupled to the S / H output and a second input coupled to the bias voltage. The voltage comparator is configured to output a comparison voltage in response to the bias voltage and a sampled charge at the S / H output. The A / D converter also includes a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code in response to the comparison voltage. The approximate digital code is varied by controlling the equivalent capacitance of the capacitor array.

[0006] In an additional aspect of the present disclosure, the capacitor array includes a plurality of switched binary-weighted capacitors. The sampled charge at the S / H output is controlled by varying the number of switched binary-weighted capacitors.

[0007] In additional aspects of the present disclosure, the equivalent capacitance is increased by increasing the number of switched binary-weighted capacitors interconnected in parallel, and the equivalent capacitance of the capacitor array is decreased by decreasing the number of switched binary-weighted capacitors interconnected in parallel.

[0008] In an additional aspect of the present disclosure, the S / H output is coupled to the bias voltage via the second switch during a sampling phase and is decoupled from the bias voltage during a holding phase.

[0009] In additional aspects of the present disclosure, during the sampling phase, both the first input and the second input of the voltage comparator are coupled to the bias voltage, and during the holding phase, the second input of the voltage comparator is coupled to the bias voltage and the first input of the voltage comparator is not coupled to the bias voltage.

[0010] In an additional aspect of the present disclosure, during the hold phase, the first input of the voltage comparator is coupled to the S / H output and the second input of the voltage comparator is coupled to the bias voltage.

[0011] In an additional aspect of the present disclosure, a fault bit is diagnosed if at least one bit of the approximate digital code fails to switch when the ratio is changed.

[0012] In an additional aspect of the present disclosure, an A / D converter with internal diagnostic circuitry includes a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of first switches and having respective second terminals coupled to a sample-and-hold (S / H) output, wherein the S / H output is selectively coupled to a bias voltage via a second switch during a sample phase and decoupled from the bias voltage via the second switch during a hold phase. The A / D converter also includes a voltage comparator having a first input coupled to the S / H output and a second input coupled to the bias voltage. The voltage comparator is configured to output a comparison voltage in response to the bias voltage and a sampled charge at the S / H output. The A / D converter also includes a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code in response to the comparison voltage. During the sampling phase, both the first and second inputs of the voltage comparator are coupled to the bias voltage, and during the holding phase, the second input of the voltage comparator is coupled to the bias voltage and the first input of the voltage comparator is not coupled to the bias voltage.

[0013] In an additional aspect of the present disclosure, an A / D converter with internal diagnostic circuitry includes a capacitor array comprising a plurality of switched binary-weighted capacitors having respective first terminals selectively coupled to a reference voltage or ground via a plurality of first switches and respective second terminals coupled to a sample-and-hold (S / H) output, wherein the S / H output is selectively coupled to a bias voltage via a second switch. The A / D converter also includes a voltage comparator having a first input coupled to the S / H output and a second input coupled to the bias voltage. The voltage comparator is configured to output a comparison voltage in response to the bias voltage and a sampled charge at the S / H output. The A / D converter also includes a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code in response to the comparison voltage. During a sampling phase, the second switch couples the S / H output to the bias voltage, and during a holding phase, the second switch decouples the S / H output from the bias voltage, and during the sampling phase, both the first and second inputs of the voltage comparator are coupled to the bias voltage, and during the holding phase, the second input of the voltage comparator is coupled to the bias voltage and the first input of the voltage comparator is not coupled to the bias voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1An external test circuit for testing an A / D converter is shown.

[0015] Figure 2 is an A / D converter according to an exemplary embodiment.

[0016] Figure 3 The equivalent circuit is shown.

[0017] Figure 4 is a graph of the voltage sampled by the comparator. DETAILED DESCRIPTION

[0018] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, in which some, but not all, embodiments are shown. Indeed, the concepts may be embodied in many different forms and should not be construed as limiting herein. Rather, these descriptions are provided so that this disclosure will meet applicable requirements.

[0019] Figure 2 FIG2 is a schematic diagram of an analog-to-digital (A / D) converter 200 according to an exemplary embodiment. A / D converter 200 includes internal diagnostic circuitry 204 that provides a controlled voltage source for testing the output bits of A / D converter 200, thereby eliminating the need for external test circuitry. A / D converter 200 can be implemented in an integrated circuit (IC) and can be used in safety / critical applications where high availability is desired.

[0020] refer to Figure 2 , the A / D converter 200 includes a capacitor array 204 comprising a plurality of capacitors having respective first terminals 206 and second terminals 208. In an exemplary embodiment, the capacitor array 204 is formed from a plurality of switched binary-weighted capacitors (e.g., C, C / 2, C / 4, ...). The A / D converter 200 further includes first switches S0-SN-1 configured to selectively couple the first terminal 206 of the capacitor array 204 to a reference voltage Vref or ground. The second terminal 208 of the capacitor array 204 is coupled to a sample-and-hold (S / H) output 212. The A / D converter 206 further includes a second switch S2 configured to selectively couple the S / H output 212 to a bias voltage Vbias. During other operating modes of the A / D converter 200, the first terminal 206 of the capacitor array 204 is connected to the input voltage Vin.

[0021] Continue to refer Figure 2, the A / D converter 200 further includes a voltage comparator 230 having a first input 232 coupled to the S / H output 212 and a second input 234 coupled to the bias voltage Vbias. The voltage comparator 230 is configured to output a comparison voltage in response to the bias voltage Vbias and the sampled charge at the S / H output 212.

[0022] In an exemplary embodiment, the sampled charge at the S / H output 212 can be varied by the number of switched binary-weighted capacitors coupled to a reference voltage Vref. The first terminals 206 of some or all of the binary-weighted capacitors can be connected to the reference voltage Vref, and the first terminals 206 of some or all of the binary-weighted capacitors can be connected to ground.

[0023] Continue to refer Figure 2 , the A / D converter 200 also includes a successive approximation register (SAR) 240 having an input 242 coupled to receive a comparison voltage. The SAR 240 is configured to generate an approximate digital code at an output 244 in response to the comparison voltage. The approximate digital code is a digital representation of the S / H voltage at the S / H output 212. The approximate digital code is varied by controlling the equivalent capacitance of the capacitor array 204. In an exemplary embodiment, the SAR 240 applies a binary search algorithm to output the approximate digital code.

[0024] Continue to refer Figure 2 The equivalent capacitance of capacitor array 204 can be controlled by changing the number of binary-weighted capacitors interconnected in parallel. By increasing the number of binary-weighted capacitors interconnected in parallel, the equivalent capacitance of capacitor array 204 increases, and by decreasing the number of binary-weighted capacitors interconnected in parallel, the equivalent capacitance of capacitor array 204 decreases.

[0025] Continue to refer Figure 2 During the sampling phase, the first terminal 206 of the capacitor array 204 is selectively connected to the reference voltage Vref or ground by closing the first switch S0-SN-1. Furthermore, during the sampling phase, the second switch S2 is closed to couple the S / H output 212 to the bias voltage Vbias. Thus, during the sampling phase, both the first input 232 and the second input 234 of the voltage comparator 230 are coupled to the bias voltage Vbias. The capacitor array 204 is charged by the reference voltage Vref and has a charge equal to the capacitance multiplied by the reference voltage Vref. The resulting sampled charge is equal to (Vref) x (∑Cn), where Cn is the switched binary-weighted capacitor connected to Vref.

[0026] Next, during the hold (or conversion) phase, second switch S2 is opened to decouple S / H output 212 from bias voltage Vbias. Thus, during the hold (conversion) phase, although first input 232 of voltage comparator 230 is decoupled from bias voltage Vbias, first input 234 of voltage comparator 230 remains coupled to S / H output 212, and second input 234 of voltage comparator 230 remains coupled to bias voltage Vbias. Voltage comparator 230 outputs a comparison voltage in response to bias voltage Vbias and the sampled charge at S / H output 212. The comparison voltage is applied to input 242 of SAR 240. SAR 240 applies a binary search algorithm to the comparison voltage and outputs an approximate digital code, which is a digital representation of the S / H voltage. SAR 240 can be implemented in hardware or software.

[0027] Figure 3 A simplified equivalent circuit 300 is shown during the hold (or conversion) phase. The first input 232 of the voltage comparator 230 is decoupled from the bias voltage Vbias. However, the first input 232 of the voltage comparator 230 remains coupled to the S / H output 212, and the second input 234 remains coupled to the bias voltage Vbias. A capacitor array 304, comprising a plurality of switched binary-weighted capacitors, is coupled to a reference voltage Vref. The sampled charge at the S / H output 212 is controlled by varying the number of switched binary-weighted capacitors in the capacitor array. A selected number of capacitors 308 are coupled to ground. Although the reference voltage Vref, available internally within the integrated circuit, has a constant voltage level, the sampled charge at the S / H output 212 is scaled by varying the equivalent capacitance of the capacitor array.

[0028] Figure 4 The voltage sampled by comparator 230 is shown. Using a user-specified code, the sampled charge at S / H output 212 is changed to a maximum value of (Vref) x (∑Cn). The sampled charge at S / H output 212 is changed to test the approximate digital code generated by SAR 240. When the sampled charge at S / H output 212 is changed using the user-specified code, if at least one bit of the approximate digital code fails to toggle independently of adjacent bits, A / D converter 200 is determined to have at least one faulty bit, which may make A / D converter 200 unsuitable for safety / critical applications requiring high availability.

[0029] Various illustrative components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. The described functionality may be implemented in different ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0030] For the sake of simplicity and clarity, the complete structure and operation of all systems suitable for use with the present disclosure are not depicted or described herein. Instead, only the most part of the system that is unique to the present disclosure or necessary to understand the present disclosure is depicted and described.

Claims

1. An analog-to-digital converter (A / D converter) having internal diagnostic circuitry, comprising: a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of first switches and having respective second terminals coupled to a sample-and-hold output, i.e., an S / H output, wherein the S / H output is selectively coupled to a bias voltage via a second switch; a voltage comparator having a first input coupled to the S / H output and having a second input coupled to the bias voltage, the voltage comparator configured to output a comparison voltage in response to the bias voltage and a sampled charge at the S / H output; as well as a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code in response to the comparison voltage, wherein the sampled charge at the S / H output is varied to test the approximate digital code generated by the successive approximation register using a specified code, and if at least one bit of the approximate digital code fails to toggle independently of adjacent bits, a faulty bit is diagnosed.

2. The A / D converter of claim 1, wherein the capacitor array comprises a plurality of switched binary-weighted capacitors.

3. The A / D converter of claim 2, wherein the sampled charge at the S / H output is controlled by varying the number of switched binary-weighted capacitors connected to the reference voltage.

4. The A / D converter of claim 3 , wherein the equivalent capacitance of the capacitor array is increased by increasing the number of switched binary-weighted capacitors interconnected in parallel, and wherein the equivalent capacitance of the capacitor array is decreased by decreasing the number of switched binary-weighted capacitors interconnected in parallel.

5. The A / D converter of claim 1, wherein the approximate digital code is a digital representation of the S / H voltage. 6 . The A / D converter of claim 1 , wherein the S / H output is coupled to the bias voltage via the second switch during a sampling phase and is decoupled from the bias voltage during a holding phase.

7. The A / D converter of claim 1 , wherein during a sampling phase, both the first and second inputs of the voltage comparator are coupled to the bias voltage, and wherein during a hold phase, the second input of the voltage comparator is coupled to the bias voltage and the first input of the voltage comparator is not coupled to the bias voltage. 8 . The A / D converter of claim 1 , wherein during a hold phase, the first input of the voltage comparator is coupled to the S / H output and the second input of the voltage comparator is coupled to the bias voltage.

9. The A / D converter of claim 1, wherein a fault bit is diagnosed if at least one bit of the approximate digital code fails to switch when the ratio is changed.

10. The A / D converter of claim 1, wherein the reference voltage is generated within an integrated circuit.

11. An analog-to-digital converter (A / D converter) having internal diagnostic circuitry, comprising: a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of first switches and having respective second terminals coupled to a sample-and-hold output, i.e., an S / H output, wherein the S / H output is selectively coupled to a bias voltage via a second switch during a sample phase and decoupled from the bias voltage via the second switch during a hold phase; a voltage comparator having a first input coupled to the S / H output and having a second input coupled to the bias voltage, the voltage comparator configured to output a comparison voltage in response to the bias voltage and a sampled charge at the S / H output; as well as a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code in response to the comparison voltage, wherein during the sampling phase, both the first input and the second input of the voltage comparator are coupled to the bias voltage, and wherein during the holding phase, the second input of the voltage comparator is coupled to the bias voltage and the first input of the voltage comparator is not coupled to the bias voltage; and wherein the sampled charge at the S / H output is varied to test the approximate digital code generated by the successive approximation register using a specified code, and if at least one bit of the approximate digital code fails to toggle independently of adjacent bits, a faulty bit is diagnosed.

12. The A / D converter of claim 11, wherein the capacitor array comprises a plurality of switched binary-weighted capacitors.

13. The A / D converter of claim 12, wherein the sampled charge at the S / H output is controlled by varying the number of switched binary-weighted capacitors connected to the reference voltage.

14. The A / D converter of claim 11, wherein the equivalent capacitance of the capacitor array is controlled by varying the number of switched binary-weighted capacitors connected in parallel.

15. The A / D converter of claim 14, wherein the equivalent capacitance of the capacitor array is increased by increasing the number of switched binary-weighted capacitors interconnected in parallel, and wherein the equivalent capacitance of the capacitor array is decreased by decreasing the number of switched binary-weighted capacitors interconnected in parallel.

16. The A / D converter of claim 11, wherein the approximate digital code is a digital representation of the S / H voltage.

17. The A / D converter of claim 11, wherein a faulty bit is diagnosed if at least one bit of the approximate digital code fails to toggle independently of adjacent bits when the ratio is changed.

18. The A / D converter of claim 11, wherein the reference voltage is generated within an integrated circuit.

19. An analog-to-digital converter (A / D converter) having internal diagnostic circuitry, comprising: a capacitor array comprising a plurality of switched binary-weighted capacitors having respective first terminals selectively coupled to a reference voltage or ground via a plurality of first switches and having respective second terminals coupled to a sample-and-hold output, i.e., an S / H output, wherein the S / H output is selectively coupled to a bias voltage via a second switch; a voltage comparator having a first input coupled to the S / H output and having a second input coupled to the bias voltage, the voltage comparator configured to output a comparison voltage in response to the bias voltage and a sampled charge at the S / H output; as well as a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code in response to the comparison voltage, wherein during a sampling phase, the second switch couples the S / H output to the bias voltage, and during a holding phase, the second switch decouples the S / H output from the bias voltage, and wherein the sampled charge at the S / H output is varied to test the approximate digital code generated by the successive approximation register using a specified code, and if at least one bit of the approximate digital code fails to toggle independently of adjacent bits, a faulty bit is diagnosed.

20. The A / D converter of claim 19, wherein the equivalent capacitance of the capacitor array is controlled by varying the number of switched binary-weighted capacitors connected in parallel.

21. The A / D converter of claim 20, wherein the equivalent capacitance of the capacitor array is increased by increasing the number of switched binary-weighted capacitors interconnected in parallel, and wherein the equivalent capacitance of the capacitor array is decreased by decreasing the number of switched binary-weighted capacitors interconnected in parallel.

22. The A / D converter of claim 19, wherein the approximate digital code is a digital representation of the S / H voltage.

23. The A / D converter of claim 19, wherein a faulty bit is diagnosed if at least one bit of the approximate digital code fails to toggle independently of adjacent bits when the ratio is changed.

24. The A / D converter of claim 19, wherein the successive approximation register applies a binary search algorithm to output the approximate digital code.

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