A method and device for integrated circuit testing and number writing

Abstract

The present disclosure provides an integrated circuit testing and numbering method, including: through a circuit testing and numbering device: determining a target interface, completing a connection with a target circuit through the target interface; starting the target circuit through the target interface; waiting for a first preset time; reading a target current of the target circuit through the target interface; determining that the target current meets a preset condition; writing a target number to a target chip in the target circuit through the target interface; and instructing the target circuit to complete shutdown through the target interface. The present application also provides a device for executing the method. The technical solution disclosed in the present disclosure can integrate electrical parameter tests and various functional tests and operations with a common workflow, without interfering with each other, and can be completed at the same time at a test workstation using a set of test fixtures and test instruments.

Description

Technical Field

[0001] The present application relates to the field of circuits, and in particular to a method and device for integrated circuit testing and number writing. Background Art

[0002] At present, a large number of smart electronic devices are used in the fields of smart home, smart wearable, smart travel, etc., and smart electronic devices are inevitably inseparable from the support of circuit structure, such as the use of analog IC, digital IC, etc. With the development of the industrialization level of smart electronic devices, they have the characteristics of small size, low power consumption, and multiple functions. This puts forward higher requirements on the integration, power consumption, and functional complexity of the circuit structure in smart electronic devices.

[0003] In the factory inspection of intelligent electronic devices, it is essential to test the electrical parameters of the circuit structure. As the circuit complexity increases and the functions increase, a large number of functional tests and operations need to be performed on the circuit at the same time, such as RF functional testing and chip number writing operations.

[0004] In the actual factory inspection process, the electrical parameter test of intelligent electronic equipment needs to be completed at a separate test workstation using a set of test fixtures and test instruments, while the chip number writing of the circuit needs to be completed at another test workstation using another set of test fixtures and test instruments. Electrical parameter testing and various functional tests and operations are all performed at different test workstations, and the various links are not coordinated with each other, resulting in a waste of manpower, test fixtures, test instruments, and test workstations, resulting in increased production costs and reduced benefits. Summary of the invention

[0005] In order to solve the above technical problems, the present disclosure proposes a method and corresponding execution equipment that integrates electrical parameter testing and various functional tests and operations in the circuit structure factory inspection link of intelligent electronic devices into a complete method.

[0006] On the one hand, the present disclosure provides an integrated circuit testing and numbering method, including: determining a target interface through a circuit testing and numbering device, completing connection with a target circuit through the target interface; starting the target circuit through the target interface; waiting for a first preset time; reading a target current of the target circuit through the target interface; determining that the target current meets a preset condition; maintaining the current working state of the target circuit, and writing a target number to a target chip in the target circuit through the target interface; and instructing the target circuit to complete shutdown through the target interface.

[0007] In some embodiments, the integrated circuit testing and numbering method further includes: after determining that the target current meets a preset condition, immediately writing a target number to a target chip in the target circuit through the target interface.

[0008] In some embodiments, the integrated circuit testing and numbering method further includes: after determining that the target current meets the preset conditions, waiting for a second preset time; and writing the target number to the target chip in the target circuit through the target interface.

[0009] In some embodiments, the integrated circuit testing and number writing method further includes: after writing the target number to the target chip in the target circuit through the target interface, determining that the target number is written successfully; and running a number verification process.

[0010] In some embodiments, in the integrated circuit testing and numbering method, determining that the target current meets a preset condition includes: under normal working conditions, determining that the operating current of the target circuit meets a preset condition.

[0011] In some embodiments, in the integrated circuit testing and numbering method, determining that the target current meets a preset condition includes: in a standby working state, determining that the standby current of the target circuit meets a preset condition.

[0012] In some embodiments, in the integrated circuit testing and numbering method, writing the target number to the target chip in the target circuit through the target interface occurs before determining that the target current satisfies a preset condition; and the method also includes: when the target number has been written to the target circuit, if the target current does not satisfy the preset condition, the target number is recycled to form a recycled target number.

[0013] In some embodiments, in the integrated circuit testing and numbering method, starting the target circuit through the target interface includes: supplying power to the target circuit through the target interface from a target power supply of the circuit testing and numbering device that is independent of the target circuit. The target power supply includes a programmable power supply. The target circuit includes a smart lock mainboard.

[0014] In some embodiments, in the integrated circuit testing and number writing method, the target number includes at least one of an IMEI number, a MEID number, and a MAC address.

[0015] In some embodiments, in the integrated circuit testing and number writing method, the target interface includes at least one of a WIFI interface, a Zigbee interface, an RS485 interface, an RS232 interface, an RS422 interface, a USB interface, and an HDMI interface.

[0016] Another aspect of the present disclosure provides an integrated circuit testing and number writing device, including: a memory, storing at least one set of instruction sets for executing circuit testing and number writing methods; a processor, communicatively connected to the memory, and executing the circuit testing and number writing method instruction set in the memory when the processor is running.

[0017] In some embodiments, the integrated circuit testing and number writing device further includes: a test fixture, which is electrically connected to the target circuit through the target interface and communicates data with the processor through the I / O component; and a target power supply, wherein the first end of the target power supply is electrically connected to the power supply outside the integrated circuit testing and number writing device when in operation, and the second end includes a power supply interface, which is electrically connected to the test fixture when in operation, providing a power source for the integrated circuit testing and number writing device, and providing standard voltage and current signals as reference signal values ​​during the circuit testing process.

[0018] In some embodiments, the integrated circuit testing and number writing device further includes: at least one group of the target numbers is stored in the memory for calling when writing numbers; and the recycled target numbers can be stored in the memory for being called again after the target numbers are recycled.

[0019] In some embodiments, the integrated circuit testing and number writing equipment further includes an MES system running, and the instructions, target numbers, and target current test data are managed and maintained through the MES system.

[0020] The technical solution disclosed in the present invention can integrate electrical parameter tests and various functional tests and operations with common workflows, so that they can be completed at one test workstation at the same time using a set of test fixtures and test instruments without interfering with each other. The technical solution disclosed in the present invention can reduce the repeated operation of the circuit structure in the factory inspection link, reduce the operation time of the factory inspection link as a whole, and reduce manpower, the number of test fixtures, test instruments and equipment, and test workstations used, thereby reducing the labor and material costs of the factory inspection link of intelligent electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of this specification, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 is a structural schematic diagram of an integrated circuit testing and number writing device 100 provided according to some embodiments of the present disclosure;

[0023] Figure 2 is a schematic diagram of the structure of an operating machine 200 provided according to some embodiments of the present disclosure;

[0024] Figure 3 It is a flowchart of an integrated circuit testing and number writing method S100-1 provided according to some embodiments of the present disclosure;

[0025] Figure 4 is a flowchart of an integrated circuit testing and number writing method S100-2 provided according to some embodiments of the present disclosure; and

[0026] Figure 5 It is a flowchart of an integrated circuit testing and numbering method S100-3 provided according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0028] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting.

[0029] In view of the following description, these and other features of the present application, as well as the operation and function of the related elements of the structure, and the economy of the combination and manufacture of the parts can be significantly improved. With reference to the accompanying drawings, all of which form a part of this application. However, it should be clearly understood that the drawings are only for the purpose of illustration and description and are not intended to limit the scope of this application.

[0030] The following description may significantly improve these and other features of the present application, as well as the operation and function of the relevant elements of the structure, and the combination of components and the economic efficiency of manufacturing. All of these refer to the accompanying drawings to form a part of this application. However, it should be clearly understood that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present application. It should also be understood that the drawings are not drawn to scale.

[0031] The following is an explanation of the technical terms in the field involved in the technical solution of the present disclosure:

[0032] MES: Manufacturing Execution System, is a production information management system for the workshop execution layer of manufacturing enterprises.

[0033] IMEI number: International Mobile Equipment Identity (IMEI), used to identify each independent mobile terminal device in the mobile network, which is equivalent to the ID card of the mobile terminal device.

[0034] MEID number: Mobile Equipment Identifier (MEID) is the identification code of a CDMA mobile terminal. It is also the unique identification code of each CDMA mobile terminal. Through this identification code, the network can track and supervise the terminal.

[0035] MAC address: Media Access Control Address, used to uniquely identify a network card in the network. If a device has one or more network cards, each network card needs and will have a unique MAC address.

[0036] Figure 1 1 is a schematic diagram of a structure of an integrated circuit testing and number writing device 100 provided according to some embodiments of the present disclosure. The device 100 may include a test fixture 110, a target power supply 120 and an operating machine 200.

[0037] In some embodiments, the operating machine 200 can be a general-purpose computer or a special-purpose computer, which is connected to the test fixture in communication, and the test parameters are sent through the test fixture to obtain the target current value and complete the operation of writing the target number. The operating machine 200 can also be a server, a personal computer, a portable computer (such as a notebook computer, a tablet computer, etc.), or an electronic device with other computing capabilities. For example, an MES system is running in the operating machine 200, and the instructions, target numbers, and target current test data are managed and maintained by the MES system. The operating machine 200 may include one or more forms of processors 220, and different forms of memory 230. The memory 230 may store at least one set of instruction sets for executing circuit testing and number writing methods; the memory 230 may store at least one set of target numbers for calling when writing numbers; the memory 230 may also store the recycled target number for being called again after the target number is recycled. The processor 220 is connected to the memory 230 in communication, and executes the circuit testing and number writing method instruction set in the memory 230 during operation.

[0038] The operating machine 200 is connected to the target circuit 002 through the test fixture 110 and tests and writes numbers to the target circuit 002. In some embodiments, the test fixture 110 may include a target interface 111; the target circuit 001 may include a circuit interface 002. The circuit interface 002 of the target circuit 001 may serve as an access point for testing and writing numbers. The test fixture 110 may be provided with at least one target interface 111 that is connected to the circuit interface 002 according to the design requirements of the target circuit 001. The test fixture 110 may be electrically connected to the target circuit 001 through the target interface 111, and may be electrically connected to the target circuit 001 through the I / O component 260 (see Figure 2 ) realizes data communication with the operating machine 200. The target interface 111 can be one or more of a WIFI interface, a Zigbee interface, an RS485 interface, an RS232 interface, an RS422 interface, a USB interface, an HDMI interface, or other interfaces that can provide corresponding functions.

[0039] The target power supply 120 is an internal power supply of the device 100, which is electrically connected to the test fixture 110 and can provide power to the target circuit 001 through the test fixture 110. For example, the target power supply 120 can be a programmable power supply; the target power supply 120 can also be connected to the external power supply 004 at the same time. Figure 1As shown, the target power supply 120 may include a first end and may also include a second end. When working, the first end of the target power supply 120 is electrically connected to the external power supply 004 of the integrated circuit testing and number writing device 100; the second end includes a power supply interface, and the power supply interface is electrically connected to the test fixture 110 when working, providing a power source for the test fixture 110 and the target circuit 001. At the same time, a filter can also be set in the target power supply 120 to filter the interference of the low-frequency signal generated by the ground wire of the external power supply 004, so that a standard voltage and / or current signal can be provided for the test fixture 110 as a reference signal value during the circuit testing process. In some embodiments, the external power supply 004 can be an AC mains.

[0040] Figure 2 is a schematic diagram of the structure of an operating machine 200 provided according to some embodiments of the present disclosure.

[0041] For example, the operating machine 200 may include a communication port 250, which may be connected to the network 003 or come out of the network 003 to which it is connected to facilitate data communication, and the operator may remotely access to execute the operation instructions therein. The operating machine 200 may also include a processor 220 in the form of one or more processors. For the sake of illustration, only one processor 220 is described in the data processing device 200 in this application. The operating machine 200 may also include an internal communication bus 210 to which different device components may be connected, and different forms of memory 230, such as a disk 232 (non-temporary memory) and a read-only memory (ROM) 234 or a random access memory (RAM) 236, etc., for storing various data files to be processed and / or transmitted. The storage medium may be a local storage medium of the operating machine 200, or a storage medium shared by the operating machine 200 (such as a shared storage medium obtained from the network 003 using the communication port 250, such as a cloud platform). The operating machine 200 may also include program instructions stored in the ROM 234 , the RAM 246 , and / or other types of non-transitory storage media to be executed by the processor 220 .

[0042] The operator 200 may also include an I / O component 260 to support data communication with other functional components in the integrated circuit testing and number writing device 100. The operator 200 may also receive remote access and obtain data via the network 003.

[0043] The processor 220 may be in the form of one or more processors. In some embodiments, the processor 220 may include one or more hardware processors, such as a microcontroller, a microprocessor, a reduced instruction set computer (RISC), an application-specific integrated circuit (ASIC), an application-specific instruction set processor (ASIP), a central processing unit (CPU), a graphics processing unit (GPU), a physical processing unit (PPU), a microcontroller unit, a digital signal processor (DSP), a field programmable gate array (FPGA), an advanced RISC machine (ARM), a programmable logic device (PLD), any circuit or processor capable of performing one or more functions, etc., or any combination thereof. For illustration purposes only, only one processor 220 is described in the operating machine 200.

[0044] However, it is understood by those skilled in the art that the operating machine 200 in the present application may also include multiple processors. Therefore, the method / step / operation performed by one processor described in the present application may also be performed by multiple processors together or separately. For example, if in the present application, the processor of the operating machine 200 may perform step A and step B simultaneously. It should be understood that step A and step B may also be performed together by two different processors. For example, the first processor performs step A, the second processor performs step B, or the first processor and the second processor perform steps A and B together.

[0045] Figure 3 It is a flowchart of a method S100-1 for integrated circuit testing and number writing provided according to some embodiments of the present disclosure. The method S100-1 can be performed by the device 100 for integrated circuit testing and number writing. For example, some steps can be performed by the operating machine 200. Specifically, the processor 220 can be connected to the memory 230 for communication when performing circuit testing and number writing, and read the one or more groups of instructions stored in the memory 230. The one or more groups of instructions instruct the processor 220 to complete the process of the method S100-1.

[0046] The operations of the method S100-1 presented below are intended to be illustrative rather than restrictive. In some embodiments, the method S100-1 may add one or more additional operations not described, and / or delete one or more operations described herein when implemented. In addition, the execution order shown in the figure and described below is not limited to this.

[0047] S110, determining a target interface, and completing connection with a target circuit through the target interface.

[0048] For example, on an actual production line, the target circuit 001 may be connected to the target interface 111 manually, or may be connected to the target interface 111 by other machines (such as automatic equipment). The test fixture 110 is electrically connected to the target circuit 001 through the target interface 111. When the connection is completed, the processor 220 can detect that a corresponding load has appeared on the target interface 111. For example, the target interface 111 may include any one or more of a WIFI interface, a Zigbee interface, an RS485 interface, an RS232 interface, an RS422 interface, a USB interface, and an HDMI interface, or other interfaces that can provide corresponding functions. For example, the target circuit 001 may be a smart lock mainboard, or it may be a circuit structure of other smart electronic devices.

[0049] S120: Start the target circuit through the target interface.

[0050] For example, the processor 220 may control the integrated circuit testing and number writing device 100 to send instructions to the target circuit 001 through the target interface 111, thereby starting the target circuit 001. Specifically, step S120 may include steps S121, S122, and S123.

[0051] S121, starting the target power supply to supply power to the target circuit.

[0052] For example, the processor 220 may instruct, through the target interface 111 , that the target power supply 120 of the circuit testing and number writing device 100 which is independent of the target circuit 001 supplies power to the target circuit 001 .

[0053] S122, instructing the target circuit to complete system startup.

[0054] For example, the processor 220 sends a handshake instruction to the target circuit 001 through the target interface 111 to activate the target circuit 001 and wait for the target circuit 001 to complete system startup.

[0055] S123, obtaining startup self-test information of the target circuit.

[0056] For example, the processor 220 obtains the startup self-check information of the target circuit 001 through the target interface 111, including system version information, startup time information, and operation status information.

[0057] S130, waiting for a first preset time period.

[0058] For example, after the target circuit 001 is started, the processor 220 waits for a preset time. When the target circuit 001 runs stably, the processor 220 executes the subsequent process method. The first preset time can be set according to different target circuits.

[0059] S140, reading a target current of a target circuit through the target interface, and determining that the target current meets a preset condition.

[0060] Specifically, step S140 may include steps S141 and S142.

[0061] S141, under normal working conditions, determining whether the operating current of the target circuit meets a preset condition.

[0062] For example, when the target circuit 001 completes startup and is in a normal working state, the processor 220 sends an instruction to read the target circuit operating current to the target circuit 001 through the target interface 111, and then receives the feedback target circuit operating current data from the target interface 111. The processor 220 compares the target circuit operating current data with the reference signal to determine whether the preset conditions are met. If the operating current meets the preset conditions, it means that the target circuit is operating normally, and the processor 220 continues to execute process step S142. Otherwise, it means that the target circuit is not operating normally and is a substandard product, and the processor 220 shuts down the target circuit.

[0063] S142, in a standby working state, determining whether the standby current of the target circuit meets a preset condition.

[0064] For example, the processor 220 sends an instruction to the target circuit 001 through the target interface 111, instructing the target circuit 001 to enter a standby working state. When the target circuit 001 is in a standby working state, the processor 220 sends an instruction to read the standby current of the target circuit to the target circuit 001 through the target interface 111, and then receives the feedback standby current data of the target circuit from the target interface 111. The processor 220 compares the standby current data of the target circuit with the reference signal to determine whether the preset conditions are met. If the standby current meets the preset conditions, it means that the target circuit is operating normally, and the processor 220 continues to execute process step S124; otherwise, it means that the target circuit is not operating normally and is an unqualified product, and the processor 220 shuts down the target circuit.

[0065] S124, the target circuit returns to a normal working state from a standby working state.

[0066] For example, the target circuit 001 has entered the standby working state, and the processor 220 cannot write the target number to the target chip in the target circuit 001 that is already in the standby state. The processor 220 instructs the target circuit 001 to restore from the standby working state to the normal working state through the target interface 111.

[0067] S150, maintaining the current working state of the target circuit, and writing a target number to a target chip in the target circuit through the target interface.

[0068] For example, after the processor 220 determines that the target current of the target circuit 001 meets the preset conditions, it instructs the target circuit 001 to maintain the current working state. The processor 220 calls the target number stored in the memory 230, and then can immediately write the target number to the target chip in the target circuit 001 through the target interface 111. In this way, the processor 220 can reduce the instruction execution time. Or the processor 220 calls the target number stored in the memory 230, and then can also wait for the second preset time length, and then write the target number to the target chip in the target circuit 001 through the target interface 111. In this way, the processor 220 can reduce the possibility of conflict between the read instruction of the target current and the write instruction of the target number. The second preset time length can be set according to different target circuits.

[0069] S160, after writing the target number to the target chip in the target circuit through the target interface, determining that the target number is written successfully, and then running a number verification process.

[0070] For example, the processor 220 reads the target number written in the target chip through the target interface 111. The processor 220 compares the read target number that has been written with the target number called from the memory 230, and then runs the number verification process. In some embodiments, the target number can be any one or more of an IMEI number, a MEID number, a MAC address, and other public address numbers.

[0071] S180, instructing the target circuit to complete shutdown through the target interface.

[0072] For example, the processor 220 sends a release instruction to the target circuit 001 through the target interface 111, and then waits for the target circuit 001 to complete system shutdown. When the target circuit 001 system is shut down, the processor 220 instructs the target circuit 001 to complete power-off through the target interface 111.

[0073] Figure 4It is a flowchart of another integrated circuit testing and numbering method S100-2 provided according to some embodiments of the present disclosure. Figure 4 Zhongtong Figure 3 The steps with the same number have the same content. The method S100-2 can be performed by the integrated circuit testing and number writing device 100. For example, some steps can be performed by the operating machine 200. Specifically, the processor 220 can be connected to the memory 230 for communication when performing circuit testing and number writing, and read the one or more groups of instructions stored in the memory 230. The one or more groups of instructions instruct the processor 220 to complete the process of the method S100-2.

[0074] S110, determining a target interface, and completing connection with a target circuit through the target interface.

[0075] S120: Start the target circuit through the target interface.

[0076] S130, waiting for a first preset time period.

[0077] S141, under normal working conditions, determining whether the operating current of the target circuit meets a preset condition.

[0078] If the operating current meets the preset condition, it means that the target circuit 001 operates normally. The processor 220 continues to execute process step S150.

[0079] If the operating current does not meet the preset condition, it means that the target circuit 001 is not operating normally and is a substandard product. The processor 220 shuts down the target circuit 001.

[0080] S150, wait for a second preset time length, maintain the current working state of the target circuit, and write the target number to the target chip in the target circuit through the target interface. For example, the processor 220 can set a reasonable second preset waiting time length according to different target circuits 001. In this way, the processor 220 can reduce the possibility of conflict between the read instruction and the write instruction.

[0081] S142, in a standby working state, determining whether the standby current of the target circuit meets a preset condition.

[0082] If the standby current meets the preset condition, it means that the target circuit 001 operates normally. The processor 220 continues to execute the process step S160 to run the number verification process.

[0083] If the standby current does not meet the preset conditions, it is considered that the target circuit 001 is not operating normally and a product quality re-inspection is required. Since the above number is usually allocated by the relevant management department, it is necessary to occupy public resources and pay a license fee. Therefore, if the target circuit 001 is a substandard product, the target number needs to be recycled. Therefore, if the standby current does not meet the preset conditions, the processor 220 executes process step S170 to recycle the target number.

[0084] S160, after writing the target number to the target chip in the target circuit through the target interface, determining that the target number is written successfully, and then running a number verification process.

[0085] S170, when the target number has been written into the target circuit, if the target current does not meet the preset conditions, the target number is recycled to form a recycled target number. For example, the processor 220 writes the target number to the target chip in the target circuit 001 through the target interface 111 before the processor 220 determines that the target current meets the preset conditions. When the target number has been written into the target circuit 001, the processor 220 determines that the target current meets the preset conditions, and then continues to execute the process steps; otherwise, the processor 220 recycles the target number to form a recycled target number, and then closes the target circuit. The recycled target number is stored in the memory 230 and can be called again.

[0086] S180, instructing the target circuit to complete shutdown through the target interface.

[0087] Figure 5 It is a flowchart of another integrated circuit testing and numbering method S100-3 provided according to some embodiments of the present disclosure. Figure 5 Zhongtong Figure 3 as well as Figure 4 The steps with the same number have the same content. The method S100-3 can be performed by the integrated circuit testing and number writing device 100. For example, some steps can be performed by the operating machine 200. Specifically, the processor 220 can communicate with the memory 230 and read the one or more groups of instructions stored in the memory 230 when performing circuit testing and number writing. The one or more groups of instructions instruct the processor 220 to complete the process of the method S100-3.

[0088] S110, determining a target interface, and completing connection with a target circuit through the target interface.

[0089] S120: Start the target circuit through the target interface.

[0090] S130, waiting for a first preset time period.

[0091] S150, maintaining the current working state of the target circuit, and writing a target number to a target chip in the target circuit through the target interface.

[0092] S141, under normal working state, determining whether the operating current of the target circuit meets a preset condition.

[0093] If the operating current meets the preset condition, it means that the target circuit 001 operates normally. The processor 220 executes process step S142.

[0094] If the operating current does not meet the preset condition, it means that the target circuit 001 is not operating normally and is a substandard product, and a product quality re-inspection is required. The processor 220 executes process step S170 to recycle the target number, and then the processor 220 instructs the target circuit to complete the shutdown.

[0095] S142, in a standby working state, determining whether the standby current of the target circuit meets a preset condition.

[0096] If the standby current meets the preset condition, it means that the target circuit 001 operates normally. The processor 220 executes process step S160.

[0097] If the standby current does not meet the preset condition, it means that the target circuit 001 is not operating normally and is a substandard product, and a product quality re-inspection is required. The processor 220 executes process step S170 to recycle the target number, and then the processor 220 instructs the target circuit to complete shutdown.

[0098] S160, after writing the target number to the target chip in the target circuit through the target interface, determining that the target number is written successfully, and then running a number verification process.

[0099] S170, when the target number has been written into the target circuit and the target current does not meet a preset condition, the target number is recycled to form a recycled target number.

[0100] S180, instructing the target circuit to complete shutdown through the target interface.

[0101] for Figure 4 as well as Figure 5In the embodiment shown in the present disclosure, the processor 220 executes step S150 to write the target number to the target circuit 001, and determines that the standby current of the target circuit 001 meets the preset condition before step S142. In this way, the target circuit 001 can avoid the need to restart and restore the normal working state after measuring the standby current before the target number can be written. The target circuit 001 can avoid repeated startup during the circuit testing and number writing process. At the same time, by setting a target number recycling mechanism, the method can avoid the waste of target numbers that may be caused by writing the target number first and then measuring the standby current.

[0102] On the other hand, the present disclosure provides a computer-readable storage medium. The storage medium stores the method instructions for the integrated circuit test and number writing. When the instructions are executed by the processor, the instructions guide the processor to implement the steps of the integrated circuit test and number writing method described in the present disclosure. In some possible implementations, various aspects of the present disclosure can also be implemented in the form of a program product, which includes program code. The program product for implementing the above method can use a portable compact disk read-only memory (CD-ROM) to include program code and can be run on a data processing device. However, the program product of the present disclosure is not limited to this. In the present disclosure, the readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system (such as processor 220) or used in combination with it. The program product can use any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of readable storage media include: an electrical connection with one or more conductors, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. The computer-readable storage medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The readable storage medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, device, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the above. Program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the processor 220, partially on the integrated circuit test and number writing device 100, as a separate software package, partially on the data processing device and partially on the remote computing device, or entirely on the remote computing device.

[0103] In summary, after reading this detailed disclosure, it will be apparent to those skilled in the art that the foregoing detailed disclosure may be presented only by way of example and may not be limiting. Although not explicitly stated herein, it will be appreciated by those skilled in the art that this disclosure is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are intended to be proposed by this disclosure and are within the spirit and scope of the exemplary embodiments of this disclosure.

[0104] In addition, certain terms in the present disclosure have been used to describe embodiments of the present disclosure. For example, "one embodiment", "embodiments" and / or "some embodiments" mean that a particular feature, structure or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present disclosure. Therefore, it can be emphasized and should be understood that two or more references to "embodiment" or "one embodiment" or "alternative embodiment" in various parts of the present disclosure do not necessarily refer to the same embodiment. In addition, specific features, structures or characteristics may be appropriately combined in one or more embodiments of the present disclosure.

[0105] It should be understood that in the foregoing description of the embodiments of the present disclosure, in order to help understand a feature and for the purpose of simplifying the present disclosure, the present disclosure sometimes combines various features in a single embodiment, drawing or its description. Alternatively, the present disclosure disperses various features in multiple embodiments of the present disclosure. However, this does not mean that the combination of these features is necessary. It is entirely possible for those skilled in the art to extract some of the features and understand them as separate embodiments when reading the present disclosure. In other words, the embodiments in the present disclosure can also be understood as the integration of multiple secondary embodiments. This is also true when the content of each secondary embodiment is less than all the features of a single aforementioned disclosed embodiment.

[0106] In some embodiments, numbers expressing quantities or properties used to describe and claim certain embodiments of the present disclosure are to be understood as being modified in some cases by the terms "about," "approximately," or "substantially." For example, unless otherwise indicated, "about," "approximately," or "substantially" may represent a ±20% variation of the value it describes. Therefore, in some embodiments, the numerical parameters listed in the written description and the attached claims are approximate values, which may vary depending upon the desired properties sought to be obtained in a particular embodiment. In some embodiments, numerical parameters should be interpreted in light of the number of reported significant digits and by applying ordinary rounding techniques. Although broad ranges of numerical ranges and parameters setting forth some embodiments of the present disclosure are approximate, numerical values ​​are listed as precisely as possible in the specific examples.

[0107] Each patent, patent publication, publication of a patent publication, and other materials, such as articles, books, publications, documents, articles, etc., cited herein may be incorporated herein by reference in its entirety for all purposes, except for any prosecution document history associated therewith, any equivalent that may be inconsistent or conflicting with this document, or any equivalent prosecution document history that may have a limiting effect on the broadest scope of the claims now or later associated with this document. For example, if there is any inconsistency or conflict between the description, definition, and / or use of a term associated with any of the incorporated materials and the term, description, definition, and / or use associated with this document, the term in this document shall control.

[0108] Finally, it should be understood that the embodiments disclosed herein are illustrations of principles. Other modified embodiments are also within the scope of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are merely examples and not limitations. Those skilled in the art can adopt alternative configurations according to the embodiments in the present disclosure to implement the technical solutions in the present disclosure. Therefore, the embodiments of the present disclosure are not limited to those embodiments that have been precisely described in the disclosure.

Claims

1. A method for integrated circuit testing and number writing, characterized in that: Including circuit testing and number writing equipment: Determine a target interface, and complete connection with a target circuit through the target interface; Starting the target circuit through the target interface, wherein starting the target circuit through the target interface includes: starting a target power supply to supply power to the target circuit; instructing the target circuit to complete system startup; obtaining startup self-test information of the target circuit, wherein the startup self-test information includes system version information, startup time information, and operation status information; Wait for a first preset time; reading a target current of the target circuit through the target interface; In a normal working state or in a standby working state, determining that the target current meets a preset condition; Maintaining the current working state of the target circuit, and writing a target number to a target chip in the target circuit through the target interface; and The target circuit is instructed to complete shutdown via the target interface.

2. The integrated circuit testing and numbering method according to claim 1, characterized in that: After determining that the target current meets the preset condition, the target number is immediately written into the target chip in the target circuit through the target interface.

3. The integrated circuit testing and numbering method according to claim 1, characterized in that: After determining that the target current meets the preset condition, the method further includes: Waiting for a second preset time period; and A target number is written into a target chip in the target circuit through the target interface.

4. The integrated circuit testing and numbering method according to claim 1, characterized in that: Also includes: After writing the target number to the target chip in the target circuit through the target interface, Determining that the target number is written successfully; as well as Run the number verification process.

5. The integrated circuit testing and numbering method according to claim 1, characterized in that: The determining that the target current meets a preset condition includes: in a normal working state, determining that an operating current of the target circuit meets a preset condition.

6. The integrated circuit testing and numbering method according to claim 1, characterized in that: The determining that the target current meets a preset condition includes: in a standby working state, determining that a standby current of the target circuit meets a preset condition.

7. The integrated circuit testing and numbering method according to claim 1, characterized in that: The starting of the target circuit through the target interface includes: supplying power to the target circuit through the target interface from a target power supply provided by the circuit testing and number writing device independent of the target circuit.

8. The integrated circuit testing and numbering method according to claim 7, characterized in that: The target power supply includes a programmable power supply.

9. The integrated circuit testing and numbering method according to claim 1, characterized in that: The target circuit includes a smart lock mainboard.

10. The integrated circuit testing and numbering method according to claim 1, characterized in that: The target number includes at least one of an IMEI number, a MEID number, and a MAC address.

11. An integrated circuit testing and number writing device, characterized in that: include: A memory storing at least one set of instruction sets for executing a circuit test and a number writing method; as well as A processor is communicatively connected to the memory, and when the processor is running, it executes the circuit testing and number writing method instruction set in the memory, and executes the method described in any one of claims 1 to 10 according to the circuit testing and number writing method instruction set.

12. The integrated circuit testing and number writing device according to claim 11, characterized in that: Also includes: a test fixture, electrically connected to the target circuit via the target interface, and communicating data with the processor via an I / O component; as well as A target power supply, wherein the first end of the target power supply is electrically connected to a power supply outside the integrated circuit testing and number writing device during operation, and the second end includes a power supply interface, wherein the power supply interface is electrically connected to a test fixture during operation to provide a power source for the integrated circuit testing and number writing device, as well as standard voltage and current signals as reference signal values ​​during the circuit testing process.

13. The integrated circuit testing and number writing device according to claim 11 is characterized in that: It also includes that at least one group of the target numbers is stored in the memory for calling when writing numbers; and the memory stores a recycled target number for being called again after the target number is recycled.

14. The integrated circuit testing and number writing device according to claim 11 is characterized in that: It also includes an MES system, through which the instruction set, target number, and target current test data are managed and maintained.

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