Data drive and display device including data drive

Abstract

This invention relates to a data driver and a display device including the data driver. The data driver includes: a gamma voltage generator configured to generate gamma voltages based on the number of data bits of pixel data; a first data module configured to generate multiple time-division gamma voltage signals corresponding to multiple gamma voltage groups; multiple time-division gamma voltage line groups for transmitting the multiple time-division gamma voltage signals; a second data module configured to select a time-division gamma voltage signal from the time-division gamma voltage signals based on the high-order bits of the pixel data in each channel; a time-division gamma voltage selection block configured to select a gamma voltage based on the low-order bits of the pixel data in each channel; and an output buffer block configured to output the selected gamma voltage in each channel.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device, and more specifically, to a data driver and a display device including the data driver. Background Technology

[0002] The display device's data driver can receive multiple pixel data and output multiple data voltages corresponding to the multiple pixel data to multiple pixels through multiple channels. In doing so, the data driver can generate multiple gamma voltages and provide them to each channel via multiple gamma voltage lines. It selects one of the multiple gamma voltages based on the pixel data for each channel and outputs the selected gamma voltage as the data voltage for each channel. The number of gamma voltage lines corresponding to the number of gamma voltages can increase the size of the data driver. For example, as the number of bits per pixel data increases by 1, the number of gamma voltage lines can be doubled, and the size of the data driver can be increased accordingly. Summary of the Invention

[0003] Some embodiments of this disclosure provide data drivers with reduced size.

[0004] Some embodiments of this disclosure provide a display device including a data driver with a reduced size.

[0005] According to one embodiment, the data driver outputs multiple data voltages to multiple pixels via multiple channels. The data driver includes a gamma voltage generator configured to generate 2... N N gamma voltages, where N is an integer greater than 1, and N corresponds to the number of data bits for each pixel data in a plurality of pixel data received by the data driver; the first data module is configured to transfer 2 N Each gamma voltage component is composed of 2 N-M A set of gamma voltages, making 2 N-M Each of the gamma voltage groups comprises 2 N 2 out of 1 gamma voltage M A number of gamma voltages, where M is an integer greater than 0 and less than N, and the first number module is configured to generate gamma voltages respectively with 2 N-M The two corresponding gamma voltage groups N-M Time-division gamma voltage signal, 2 N-M Each time-division gamma voltage signal in the time-division gamma voltage signal is represented by dividing a horizontal time. M One gamma voltage; 2 N-M A time-division gamma voltage line group is used to transmit 2 N-M Time-division gamma voltage signal, 2 N-MEach time-division gamma voltage line group in the time-division gamma voltage line group includes K time-division gamma voltage lines, where K is greater than 1 and less than or equal to the number of channels; the second counting module is configured to pass through 2 N-M The hourly gamma voltage line group receives 2 N-M A time-division gamma voltage signal, and based on the N bits of the high NM bits of the corresponding pixel data in each of the multiple channels in the multiple pixel data, in 2 N -M The time-division gamma voltage signal is selected from among the time-division gamma voltage signals; the time-division gamma voltage selection block is configured to select the time-division gamma voltage signal based on the lower M bits of the N bits of the corresponding pixel data in each of the multiple channels of the multiple pixel data. M Among the gamma voltages, one gamma voltage represented by the time-division gamma voltage signal selected by the second data module is selected; and the output buffer block is configured to output the gamma voltage of each of the multiple channels as the data voltage among the multiple data voltages.

[0006] In this embodiment, multiple channels can be divided into K channel groups, and K time-division gamma voltage lines can be coupled to the K channel groups respectively.

[0007] In an embodiment, the multiple channels may include K*L channels, where L is an integer greater than zero. The K*L channels can be divided into K channel groups, such that the K*I+Jth channel among the K*L channels is divided into the Jth channel group among the K channel groups, where I is an integer greater than or equal to zero and less than L, and J is an integer greater than zero and less than or equal to K. Furthermore, K time-division gamma voltage lines can be coupled to the K channel groups respectively, such that each of the K time-division gamma voltage lines is coupled to L channels among the K*L channels.

[0008] In this embodiment, the K time-division gamma voltage lines can be four time-division gamma voltage lines, and the multiple channels can include 4*L channels, where L is an integer greater than zero. The 4*L channels can be divided into 4 channel groups, such that the 4*1+Jth channel among the 4*L channels is divided into the Jth channel group among the 4 channel groups, where I is an integer greater than or equal to zero and less than L, and J is an integer greater than zero and less than or equal to 4. The four time-division gamma voltage lines can be coupled to the 4 channel groups respectively, such that each of the four time-division gamma voltage lines is coupled to the corresponding L channels among the 4*L channels.

[0009] In an embodiment, the multiple channels may include K*L channels, where L is an integer greater than zero. The K*L channels can be divided into K channel groups, such that L consecutive channels in the K*L channels are grouped into channel groups within the K channel groups. Furthermore, K time-division gamma voltage lines can be coupled to the K channel groups respectively, such that each of the K time-division gamma voltage lines is coupled to L consecutive channels in the K*L channels.

[0010] In this embodiment, the K time-division gamma voltage lines can be four time-division gamma voltage lines, and the multiple channels can include 4*L channels, where L is an integer greater than zero. The first to the Lth channel of the 4*L channels can be grouped into a first channel group, the (L+1)th to the 2Lth channel of the 4*L channels can be grouped into a second channel group, the (2L+1)th to the 3Lth channel of the 4*L channels can be grouped into a third channel group, and the (3L+1)th to the 4Lth channel of the 4*L channels can be grouped into a fourth channel group. The four time-division gamma voltage lines can be coupled to the first, second, third, and fourth channel groups respectively, such that each of the four time-division gamma voltage lines is coupled to L channels of the 4*L channels.

[0011] In an embodiment, a horizontal time period can be equally divided into 2 segments with the same time interval. M The time is divided into 2 time segments, and each time-division gamma voltage signal can be represented in 2... M Two voltage intervals with nonlinearity in each time division M One gamma voltage.

[0012] In an embodiment, a horizontal time period can be equally divided into 2 segments with the same time interval. M The time is divided into 2 time segments, and each time-division gamma voltage signal can be represented in 2... M Two time intervals with the same voltage interval M One gamma voltage.

[0013] In an embodiment, a horizontal time can be divided into 2 time periods with different durations. M The time is divided into 2 time segments, and each time-division gamma voltage signal can be represented in 2... M Two time intervals with the same voltage interval M One gamma voltage.

[0014] In an embodiment, the gamma voltage generator may include 2 N +1 resistor, the 2 N+1 resistor is connected in series between the high-voltage first line and the low-voltage second line, and is configured to generate 2 by dividing the voltage between the high and low voltages. N One gamma voltage.

[0015] In the embodiment, the 2 generated by the gamma voltage generator N The gamma voltage can be gradually decreased from the first gamma voltage to the second. N Gamma voltage.

[0016] In the embodiment, the 2 generated by the gamma voltage generator N The gamma voltage can be gradually increased from the first gamma voltage to the second. N Gamma voltage.

[0017] In the embodiment, 2 N The first voltage interval between gamma voltages in the low grayscale region can be less than 2. N The second voltage interval between gamma voltages in the high grayscale region.

[0018] In an embodiment, the first number module may include: a clock generator configured to generate a clock with 2 during a horizontal time period. M A clock signal; a bit counter configured to generate a representation of 1 to 2 in response to the clock signal. M The counting signal; and 2 N-M An M-bit analog-to-digital converter is configured to output 2... N-M Time-division gamma voltage signal, 2 N-M Each of the M-bit analog-to-digital converters is configured to sequentially output 2 in response to a counting signal. M A gamma voltage as 2 N -M The time-division gamma voltage signal in the time-division gamma voltage signal.

[0019] In an embodiment, the second data module may include a plurality of NM bit-to-analog converters, each corresponding to a plurality of channels. Each of the plurality of NM bit-to-analog converters is configured to, based on the high NM bits of a corresponding pixel data from a plurality of pixel data, in 2 N-M Select a time-division gamma voltage signal from the time-division gamma voltage signals.

[0020] In an embodiment, each of the plurality of NM bit-to-analog converters may include: a decoder configured to generate 2 based on the high NM bits of a corresponding pixel data from a plurality of pixel data. N-M One switch signal; and 2 N-M A switch is configured to respond to 2 N-MTwo switch signals are selectively output. N-M A time-division gamma voltage signal.

[0021] In an embodiment, the time-division gamma voltage selection block may include: a plurality of switch signal generators, each corresponding to a plurality of channels, wherein each of the plurality of switch signal generators is configured to operate at 2 in a horizontal time. M During the time division corresponding to the lower M bits of a pixel data in a plurality of pixel data, a time-division switching signal with an effective level is generated; and a plurality of time-division gamma voltage selection switches, each corresponding to a plurality of channels, are generated. Each of the plurality of time-division gamma voltage selection switches is configured to respond to the time-division switching signal with an effective level in 2 M Choose a gamma voltage from among the gamma voltages.

[0022] In an embodiment, the data driver may further include: a shift register block configured to sequentially generate sampling signals in response to a start signal and a clock signal; a sampling latch block configured to sequentially sample a plurality of pixel data in response to the sampling signals; and a holding latch block configured to store the plurality of pixel data sampled by the sampling latch block in response to a load signal.

[0023] In an embodiment, the high NM bits of each pixel data in the plurality of pixel data output from the holding latch block can be provided to the second data module, and the low M bits of each pixel data in the plurality of pixel data output from the holding latch block can be provided to the time-division gamma voltage selection block.

[0024] According to one embodiment, a display device includes: a display panel including a plurality of pixels; a data driver configured to receive a plurality of pixel data, each having N bits, and to output a plurality of data voltages corresponding to the plurality of pixel data to the plurality of pixels through a plurality of channels, wherein N is an integer greater than 1; and a controller configured to provide the plurality of pixel data to the data driver. The data driver includes: a gamma voltage generator configured to generate 2 N One gamma voltage; the first number module is configured to output 2 gamma voltages. N Each gamma voltage component is composed of 2 N-M A set of gamma voltages, making 2 N-M Each of the gamma voltage groups comprises 2 N 2 out of 1 gamma voltage M A number of gamma voltages, where M is an integer greater than 0 and less than N, and the first number module is configured to generate gamma voltages respectively with 2 N-M The two corresponding gamma voltage groups N-M Time-division gamma voltage signal, 2 N-MEach time-division gamma voltage signal in the time-division gamma voltage signal is represented by dividing a horizontal time. M One gamma voltage; 2 N-M A time-division gamma voltage line group is used to transmit 2 N-M Time-division gamma voltage signal, 2 N-M Each time-division gamma voltage line group in the time-division gamma voltage line group includes K time-division gamma voltage lines, where K is greater than 1 and less than or equal to the number of channels; the second counting module is configured to pass through 2 N-M The hourly gamma voltage line group receives 2 N-M A time-division gamma voltage signal, and based on the N bits of the high NM bits of the corresponding pixel data in each of the multiple channels in the multiple pixel data, in 2 N-M The time-division gamma voltage signal is selected from among the time-division gamma voltage signals; the time-division gamma voltage selection block is configured to select the time-division gamma voltage signal based on the lower M bits of the N bits of the corresponding pixel data in each of the multiple channels of the multiple pixel data. M The gamma voltage represented by the time-division gamma voltage signal selected by the second data module is chosen from among the gamma voltages; and the output buffer block is configured to output the gamma voltage of each of the multiple channels as the data voltage among the multiple data voltages.

[0025] As described above, in the data driver and display device according to the embodiment, the first data module can generate 2 N-M The second data module can select 2 time-division gamma voltage signals based on the high NM bits of each pixel data in each channel. N-M One of the 2M time-division gamma voltage signals, and the time-division gamma voltage selection block can select one gamma voltage from the selected time-division gamma voltage signal based on the low M bits of each pixel data in each channel. Therefore, the size and power consumption of the data driver can be reduced.

[0026] Furthermore, in the data driver and display device according to the embodiment, each time-division gamma voltage signal can be transmitted to multiple channels via K time-division gamma voltage lines, where K is greater than 1 and less than or equal to the number of multiple channels, and each time-division gamma voltage line can be coupled only to the corresponding portion of the multiple channels. Therefore, the delay (e.g., RC delay) of the time-division gamma voltage signal can be reduced, and the time-division gamma voltage signal can be accurately transmitted to multiple channels. Attached Figure Description

[0027] The exemplary and non-limiting embodiments of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1This is a block diagram of a data driver according to an embodiment.

[0029] Figure 2 This is a circuit diagram of a gamma voltage generator included in a data driver according to an embodiment.

[0030] Figure 3 The illustration shows an example of a gamma voltage generated by a gamma voltage generator according to an embodiment.

[0031] Figure 4 The illustration shows another example of a gamma voltage generated by a gamma voltage generator according to an embodiment.

[0032] Figure 5 This is a block diagram of a first data module included in a data driver according to an embodiment.

[0033] Figure 6 The illustration shows an example of a time-division gamma voltage signal output by each M-bit analog-to-digital converter of the first number module.

[0034] Figure 7 The illustration shows another example of the time-division gamma voltage signal output by each M-bit analog-to-digital converter of the first number module.

[0035] Figure 8 The illustration shows another example of the time-division gamma voltage signal output by each M-bit analog-to-digital converter of the first number module.

[0036] Figure 9 This is a block diagram of a data driver according to an embodiment, including multiple time-division gamma voltage line groups coupled to multiple channels.

[0037] Figure 10 This is a circuit diagram of a time-division gamma voltage line used to describe an example of the delay of a time-division gamma voltage signal.

[0038] Figure 11 This is a block diagram of a data driver including multiple time-division gamma voltage line groups coupled to multiple channels, according to another embodiment.

[0039] Figure 12 This is a block diagram of a second data module included in a data driver according to an embodiment.

[0040] Figure 13 This is a block diagram of a time-division gamma voltage selection block included in a data driver according to an embodiment.

[0041] Figure 14 Illustration Figure 13 An example of the operation of the time-division gamma voltage selection block.

[0042] Figure 15 This is a block diagram of a display device including a data driver according to an embodiment.

[0043] Figure 16 This is a circuit diagram of pixels included in a display device according to an embodiment.

[0044] Figure 17 This is a circuit diagram of another example of a pixel included in a display device according to an embodiment.

[0045] Figure 18 This is a block diagram of an electronic device including a display device according to an embodiment. Detailed Implementation

[0046] Embodiments of the present disclosure are described more fully below with reference to the accompanying drawings. Throughout this disclosure, the same or similar reference numerals refer to the same or similar elements.

[0047] Figure 1 This is a block diagram of a data driver according to an embodiment. Figure 2 This is a circuit diagram of a gamma voltage generator included in a data driver according to an embodiment. Figure 3 The illustration shows an example of a gamma voltage generated by a gamma voltage generator according to an embodiment. Figure 4 The illustration shows another example of a gamma voltage generated by a gamma voltage generator according to an embodiment. Figure 5 This is a block diagram of a first data module included in a data driver according to an embodiment. Figure 6 The illustration shows an example of the time-division gamma voltage signal output by each M-bit analog-to-digital converter of the first number module. Figure 7 The illustration shows another example of the time-division gamma voltage signal output by each M-bit analog-to-digital converter of the first number module. Figure 8 The illustration shows another example of the time-division gamma voltage signal output by each M-bit analog-to-digital converter of the first digital module. Figure 9 This is a block diagram of a data driver according to an embodiment, including multiple time-division gamma voltage line groups coupled to multiple channels. Figure 10 This is a circuit diagram of a time-division gamma voltage line used to describe an example of the delay of a time-division gamma voltage signal. Figure 11 This is a block diagram of a data driver according to another embodiment, including multiple time-division gamma voltage line groups coupled to multiple channels in a data driver. Figure 12 This is a block diagram of a second data module included in a data driver according to an embodiment. Figure 13 This is a block diagram of a time-division gamma voltage selection block included in a data driver according to an embodiment, and Figure 14 Illustration Figure 13 An example of the operation of the time-division gamma voltage selection block.

[0048] Reference Figure 1The data driver 100 can receive multiple pixel data PDAT and output multiple data voltages VD corresponding to the multiple pixel data PDAT to multiple pixels of the display panel through multiple channels CH. The data driver 100 may include a gamma voltage generator 150, a first data module 160, and 2... N-M Time-division gamma voltage line group TDGVLG1 to TDGVLG2 N-M The data driver 100 includes a second data module 170, a time-division gamma voltage selection block 180, and an output buffer block 190. In some embodiments, the data driver 100 may further include a shift register block 110, a sampling latch block 120, a holding latch block 130, and a level shifter block 140.

[0049] Shift register block 110 can sequentially generate sampling signals SS in response to a start signal STS and a clock signal CLK. In some embodiments, shift register block 110 may include a plurality of serially connected shift registers, which sequentially output sampling signals SS in response to a shift start signal STS via a clock signal CLK.

[0050] The sampling latch block 120 can respond to the sampling signal SS received from the shift register block 110, sequentially sampling signals from the controller (e.g., Figure 15 The controller 440 in the middle samples the output image data ODAT or the multiple pixel data PDAT of multiple pixels. In some embodiments, the sampling latch block 120 may include multiple sampling latches, which sample the multiple pixel data PDAT respectively in response to the sampling signal SS.

[0051] Hold latch block 130 can store multiple pixel data PDAT sampled by sampling latch block 120 in response to load signal LOAD. In some embodiments, hold latch block 130 may include multiple hold latches corresponding to multiple sampling latches of sampling latch block 120.

[0052] Level shifter block 140 can change the voltage level of multiple pixel data PDAT output from holding latch block 130 to a voltage level suitable for second data module 170 and / or time-division gamma voltage selection block 180. In some embodiments, level shifter block 140 may include multiple level shifters corresponding to multiple holding latches of holding latch block 130.

[0053] In some embodiments, each pixel data PDAT may have N bits, where N is an integer greater than 1. In each channel CH, the high NM bits of each pixel data PDAT output from the holding latch block 130 via the level shifter block 140 can be provided to the second number module 170, and the low M bits of each pixel data PDAT output from the holding latch block 130 via the level shifter block 140 can be provided to the time-division gamma voltage selection block 180, where M is an integer greater than 0 and less than N. For example, when N is 10 and M is 4, the holding latch block 130 can provide the high 6 bits of each pixel data PDAT to the second number module 170, and can provide the low 4 bits of each pixel data PDAT to the time-division gamma voltage selection block 180.

[0054] The gamma voltage generator 150 can generate a 2x2 voltage that can be represented by PDAT data with N bits per pixel. N 2 corresponding to each gray level N A gamma voltage. In some embodiments, the gamma voltage generator 150 can receive a gamma voltage with a value of 2 from a controller (not shown) or a gamma reference voltage generator (not shown). N A gamma reference voltage for a portion of the grayscale levels, and gamma reference voltages for all 2 grayscale levels can be generated based on the gamma reference voltages. N 2 corresponding to each gray level N One gamma voltage.

[0055] In some embodiments, such as Figure 2 As illustrated in the diagram, the gamma voltage generator 150 may include two components connected in series between the high voltage VDD line and the low voltage VSS line. N +1 resistor R1 to R2 N +1.2 N +1 resistor R1 to R2 N +1 can be generated by voltage division between the high voltage VDD and the low voltage VSS. N Gamma voltages GV1 to GV2 N In some embodiments, such as Figure 3 The diagram shows the 2 generated by the gamma voltage generator 150. N Gamma voltages GV1 to GV2 N The first gamma voltage GV1, corresponding to the first gray level (e.g., gray level 0), can be gradually decreased to the second gamma voltage. N The second gray level (e.g., 255 gray levels when N is 8) corresponds to the gray level. N Gamma voltage GV2 N In other embodiments, such as Figure 4 The diagram shows the 2 generated by the gamma voltage generator 150.N Gamma voltages GV1 to GV2 N The first gamma voltage GV1, corresponding to the first gray level (e.g., gray level 0), can be gradually increased to the second gamma voltage. N The second gray level (e.g., 255 gray levels when N is 8) corresponds to the gray level. N Gamma voltage GV2 N For example, such as Figure 16 As illustrated in the diagram, with each pixel PX including a driving transistor PT1 implemented using a P-type metal-oxide-semiconductor (PMOS) transistor, the gamma voltage generator 150 can generate (but is not limited to) the following: Figure 3 The figure in the middle is 2 N Gamma voltages GV1 to GV2 N In another example, such as Figure 17 As illustrated in the diagram, with each pixel PX including a driving transistor NT1 implemented using an N-type metal-oxide-semiconductor (NMOS) transistor, the gamma voltage generator 150 can generate, but is not limited to, the following: Figure 4 The figure in the middle is 2 N Gamma voltages GV1 to GV2 N In yet another example, regardless of the type of driving transistor, the 2 generated by the gamma voltage generator 150 N Gamma voltages GV1 to GV2 N The voltage can be increased and / or decreased from the first gamma voltage GV1 to the second. N Gamma voltage GV2 N Furthermore, in some embodiments, such as Figure 3 and Figure 4 As shown in the diagram, in the low grayscale area (e.g., from the first grayscale level to the second grayscale level) M The gamma voltage in the grayscale level (e.g., the first gamma voltage GV1 to the second gamma voltage GV1) M Gamma voltage GV2 M The voltage interval between () can be smaller than that in the high grayscale region (e.g., from the 2nd) N -2 M +1 gray level to the 2nd N The gamma voltage in grayscale levels (e.g., the second) N -2 M +1 Gamma voltage GV2 N -2 M +1 to 2 N Gamma voltage GV2 N The voltage interval between ( ). For example, as the gray level increases, or as 2 ) N Gamma voltages GV1 to GV2 N Increase the first gamma voltage GV1 to the second N Gamma voltage GV2N ,2 N Gamma voltages GV1 to GV2 N The voltage interval between two adjacent gamma voltages can be gradually increased. In this case, 2 N Gamma voltages GV1 to GV2 N It can have relatively small voltage intervals in low grayscale areas, thus allowing for more accurate representation of grayscale levels in low grayscale areas.

[0056] Furthermore, in some embodiments, such as Figure 2 As shown in the diagram, 2 N Gamma voltages GV1 to GV2 N It can be divided into 2 (via the first number module 160) N-M Gamma voltage groups GVG1 to GVG2 N-M This allows each gamma voltage group (e.g., the first gamma voltage group GVG1) to include 2 N Gamma voltages GV1 to GV2 N Among them 2 M Each gamma voltage (e.g., the first gamma voltage GV1 to the second) M Gamma voltage GV2 M For example, when N is 10 and M is 4, the first gamma voltage GV1 to the sixteenth gamma voltage GV16 can be grouped into the first gamma voltage group GVG1, the seventeenth gamma voltage GV17 to the thirty-second gamma voltage GV32 can be grouped into the second gamma voltage group GVG2, and the first 1009 gamma voltage GV1009 to the first 1024 gamma voltage GV1024 can be grouped into the sixty-fourth gamma voltage group GVG64.

[0057] The first data module 160 can receive 2 from the gamma voltage generator 150. N-M Gamma voltage groups GVG1 to GVG2 N-M Each gamma voltage group (e.g., the first gamma voltage group GVG1) includes 2 M Each gamma voltage (e.g., the first gamma voltage GV1 to the second) M Gamma voltage GV2 M ), and the first number module 160 can generate numbers respectively with 2 N-M Gamma voltage groups GVG1 to GVG2 N-M Corresponding 2 N-M The time-division gamma voltage signals TDGVS1 to TDGVS2 N-M Each time-division gamma voltage signal TDGVS (e.g., the first time-division gamma voltage signal TDGVS1) can be represented by dividing a horizontal time 1H. MEach gamma voltage (e.g., the first gamma voltage GV1 to the second) M Gamma voltage GV2 M A horizontal time of 1H indicates the time required to process one row of pixels.

[0058] In some embodiments, such as Figure 5 As shown in the diagram, the first number module 160 may include an M-clock generator 161, an M-bit counter 162, and a 2-bit counter 163. N-M M-bit analog-to-digital converters (DACs) 163, 164, ..., 166. An M-clock generator 161 can generate clocks with 2... M The M-bit counter 162 generates an M-clock signal MCLK that increments from 1 to 2 during a horizontal time period of 1H by counting the clock signals MCLK. M The value of the M-count signal MCS. 2 N-M Each M-bit DAC (163, 164, ..., 166) can output 2... N-M The time-division gamma voltage signals TDGVS1 to TDGVS2 N-M Each M-bit DAC (e.g., the first M-bit DAC 163) can receive a corresponding gamma voltage group (e.g., the first gamma voltage group GVG1) or 2 M Each gamma voltage (e.g., the first gamma voltage GV1 to the second) M Gamma voltage GV2 M It can sequentially output 2 in response to the M counting signal MCS. M Each gamma voltage (e.g., the first gamma voltage GV1 to the second) M Gamma voltage GV2 M ) as 2 N-M The time-division gamma voltage signals TDGVS1 to TDGVS2 N-M The corresponding time-division gamma voltage signal TDGVS (e.g., the first time-division gamma voltage signal TDGVS1). For example, when M is 3, such as Figure 6 As shown in the diagram, a horizontal time interval of 1 hour can be equally divided into 2... M (Or 8) time divisions with the same time interval 1H / 8, and each time-division gamma voltage signal TDGVS output from each M-bit DAC (e.g., the first M-bit DAC 163) can respectively represent the corresponding 2 with nonlinear voltage intervals in the 8 time divisions. M (Or 8) gamma voltages GV1, GV2, GV3, GV4, GV5, GV6, GV7, and GV8. In Figure 6In this example, the eight gamma voltages GV1, GV2, GV3, GV4, GV5, GV6, GV7 and GV8 of the time-division gamma voltage signal TDGVS can have gradually increasing voltage intervals over a horizontal time period of 1H.

[0059] In other embodiments, such as Figure 7 As shown in the diagram, a horizontal time interval of 1 hour can be equally divided into 2... M There are 8 (or 8 in this example, where M is 3) time divisions with the same time period of 1H / 8, and each time-division gamma voltage signal TDGVS can represent 8 gamma voltages GV1 to GV8 with substantially the same voltage interval in the 8 time divisions. Figure 7 In this example, the eight gamma voltages GV1 to GV8 of the time-division gamma voltage signal TDGVS can decrease linearly with time over a horizontal time period of 1H.

[0060] In yet another embodiment, such as Figure 8 As shown in the diagram, a horizontal time period of 1 hour can be divided into 2 time periods with different durations. M Divide the time into 1 (or 8 in this example, where M is 3) segments from time T1 to T8. Figure 8 In this example, the eight time divisions T1 to T8 can have progressively increasing time intervals within a horizontal time period 1H. Furthermore, each time-division gamma voltage signal TDGVS can represent eight gamma voltages GV1 to GV8 with substantially the same voltage interval across the eight time divisions.

[0061] For example, such as Figure 6 , Figure 7 and Figure 8 As shown in the diagram, due to 2 N-M Each M-bit DAC (163, 164, ..., 166) generates 2... N-M The time-division gamma voltage signals TDGVS1 to TDGVS2 N-M Therefore, 2 can be adjusted separately or independently. N-M The time-division gamma voltage signals TDGVS1 to TDGVS2 N-M .

[0062] Reference Figure 1 2 generated by the first number module 160 N-M The time-division gamma voltage signals TDGVS1 to TDGVS2 N-M It can be provided to multiple CH channels, or via 2 N-M Time-division gamma voltage line group TDGVLG1 to TDGVLG2 N-M Multiple NM-bit DACs 172 provided to the second number module 170 in multiple channel CHs (see Figure 12 In addition, such as Figure 1 As shown in the diagram, 2 N-M Time-division gamma voltage line group TDGVLG1 to TDGVLG2 N-M Each of these can include K time-division gamma voltage lines (TDGVL) (in Figure 1 The term "CH" also refers to K lines, where K is greater than 1 and less than or equal to the number of multiple channels (CH). Furthermore, each time-division gamma voltage line group (TDGVLG) (e.g., the first time-division gamma voltage line group TDGVLG1) has K time-division gamma voltage lines (TDGVL) that can transmit 2... N-M The time-division gamma voltage signals TDGVS1 to TDGVS2 N-M The same time-division gamma voltage signal TDGVS (e.g., the first time-division gamma voltage signal TDGVS1) in the process.

[0063] In the data driver 100 according to an embodiment, multiple channels CH can be grouped into K channel groups, and the K time-division gamma voltage lines TDGVL of each time-division gamma voltage line group TDGVLG can be coupled to the K channel groups respectively. Therefore, each time-division gamma voltage line TDGVL can be coupled to only a portion of the multiple channel CHs. Therefore, the load on each time-division gamma voltage line TDGVL and the channel CH coupled to each time-division gamma voltage line TDGVL can be reduced, and the delay (e.g., RC delay) of the time-division gamma voltage signal TDGVS transmitted through the time-division gamma voltage line TDGVL can be reduced.

[0064] In some embodiments, the multiple channels CH in the data driver 100 may include K*L channels, where L is an integer greater than 0, and the K*L channels may be divided into K channel groups, such that the K*I+J-th channel among the K*L channels is divided into the J-th channel group among the K channel groups, where I is an integer greater than or equal to 0 and less than L, and J is an integer greater than 0 and less than or equal to K. In this case, K time-division gamma voltage lines TDGVL can be coupled to the K channel groups respectively, such that each of the K time-division gamma voltage lines TDGVL is coupled to the corresponding L channels among the K*L channels.

[0065] Reference Figure 9Each time-division gamma voltage line group (TDGVLG) (e.g., the first time-division gamma voltage line group TDGVLG1) may include four time-division gamma voltage lines (TDGVL) as K time-division gamma voltage lines (TDGVL). For example, the first time-division gamma voltage line group TDGVLG1 may include four time-division gamma voltage lines (TDGVL1_1, TDGVL1_2, TDGVL1_3, and TDGVL1_4) for transmitting the first time-division gamma voltage signal TDGVS1, and the second time-division gamma voltage line group TDGVLG2 may include four time-division gamma voltage lines (TDGVL2_1, TDGVL2_2, TDGVL2_3, and TDGVL2_4) for transmitting the second time-division gamma voltage signal TDGVS2, and the second... N-M Time-division gamma voltage line group TDGVLG2 N-M It may include the transmission of the second N-M Time-division gamma voltage signal TDGVS2 N-M The four time-division gamma voltage lines TDGVL2 N-M _1、TDGVL2 N-M _2、TDGVL2 N-M _3 and TDGVL2 N-M 4. The 4*L channels CH1 to CH4L can be divided into four channel groups CHG1, CHG2, CHG3, and CHG4. For example, the first channel CH1, the fifth channel CH5, ... and the 4L-3 channel CH4L-3 can be divided into the first channel group CHG1; the second channel CH2, the sixth channel CH6, ... and the 4L-2 channel CH4L-2 can be divided into the second channel group CHG2; the third channel CH3, the seventh channel CH7, ... and the 4L-1 channel CH4L-1 can be divided into the third channel group CHG3; and the fourth channel CH4, the eighth channel CH8, ... and the 4L channel CH4L can be divided into the fourth channel group CHG4. Each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) has four time-division gamma voltage lines TDGVL (e.g., time-division gamma voltage lines TDGVL1_1, TDGVL1_2, TDGVL1_3, and TDGVL1_4), which can be coupled to four channel groups CHG1, CHG2, CHG3, and CHG4, respectively. Figure 9In the example, the second data module 170a may include 4*L NM-bit DACs 211a to 222a in 4*L channels CH1 to CH4L. The first time-division gamma voltage line TDGVL (e.g., the first time-division gamma voltage line TDGVL1_1) of each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) may be coupled to the NM-bit DACs 211a, 215a, ..., 219a in channels CH1, CH5, ..., CH4L-3 of the first channel group CHG1. The second time-division gamma voltage line TDGVL (e.g., the second time-division gamma voltage line TDGVL1_2) of each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) may be coupled to the NM-bit DACs in channels CH2, CH6, ..., CH4L-2 of the second channel group CHG2. 212a, 216a, ..., 220a, the third time-division gamma voltage line TDGVL (e.g., the third time-division gamma voltage line TDGVL1_3) of each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) can be coupled to the NM-bit DACs 213a, 217a, ..., 221a in channels CH3, CH7, ..., CH4L-1 belonging to the third channel group CHG3, and the fourth time-division gamma voltage line TDGVL (e.g., the fourth time-division gamma voltage line TDGVL1_4) of each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) can be coupled to the NM-bit DACs 214a, 218a, ..., 222a in channels CH4, CH8, ..., CH4L belonging to the fourth channel group CHG4. That is, each time-division gamma voltage line TDGVL (e.g., the first time-division gamma voltage line TDGVL1_1) can be coupled to only L channels out of 4*L channels CH1 to CH4L (e.g., channels CH1, CH5, ..., CH4L-3). In this case, as Figure 10As shown in the diagram, the time-division gamma voltage line TDGVL used to transmit the time-division gamma voltage signal TDGVS is only coupled to L channels CH1, CH5, ..., CH4L-3 out of the 4*L channels CH1 to CH4L. Therefore, the time-division gamma voltage signal TDGVS is not affected by all 4*L parasitic capacitors PC1 to PC4L of the 4*L channels CH1 to CH4L, but is only affected by L parasitic capacitors PC1, PC5, ..., PC4L-3 of the L channels CH1, CH5, ..., CH4L-3. Therefore, compared to the case where each time-division gamma voltage line TDGVL is coupled to all channels CH1 to CH4L, in the data driver 100 according to the embodiment, the load of each time-division gamma voltage line TDGVL and the channels CH1, CH5, ..., CH4L-3 coupled to that time-division gamma voltage line TDGVL can be reduced, and the delay (e.g., RC delay) of the time-division gamma voltage signal TDGVS transmitted through the time-division gamma voltage line TDGVL can be reduced.

[0066] In other embodiments, the multiple channels CH of the data driver 100 may include K*L channels, and the K*L channels may be grouped into K channel groups, such that L consecutive channels among the K*L channels are grouped into the same channel group. Furthermore, the K time-division gamma voltage lines TDGVL may be coupled to the K channel groups respectively. In this case, each of the K time-division gamma voltage lines TDGVL may be coupled to only the corresponding L channels among the K*L channels.

[0067] Reference Figure 11Each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) may include four time-division gamma voltage lines TDGVL (e.g., time-division gamma voltage lines TDGVL1_1, TDGVL1_2, TDGVL1_3, and TDGVL1_4) as K time-division gamma voltage lines TDGVL. The 4*L channels CH1 to CH4L can be divided into four channel groups CHG1, CHG2, CHG3, and CHG4. For example, the first channel CH1 to the Lth channel CHL can be divided into the first channel group CHG1, the (L+1)th channel CHL+1 to the 2Lth channel CH2L can be divided into the second channel group CHG2, the (2L+1)th channel CH2L+1 to the 3Lth channel CH3L can be divided into the third channel group CHG3, and the (3L+1)th channel CH3L+1 to the 4Lth channel CH4L can be divided into the fourth channel group CHG4. Each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) has four time-division gamma voltage lines TDGVL (e.g., time-division gamma voltage lines TDGVL1_1, TDGVL1_2, TDGVL1_3, and TDGVL1_4), which can be coupled to four channel groups CHG1, CHG2, CHG3, and CHG4, respectively. Figure 11In the example, the second data module 170b may include 4*L NM-bit DACs 211b to 218b in 4*L channels CH1 to CH4L. The first time-division gamma voltage line TDGVL (e.g., the first time-division gamma voltage line TDGVL1_1) of each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) may be coupled to the NM-bit DACs 211b, ..., 212b in channels CH1 to CHL belonging to the first channel group CHG1. The second time-division gamma voltage line TDGVL (e.g., the second time-division gamma voltage line TDGVL1_2) of each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) may be coupled to the NM-bit DACs in channels CHL+1 to CH2L belonging to the second channel group CHG2. 213b, ..., 214b, the third time-division gamma voltage line TDGVL (e.g., the third time-division gamma voltage line TDGVL1_3) of each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) can be coupled to the NM-bit DAC 215b, ..., 216b in channels CH2L+1 to CH3L belonging to the third channel group CHG3, and the fourth time-division gamma voltage line TDGVL (e.g., the fourth time-division gamma voltage line TDGVL1_4) of each time-division gamma voltage line group TDGVLG (e.g., the first time-division gamma voltage line group TDGVLG1) can be coupled to the NM-bit DAC 217b, ..., 218b in channels CH3L+1 to CH4L belonging to the fourth channel group CHG4. That is, each time-division gamma voltage line TDGVL (e.g., the first time-division gamma voltage line TDGVL1_1) can be coupled to only L channels (e.g., channels CH1 to CHL) out of 4*L channels CH1 to CH4L. Therefore, the load on each time-division gamma voltage line TDGVL and the channels CH1 to CHL coupled to it can be reduced, and the delay (e.g., RC delay) of the time-division gamma voltage signal TDGVS (e.g., the first time-division gamma voltage signal TDGVS1) transmitted through the time-division gamma voltage line TDGVL (e.g., the first time-division gamma voltage line TDGVL1_1) can be reduced.

[0068] although Figure 9 and Figure 11 The illustration shows an example where each time-division gamma voltage line group (TDGVLG) includes four time-division gamma voltage lines (TDGVL), but the number of time-division gamma voltage lines (TDGVL) included in each time-division gamma voltage line group (TDGVLG) is not limited to this. Figure 9 and Figure 11 Examples. Furthermore, Figure 9 and Figure 11The diagram illustrates an example of connecting a time-division gamma voltage line (TDGVL) to multiple channel CHs. The connection relationships between the TDGVL and the multiple channel CHs are not limited to... Figure 9 and Figure 11 Examples.

[0069] Refer again Figure 1 The second data module 170 can receive the high NM bits of each pixel data PDAT from the holding latch block 130 (via the level shifter block 140), which can be accessed via 2 N-M Time-division gamma voltage line group TDGVLG1 to TDGVLG2 N-M Receive 2 from the first data module 160 N-M The time-division gamma voltage signals TDGVS1 to TDGVS2 N-M Furthermore, based on the high NM bits of the N-bit pixel data PDAT in each channel CH, in 2 N-M The time-division gamma voltage signals TDGVS1 to TDGVS2 N-M One of these is a time-division gamma voltage signal STDGVS. For example, when N is 10 and M is 4, the second number module 170 can select one of the 64 time-division gamma voltage signals STDGVS1 to STDGVS2 based on the high 6 bits of the pixel data PDAT in each channel CH. 6 Select one of the time-division gamma voltage signals, STDGVS.

[0070] In some embodiments, such as Figure 12 As illustrated in the diagram, the second data module 170 may include multiple NM-bit DACs 172, each corresponding to a plurality of channels CH. That is, the number of NM-bit DACs 172 in the second data module 170 can correspond to the number of channels CH. The NM-bit DAC 172 in each channel CH can be configured based on the high NM bits of the pixel data PDAT. N-M The time-division gamma voltage signals TDGVS1 to TDGVS2 N-M One of these is a time-division gamma voltage signal, STDGVS. To perform this operation, the NM-bit DAC 172 in each channel CH may include a decoder 174 and 2... N-M Switches SW1 to SW2 N-M Decoder 174 can generate 2 based on the high NM bits of pixel data PDAT. N-M Switch signals SWS1 to SWS2 N-M 2 N-M Switches SW1 to SW2 N-M Can respond to 2 respectively N-M Switch signals SWS1 to SWS2 N-M Selectively output 2N-M The time-division gamma voltage signals TDGVS1 to TDGVS2 N-M 2 N-M Switch signals SWS1 to SWS2 N-M One of them can have a conduction level based on the high NM bit of the pixel data PDAT, 2 N-M Switches SW1 to SW2 N-M One of them can be turned on in response to a switch signal with an on level, and therefore, 2 N-M The time-division gamma voltage signals TDGVS1 to TDGVS2 N-M One of them can be output as the selected time-division gamma voltage signal STDGVS. Although Figure 12 The illustration shows an example of implementing the second number module 170 using a decoder-type DAC including decoder 174, but according to the embodiment, the second number module 170 can be implemented using a read-only memory (ROM) type DAC, a tree-type DAC, or any other type of DAC.

[0071] Refer again Figure 1 The time-division gamma voltage selection block 180 can receive the lower M bits of each pixel data PDAT from the holding latch block 130 via the level shifter block 140, and can receive the selected time-division gamma voltage signal STDGVS from the second data module 170 in each channel CH. Furthermore, based on the lower M bits of the pixel data PDAT in each channel CH, it can select the appropriate time-division gamma voltage signal STDGVS. M A gamma voltage (e.g., gamma voltages GV1 to GV2) M A gamma voltage SGV can be selected from among the selected time-division gamma voltage signals STDGVS. For example, when N is 10 and M is 4, the time-division gamma voltage selection block 180 can select from 16 gamma voltages (e.g., gamma voltages GV1 to GV2) represented by the selected time-division gamma voltage signal STDGVS based on the lower 4 bits of the pixel data PDAT in each channel CH. 4 Select a gamma voltage SGV from among them.

[0072] In some embodiments, such as Figure 13 As illustrated, the time-division gamma voltage selection block 180 may include multiple switch signal generators 182 corresponding to multiple channels CH, and multiple time-division gamma voltage selection switches TDSW corresponding to multiple channels CH. That is, the number of switch signal generators 182 and the number of time-division gamma voltage selection switches TDSW can correspond to the number of channels CH. The switch signal generator 182 in each channel CH can operate at 2... MDuring the time division corresponding to the lower M bits of the pixel data PDAT within a time division, a time-division switching signal TDSS with an effective level (e.g., high level) is generated. For example, the switching signal generator 182 can receive a signal with a valid level (e.g., high level) from the M clock generator 161 or another clock generator during a horizontal time 1H. M The M clock signal MCLK can be used to calculate the clock of the M clock signal MCLK, and when the number of counted clocks corresponds to the value of the lower M bits of the pixel data PDAT, a time-division switching signal TDSS with an effective level can be generated. Figure 14 In the example shown in the diagram, where M is 3, a horizontal time 1H is divided into 8 sub-times, and the lower 3 bits of the pixel data PDAT are 5, the switch signal generator 182 can generate a time-division switching signal TDSS with an active level during the fifth sub-time of the 8 sub-times in a horizontal time 1H (e.g., from time point 4H / 8 to time point 5H / 8). The time-division gamma voltage selection switch TDSW can respond to the time-division switching signal TDSS with an active level in 2... M A gamma voltage (e.g., gamma voltages GV1 to GV2) M Select a gamma voltage SGV from the options. Figure 14 In the example shown in the diagram, the selected time-division gamma voltage signal STDGVS represents the first gamma voltage GV1 to the eighth gamma voltage GV8 in the eight time divisions, and the time-division switch signal TDSS has an active level during the fifth division time (e.g., from the time point 4H / 8 to the time point 5H / 8) in the eight time divisions. The time-division gamma voltage selection switch TDSW can select the fifth gamma voltage GV5 from the first gamma voltage GV1 to the eighth gamma voltage GV8 during the fifth division time.

[0073] Refer again Figure 1 The output buffer block 190 can receive the selected gamma voltage SGV from each channel CH from the time-division gamma voltage selection block 180, and can output the selected gamma voltage SGV as the data voltage VD in each channel CH. In some embodiments, the output buffer block 190 may include multiple output buffers corresponding to multiple channels CH respectively.

[0074] As described above, the data driver 100 can use the second data module 170 to select 2 based on the high NM bits of the pixel data PDAT in each channel CH. N-M The time-division gamma voltage signals TDGVS1 to TDGVS2 N-MOne of them, and can use the first number module 160 and the time-division gamma voltage selection block 180 to select 2 based on the low M bits of the pixel data PDAT in each channel CH. M A gamma voltage (e.g., gamma voltages GV1 to GV2) M The selected time-division gamma voltage signal STDGVS is represented in the data driver 100. Therefore, the size and power consumption of the data driver 100 can be reduced. Furthermore, in the data driver 100, each time-division gamma voltage signal STDGVS (e.g., the first time-division gamma voltage signal STDGVS1) can be transmitted to multiple channels CH via K time-division gamma voltage lines STDGVL, and each time-division gamma voltage line STDGVL can be coupled only to the corresponding portion of the multiple channels CH. Therefore, the delay (e.g., RC delay) of each time-division gamma voltage signal STDGVS (e.g., the first time-division gamma voltage signal STDGVS1) can be reduced, and the time-division gamma voltage signal STDGVS (e.g., the first time-division gamma voltage signal STDGVS1) can be accurately transmitted to the multiple channels CH.

[0075] Figure 15 This is a block diagram of a display device including a data driver according to an embodiment. Figure 16 This is a circuit diagram of pixels included in a display device according to an embodiment, and Figure 17 This is a circuit diagram of another example of a pixel included in a display device according to an embodiment.

[0076] Reference Figure 15 The display device 400 may include a display panel 410 containing a plurality of pixels PX, a scan driver 420 that provides a scan signal SCAN to the plurality of pixels PX, a data driver 430 that provides a data voltage VD to the plurality of pixels PX, and a controller 440 that controls the scan driver 420 and the data driver 430.

[0077] Display panel 410 may include scan lines, data lines, and a plurality of pixels PX coupled to the scan lines and data lines. In some embodiments, display panel 410 may be an OLED display panel. In this case, each pixel PX may include at least two transistors, at least one capacitor, and an organic light-emitting diode (OLED). (See reference...) Figure 16Each pixel PX may include a switching transistor PT2 that transmits a data voltage VD in response to a scan signal SCAN, a storage capacitor CST that stores the data voltage VD transmitted by the switching transistor PT2, a driving transistor PT1 that provides a driving current for a line from a first power supply voltage ELVDD to a second power supply voltage ELVSS based on the data voltage VD stored in the storage capacitor CST, and an organic light-emitting diode EL that emits light based on the driving current provided by the driving transistor PT1. In some embodiments, such as Figure 16 As illustrated in the diagram, a PMOS transistor can be used to implement the driving transistor PT1 and the switching transistor PT2. In other embodiments, such as... Figure 17 As illustrated in the diagram, NMOS transistors can be used to implement the driving transistor NT1 and the switching transistor NT2. In yet another embodiment, each pixel PX may include at least one PMOS transistor and at least one NMOS transistor. In other embodiments, the display panel 410 may be a liquid crystal display (LCD) panel. In this case, each pixel PX may include a switching transistor and a liquid crystal capacitor coupled to the switching transistor. However, the display panel 410 is not limited to OLED panels and LCD panels, and the display panel 410 may be any suitable display panel for displaying images.

[0078] The scan driver 420 can generate a scan signal SCAN based on a scan control signal SCTRL received from the controller 440, and can sequentially provide the scan signal SCAN to multiple pixels PX line by line via scan lines. In some embodiments, the scan control signal SCTRL may include, but is not limited to, a scan start signal (e.g., Figure 1 The start signal STS), scan clock signal (e.g., Figure 1 The clock signal CLK, etc. In some embodiments, the scan driver 420 may be integrated or formed in the peripheral portion of the display panel 410. In other embodiments, the scan driver 420 may be implemented as an integrated circuit (IC).

[0079] The data driver 430 can generate a data voltage VD based on the output image data ODAT (or pixel data PDAT) received from the controller 440 and the data control signal DCTRL, and can provide the data voltage VD to multiple pixels PX via data lines. In some embodiments, the data control signal DCTRL may include, but is not limited to, […]. Figure 1The start signal STS, clock signal CLK, and load signal LOAD are included. In some embodiments, the data driver 430 and controller 440 can be implemented as a single integrated circuit, referred to as a timing controller embedded data driver (TED). In other embodiments, the data driver 430 and controller 440 can be implemented as separate integrated circuits.

[0080] In some embodiments, the data drive 430 may be Figure 1 Data driver 100. Data driver 430 can use a second data module 170 to select 2 based on the high NM bits of the pixel data PDAT in each channel CH. N-M One of the time-division gamma voltage signals TDGVS, and can be selected using the first number module 160 and the time-division gamma voltage selection block 180 based on the low M bits of the pixel data PDAT in each channel CH. M One of the gamma voltages is represented by the selected time-division gamma voltage signal STDGVS. Therefore, the size and power consumption of the data driver 430 can be reduced. Furthermore, in the data driver 430, each time-division gamma voltage signal STDGVS can be transmitted to multiple channels CH via K time-division gamma voltage lines STDGVL, and each time-division gamma voltage line STDGVL can be coupled only to the corresponding portion of the multiple channels CH. Therefore, the delay (e.g., RC delay) of each time-division gamma voltage signal STDGVS can be reduced, and the time-division gamma voltage signal STDGVS can be accurately transmitted to the multiple channels CH.

[0081] Controller 440 (e.g., a timing controller (TCON)) can receive input image data IDAT and control signals CTRL from an external host (e.g., a graphics processing unit (GPU), graphics card, etc.). For example, the input image data IDAT can be, but is not limited to, RGB image data including, but not limited to, red, green, and blue image data. Furthermore, the control signal CTRL can include, but is not limited to, a data enable signal, a master clock signal, etc. Controller 440 can generate output image data ODAT, a data control signal DCTRL, and a scan control signal SCTRL based on the input image data IDAT and the control signal CTRL. Controller 440 can control the operation of scan driver 420 by providing the scan control signal SCTRL to scan driver 420, and can control the operation of data driver 430 by providing the output image data ODAT and the data control signal DCTRL to data driver 430.

[0082] As described above, in the display device 400 according to the embodiment, the data driver 430 can use the second data module 170 to perform an NM-bit gamma voltage selection operation based on the high NM bits of the pixel data PDAT in a spatial partitioning scheme, and can use the first data module 160 and the time-division gamma voltage selection block 180 to perform an M-bit gamma voltage selection operation based on the low M bits of the pixel data PDAT in a time-division scheme. Therefore, the size and power consumption of the data driver 430 can be reduced. Furthermore, in the data driver 430, each time-division gamma voltage signal TDGVS can be transmitted to multiple channels CH via K time-division gamma voltage lines TDGVL. Therefore, the delay of each time-division gamma voltage signal TDGVS can be reduced, and the time-division gamma voltage signal TDGVS can be accurately transmitted to multiple channels CH.

[0083] Figure 18 This is a block diagram of an electronic device including a display device according to an embodiment.

[0084] Reference Figure 18 Electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. Electronic device 1100 may further include multiple ports for communicating with various peripheral devices, including but not limited to video cards, sound cards, memory cards, universal serial bus (USB) devices, and other electronic devices.

[0085] Processor 1110 can perform various computing functions or tasks. Processor 1110 can be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. Processor 1110 can be coupled to other components of electronic device 1100 via address bus, control bus, data bus, etc. Furthermore, in some embodiments, processor 1110 can be further coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0086] The memory device 1120 can store data for operating the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

[0087] Storage device 1130 may be a solid-state drive (SSD), hard disk drive (HDD), CD-ROM, etc. I / O device 1140 may be an input device such as a keyboard, keypad, mouse, touchscreen, etc., and an output device such as a printer, speaker, etc. Power supply 1150 provides power for operating electronic device 1100. Display device 1160 may be coupled to other components via a bus or other communication link.

[0088] The display device 1160 may be Figure 15 The display device 400. The display device 1160 includes a data driver that uses a second data module 170 to perform an NM-bit gamma voltage selection operation based on the high NM bits of the pixel data PDAT in a spatial division scheme, and can use a first data module 160 and a time-division gamma voltage selection block 180 to perform an M-bit gamma voltage selection operation based on the low M bits of the pixel data PDAT in a time-division scheme. Therefore, the size and power consumption of the display device 1160 can be reduced. Furthermore, in the display device 1160, each time-division gamma voltage signal TDGVS can be transmitted to multiple channels CH via K time-division gamma voltage lines TDGVL. Therefore, the delay of each time-division gamma voltage signal TDGVS can be reduced, and the time-division gamma voltage signal TDGVS can be accurately transmitted to multiple channels CH.

[0089] According to an embodiment, the electronic device 1100 may be any electronic device including the display device 1160, such as a digital television, a three-dimensional (3D) television, a personal computer (PC), a home appliance, a laptop computer, a mobile phone, a smartphone, a tablet computer, a wearable device, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, etc.

[0090] The foregoing is illustrative of embodiments of this disclosure and should not be construed as limiting the embodiments of this disclosure. Although some embodiments have been described, those skilled in the art will readily understand that variations and / or modifications may be made in the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, such variations and / or modifications are intended to be included within the scope of the inventive concept of this disclosure, including the claims. It should therefore be understood that the foregoing is illustrative of various embodiments and should not be construed as limiting to the specific embodiments disclosed, and variations and / or modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of this disclosure, including the appended claims.

Claims

1. A data driver that outputs multiple data voltages to multiple pixels through multiple channels, the data driver comprising: The gamma voltage generator is configured to generate 2 N N gamma voltages, where N is an integer greater than 1, and N corresponds to the number of data bits for each pixel data in a plurality of pixel data received by the data driver; The first number module is configured to store the 2 N Each gamma voltage component is composed of 2 N-M A set of gamma voltages, making the 2 N-M Each of the 2 gamma voltage groups includes the 2 N 2 out of 1 gamma voltage M A gamma voltage, where M is an integer greater than 0 and less than N, and the first number module is configured to generate gamma voltages respectively with respect to the 2 N-M The two corresponding gamma voltage groups N-M The 2 time-division gamma voltage signal, N-M Each time-division gamma voltage signal in the 2 time-division gamma voltage signals is represented by dividing a horizontal time segment. M One gamma voltage; 2 N-M A time-division gamma voltage line group is used to transmit the 2 N-M The 2 time-division gamma voltage signal, N-M Each time-division gamma voltage line group in the time-division gamma voltage line group includes K time-division gamma voltage lines, where K is greater than 1 and less than or equal to the number of the plurality of channels; The second number module is configured to pass through the 2 N-M The time-division gamma voltage line group receives the 2 N-M A time-division gamma voltage signal, and based on the high NM bits of the N bits of the corresponding pixel data in each of the multiple channels of the multiple pixel data, in the 2 N-M Select a time-division gamma voltage signal from among the time-division gamma voltage signals; A time-division gamma voltage selection block is configured to select a pixel based on the lower M bits of the N bits of a corresponding pixel data in each of the plurality of channels of the plurality of pixel data, in the 2 M Select the gamma voltage represented by the time-division gamma voltage signal selected by the second data module from among the gamma voltages; as well as The output buffer is configured to output the gamma voltage of each of the plurality of channels as the data voltage among the plurality of data voltages. The plurality of channels includes K*L channels, where L is a positive integer. Wherein, the K*L channels are divided into K channel groups, such that the K*I+J-th channel of the K*L channels is divided into the J-th channel group of the K channel groups, where I is an integer greater than or equal to zero and less than L, and J is an integer greater than zero and less than or equal to K; or such that L consecutive channels of the K*L channels are divided into channel groups within the K channel groups, and The K time-division gamma voltage lines are respectively coupled to the K channel groups, such that each of the K time-division gamma voltage lines is coupled to L channels in the K*L channels or the L consecutive channels.

2. The data driver according to claim 1, wherein, The K time-division gamma voltage lines are four time-division gamma voltage lines. The plurality of channels includes 4*L channels, where L is a positive integer. The 4*L channels are divided into 4 channel groups, such that the 4*1+Jth channel of the 4*L channels is divided into the Jth channel group of the 4 channel groups, where I is an integer greater than or equal to zero and less than L, and J is an integer greater than zero and less than or equal to 4. The four time-division gamma voltage lines are respectively coupled to the four channel groups, such that each of the four time-division gamma voltage lines is coupled to L of the 4*L channels.

3. The data driver according to claim 1, wherein, The K time-division gamma voltage lines are four time-division gamma voltage lines. The plurality of channels includes 4*L channels, where L is a positive integer. Specifically, the first to the Lth channel of the 4*L channels are grouped into a first channel group; the (L+1)th to the 2Lth channel of the 4*L channels are grouped into a second channel group; the (2L+1)th to the 3Lth channel of the 4*L channels are grouped into a third channel group; and the (3L+1)th to the 4Lth channel of the 4*L channels are grouped into a fourth channel group. The four time-division gamma voltage lines are respectively coupled to the first channel group, the second channel group, the third channel group, and the fourth channel group, such that each of the four time-division gamma voltage lines is coupled to L of the 4*L channels.

4. The data driver according to claim 1, wherein, The horizontal time is equally divided into 2 segments with the same time interval. M Divide the time into segments, and Each time-division gamma voltage signal is represented in the 2 M The 2 having nonlinear voltage intervals in each time division M One gamma voltage.

5. The data driver according to claim 1, wherein, The horizontal time is equally divided into 2 segments with the same time interval. M Divide the time into segments, and Each time-division gamma voltage signal is represented in the 2 M The 2 having the same voltage interval in each time division M One gamma voltage.

6. The data driver according to claim 1, wherein, The horizontal time is divided into 2 different time periods. M Divide the time into segments, and Each time-division gamma voltage signal is represented in the 2 M The 2 having the same voltage interval in each time division M One gamma voltage.

7. The data driver according to claim 1, wherein, The gamma voltage generator includes: 2 N +1 resistor, connected in series between the high-voltage first line and the low-voltage second line, and configured to generate the 2 by voltage division between the high voltage and the low voltage. N One gamma voltage.

8. The data driver according to claim 1, wherein, The 2 generated by the gamma voltage generator N The gamma voltage gradually decreases from the first gamma voltage to the second. N Gamma voltage.

9. The data driver according to claim 1, wherein, The 2 generated by the gamma voltage generator N The gamma voltage gradually increases from the first gamma voltage to the second. N Gamma voltage.

10. The data driver according to claim 1, wherein, The 2 N The first voltage interval between the gamma voltages in the low grayscale region is less than the 2. N The second voltage interval between gamma voltages in the high grayscale region.

11. The data driver according to claim 1, wherein, The first data module includes: A clock generator is configured to generate a clock with 2 during the said one horizontal time period. M A clock signal for each clock cycle; A bit counter is configured to generate a representation of 1 to 2 in response to the clock signal. M The counting signal; and 2 N-M An M-bit analog-to-digital converter is configured to output the 2 N-M The 2 time-division gamma voltage signal, N-M Each of the M-bit analog-to-digital converters is configured to sequentially output the 2 in response to the counting signal. M The gamma voltage is used as the 2 N-M The time-division gamma voltage signal in the time-division gamma voltage signal.

12. The data driver according to claim 1, wherein, The second data module includes: Multiple NM bit-to-analog converters, each corresponding to one of the multiple channels, are configured to, based on the high NM bits of a corresponding pixel data in the multiple pixel data, in the 2 N-M The time-division gamma voltage signal is selected from the time-division gamma voltage signals.

13. The data driver according to claim 12, wherein, Each of the plurality of NM bit-to-analog converters includes: The decoder is configured to generate 2 based on the high NM bits of the corresponding pixel data from the plurality of pixel data. N-M A switch signal; and 2 N-M A switch is configured to respond to the 2 N-M The two switch signals are selectively output. N-M A time-division gamma voltage signal.

14. The data driver according to claim 1, wherein, The time-division gamma voltage selection block includes: Multiple switch signal generators, each corresponding to one of the multiple channels, are configured to operate at 2... M During the time division period corresponding to the lower M bits of the corresponding pixel data in the plurality of pixel data, a time-division switching signal with an effective level is generated; and Multiple time-division gamma voltage selection switches, each corresponding to one of the multiple channels, are configured to respond to a time-division switching signal having the effective level in the 2 M The gamma voltage is selected from the gamma voltages.

15. The data driver of claim 1, further comprising: The shift register block is configured to sequentially generate sampled signals in response to a start signal and a clock signal; A sampling latch block is configured to sequentially sample the plurality of pixel data in response to the sampling signal; as well as The holding latch block is configured to store the plurality of pixel data sampled by the sampling latch block in response to a load signal.

16. The data driver of claim 15, wherein, The high NM bits of the N bits of each pixel data in the plurality of pixel data output from the holding latch block are provided to the second data module, and Specifically, the lower M bits of the N bits of each pixel data in the plurality of pixel data output from the holding latch block are provided to the time-division gamma voltage selection block.

17. A display device, comprising: The display panel includes multiple pixels; Data driver according to any one of claims 1 to 16; as well as The controller is configured to provide the plurality of pixel data to the data driver.

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