Flash memory and method of controlling a pass voltage

Abstract

This invention discloses a flash memory and a method for controlling through voltage. The flash memory includes multiple memory cell strings and a through voltage generator. Each memory cell string has multiple memory cells. The through voltage generator provides through voltage to multiple word lines of multiple unselected memory cells in a selected memory cell string. During a read operation, the through voltage generator causes the through voltage to rise from a first voltage at a first time point and rise to a second voltage at a second time point. The second voltage is less than a target voltage multiplied by a preset ratio. The first time point is earlier than the start time point of the bit line voltage received by the selected memory cell string, and the second time point occurs at the start time point of the bit line voltage.

Description

Technical Field

[0001] This invention relates to a flash memory and a method of operating the same, and more particularly to a NAND flash memory and a method for controlling the voltage. Background Technology

[0002] Flash memory is widely used in modern electronic devices as a data storage medium. With advancements in integrated circuit technology, memory density has been significantly increased to enhance data storage capacity. To reduce product costs, the number of read operations also increases with increasing bit density and the number of storage cells.

[0003] Regardless, read interference can occur when performing a high number of read operations on a single page of flash memory. Multiple read operations may fail when the digital value at a specific location changes from 1 to 0. This read interference phenomenon is a significant factor affecting the reliability of flash memory. Summary of the Invention

[0004] This invention provides a flash memory and its operation method, which effectively reduces the probability of read interference.

[0005] The flash memory of the present invention includes a plurality of memory cell strings and a voltage generator. Each memory cell string has a plurality of memory cells. The voltage generator is coupled to the memory cell string to provide a voltage through multiple word lines to a plurality of unselected memory cells in a selected memory cell string. During a read operation, the voltage generator causes the voltage through to rise from a first voltage at a first time point and rise to a second voltage at a second time point. The second voltage is less than a target voltage multiplied by a preset ratio. The first time point is earlier than the start time point of the bit line voltage received by the selected memory cell string, and the second time point occurs at the start time point of the bit line voltage.

[0006] The flash memory operation method of the present invention includes: providing a pass voltage to multiple word lines of multiple unselected memory cells of a selected memory cell string; during a read operation, causing the pass voltage to rise from a first voltage at a first time point and rise to a second voltage at a second time point, wherein the second voltage is less than a target voltage multiplied by a preset ratio, the first time point being earlier than the start time point of a bit line voltage received by the selected memory cell string, and the second time point occurring at the start time point of the bit line voltage.

[0007] Based on the above, when performing a read operation on a memory cell, the present invention gradually increases the voltage to a second voltage that is less than the target voltage multiplied by a preset ratio before the start time of the bit line voltage. This can effectively reduce the disturbance phenomenon caused by the voltage increase on the bit line and reduce the probability of read interference. Attached Figure Description

[0008] Figure 1 A schematic diagram illustrating a flash memory according to an embodiment of the present invention is shown.

[0009] Figure 2 A voltage waveform diagram of a flash memory according to an embodiment of the present invention is shown.

[0010] Figure 3 A diagram showing the comparison between the selected memory cell string and the voltage waveform in an embodiment of the present invention is provided.

[0011] Figure 4 A waveform diagram of the voltage through another embodiment of the present invention is shown.

[0012] Figure 5A as well as Figure 5B Schematic diagrams illustrating different embodiments of the voltage generator according to the present invention are shown.

[0013] Figure 6 A schematic diagram illustrating another embodiment of the present invention via a voltage generator is shown.

[0014] Figure 7 A schematic diagram illustrating another embodiment of the present invention via a voltage generator is shown.

[0015] Figure 8 A flowchart illustrating the operation method of a flash memory according to an embodiment of the present invention is shown.

[0016] [Symbol Explanation]

[0017] 100 flash memory

[0018] 110: Through voltage generator

[0019] 510, 520, 600, 700: via voltage generator

[0020] 511, 521: Target voltage generator

[0021] 512, 522: Boost circuit

[0022] 513, 523: Switches

[0023] 524: Frequency Generator

[0024] 525: Frequency Regulator

[0025] 610: Digital-to-Analog Converter

[0026] 711: Candidate Voltage Generator

[0027] 712: Voltage Selector

[0028] CLK: Frequency signal

[0029] CLK0: Reference frequency signal

[0030] CS: Adjust signal

[0031] DAC[N:0]: Target voltage code

[0032] dL1: Delay time

[0033] En: Enable signal

[0034] MC1~MC m Storage unit

[0035] MS1: String of storage cells

[0036] RA1: Preset ratio

[0037] S810, S820: Control steps via voltage

[0038] SR1~SR4: Pull-up curve

[0039] SSL, GSL: Select Signal

[0040] SV1~SVN: Candidate voltages

[0041] SW1, SW2: Switches

[0042] TP1, TP1', TP2, TP3: Time points

[0043] TSEN: Sensing Time Interval

[0044] V1, V2, V3: Voltage

[0045] VBL: Bit line voltage

[0046] VPASSR: Through voltage

[0047] VSR: Control Voltage

[0048] VTG: Target Voltage

[0049] WLn: Word line voltage Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0051] Please refer to Figure 1 , Figure 1 A schematic diagram illustrating a flash memory according to an embodiment of the present invention is shown. The flash memory 100 includes a voltage generator 110 and a plurality of... Figure 1 The illustrated memory cell string MS1. To simplify the explanation, Figure 1Only a single memory cell string MS1 is drawn. A voltage generator 110 is used to generate a pass voltage VPASSR. During the read operation of the voltage generator 110, the pass voltage VPASSR is provided to multiple unselected memory cells (memory cells MC1 to MC2) of the selected memory cell string (taking memory cell string MS1 as an example). n-1 and MC m Multiple word lines. Select memory cell MC. n The word line receives the word line voltage WL corresponding to the read operation. n Additionally, the storage cell string MS1 includes switches SW1 and SW2 to be coupled to selection signals SSL and GSL, respectively.

[0052] Please refer to this simultaneously. Figure 1 as well as Figure 2 ,in Figure 2 A voltage waveform diagram of the flash memory according to an embodiment of the present invention is shown. During a read operation, the voltage generator 110 causes the generated pass voltage VPASSR to rise from the first voltage V1 at a first time point TP1, and then pulls the pass voltage VPASSR up to the second voltage V2 at a second time point TP2. The second voltage V2 is less than the target voltage VTG multiplied by a preset ratio RA1.

[0053] In this embodiment, the first time point TP1 and the selected storage unit MC n Received word line voltage WL n The startup time points are the same. The second time point TP2 is the same as the startup time point of the bit line voltage VBL received by the bit line corresponding to the selected memory cell string MS1. That is to say, the word line voltage WL... n At the first time point, TP1 is started to rise, while the bit line voltage VBL is started to rise at the second time point, TP2, which is after the first time point TP1.

[0054] Incidentally, the word line voltage WL that enables TP1 at the first time point n The pull-up action is used to select the memory cell MC. n The word line performs a pre-charge operation. At the second time point TP2 after the bit line voltage VBL is activated, the memory cell MC is selected. n The data is sensed within the sensing time interval TSEN. During the sensing time interval TSEN, the voltage generator 110 can pull up the through voltage VPASR to the target voltage VTG.

[0055] The aforementioned preset ratio RA1 can be determined by the designer based on the actual design of the flash memory. In this embodiment of the invention, the preset ratio RA1 can be 90%.

[0056] In this embodiment of the invention, the flash memory 100 can be a NAND flash memory. In terms of hardware architecture, the flash memory 100 can be a two-dimensional or three-dimensional flash memory. Furthermore, the flash memory 100 can provide single-level cell (SLC), multiple-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), or a combination thereof.

[0057] Figure 3 A comparison diagram of selected memory cell strings and voltage waveforms (via voltage VPASS) is shown in the prior art, comparing them with those of the present invention. In the prior art, the via voltage VPASS (as shown by the dashed line portion of the via voltage VPASS waveform in the diagram) has a high rise rate and is pulled up to the target voltage VTG before the sensing time interval TSEN. The via voltage generator of the present invention effectively reduces the impact of the via voltage VPASSR on the memory cell string channel and reduces the jitter of the bit line voltage VBL caused by the rise of the via voltage VPASSR by slowing down the rise rate of the via voltage VPASSR (as shown by the solid line portion of the via voltage VPASSR waveform in the diagram) and does not pull the via voltage VPASSR to the target voltage VTG before the sensing time interval TSEN. This reduces the probability of read interference.

[0058] Please refer to Figure 4 , Figure 4 The diagram illustrates the voltage waveforms of other embodiments of the present invention. In these embodiments, the voltage VPASR can be raised in various ways during the read operation. Figure 4 The stretching curves SR1 to SR4 in the figure correspond to the four implementation methods of the present invention, respectively.

[0059] In the first embodiment, the word line voltage WL is selected by a voltage generator corresponding to the rise curve SR1 of the voltage VPASSR. n The start-up time point is taken as the first time point TP1, and at the first time point TP1, the through voltage VPASSR is pulled up from the first voltage V1. At the second time point TP2 (the start-up time point of the bit line voltage VBL), the voltage generator makes the through voltage VPASSR (the second voltage) less than the product of the target voltage VTG and the preset ratio RA1.

[0060] In the second embodiment, the rise curve SR2 of the voltage VPASSR (as shown by the dashed line portion of the VPASSR waveform in the icon) can be divided into two segments. The word line voltage WL is selected via a voltage generator.n The startup time is designated as the first time point TP1. At TP1, the voltage V1 is initially increased, and at the third time point TP3, the voltage VPASR is increased to the third voltage V3. Then, at the third time point TP3, the voltage generator causes the voltage VPASR to increase from the third voltage V3, and at the second time point TP2, the voltage VPASR is increased to the second voltage V2. The third voltage V3 is greater than the first voltage V1 and less than the second voltage V2. The third time point TP3 is later than the first time point TP1 and earlier than the second time point TP2.

[0061] It is worth mentioning that the voltage generator can boost the voltage VPASR from the first time point TP1 to the third time point TP3 using the first driving capability, and from the third time point TP3 to the second time point TP2 using the second driving capability. The first driving capability and the second driving capability are different.

[0062] In addition, in the third embodiment, the word line voltage WL is also set by a voltage generator. n The start-up time is taken as the first time point TP1, and the through voltage VPASSR is started to rise at the first time point TP1. According to the rise curve SR3, the through voltage generator can rise the through voltage VPASSR for a period of time and then maintain the through voltage VPASSR at a constant value. And the voltage value at the second time point TP2 is less than the through voltage VPASSR at the second time point TP2 corresponding to the above-mentioned multiple rise curves SR1, SR2, and of course, it must also be less than the product of the target voltage VTG and the preset ratio RA1.

[0063] Furthermore, in the fourth embodiment, the word line voltage WL is not set by the voltage generator. n The start-up time point is used as the start-up time point for raising the voltage VPASR. The first time point TP1' is changed to be on word line WL. n The time point after the start-up time point of the word line voltage VBL, and before the start-up time point of the bit line voltage VBL (second time point TP2), is the first time point TP1'. Correspondingly, the pull-up curve SR4 starts to rise from the first voltage V1 at the first time point TP1', and is pulled up to a voltage value less than the product of the target voltage VTG and the preset ratio RA1 at the second time point TP2. Here, the first time point TP1' and the word line voltage VBL... n There is a delay time dL1 between the start time points.

[0064] Incidentally, the aforementioned delay time can be set between 0 and 71 microseconds. Furthermore, the time from the start-up time of the memory cell string after the bit line voltage VBL (time point TP2) to entering the sensing zone is 0 to 36 microseconds. Of course, the above time range can be adjusted according to the process technology, operating voltage, or other variables used in the memory device. The above description is merely illustrative and is not intended to limit the scope of protection of this invention.

[0065] As can be seen from the above description, in the embodiments of the present invention, the voltage VPASSR can be pulled up in different ways. There are no specific limitations on the waveform of the voltage VPASSR pull-up process. The key point is that the voltage VPASSR needs to be pulled up to a value less than the product of the target voltage VTG and the preset ratio RA1 at the start time of the bit line voltage VBL (second time point TP2), thereby reducing the interference caused to the bit line voltage VBL by the pull-up process.

[0066] Please refer to the following: Figure 5A as well as Figure 5B , Figure 5A as well as Figure 5B Schematic diagrams illustrating different embodiments of the voltage generator according to the present invention are shown. Figure 5A In this embodiment, the voltage generator 510 includes a target voltage generator 511, a boost circuit 512, and a switch 513. The target voltage generator 511 is used to generate a target voltage VTG. In this embodiment, the target voltage generator 511 can determine the voltage value of the target voltage VTG based on the target voltage code DAC[N: 0], wherein the number of bits in the target voltage code can be 1 (N=0) or more (N>0), and the target voltage generator 511 can be a digital-to-analog converter.

[0067] The boost circuit 512 receives a frequency signal CLK and an enable signal En. The boost circuit 512 can be activated according to the enable signal En and, based on the frequency signal CLK, performs a pumping-up operation against a reference voltage to generate a control voltage VSR. In this embodiment, the boost circuit 512 can be a charge pump circuit.

[0068] Switch 513 can be a transistor switch. One end of switch 513 receives the target voltage VTG, the control terminal of switch 513 receives the control voltage VSR, and the other end of switch 513 provides the pass voltage VPASSR. Note that switch 513 can act as a clamp. When the control voltage VSR is less than the target voltage VTG plus the threshold voltage VTH of switch 513, the pass voltage VPASSR is equal to the control voltage VSR minus the threshold voltage VTH of switch 513. When the control voltage VSR is greater than or equal to the sum of the target voltage VTG and the threshold voltage VTH of switch 513, the pass voltage VPASSR is equal to the target voltage VTG.

[0069] The voltage value of VPASSR can be adjusted using the equivalent resistance provided by switch 513. The voltage value of VPASSR is negatively correlated with the equivalent resistance of switch 513. When the equivalent resistance of switch 513 is substantially equal to 0, the voltage VPASSR can be equal to the target voltage VTG.

[0070] As can be seen from the above description, when the flash memory performs a read operation, the boost circuit 512 can increase the voltage value of the control voltage VSR over time, thereby controlling the equivalent resistance provided by the switch 513, so that the through voltage VPASSR can gradually increase over time.

[0071] exist Figure 5B In this configuration, voltage generator 520 includes a target voltage generator 521, a boost circuit 522, a switch 523, a frequency adjuster 525, and a frequency generator 524. The target voltage generator 511 is used to generate the target voltage VTG. Figure 5A In different embodiments, the frequency of the frequency signal CLK received by the boost circuit 522 can be adjusted. Specifically, the frequency generator 524 generates a reference frequency signal CLK0, and the frequency adjuster 525 generates the frequency signal CLK by adjusting the frequency of the reference frequency signal CLK0 according to the adjustment signal CS.

[0072] In this embodiment, the frequency adjuster 525 can dynamically change the frequency of the frequency signal CLK. For example, the frequency adjuster 525 can perform a frequency division operation on the reference frequency signal CLK0 to generate the frequency signal CLK, wherein the frequency adjuster 525 can generate the divisor of the frequency division signal based on the adjustment signal CS. Here, the adjustment signal CS can be dynamically changed.

[0073] By dynamically adjusting the frequency of the frequency signal CLK, the increasing process of the control voltage VSR can be carried out in a linear or non-linear manner, and the voltage VPASSR can be pulled up in a one-stage or multi-stage manner.

[0074] On the other hand, the target voltage code DAC[N:0] received by the target voltage generator 522 can also be dynamically adjusted in sequence during the voltage VPASSR process, thereby adjusting the rise rate of the voltage VPASSR.

[0075] Please refer to the following: Figure 6 , Figure 6 A schematic diagram illustrating another embodiment of the present invention via a voltage generator is shown. Figure 6 In this embodiment, the voltage generator 600 includes a digital-to-analog converter 610. The digital-to-analog converter 610 receives a voltage control code DAC[N:0] and converts the voltage control code DAC[N:0] to generate an output voltage as the pass voltage VPASSR. Note that the voltage control code DAC[N:0] undergoes multiple changes in a timing sequence. Specifically, this is explained in relation to the present invention. Figure 2 In this embodiment, multiple sub-time points can be divided between the first time point TP1 and the second time point TP2. The voltage control code DAC[N:0] can be incremented sequentially corresponding to the multiple time points mentioned above. In this way, the digital-to-analog converter 610 can increase the voltage value of the through voltage VPASSR at multiple time points, corresponding to the incrementing voltage control code DAC[N:0].

[0076] In this embodiment of the invention, the increment of the voltage control code DAC[N:0] can be linear or non-linear. The increment value of the voltage control code DAC[N:0] each time can be fixed or variable, without any specific limitation. Furthermore, the number of sub-time points can also be set by the designer, again without any fixed limitation.

[0077] Please refer to the following: Figure 7 , Figure 7 A schematic diagram illustrating another embodiment of the voltage generator of the present invention is shown. The voltage generator 700 includes a candidate voltage generator 711 and a voltage selector 712. The candidate voltage generator 711 can generate multiple candidate voltages SV1 to SVN with different voltage values. And corresponding to the present invention... Figure 2 In this embodiment, multiple sub-time points can be divided between the first time point TP1 and the second time point TP2. The voltage selector 712 then selects multiple candidate voltages SV1 to SVN for output at each of these sub-time points, generating a pass voltage VPASR. Taking candidate voltage SV1 < candidate voltage SV2 < ... < candidate voltage SVN as an example, the voltage selector 712 can sequentially select candidate voltages SV1, SV2, ..., SVN for output according to the timing sequence, thereby generating a pass voltage VPASR that is sequentially increased.

[0078] In this embodiment, the candidate voltage generator 711 can generate candidate voltages SV1 to SVN by performing a multi-segment voltage divider (using a voltage divider circuit well known to those skilled in the art) on a reference voltage. The voltage selector 712 can be implemented using a voltage selection circuit well known to those skilled in the art, without any specific limitations.

[0079] Please refer to Figure 8 , Figure 8 A flowchart illustrating a voltage control method according to an embodiment of the present invention is provided. In step S810, a voltage is provided to multiple word lines of multiple unselected memory cells in a selected memory cell string. In step S820, during a read operation, the voltage is increased from a first voltage at a first time point and then increased to a second voltage at a second time point. The second voltage is less than a target voltage multiplied by a preset ratio. The first time point is earlier than the start time point of the bit line voltage received by the selected memory cell string, and the second time point occurs at the start time point of the bit line voltage.

[0080] The implementation details of the above steps have been described in detail in the aforementioned embodiments and implementation methods, and will not be repeated here.

[0081] In summary, this invention reduces potential interference between the through voltage and the bit line voltage by adjusting the rise rate of the through voltage before the sensing time interval during flash memory read operations. This reduces read interference during read operations and lowers the probability of read errors.

[0082] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A flash memory, comprising: a plurality of memory cell strings, each of the memory cell strings having a plurality of memory cells; a pass voltage generator coupled to the memory cell strings to provide a pass voltage to a plurality of word lines of unselected memory cells of a selected memory cell string, wherein, during a read operation, the pass voltage generator raises the pass voltage from a first voltage at a first time point and raises the pass voltage to a second voltage at a second time point, wherein the second voltage is less than a target voltage multiplied by a preset ratio, the first time point is earlier than a start time point of a bit line voltage received by the selected memory cell string, and the second time point occurs after the start time point of the bit line voltage; during a sensing time interval after the second time point, the pass voltage generator pulls up the pass voltage to the target voltage; and the preset ratio is 90%.

2. The flash memory of claim 1, wherein the first time point occurs at a start time point of a word line voltage received by a selected memory cell, or the first time point is later than the start time point of the word line voltage and earlier than the start time point of the bit line voltage.

3. The flash memory of claim 1, wherein, during the read operation, the pass voltage generator pulls up the pass voltage to a third voltage at a third time point between the first time point and the second time point, wherein the third voltage is greater than the first voltage and less than the second voltage, the pass voltage generator provides a first driving capability between the first time point and the third time point, and provides a second driving capability between the third time point and the second time point, the first driving capability is different from the second driving capability.

4. The flash memory of claim 1, wherein the pass voltage generator comprises: a boost circuit receiving a frequency signal and generating a control voltage by performing a pumping operation with respect to a reference voltage according to the frequency signal; a target voltage generator to generate the target voltage; and a switch having a first terminal to receive the target voltage, the switch being controlled by the control voltage to provide an equivalent resistance and to provide the pass voltage at a second terminal.

5. The flash memory of claim 4, wherein the pass voltage generator further comprises: a frequency generator to generate a reference frequency signal; and a frequency adjuster to adjust a frequency of the reference frequency signal according to an adjustment signal to generate the frequency signal.

6. The flash memory of claim 4, wherein the target voltage generator is a digital-to-analog converter to receive a digital target voltage code and to convert the target voltage code to generate the target voltage.

7. The flash memory of claim 1, wherein the pass voltage generator sequentially provides a plurality of output voltages with increasing values at a plurality of sub-time points between the first time point and the second time point to generate the pass voltage.

8. The flash memory of claim 7, wherein the pass voltage generator comprises: a candidate voltage generator to generate the plurality of output voltages; and a voltage selector to sequentially select each of the output voltages as the pass voltage corresponding to each of the sub-time points. ​ ​ ​ 9. The flash memory of claim 7 wherein the pass voltage generator comprises: a digital-to-analog converter receiving a plurality of voltage control codes corresponding to the sub-time points in sequence and converting the voltage control codes in sequence to generate the output voltages.

10. The flash memory of claim 9 wherein the pass voltage generator further comprises: a control code generator coupled to the digital-to-analog converter to generate the output voltage control codes.

11. A method for controlling a pass voltage, comprising: providing a pass voltage generator to provide a pass voltage to a plurality of word lines of a plurality of unselected memory cells of a selected memory cell string; in a read operation, providing the pass voltage generator to ramp up the pass voltage from a first voltage at a first time point and to a second voltage at a second time point, wherein the second voltage is less than a target voltage multiplied by a preset ratio, the first time point is earlier than a start time point of a bit line voltage received by the selected memory cell string, and the second time point occurs after the start time point of the bit line voltage; and after a sensing time interval from the second time point, the pass voltage generator ramps up the pass voltage to the target voltage; wherein the preset ratio is 90%.

12. The method for controlling a pass voltage of claim 11, further comprising: causing the first time point to occur at a start time point of a word line voltage received by a selected memory cell, or causing the first time point to be earlier than the start time point of the word line voltage and later than the start time point of the bit line voltage.

13. The method for controlling a pass voltage of claim 11, further comprising: causing the pass voltage generator to provide a first driving capability to ramp up the pass voltage to a third voltage at a third time point between the first time point and the second time point; and causing the pass voltage generator to provide a second driving capability to ramp up the pass voltage to the second voltage between the third time point and the second time point.

14. The method for controlling a pass voltage of claim 11, wherein the step of providing the pass voltage generator to ramp up the pass voltage from the first voltage at the first time point and to the second voltage at the second time point comprises: generating a control voltage by performing a pumping action for a reference voltage according to a frequency signal; and causing a switch to provide an equivalent resistance according to the control voltage, and causing a target voltage to pass through the equivalent resistance of the switch to generate the pass voltage.

15. The method for controlling a pass voltage of claim 14, further comprising: generating the frequency signal according to an adjustment signal to adjust a frequency of a reference frequency signal.

16. The method for controlling a pass voltage of claim 11, wherein the step of providing the pass voltage generator to ramp up the pass voltage from the first voltage at the first time point and to the second voltage at the second time point comprises: providing a plurality of output voltages in sequence to generate the supply voltage at a plurality of sub-time points between the first time point and the second time point. ​ ​

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