Flip chip package with reduced bottom fill area

Abstract

A flip-chip package and a method for assembling a flip-chip package, comprising: positioning a bare die on a substrate and introducing an underfill material into a space between the bare die and the substrate, wherein a portion of the underfill material extends beyond the edge of the bare die and forms a fillet, the fillet at least partially surrounding the bare die. The underfill material is cured, and a portion of the fillet is removed to reduce the area of ​​the fillet.

Description

Technical Field

[0001] This disclosure relates to packaging for bare integrated circuit (IC) dies, particularly flip-chip packaging. In some embodiments, this disclosure includes methods for reducing the bottom fill area surrounding the flip-chip die. Background Technology

[0002] Integrated circuit (IC) dies can be packaged using different methods. For example, in a conventional wire bonding package, the die is mounted upright on a substrate (e.g., a printed circuit board (PCB)) with external circuitry, and leads are used to interconnect bonding pads on the die to the external circuitry on the substrate. In a flip-chip package, solder bumps are deposited on die bonding pads on the top side of the die. To connect the die to the external circuitry on the substrate, the die is "flipped" so that its top side faces down toward the substrate and is positioned such that the solder balls align with matching pads on the substrate. Solder reflow is performed to bond the solder bumps to the substrate pads.

[0003] A mismatch in the coefficients of thermal expansion between the bare core and the substrate can generate stress at the solder joint between them, potentially leading to fatigue and breakage in the connection. To enhance adhesion between the bare core and the substrate, an underfill material can be applied between them to improve adhesion and / or disperse thermal stress. The underfill material may comprise, for example, a resin (e.g., epoxy resin), which is applied as a flowable liquid between the bare core and the substrate and then (e.g., through a curing process) hardens. The underfill material can be injected into the space between the bare core and the substrate, for example, from one or more sides of the bare core.

[0004] Due to the flowable nature of the underfill material, a portion of it typically flows beyond the edge of the bare core onto the surrounding substrate. Upon hardening or curing, this excess underfill forms a fillet around the bare core, causing the underfill footprint on the substrate to typically extend beyond the footprint of the bare core itself. The area of ​​the substrate occupied by the underfill fillet is generally unusable for placing additional bare cores or other components and may be referred to herein as a “keep-out zone” or “KOZ.” Reducing the size of the KOZ is advantageous. Summary of the Invention

[0005] According to some embodiments, this disclosure provides a flip-chip package having a reduced underfill area. In some such embodiments, the reduced underfill area provides a larger area on the substrate available for other components (e.g., NAND dies or other flash memory chips), allowing more components to be attached to a given substrate. The reduced underfill area also allows other dies to be positioned closer to the flip-chip die. This capability can be particularly advantageous, for example, to increase package capacity or reduce package size.

[0006] In some embodiments, the flip-chip package according to this disclosure removes a portion of the bottom filler corner surrounding the IC die to reduce the area (KOZ) occupied by the filler corner on the substrate. In some embodiments, the bottom filler corner is truncated (e.g., laser-cut) after the underfill material has hardened or cured, and a portion of the bottom filler corner is removed to reclaim area on the substrate for placement of other components (e.g., NAND die or other chips). In some embodiments, the bottom filler corner is truncated at or near the edge of the solder mask on the substrate. In other embodiments, a release film is applied to the substrate, and a portion of the filler corner is formed on the release film. In some embodiments, the bottom filler corner is truncated at or near the edge of the release film, and the release film is removed from the substrate, thereby removing the remaining portion of the filler corner on the release film.

[0007] In some embodiments, a method for packaging an IC die includes: positioning the die on a surface of a substrate; introducing an underfill material into a space between the die and the substrate, wherein a portion of the underfill material extends beyond an edge of the die; curing the underfill material, wherein the portion of the underfill material extending beyond the edge of the die forms a filler corner, the filler corner at least partially surrounding the die; and removing a portion of the filler corner. In some embodiments, the method further includes applying a release film to the substrate prior to introducing and / or curing the underfill material, wherein the filler corner at least partially overlaps a portion of the release film. In some embodiments, the substrate includes a solder mask, and the release film is applied over the solder mask.

[0008] In other embodiments, the method includes cutting the filler corner. In some such embodiments, cutting the filler corner involves laser-cutting the filler corner at or near the edge of the release film. In other embodiments, cutting the filler corner involves dividing the filler corner into at least a first portion and a second portion, wherein the first portion of the filler corner overlaps that portion of the release film, and the second portion of the filler corner is adjacent to the IC bare die. In some embodiments, removing this segment of the filler corner involves removing the release film from the substrate together with the first portion of the filler corner. In some embodiments, removing this segment of the filler corner reduces the area of ​​the underfill material by, for example, at least 30%, at least 40%, or at least 50%. In some embodiments, the second portion of the filler corner includes a truncated surface that is flat or substantially flat. According to some embodiments, the truncated surface may be perpendicular to the surface of the substrate. In other embodiments, the truncated surface may be inclined to the surface of the substrate.

[0009] In some embodiments, the method according to this disclosure includes positioning at least one additional component (e.g., a NAND die or other memory chip) adjacent to the IC die on a substrate. In some such embodiments, the at least one additional component is positioned at least partially over the area of ​​a segment of the substrate with the filler removed.

[0010] In other embodiments, this disclosure provides an IC die package assembled using the methods described herein. In some embodiments, the IC die package includes a substrate, an IC die (e.g., a flip-chip die or “FC die”) positioned on a surface of the substrate, and an underfill material at least partially disposed between the IC die and the surface of the substrate, with a portion of the underfill material extending beyond the edge of the IC die to form a filler corner at least partially surrounding the IC die, wherein the filler corner includes a truncated portion. In some embodiments, the substrate includes a solder mask, and the filler corner includes a truncated surface at or near the edge of the solder mask. In some embodiments, the truncated surface is substantially perpendicular to the surface of the substrate.

[0011] In some embodiments, the IC die package includes at least one NAND die positioned on a solder mask. In some embodiments, the at least one NAND die is positioned near or adjacent to a cut-off surface of the filler. In other embodiments, the at least one NAND die is positioned less than 1000 μm from the IC die. Attached Figure Description

[0012] The foregoing overview and the following detailed description will be better understood when read in conjunction with the accompanying drawings. For the purpose of illustrating the invention, presently preferred embodiments are shown in the drawings, wherein the same reference numerals denote the same elements throughout. However, it should be understood that the invention may be embodied in different forms and therefore should not be construed as limited to the illustrated embodiments set forth herein. It should also be understood that the drawings may not be drawn to scale.

[0013] Figure 1A This is an illustration of a portion of a conventional flip-chip package having bare dies positioned on a substrate;

[0014] Figure 1B This occurs after an underfill material has been applied between the bare core and the substrate. Figure 1A A diagram of this part of the flip-chip package;

[0015] Figure 2A –2D is an illustration of the steps of packaging a flip chip die to manufacture a flip chip package with a reduced KOZ (Knockout Zone) according to certain embodiments of the present invention;

[0016] Figures 3A and 3B are illustrations comparing the KOZ distance between a conventional flip-chip package (Figure 3A) and a flip-chip package with a reduced bottom fill area according to an embodiment of the present invention (Figure 3B); and

[0017] Figures 4A and 4B are illustrations comparing the relative arrangement of additional components (e.g., NAND bare die) on a typical flip chip package (Figure 4A) with a flip chip package (Figure 4B) having a reduced bottom fill area according to an embodiment of the present invention.

[0018] Figure 5 This is a diagram showing the encapsulation of the component in Figure 4B. Detailed Implementation

[0019] The subject matter will now be described more fully below with reference to the accompanying drawings, in which representative embodiments are illustrated. However, the subject matter may be implemented in different forms and should not be construed as limited to the particular embodiments. Rather, these embodiments are provided for description and to enable those skilled in the art to use them. Furthermore, the elements illustrated in the drawings are not necessarily drawn to scale and may be exaggerated to highlight important features of the subject matter.

[0020] Figure 1A and Figure 1B This is an illustration of a portion of a conventional flip-chip package 100. The flip-chip package 100 includes, for example, an IC die 102 (e.g., a flip-chip die) positioned on a surface 106 of a substrate 104. The substrate 104 may be a circuit board (e.g., a PCB) having external circuitry electrically connected to the IC die 102, for example, via one or more solder points 108. The substrate 104 may also include a solder mask 110 on surface 106 configured to be electrically connected to one or more additional components, such as one or more NAND flash dies or other memory chips.

[0021] like Figure 1BAs shown, an underfill material 112 can be applied to further adhere the IC die 102 to the substrate 104. The underfill material 112 can be an electrically insulating material configured to fill the space between the IC die 102 and the substrate 104. The underfill material 112 can, for example, comprise a curable resin selected to disperse thermal expansion mismatch between the IC die 102 and the substrate 104 to prevent or reduce stress concentration in the solder joint 108. To apply the underfill material 112, it can be injected or otherwise dispensed in liquid form onto one or more sides of the IC die 102, allowing it to flow around the solder joint 108 and ideally, completely filling the volume between the IC die 102 and the surface 106 of the substrate 104. After the underfill material 112 is applied, it can be cured or hardened (e.g., thermosetting) to solidify.

[0022] Due to the flowable state of the underfill material 112 during application, a portion of the underfill material 112 can extend beyond the edge of the IC bare die 102, such as... Figure 1B As shown. In some cases, an excess of underfill material 112 is applied to ensure that the space between the IC die 102 and the substrate 104 is completely underfilled. In some cases, capillary action causes a portion of the underfill material 112 to be drawn away from the IC die 102 along the surface 106 of the substrate 104. In some cases, the underfill material 112 may also be pulled up along the side of the IC die 102. Therefore, the underfill material 112 can form a meniscus on the side of the IC die 102, and the underfill material 112 tapers away from the IC die 102.

[0023] When hardening or curing, a portion of the underfill material 112 extending beyond the edge of the IC die 102 creates a filler corner 114 that at least partially surrounds the IC die 102. In some cases, the filler corner 114 extends over the solder mask 110 and may prevent other components from being attached adjacent to the IC die 102. Because other dies or components (e.g., NAND dies) cannot be placed on or over the filler corner 114, the area occupied by the filler corner 114 is considered a wasted area on the substrate 104 and may be referred to as a “no-go zone” or KOZ. The farther the filler corner 114 extends away from the IC die 102, the larger the KOZ area. In some cases, for example, the filler corner 114 may extend a distance of approximately 1000 μm or more away from the IC die 102.

[0024] According to some embodiments, the present invention provides a flip-chip package having a reduced KOZ area compared to conventional flip-chip packages. In some embodiments, as discussed, having a reduced KOZ area provides a larger area on the substrate available for placing other components (e.g., NAND dies, other flash memory chips, or other integrated circuits), allowing more components to be attached to a given substrate. In some embodiments, having a reduced KOZ area allows other components to be positioned on the substrate closer to the IC die, which in turn allows for a smaller overall package size.

[0025] Figure 2A – A 2D illustration shows the steps involved in manufacturing a flip-chip package 200 with a reduced KOZ area according to certain embodiments of the present invention. Special reference: Figure 2A The flip-chip package 200 includes, for example, an IC die 202 (e.g., a flip-chip die) positioned on a surface 206 of a substrate 204. The substrate 204 may be a circuit board (e.g., a PCB) having external circuitry electrically connected to the IC die 202. For example, the IC die 202 may include contacts configured to make electrical contact with the substrate via, for example, one or more solder points 208. The substrate 204 may also include a solder mask 210 on surface 206 configured to be electrically connected to one or more additional components, such as one or more NAND flash dies or other memory chips. In these aspects, according to some embodiments, the flip-chip package 200 may be as follows: Figure 1A It is configured similarly to a conventional flip-chip package 100.

[0026] Further reference Figure 2A Release film 216 may be stacked over at least a portion of substrate 204. In some embodiments, release film 216 is stacked over at least a portion of surface 206 of substrate 204. In some embodiments, release film 216 is stacked over solder mask 210. In some embodiments, release film 216 is sized and positioned on substrate 204 to surround IC die 202. In some embodiments, release film 216 is a polymer film, sheet, or coating removably applied to substrate 204 such that release film 216 can subsequently be removed from substrate 204, as will be further described. In some embodiments, release film is an organic or inorganic tape, such as mask tape (acrylic) or thermal release (TR) film having a thickness of 5-100 μm. In some embodiments, the size of the film may be based on the size of the flip chip die, wherein the size of the film is equal to or greater than the size of the flip chip die. In some embodiments, release film may be applied to substrate using a tape-on machine.

[0027] like Figure 2BAs shown, an underfill material 212 can be applied to further adhere the IC die 202 to the substrate 204. In the case of the aforementioned underfill material 112, the underfill material 212 can be an electrically insulating material configured to fill the space between the IC die 202 and the substrate 204. The underfill material 212 may, for example, comprise a curable resin selected to disperse thermal expansion mismatch between the IC die 202 and the substrate 204 to prevent or reduce stress concentration in the solder joint 208. To apply the underfill material 212, it can be injected or otherwise dispensed in liquid form onto one or more sides of the IC die 202, allowing it to flow around the solder joint 208 and ideally, completely filling the volume between the IC die 202 and the surface 206 of the substrate 204. After the underfill material 212 is applied, it can be cured or hardened (e.g., thermosetting) to solidify. Figure 2B It is also shown that a portion of the underfill material 212 extending beyond the edge of the IC die 202 creates a filler corner 214 that at least partially surrounds the IC die 202. In some such embodiments, at least a portion of the filler corner 214 extends over the solder mask 210. In some embodiments, the filler corner 214 extends over at least a portion of the release film 216, as shown. In some embodiments, the portion of the filler corner 214 extending over the release film 216 is adhered to the release film 216.

[0028] In some embodiments, the process for manufacturing a flip-chip package according to the present invention includes truncating the filler corner 214. In some embodiments, truncating the filler corner 214 allows a portion of the filler corner 214 to be removed in order to reduce the area occupied by the filler corner 214. Figure 2CAs shown, in some embodiments, filler 214 is truncated by cutting (e.g., by mechanical cutting or, more preferably, by laser cutting). In some embodiments, filler 214 is cut at a predetermined location and / or depth. In some embodiments, filler 214 is cut at or near the edge of solder mask 210. In some embodiments, filler 214 is cut at or near the edge of release film 216. In some embodiments, filler 214 is cut at or near the edge of IC die 202. In some embodiments, filler 214 is cut at a location between solder mask 210 and IC die 202. In some embodiments, cutting filler 214 does not involve cutting into substrate 204 and / or solder mask 210. In some embodiments, filler 214 may be cut such that filler 214 is at least divided into a first portion 214a and a second portion 214b, which are separated by cuts. In some embodiments, the first portion 214a may be positioned further from the IC die 202 than the second portion 214b. In some embodiments, the second portion 214b includes a portion of the filler 214 immediately adjacent to the IC die 202. In some embodiments, the first portion 214a may be partially or completely positioned on the release film 216. In some embodiments, the first portion 214a may have a larger area (footprint) on the substrate 204 than the second portion 214b.

[0029] Following the cutting step, according to some embodiments, the first portion 214a of the filler 214 is removed. In some such embodiments, where the first portion 214a is positioned on the release film 216, the first portion 214a is removed by removing the release film 216 from the substrate 204. In some embodiments, the first portion 214a of the filler 214 is adhered to the release film 216 such that the first portion 214a of the filler 214 can be removed together with the release film 216. For example, the release film 216 can be peeled off from the substrate 204 and / or the solder mask 210.

[0030] Figure 2DA flip-chip package 200 according to certain embodiments is shown after the first portion 214a and release film 216 have been removed. In some embodiments, after the release film 216 and the first portion 214a are removed, a second portion 214b of filler 214 may remain on the substrate 204. In some embodiments, the second portion 214b includes a truncated surface 214c where the filler 214 is cut. In some embodiments, after the first portion 214a is removed, at least a portion of the truncated surface 214c of the second portion 214b remains exposed. In some embodiments, the truncated surface 214c may be flat or substantially flat and may be perpendicular to the surface 206 of the substrate 204. In other embodiments, (e.g., if the filler 214 is cut at an angle) the truncated surface 214c may be angled (sloped) with respect to the surface 206 of the substrate 204. As illustrated in the embodiments, removing a portion (e.g., a first portion 214a) of the overlay solder mask 210 covering the filler 214 results in a significantly smaller underfill area and a reduced KOZ. In some embodiments, removing the first portion 214a of the filler 214 results in a reduction of the underfill area of ​​at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, or at least 90%. In some embodiments, removing the first portion 214a of the filler 214 results in a reduction of the bottom filler area by about 10% to about 20%, about 15% to about 25%, about 20% to about 30%, about 25% to about 35%, about 30% to about 40%, about 35% to about 45%, about 40% to about 50%, about 45% to about 55%, about 50% to about 60%, about 55% to about 65%, about 60% to about 70%, about 65% to about 75%, about 70% to about 80%, about 75% to about 85%, or about 80% to about 90%.

[0031] Figures 3A and 3B provide illustrations comparing the KOZ distance between a conventional flip chip package 100 (Figure 3A) and a flip chip package 200 (Figure 3B) with a reduced underfill area according to an embodiment of the invention. In the flip chip package 100, the fillet 114 of the underfill material 112 is entirely retained on the substrate 104 and overlaps a portion of the solder mask 110. The KOZ distance of the flip chip package 100 is the distance by which the fillet 114 extends away from the IC die 102, and can be, for example, approximately 1000 μm or, in some cases, larger. In contrast, the flip chip package 200 includes a truncated fillet 214 (e.g., a second portion 214b), such that the KOZ distance of the flip chip package 200 is significantly smaller than that of the flip chip package 100. The KOZ distance of the flip chip package 200 can be considered as the distance between the truncated surface 214c and the IC die 202. In some embodiments, the KOZ distance of the flip chip package 200 can be, for example, less than 1000 μm, less than 900 μm, less than 800 μm, less than 700 μm, less than 600 μm, less than 500 μm, less than 400 μm, less than 300 μm, less than 200 μm, or less than 100 μm. The released area shown in Figure 3B refers to the first portion 214a on the substrate 204 previously removed by filler 214. Figure 2C The area occupied by the truncated filler 214. In some embodiments, the released area represents a portion of substrate 204 that has been recovered by the truncated filler 214 and is now available for placement of additional components (e.g., NAND die or other chips). In the illustrated example, the released area has a dimension equal to the difference between the KOZ distances of flip chip package 100 and flip chip package 200. In some embodiments, the truncated filler 214 results in a reduction of the KOZ distance of at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, or at least 90%. In some embodiments, the truncated filler 214 results in a reduction of the KOZ distance of approximately 10% to approximately 20%, approximately 15% to approximately 25%, approximately 20% to approximately 30%, approximately 25% to approximately 35%, approximately 30% to approximately 40%, approximately 35% to approximately 45%, approximately 40% to approximately 50%, approximately 45% to approximately 55%, approximately 50% to approximately 60%, approximately 55% to approximately 65%, approximately 60% to approximately 70%, approximately 65% ​​to approximately 75%, approximately 70% to approximately 80%, approximately 75% to approximately 85%, or approximately 80% to approximately 90%.

[0032] Figures 4A and 4B provide illustrations comparing the relative arrangements of additional components 118, 218 (e.g., NAND die) on a conventional flip chip package 100 (Figure 4A) and on a flip chip package 200 (Figure 4B) with a reduced underfill area according to an embodiment of the invention. In the flip chip package 100, as discussed above, the filler corner 114 of the underfill material 112 remains entirely on the substrate 104 and overlaps a portion of the solder mask 110. The additional component 118 must therefore be sufficiently remote from the IC die 102 so that the additional component 118 can be positioned on the solder mask 110 without overlapping the filler corner 114. In contrast, according to some embodiments, because the portion of the filler corner 214 overlapping the solder mask 210 has been removed, the truncated filler corner 214 of the flip chip package 200 allows the additional component 218 to be positioned closer to the IC die 202. In some embodiments, the additional component 218 is positioned close to or adjacent to the cut surface 214c of the filler 214. Therefore, the flip-chip package 200 allows for closer positioning of the additional component 218, which can reduce the overall package size and / or allow more additional components 218 to be disposed on the surface of the substrate or the solder mask, as appropriate. In some embodiments, the additional component 218 may be positioned less than 1000 μm, less than 900 μm, less than 800 μm, less than 700 μm, less than 600 μm, less than 500 μm, less than 400 μm, less than 300 μm, less than 200 μm, or less than 100 μm from the IC die 202.

[0033] Turning Figure 5 In some embodiments, components of the flip chip package 200 may be encapsulated. For example, the IC die 202, additional components 218, and / or filler 214 may be encapsulated by molding compound 220. In some embodiments, molding compound 220 may fill the space or gap between the cut surface 214c of filler 214 and additional components 218.

[0034] It should be understood that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. It should also be apparent that individual elements identified herein as belonging to a particular embodiment may be included in other embodiments of the invention. Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, and material compositions, means, methods, and steps described in the specification. The scope of the invention is also not intended to be limited by the title or abstract, as these portions of the application are provided to facilitate the searching of specific features disclosed herein. As will be readily understood from this disclosure by those skilled in the art, existing or developing processes, machines, manufactures, material compositions, means, methods, or steps that perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to the invention.

Claims

1. A method for packaging a bare integrated circuit die, the method comprising: The integrated circuit die is positioned on the surface of a substrate, wherein the integrated circuit die includes a contact body that makes electrical contact with the substrate; An underfill material is introduced into the space between the surface of the integrated circuit die and the substrate, with a portion of the underfill material extending beyond the edge of the integrated circuit die; The underfill material is cured, wherein the portion of the underfill material extending beyond the edge of the integrated circuit die forms a filler, the filler at least partially surrounding the integrated circuit die; as well as Remove one segment of the filler; and The method further includes applying a release film to the surface of the substrate prior to the introduction of the underfill material, wherein the filler at least partially overlaps a portion of the release film; The substrate includes a solder resist mask, and the release film is applied over the solder resist mask. The method also includes cutting the filler corner; The cutting of the filler corner includes dividing the filler corner into at least a first part and a second part, wherein the first part of the filler corner overlaps the portion of the release film, and the second part of the filler corner is adjacent to the bare integrated circuit die; The removal of the segment of the filler includes removing the release film from the substrate together with the first portion of the filler; The second portion of the filler includes a truncated surface that is flat and perpendicular to the surface of the substrate; and The cut surface of the bottom filler material is in direct contact with the edge of the solder mask.

2. The method of claim 1, wherein cutting the filler corner comprises laser cutting the filler corner at or near the edge of the release film.

3. The method of claim 1, further comprising positioning at least one NAND bare die on the surface of the substrate at least partially on the area of ​​the segment of the substrate from which the filler is removed.

4. The method of claim 1, wherein removing the segment of the filler reduces the area of ​​the bottom filler material by at least 30%.

5. The method of claim 1, wherein removing the segment of the filler reduces the area of ​​the bottom filler material by at least 50%.

6. An integrated circuit bare die package, comprising: Substrates including solder mask; An integrated circuit die is positioned on the surface of the substrate, the integrated circuit die including a contact body configured to make electrical contact with the substrate; Molding compound for encapsulating the bare die of the integrated circuit; An underfill material is disposed at least partially between the surfaces of the integrated circuit die and the substrate, and a portion of the underfill material extends beyond the edge of the integrated circuit die to form a filler corner at least partially surrounding the integrated circuit die, wherein the filler corner includes a truncated surface in direct contact with the molding compound; as well as The second bare integrated circuit die positioned on the solder mask. The cut surface of the bottom filler material is in direct contact with the edge of the solder mask.

7. The integrated circuit bare die package of claim 6, wherein the cut surface is substantially perpendicular to the surface of the substrate.

8. The integrated circuit die package of claim 6, wherein the second integrated circuit die comprises at least one NAND die positioned on the solder mask.

9. The integrated circuit die package of claim 8, wherein the at least one NAND die is positioned near the cut-off surface of the filler.

10. The integrated circuit die package of claim 9, wherein the at least one NAND die is positioned less than 1000 μm from the integrated circuit die.

11. The integrated circuit bare die package of claim 6, wherein the area of ​​the substrate occupied by the underfill material does not include the solder mask.

12. An integrated circuit bare die package, comprising: A substrate component for providing electrical interconnects, including a solder mask on the substrate component for providing electrical interconnects; An integrated circuit die is attached to a substrate component for providing electrical interconnects, wherein the integrated circuit die includes components for electrically connecting the integrated circuit die to the substrate component for providing electrical interconnects; Components used to encapsulate the bare die of the integrated circuit; An underfill material is disposed between the integrated circuit die and a substrate member for providing electrical interconnection, wherein a portion of the underfill material extends beyond the edge of the integrated circuit die, thereby forming a filler corner, the filler corner at least partially surrounding the integrated circuit die, wherein the filler corner includes a truncated surface in direct contact with the member for encapsulating the integrated circuit die; as well as The second bare integrated circuit die positioned on the solder mask. The cut surface of the bottom filler material is in direct contact with the edge of the solder mask.

13. The integrated circuit die package of claim 12, wherein the second integrated circuit die includes at least one memory die, the at least one memory die being attached to and electrically connected to a substrate member for providing electrical interconnection adjacent to the cut surface, wherein the substrate member for providing electrical interconnection connects the at least one memory die to the integrated circuit die, and The component used to encapsulate the integrated circuit die covers the at least one memory die, the integrated circuit die, and the filler component.

14. The integrated circuit bare die package of claim 12, wherein the area of ​​the substrate member for providing electrical interconnection occupied by the underfill material does not include the solder mask.

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