Multi-chip package and method for manufacturing the same

Abstract

The present invention discloses a multi-chip package and a manufacturing method thereof. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, through vias penetrating the dielectric body, and wiring structures in each of the plurality of semiconductor bodies; a plurality of semiconductor chips arranged side by side on a first surface of the interposer and electrically connected to the wiring structures; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a reconfiguration circuit structure located on a second surface of the interposer, the second surface of the interposer being opposite to the first surface of the interposer, the reconfiguration circuit structure being electrically connected to the plurality of semiconductor chips through the through vias.

Description

Technical Field

[0001] The present invention relates to a semiconductor package and a manufacturing method thereof, and particularly to a multi-chip package and a manufacturing method thereof. Background Art

[0002] In order to make a semiconductor package have both a thin and light volume and high performance, current packaging technologies have attempted to integrate multiple semiconductor chips into a single semiconductor package to form a multi-chip package or stack multiple semiconductor packages using 3D stacking technology to form a stacked package (Package on package, PoP) or a system-in-package. However, the signal communication speed between multiple semiconductor chips in existing multi-chip packages is limited, so the overall performance of the semiconductor package still needs to be further improved. Summary of the Invention

[0003] An object of the present invention is to provide a multi-chip package with good performance.

[0004] The present invention provides a multi-chip package, including an interposer, a plurality of semiconductor chips, an encapsulant, and a reconfiguration circuit structure. The interposer includes a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, through vias penetrating the dielectric body, and wiring structures located in each of the plurality of semiconductor bodies. The plurality of semiconductor chips are arranged side by side on a first surface of the interposer and are electrically connected to the wiring structures. The encapsulant is located on the first surface of the interposer and encapsulates at least a part of the plurality of semiconductor chips. The reconfiguration circuit structure is located on a second surface of the interposer and is electrically connected to the plurality of semiconductor chips through the through vias, and the second surface of the interposer is opposite to the first surface of the interposer.

[0005] The present invention provides a multi-chip package, including an interposer, a plurality of semiconductor chips, and a reconfiguration circuit structure. The interposer includes a dielectric body, a semiconductor body, through vias penetrating the dielectric body, and a wiring structure located in the semiconductor body, and the through vias and the wiring structure are spaced apart from each other. The plurality of semiconductor chips are arranged side by side on a first surface of the interposer and each of the plurality of semiconductor chips is electrically connected to both the wiring structure and the through vias at the same time. The reconfiguration circuit structure is located on a second surface of the interposer and is electrically connected to the through vias, and the second surface of the interposer is opposite to the first surface of the interposer.

[0006] The present invention provides a method for manufacturing a multi-chip package, including the following steps. Provide a plurality of semiconductor chips on a first surface of a semiconductor substrate such that each of the plurality of semiconductor chips is electrically connected to a wiring structure in the semiconductor substrate. Form an encapsulant on the first surface of the semiconductor substrate to encapsulate the plurality of semiconductor chips. Remove at least a portion of the semiconductor substrate from a second surface of the semiconductor substrate opposite to the first surface such that remaining portions of the semiconductor substrate are spaced apart from each other. Form a dielectric body in a space generated after the removal of the semiconductor substrate. Form vias that penetrate the dielectric body and are connected to the plurality of semiconductor chips in the dielectric body. Form a reconfiguration wiring structure on the remaining portions of the semiconductor substrate and the dielectric body, the reconfiguration wiring structure being electrically connected to the vias.

[0007] Based on the above, the multi-chip package of the present invention can improve the overall performance of the multi-chip package.

[0008] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional schematic view of a multi-chip package according to an embodiment of the present invention;

[0010] Figure 2 is Figure 1 a plan view of the multi-chip package taken along the cutting line I-I' of;

[0011] Figures 3A to 3H is a cross-sectional schematic view of the manufacturing process steps of manufacturing a multi-chip package according to an embodiment of the present invention;

[0012] Figure 4A and Figure 4B is a cross-sectional schematic view of a method for bonding chips according to an embodiment of the present invention;

[0013] Figure 5A and Figure 5B is a cross-sectional schematic view of a method for bonding chips according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0015] Examples will be listed below and described in detail with reference to the accompanying drawings. However, the provided examples are not intended to limit the scope covered by the present invention. In addition, the drawings are for illustrative purposes only, not drawn to the original scale, and may enlarge or reduce different film layers or regions and show them in a single drawing. Moreover, although terms such as "first" and "second" are used in the text to describe different components, regions, and / or members, these components, regions, and / or members should not be limited by these terms. Instead, these terms are only used to distinguish one component, region, or member from another component, region, or member. Therefore, the first component, region, or member discussed below can be referred to as the second component, region, or member without violating the teachings of the examples. The same or similar reference numerals represent the same or similar components, and will not be repeated in the following paragraphs.

[0016] In this document, spatial relative terms such as "upper" and "lower" are defined with reference to the accompanying drawings. Therefore, it should be understood that the term "upper surface" can be used interchangeably with the term "lower surface", and when a component such as a layer or film is described as being disposed on another component, the component can be directly placed on the other component, or there can be an intermediate component between the two components. On the other hand, when a component is described as being directly disposed on another component, there is no intermediate component between the two components. Similarly, when a component is described as being connected or joined to another component, the component can be directly connected or directly joined to the other component, or there can be an intermediate component between the two components. On the other hand, when a component is described as being directly connected or directly joined to another component, there is no intermediate component between the two components.

[0017] Figure 1 A cross-sectional schematic view of a multi-chip package according to an embodiment of the present invention is shown. Figure 2 is a plan view taken along Figure 1 section line I-I' of the multi-chip package.

[0018] Referring to Figure 1 , a multi-chip package 100 according to an embodiment of the present invention includes an interposer 150, a semiconductor chip 120 on a first surface 150A of the interposer 150, and a reconfigured wiring structure 110 on a second surface 150B of the interposer 150 opposite to the first surface 150A. Referring to Figure 2, the main body of the interposer 150 may be composed of a dielectric body 150R and a plurality of semiconductor bodies 150S separated by the dielectric body 150R. A through-via 153 penetrating the dielectric body 150R is formed in the dielectric body 150R. A wiring structure 150W is formed in the semiconductor body 150S. The wiring structure 150W can be used to transmit signals, especially high-bandwidth signals, between the side-by-side semiconductor chips 120. The through-via 153 can be used as a ground path or a power path between the semiconductor chip 120 and the reconfigurable wiring structure 110 for transmitting a large current.

[0019] In current System in Package, a reconfigurable wiring structure is used to transmit signals between side-by-side semiconductor chips. However, with the increase in high-performance computing applications, the demand for high-bandwidth signal transmission is also continuously increasing. The reconfigurable wiring structure is limited by the line width and pitch and the exposure and development capabilities of the organic dielectric layer, and the number of wiring layers is not large. Therefore, a connection structure with a higher line density is still required to meet the bandwidth requirements of, for example, High Bandwidth Memory (HBM). The multi-chip package of the present invention transmits signals between the semiconductor chips 120 by using a wiring structure 150W with a higher line density (i.e., smaller line width and pitch and more layers) compared to the reconfigurable wiring structure to achieve faster signal transmission.

[0020] For example, the number of layers of the reconfigurable wiring structure is generally 3, and the line width of the reconfigurable wiring structure is generally about 2 microns, the pitch is generally about 2 microns, and the size of the via is generally about 2 microns. While the number of layers of the wiring structure 150W in the multi-chip package according to the present invention can be 4 or more, and its line width can be in the range of about 0.01 microns to 1 micron (e.g., about 0.2 microns, about 0.4 microns, about 0.6 microns, or about 0.8 microns), its pitch can be in the range of about 0.01 microns to 1 micron (e.g., about 0.2 microns, about 0.4 microns, about 0.6 microns, or about 0.8 microns), and its via size can be in the range of about 0.01 microns to 1 micron (e.g., about 0.2 microns, about 0.4 microns, about 0.6 microns, or about 0.8 microns). Since the wiring structure 150W with a line width less than or equal to 1 micron is used to connect the semiconductor chips 120 in the multi-chip package of the present invention, high-bandwidth signal transmission can be performed between different semiconductor chips 120.

[0021] In addition, the interposer 150 in the multi-chip package according to the present invention is composed of a dielectric body 150R and a semiconductor body 150S, and the through-via 153 is formed in the dielectric body 150R. Therefore, the interposer 150 of the multi-chip package according to the present invention can omit the through-silicon vias to reduce costs and improve yield.

[0022] Specifically, the main body of the interposer 150 may be composed of a dielectric main body 150R and a plurality of semiconductor main bodies 150S separated by the dielectric main body 150R. The plurality of semiconductor main bodies 150S may be physically separated from each other. The material of the semiconductor main body 150S may be, for example, a semiconductor material such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. The material of the dielectric main body 150R may include polyimide, epoxy resin, acrylic resin, phenolic resin, bismaleimide-triazine resin (BT resin), or any other suitable polymer-based dielectric material, as well as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or other suitable silicon dielectric materials. In some embodiments, the material of the dielectric main body 150R may include a photosensitive insulating resin. The interface between the dielectric main body 150R and the semiconductor main body 150S may not be perpendicular to the surface of the interposer 150. For example, the angle α between the side wall of the semiconductor main body 150S and the second surface 150B may be greater than 90°. In other words, the width of the semiconductor main body 150S decreases as the distance from the semiconductor chip 120 increases, and the width of the dielectric main body 150R increases as the distance from the semiconductor chip 120 increases. However, this specification is not limited thereto. For example, the interface between the dielectric main body 150R and the semiconductor main body 150S may also be perpendicular to the surface of the interposer 150. As used herein, "width" refers to the length of the described component in the horizontal direction in the longitudinal cross-sectional schematic diagram of the multi-chip package according to the present invention (such as Figure 1 ).

[0023] A wiring structure 150W is formed in the semiconductor main body 150S. The wiring structure 150W can be used to transmit signals, especially high-bandwidth signals, between the semiconductor chips 120. The material of the wiring structure 150W may include, for example, a conductive material such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), or an alloy thereof, or other metals or alloys with excellent electrical properties. As described above, the wiring structure 150W has a high line density. In some embodiments, the number of layers of the wiring structure 150W may be, for example, a multi-layer of 4 layers or more, and the line width size may be in the range of about 0.01 micrometer to 1 micrometer (such as about 0.2 micrometer, about 0.4 micrometer, about 0.6 micrometer, or about 0.8 micrometer), the line pitch size may be in the range of about 0.01 micrometer to 1 micrometer (such as about 0.2 micrometer, about 0.4 micrometer, about 0.6 micrometer, or about 0.8 micrometer), and the via size may be in the range of about 0.01 micrometer to 1 micrometer (such as about 0.2 micrometer, about 0.4 micrometer, about 0.6 micrometer, or about 0.8 micrometer).

[0024] A through - via 153 penetrating the first surface 150A and the second surface 150B is formed in the dielectric body 150R. The material of the through - via 153 may include conductive materials such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), or their alloys. The through - via 153 can be used to connect the semiconductor chip 120 and the reconfigurable wiring structure 110 to each other. The upper width of the through - via 153 may be smaller than the lower width. That is, the width of the through - via 153 increases as the distance from the semiconductor chip 120 increases. Since the through - via 153 is formed in the dielectric body 150R, the multi - chip package 100 of the present invention can omit the process of forming through - silicon vias, thereby reducing costs and improving yield.

[0025] An interposer connection conductor 150P is formed on the first surface 150A of the interposer 150. The interposer connection conductor 150P is connected to the wiring structure 150W and the through - via 153 of the interposer 150. The interposer connection conductor 150P can be used to connect the interposer 150 to other devices. The material of the interposer connection conductor 150P may include conductive materials such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), or their alloys, or other metals or their alloys with excellent electrical properties. The shape of the interposer connection conductor 150P may include various shapes such as columnar or stud bump. The interposer connection conductor 150P may have different sizes. For example, the interposer connection conductor 150P may include a first interposer connection conductor 150P1 with a larger size and a second interposer connection conductor 150P2 with a smaller size. That is, the width DA of the first interposer connection conductor 150P1 is greater than the width DB of the second interposer connection conductor 150P2. The larger first interposer connection conductor 150P1 can be connected to the through - via 153 of the interposer 150, and the smaller second interposer connection conductor 150P2 can be connected to the wiring structure 150W. In other embodiments, the interposer connection conductor 150P may have the same size.

[0026] The semiconductor chip 120 can be any suitable integrated circuit (IC) chip, such as a memory chip, a logic chip, a digital chip, an analog chip, a sensor chip, an artificial intelligence chip (AI chip), a wireless and radio frequency chip, or a voltage regulator chip. Among them, the sensor chip can be an image sensor chip, at least including a charge - coupled device (CCD) or a complementary metal - oxide - semiconductor image sensor (CMOS image sensor). Although Figure 1The multi-chip package 100 includes two semiconductor chips 120, but the present invention is not limited thereto. For example, the multi-chip package of the present invention may include three or more semiconductor chips.

[0027] The semiconductor chip 120 has chip connection conductors 120P on the active surface. The material of the chip connection conductors 120P may include conductive materials such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), or alloys thereof, or other metals or alloys with excellent electrical properties. The shape of the chip connection conductors 120P may include various shapes such as columnar or stud bump. The chip connection conductors 120P may have different sizes. For example, the chip connection conductors 120P may include a first chip connection conductor 120P1 with a larger size and a second chip connection conductor 120P2 with a smaller size. That is, the width D1 of the first chip connection conductor 120P1 is greater than the width D2 of the second chip connection conductor 120P2. The chip connection conductors 120P are joined to at least a part of the interposer connection conductors 150P. In some embodiments, the chip connection conductors 120P and the interposer connection conductors 150P that are joined to each other may have corresponding sizes. For example, the larger first chip connection conductor 120P1 may be joined to the larger first interposer connection conductor 150P1, and the smaller second chip connection conductor 120P2 may be joined to the smaller second interposer connection conductor 150P2. In this case, the larger first chip connection conductor 120P1 and the first interposer connection conductor 150P2 may be used to transmit large currents (such as ground), while the smaller second chip connection conductor 120P2 and the second interposer connection conductor 150P2 may be used to transmit high-bandwidth signals. The joining surface of the chip connection conductors 120P and the interposer connection conductors 150P may be a solderless joining surface. Since the interposer 150 and the semiconductor chip 120 are connected to each other via the chip connection conductors 120P and the interposer connection conductors 150P instead of a reconfigured circuit structure, the power and / or signal transfer path between the interposer 150 and the semiconductor chip 120 can be shortened, and the power and / or signal transfer speed and quality can be improved. In some embodiments, the chip connection conductors 120P and the interposer connection conductors 150P may be joined using a solder such as a solder alloy of Cu / Sn, Cu / Ni / Sn, Cu / Ni / SnBi, etc. In some embodiments, bumps (such as Figure 4B as shown) may be further included between the chip connection conductors 120P and the interposer connection conductors 150P.

[0028] In addition, a plurality of semiconductor chips 120 arranged side by side can be connected to each other via a wiring structure 150W in the interposer 150. As described above, the wiring structure 150W has a line width less than or equal to 1 micron, and the wiring structure 150W can transmit high-bandwidth signals between the semiconductor chips 120. In addition, depending on the signals or currents to be transmitted, high-bandwidth signals requiring a faster transmission speed can be transmitted via the second chip connection conductor 120P2, the second interposer connection conductor 150P2, and the wiring structure 150W, while other signals or grounds can be transmitted via the first chip connection conductor 120P1, the first interposer connection conductor 150P1, the through-via 153, and the reconfigured wiring structure 110. That is to say, in the multi-chip package 100 of the present invention, the signal transmission between the semiconductor chips 120 can be transmitted via different paths depending on the nature of the signals.

[0029] The multi-chip package 100 according to the present invention may include an underfill 170 between the semiconductor chip 120 and the interposer 150. The underfill 170 can fill the space between the semiconductor chip 120 and the interposer 150 and encapsulate the interposer connection conductor 150P and the chip connection conductor 120P. The underfill 170 has an inclined sidewall, and the upper width of the underfill 170 is smaller than the lower width of the underfill 170. In some embodiments, the width of the underfill 170 is tapered, and the width of the underfill 170 gradually decreases from one end closer to the interposer 150 towards the other end closer to the semiconductor chip 120. The material of the underfill 170 is not particularly limited, and may be an insulating material such as epoxy resin, etc. In other embodiments, a protective layer 175 can replace the underfill 170 between the semiconductor chip 120 and the interposer 150 in the multi-chip package 100 according to the present invention (see Figure 5B ).

[0030] The multi-chip package 100 according to the present invention may include an encapsulant 180 on the interposer 150 to encapsulate the semiconductor chip 120 and the interposer 150. The material of the encapsulant 180 may include a molding compound, a molding underfill, a resin, or an epoxy molding compound (EMC), etc. Optionally, inorganic fillers can be doped in the encapsulant 180. The sidewalls of the encapsulant 180, the sidewalls of the interposer 150, and the sidewalls of the reconfigured wiring structure 110 can be aligned with each other.

[0031] The reconfiguration wiring structure 110 is located on the second surface 150B of the interposer 150 and can be used to rewire the output / input terminals of the semiconductor chip 120. For example, the reconfiguration wiring structure 110 can be used to fan out the output / input terminals of the semiconductor chip 120 to connect the semiconductor chip 120 to a printed circuit board (PCB) (not shown). The reconfiguration wiring structure 110 includes a plurality of reconfiguration dielectric layers 114 and a plurality of reconfiguration wiring layers 116 embedded in the reconfiguration dielectric layers 114 and connected to the vias 153. The material of the reconfiguration dielectric layers 114 can include polyimide, epoxy resin, acrylic resin, phenolic resin, bismaleimide-trazine resin (BT resin), or any other suitable polymer-based dielectric material, as well as silicon oxide layer, silicon nitride layer, silicon oxynitride layer, or other suitable silicon dielectric materials. In some embodiments, the material of the reconfiguration dielectric layers 114 can include photosensitive insulating resin. The material of the reconfiguration wiring layers 116 can include conductive materials such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), or their alloys.

[0032] The reconfiguration wiring structure 110 may further include reconfiguration vias 118, which can be used to connect the reconfiguration wiring layers 116 located on different layers. The material of the reconfiguration vias 118 can include conductive materials such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), or their alloys. The upper width W1 of the reconfiguration via 118 can be smaller than the lower width W2 of the reconfiguration via 118. That is, the angle β between the inclined sidewall of the reconfiguration via 118 and the lower surface of the reconfiguration dielectric layer 114 can be greater than 90°.

[0033] Although Figure 1 the reconfiguration wiring structure 110 in [the figure] is shown as including three reconfiguration dielectric layers 114 and three reconfiguration wiring layers 116, the present invention is not limited thereto. The multi-chip package 100 according to the present invention can include more or fewer layers of reconfiguration dielectric layers 114 and reconfiguration wiring layers 116 than shown in the figure.

[0034] The multi-chip package 100 according to the present invention may further include conductive terminals 190. The conductive terminals 190 are partially embedded in the lowermost reconfiguration dielectric layer 114 to connect to the lowermost reconfiguration wiring layer 116. The conductive terminals 190 can be used to connect the multi-chip package 100 to an external device such as a printed circuit board. The conductive terminals 190 can be, for example, solder balls, but the present invention is not limited thereto.

[0035] In the multi-chip package 100 according to the present invention, a plurality of semiconductor chips 120 arranged side by side can be connected to each other through a wiring structure 150W with high density and high number of layers to achieve high-efficiency signal transmission. In addition, the multi-chip package 100 according to the present invention also provides other electrical paths for transmitting high current to improve the reliability of the multi-chip package 100 of the present invention. At the same time, the multi-chip package 100 according to the present invention can achieve a fan-out package by reconfiguring the wiring structure 110 to rewire the semiconductor chips 120.

[0036] Figures 3A to 3H is a cross-sectional schematic diagram of the manufacturing process steps of manufacturing a multi-chip package according to an embodiment of the present invention. Figure 4A and Figure 4B shows a cross-sectional schematic diagram of a method of bonding chips according to an embodiment of the present invention. Figure 5A and Figure 5B shows a cross-sectional schematic diagram of a method of bonding chips according to another embodiment of the present invention.

[0037] Referring to Figure 3A , a semiconductor substrate 15 having a wiring structure 150W is provided. The semiconductor substrate 15 can be, for example, a silicon substrate. Although only the process of forming one multi-chip package using the semiconductor substrate 15 is shown in the drawings, in some embodiments, a semiconductor substrate 15 with a large size can be used to form a plurality of multi-chip packages simultaneously. For example, a silicon wafer or a panel-level silicon substrate can be used as the semiconductor substrate 15. The semiconductor substrate 15 has an interposer connection conductor 150P on the first surface 150A, and the interposer connection conductor 150P is electrically connected to the wiring structure 150W. The interposer connection conductor 150P includes a first interposer connection conductor 150P1 and a second interposer connection conductor 150P2 with different sizes. That is, the width DA of the first interposer connection conductor 150P1 can be greater than the width DB of the second interposer connection conductor 150P2.

[0038] Referring to Figure 3B, a plurality of semiconductor chips 120 are provided on a semiconductor substrate 15 so that chip connection conductors 120P and interposer connection conductors 150P are joined to each other. The chip connection conductors 120P include a first chip connection conductor 120P1 and a second chip connection conductor 120P2 having different sizes. That is, the width D1 of the first chip connection conductor 120P1 may be greater than the width D2 of the second chip connection conductor 120P2. In some embodiments, the first chip connection conductor 120P1 with a larger size is joined to the first interposer connection conductor 150P1, and the second chip connection conductor 120P2 with a smaller size is joined to the second interposer connection conductor 150P2. The joining method of the chip connection conductors 120P and the interposer connection conductors 150P may be, for example, direct joining by heating and / or pressure. After the chip connection conductors 120P and the interposer connection conductors 150P are joined, an underfill 170 may be applied on the semiconductor substrate 15 to encapsulate the chip connection conductors 120P and the interposer connection conductors 150P.

[0039] In some embodiments, the chip connection conductors 120P and the interposer connection conductors 150P may be joined to each other by bumps. Refer to Figure 4A, a first bump 155 can be formed on the interposer connection conductor 150P and a second bump 165 can be formed on the chip connection conductor 120P. Then, the first bump 155 and the second bump 165 are joined using heat energy and / or pressure. The materials of the first bump 155 and the second bump 165 can be, for example, solder alloys (such as Cu / Sn, Cu / Ni / Sn, Cu / Ni / SnBi), copper, gold, silver, indium, palladium, titanium, manganese, cobalt, or their alloys (such as Ni / Au, Cu / Ni / Au, Cu / Ni / In), etc., as bonding metals. The materials of the first bump 155 and the second bump 165 can be different from each other. For example, the material of the first bump 155 can be pure copper with surface treatment, Ni / Au alloy, Cu / Ni / Au alloy, or Cu / Ni / In alloy, etc., and the material of the second bump 165 can be Cu / Sn, Cu / Ni / Sn, or Cu / Ni / SnBi alloy, etc. In some embodiments, the materials of the first bump 155 and the second bump 165 do not contain solder components. In some embodiments, the materials of the first bump 155 and the second bump 165 can be low-temperature bonding metals with a melting point lower than 200°C. For example, the low-temperature bonding metals can include bicrystal copper, bicrystal silver, or other nanobicrystal materials, indium tin alloy, tin bismuth alloy, porous gold, or combinations thereof. Compared with the reflow temperature required for traditional solder balls or solders, which is mostly higher than or equal to 250°C, using low-temperature bonding metals can achieve stable bonding of the connection structure at a relatively low heating temperature (for example, at a temperature lower than 200°C or lower than 150°C), and meet the reliability requirements for electrical connection. In some embodiments, only one of the first bump 155 and the second bump 165 can be formed. For example, only the first bump 155 can be formed on the interposer connection conductor 150P and the first bump 155 can be joined to the chip connection conductor 120P.

[0040] Next, referring to Figure 4B , after the first bump 155 and the second bump 165 are joined, an underfill 170 can be applied on the semiconductor substrate 15 to encapsulate the chip connection conductor 120P, the interposer connection conductor 150P, the first bump 155, and the second bump 165. The underfill 170 can fill the space between the semiconductor chip 120 and the semiconductor substrate 15 and encapsulate the interposer connection conductor 150P, the chip connection conductor 120P, the first bump 155, and the second bump 165.

[0041] Referring to Figure 5A and Figure 5B, in some embodiments, a protective layer 175 may be formed on the semiconductor chip 120. The material of the protective layer 175 may be an organic material such as resin, non-conductive film, dielectric material, etc. The surface of the protective layer 175 between the surface of the chip connection conductor 120P and the semiconductor chip 120 may be coplanar. When the chip connection conductor 120P and the interposer connection conductor 150P are joined to each other, since the chip connection conductor 120P is encapsulated by the protective layer 175 and only the surface is exposed for connection, it can be protected from external force impact and damage, thus improving the yield rate.

[0042] Return reference Figure 3C , an encapsulation body 180 is formed on the semiconductor substrate 15. The method of forming the encapsulation body 180 includes the following steps. An encapsulation material layer covering the semiconductor substrate 15 and the semiconductor chip 120 is formed on the semiconductor substrate 15 by a suitable process (such as a molding process or a deposition process). Thereafter, a surface grinding and polishing process (grinding) or a surface planarization process is performed to expose the upper surface of the semiconductor chip 120.

[0043] Then refer jointly to Figure 3C And Figure 3D , the Figure 3C resulting structure is inverted upside down, and a thinning process such as a grinding process or an etching process is performed on the back surface of the semiconductor substrate 15 to reduce the thickness of the semiconductor substrate 15. The purpose of reducing the thickness of the semiconductor substrate 15 is to miniaturize and thin the final multi-chip package. In addition, reducing the thickness of the semiconductor substrate 15 also helps in the formation of the subsequent dielectric body 150R. Optionally, this step may be omitted.

[0044] Refer to Figure 3E , a portion of the semiconductor substrate 15 is removed by, for example, an etching process to form a plurality of semiconductor bodies 150S that are physically separated from each other and expose a portion of the interposer connection conductor 150P, the underfill 170, and / or the encapsulation body 180. At least one semiconductor body 150S overlaps at least a portion of at least 2 semiconductor chips 120 in a direction perpendicular to the first surface 150A to be connected to the at least 2 semiconductor chips 120 simultaneously. Other semiconductor bodies 150S may not overlap with the semiconductor chips 120 in a direction perpendicular to the first surface 150A. In some embodiments, other semiconductor bodies 150S may partially overlap with the semiconductor chips 120 in a direction perpendicular to the first surface 150A, but each of the semiconductor bodies 150S is physically spaced apart from each other.

[0045] Refer to Figure 3F, the dielectric body 150R can be formed between the semiconductor bodies 150S on the encapsulation body 180 by any suitable method such as spin coating. The dielectric body 150R can be formed over the second surface 150B of the semiconductor body 150S, and then a portion of the dielectric body 150R is removed by a planarization process so that the surface of the dielectric body 150R is substantially coplanar with the surface of the semiconductor body 150S to complete the preparation of the body of the interposer 150. Then, vias 153 can be formed in the dielectric body 150R and a reconfiguration wiring layer 116 can be formed on the second surface 150B of the interposer 150. First, via holes are formed in the dielectric body 150R that penetrate the second surface 150B and the first surface 150A of the interposer to expose the interposer connection conductor 150P, and the method of forming the via holes in the dielectric body 150R can employ different processes depending on the material of the dielectric body 150R. When the dielectric body 150R is a photosensitive insulating layer including a photosensitive insulating resin, the dielectric body 150R can be patterned by a photolithography process to form the via holes. When the dielectric body 150R is a non-photosensitive insulating layer, via holes can be formed in the dielectric body 150R by a photolithography / etching process, a laser drilling process, or a mechanical drilling process. The reconfiguration wiring layer 116 and the vias 153 can be integrally formed. For example, the process of forming the reconfiguration wiring layer 116 and the vias 153 includes the following steps. First, a seed layer is sputtered or deposited on the second surface 150B of the interposer 150 and the surface of the via holes, and the material of the seed layer can be a conductive material such as titanium / copper. Then, a patterned photoresist layer is formed on the seed layer to expose the seed layer. A conductive material is formed on the seed layer exposed by the patterned photoresist layer by an electroplating process, and the conductive material can include copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W), or an alloy thereof. Then, the photoresist layer and the portion of the seed layer not covered by the conductive material are removed to form the reconfiguration wiring layer 116 and the vias 153.

[0046] Referring to Figure 3G , a reconfiguration dielectric layer 114 can be formed on the reconfiguration wiring layer 116 and the vias 153 in a manner similar to that of forming the dielectric body 150R, thereby forming a redistribution circuit structure 110.

[0047] The reconfiguration wiring structure 110 may include multiple layers or a single layer of reconfiguration wiring layers 116. When the reconfiguration wiring structure 110 includes multiple layers of reconfiguration wiring layers 116, the process of forming the upper reconfiguration wiring layer 116 includes the following steps. First, via holes are formed in the reconfiguration dielectric layer 114 to expose the underlying reconfiguration wiring layer 116, and the method of forming the via holes in the reconfiguration dielectric layer 114 may employ different processes depending on the material of the reconfiguration dielectric layer 114. When the reconfiguration dielectric layer 114 is a photosensitive insulating layer including a photosensitive insulating resin, the reconfiguration dielectric layer 114 may be patterned through a photolithography process to form the via holes. When the reconfiguration dielectric layer 114 is a non-photosensitive insulating layer, the reconfiguration dielectric layer 114 may be patterned through a photolithography / etching process, a laser drilling process, or a mechanical drilling process to form the via holes. Then, the upper reconfiguration wiring layer 116 and the reconfiguration vias 118 filling the via holes are formed in the same manner as the method of forming the reconfiguration wiring layer 116 above to connect to the reconfiguration wiring layer 116 exposed through the via holes. Although in the drawings, the reconfiguration wiring structure 110 is depicted as including three layers of reconfiguration dielectric layers 114 and three layers of reconfiguration wiring layers 116, the present invention is not limited thereto, and the reconfiguration wiring structure 110 may include more or fewer layers of reconfiguration dielectric layers 114 and reconfiguration wiring layers 116 than those in the drawings.

[0048] Referring to Figure 3H , a plurality of conductive terminals 190 may be formed on the reconfiguration wiring structure 110 to complete the multi-chip package 100 of the present invention as Figure 1 shown. A large-sized semiconductor substrate 15 may be used to simultaneously form a plurality of multi-chip packages 100 of the present invention, and then, through processes such as cutting, the individual multi-chip packages 100 are separated. Therefore, the sidewalls of the interposer 150 and the sidewalls of the encapsulant 180 in the multi-chip package 100 of the present invention may be aligned with the sidewalls of the reconfiguration wiring structure 110.

[0049] In summary, the present invention provides a multi-chip package and a manufacturing method thereof. The multi-chip package of the present invention can shorten the transmission paths of power and / or signals in the multi-chip package and improve the overall performance of the multi-chip package. At the same time, the multi-chip package of the present invention also has a re-wiring structure and has the design freedom of a fan-out package.

[0050] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-chip package, characterized in that, comprising: an interposer, including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, through-vias penetrating the dielectric body, and wiring structures in each of the plurality of semiconductor bodies; a plurality of semiconductor chips, arranged side by side on a first surface of the interposer and electrically connected to the wiring structures; an encapsulant, located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a reconfiguration circuit structure, located on a second surface of the interposer, the second surface of the interposer being opposite to the first surface of the interposer, the reconfiguration circuit structure being electrically connected to the plurality of semiconductor chips through the through-vias, wherein an interface between the dielectric body and the semiconductor body is not perpendicular to the first surface of the interposer, wherein a width of the dielectric body increases as a distance from the plurality of semiconductor chips increases.

2. The multi-chip package according to claim 1, wherein a line width of the wiring structure is less than 1 micrometer.

3. The multi-chip package according to claim 1, wherein an interposer connection conductor is disposed on the first surface of the interposer, and a chip connection conductor is disposed on a surface of each of the plurality of semiconductor chips adjacent to the interposer, and the interposer connection conductor and the chip connection conductor are joined to each other.

4. The multi-chip package according to claim 3, wherein a joint surface between the interposer connection conductor and the chip connection conductor is a solderless joint surface.

5. The multi-chip package according to claim 3, wherein the interposer connection conductor and the chip connection conductor are joined by solder.

6. The multi-chip package according to claim 3, wherein the interposer connection conductor and the chip connection conductor are joined by a joining metal having a melting point lower than 200 °C.

7. The multi-chip package according to claim 3, further comprising a first bump located between the interposer connection conductor and the chip connection conductor.

8. The multi-chip package according to claim 7, further comprising a second bump located between the first bump and the chip connection conductor.

9. The multi-chip package according to claim 3, further comprising: a protective layer, disposed between the interposer and the plurality of semiconductor chips and encapsulating the interposer connection conductor and the chip connection conductor.

10. The multi-chip package according to claim 3, wherein the interposer connection conductor includes a first interposer connection conductor and a second interposer connection conductor, and a width of the first interposer connection conductor is greater than a width of the second interposer connection conductor.

11. The multi-chip package according to claim 10, wherein the chip connection conductor includes a first chip connection conductor and a second chip connection conductor, and a width of the first chip connection conductor is greater than a width of the second chip connection conductor.

12. The multi-chip package according to claim 11, wherein the first interposer connection conductor and the first chip connection conductor are joined to each other, and the second interposer connection conductor and the second chip connection conductor are joined to each other.

13. The multi-chip package according to claim 10, wherein the through-via is connected to the first interposer connection conductor, and the wiring structure is connected to the second interposer connection conductor.

14. The multi-chip package according to claim 1, wherein the reconfigurable wiring structure includes a reconfigurable dielectric layer and a reconfigurable wiring layer, and the line width of the reconfigurable wiring layer is greater than the line width of the wiring structure.

15. The multi-chip package according to claim 1, wherein the sidewalls of the encapsulant, the sidewalls of the interposer, and the sidewalls of the reconfigurable wiring structure are aligned with each other.

16. The multi-chip package according to claim 1, further comprising: An underfill disposed between the interposer and the plurality of semiconductor chips, wherein the width of the underfill increases as the distance from the plurality of semiconductor chips increases.

17. The multi-chip package according to claim 1, wherein at least one of the plurality of semiconductor bodies overlaps at least two of the plurality of semiconductor chips in a direction perpendicular to the first surface.

18. A multi-chip package, characterized in that, comprising: An interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through-via penetrating the dielectric body, and a wiring structure located in the semiconductor body, the through-via and the wiring structure being spaced apart from each other; A plurality of semiconductor chips arranged side by side on a first surface of the interposer, and each of the plurality of semiconductor chips being electrically connected to the wiring structure and the through-via at the same time; and A reconfigurable wiring structure located on a second surface of the interposer and electrically connected to the through-via, the second surface of the interposer being opposite to the first surface of the interposer, wherein the interface between the dielectric body and the semiconductor body is not perpendicular to the first surface of the interposer, wherein the width of the dielectric body increases as the distance from the plurality of semiconductor chips increases.

19. The multi-chip package according to claim 18, wherein the line width of the wiring structure is less than 1 micron.

20. A method of manufacturing a multi-chip package, comprising: Providing a plurality of semiconductor chips on a first surface of a semiconductor substrate such that each of the plurality of semiconductor chips is electrically connected to a wiring structure in the semiconductor substrate; Forming an encapsulant on the first surface of the semiconductor substrate to encapsulate the plurality of semiconductor chips; Removing at least a portion of the semiconductor substrate from a second surface of the semiconductor substrate opposite to the first surface such that the remaining portions of the semiconductor substrate are separated from each other to form a plurality of semiconductor bodies separated from each other; Forming a dielectric body in the space generated after the removal of the semiconductor substrate; Forming a through-via in the dielectric body that penetrates the dielectric body and is connected to the plurality of semiconductor chips; and A reconfiguration circuit structure is formed on the remaining portion of the semiconductor substrate and the dielectric body, and the reconfiguration circuit structure is electrically connected to the through-via. Wherein an interface between the dielectric body and the semiconductor body is not perpendicular to the first surface of the semiconductor substrate. Wherein a width of the dielectric body increases as a distance from the plurality of semiconductor chips increases.

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