Semiconductor device and method of manufacturing the same

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof. One embodiment of the present invention is a semiconductor device including a semiconductor over a substrate, a first conductor and a second conductor over the semiconductor, a first insulator over the first conductor and the second conductor, a second insulator over the semiconductor, a third insulator over the second insulator, and a third conductor over the third insulator, wherein the third insulator is in contact with a side surface of the first insulator, the semiconductor includes a first region where a bottom surface of the semiconductor overlaps with the first conductor, a second region where a bottom surface of the semiconductor overlaps with the second conductor, and a third region where a bottom surface of the semiconductor overlaps with the third conductor, and a length between a top surface of the semiconductor and a bottom surface of the third conductor is longer than a length between the first region and the third region.

Description

[0001] This application is a divisional application of the invention patent application with application number 201680021254.9, application date March 30, 2016, entitled "Semiconductor Device and Method of Manufacturing Thereof". Technical Field

[0002] This invention relates, for example, to a transistor, a semiconductor device, and a method for manufacturing the same. Additionally, this invention relates, for example, to a display device, a light-emitting device, a lighting device, a power storage device, a memory device, a camera device, a processor, and an electronic device. Furthermore, it relates to a method for manufacturing a display device, a liquid crystal display device, a light-emitting device, a memory device, a camera device, and an electronic device. Additionally, it relates to a driving method for a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a memory device, and an electronic device.

[0003] Note that one aspect of the present invention is not limited to the technical fields described above. The technical field of one aspect of the invention disclosed in this specification relates to objects, methods, or manufacturing methods. Additionally, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter.

[0004] Note that, as used in this specification, "semiconductor device" refers to all devices capable of operating using the properties of semiconductors. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices sometimes include semiconductor devices. Background Technology

[0005] In recent years, transistors using oxide semiconductors have attracted much attention. It is known that the leakage current of transistors using oxide semiconductors is extremely small in the off state. For example, a low-power CPU that utilizes the low leakage current characteristic of transistors using oxide semiconductors has been disclosed (see Patent Document 1).

[0006] [References]

[0007] [Patent Literature]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 Summary of the Invention

[0009] The present invention aims to provide a miniature transistor. Other objectives include providing a transistor with low parasitic capacitance, providing a transistor with high frequency characteristics, providing a transistor with good electrical characteristics, providing a transistor with stable electrical characteristics, providing a transistor with low off-state current, providing a novel transistor, providing a semiconductor device including the aforementioned transistor, providing a semiconductor device with high operating speed, providing a novel semiconductor device, providing a module including the semiconductor device, and providing an electronic device including the semiconductor device or the module.

[0010] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Furthermore, objectives other than those described above are readily apparent from the description, drawings, claims, etc., and can be extracted from these descriptions.

[0011] One aspect of the present invention is a semiconductor device comprising: a semiconductor on a substrate; a first conductor and a second conductor on the semiconductor; a first insulator on the first conductor and the second conductor; a second insulator on the semiconductor; a third insulator on the second insulator; and a third conductor on the third insulator, the third insulator being in contact with a side surface of the first insulator, the semiconductor including a first region overlapping the bottom surface of the semiconductor and the first conductor, a second region overlapping the bottom surface of the semiconductor and the second conductor, and a third region overlapping the bottom surface of the semiconductor and the third conductor, wherein the length between the top surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region.

[0012] One aspect of the present invention is a semiconductor device comprising: a semiconductor on a substrate; a first conductor and a second conductor on the semiconductor; a first insulator on the first conductor and the second conductor; a second insulator on the semiconductor; a third insulator on the second insulator; a third conductor on the third insulator; and a fourth conductor on the first insulator and the third conductor, wherein the third insulator is in side contact with the first insulator, the semiconductor including a first region overlapping the bottom surface of the semiconductor and the first conductor, a second region overlapping the bottom surface of the semiconductor and the second conductor, and a third region overlapping the bottom surface of the semiconductor and the third conductor, wherein the length between the top surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region, and the length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first region and the second region.

[0013] One aspect of the present invention is a semiconductor device comprising: a semiconductor on a substrate; a first conductor and a second conductor on the semiconductor; a first insulator on the first conductor and the second conductor; a second insulator on the semiconductor; a third insulator on the second insulator; a fourth insulator on the third insulator; and a third conductor on the fourth insulator, the fourth insulator being in contact with a side surface of the first insulator, the semiconductor including a first region overlapping the bottom surface of the semiconductor and the first conductor, a second region overlapping the bottom surface of the semiconductor and the second conductor, and a third region overlapping the bottom surface of the semiconductor and the third conductor, wherein the length between the top surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region.

[0014] One aspect of the present invention is a semiconductor device comprising: a semiconductor on a substrate; a first conductor and a second conductor on the substrate; a first insulator on the first conductor and the second conductor; a second insulator on the semiconductor; a third insulator on the second insulator; a fourth insulator on the third insulator; a third conductor on the fourth insulator; and a fourth conductor on the first insulator and the third conductor, the fourth insulator being in contact with a side surface of the first insulator. The semiconductor includes a first region overlapping the bottom surface of the semiconductor and the first conductor, a second region overlapping the bottom surface of the semiconductor and the second conductor, and a third region overlapping the bottom surface of the semiconductor and the third conductor. The length between the top surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region, and the length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first region and the second region.

[0015] In one embodiment of the invention, the length between the first conductor or the second conductor and the fourth conductor is more than 1.5 times and less than 2 times the length between the first region and the second region.

[0016] This invention can provide a miniature transistor; a transistor with low parasitic capacitance; a transistor with high frequency characteristics; a transistor with good electrical characteristics; a transistor with stable electrical characteristics; a transistor with low off-state current; a novel transistor; a semiconductor device including the above-described transistor; a semiconductor device with high operating speed; a novel semiconductor device; a module including the semiconductor device; and an electronic device including the semiconductor device or the module.

[0017] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the invention does not necessarily require all of the aforementioned effects. Furthermore, effects other than those described above are readily apparent from the description, drawings, claims, etc., and can be extracted from these descriptions. Attached Figure Description

[0018] Figures 1A to 1C This is a top view and a cross-sectional view of a transistor illustrating one aspect of the present invention;

[0019] Figures 2A to 2C This is a top view and a cross-sectional view of a transistor illustrating one aspect of the present invention;

[0020] Figures 3A to 3C This is a top view and a cross-sectional view of a transistor illustrating one aspect of the present invention;

[0021] Figures 4A to 4C This is a top view and a cross-sectional view of a transistor illustrating one aspect of the present invention;

[0022] Figures 5A to 5C This is a top view and a cross-sectional view of a transistor illustrating one aspect of the present invention;

[0023] Figures 6A to 6C This is a top view and a cross-sectional view of a transistor illustrating one aspect of the present invention;

[0024] Figures 7A to 7H This is a cross-sectional view illustrating a portion of a transistor according to one aspect of the present invention;

[0025] Figures 8A to 8F This is a cross-sectional view illustrating a portion of a transistor according to one aspect of the present invention;

[0026] Figures 9A to 9D This is a cross-sectional view illustrating a portion of a transistor according to one aspect of the present invention;

[0027] Figures 10A to 10C This is a top view and a cross-sectional view of a transistor illustrating one aspect of the present invention;

[0028] Figure 11A and Figure 11B This is a cross-sectional view of a transistor illustrating one aspect of the present invention;

[0029] Figures 12A to 12C This is a top view and a cross-sectional view of a transistor illustrating one aspect of the present invention;

[0030] Figure 13A and Figure 13B This is a cross-sectional view of a transistor illustrating one aspect of the present invention;

[0031] Figures 14A to 14C This is a top view and a cross-sectional view of a transistor illustrating one aspect of the present invention;

[0032] Figures 15A to 15C This is a top view and a cross-sectional view of a transistor illustrating one aspect of the present invention;

[0033] Figures 16A to 16C This is a top view and a cross-sectional view of a transistor illustrating one aspect of the present invention;

[0034] Figures 17A to 17C This is a top view and a cross-sectional view of a transistor illustrating one aspect of the present invention;

[0035] Figures 18A to 18H This is a cross-sectional view illustrating a portion of a transistor according to one aspect of the present invention;

[0036] Figures 19A to 19F This is a cross-sectional view illustrating a portion of a transistor according to one aspect of the present invention;

[0037] Figures 20A to 20F This is a cross-sectional view illustrating a portion of a transistor according to one aspect of the present invention;

[0038] Figure 21 This is a cross-sectional view showing a portion of the sputtering apparatus;

[0039] Figure 22 This is a cross-sectional view showing a portion of the sputtering apparatus;

[0040] Figure 23 This is a top view showing an example of a deposition apparatus;

[0041] Figures 24A to 24C This is a diagram illustrating an example of the structure of a deposition apparatus;

[0042] Figure 25 This is a top view illustrating a manufacturing apparatus according to one aspect of the present invention;

[0043] Figure 26 This is a top view illustrating a chamber according to one aspect of the present invention;

[0044] Figure 27 This is a top view illustrating a chamber according to one aspect of the present invention;

[0045] Figures 28A to 28D These are Cs-corrected high-resolution TEM images of the cross-section of CAAC-OS and schematic diagrams of the cross-section of CAAC-OS.

[0046] Figures 29A to 29D It is a Cs-corrected high-resolution TEM image of the CAAC-OS plane;

[0047] Figures 30A to 30C This is a figure illustrating the structural analysis results of CAAC-OS and single-crystal oxide semiconductors obtained by XRD;

[0048] Figure 31A and Figure 31B This is a diagram showing the electron diffraction pattern of CAAC-OS;

[0049] Figure 32 This is a diagram showing the changes in the crystal structure of In-Ga-Zn oxide after electron irradiation;

[0050] Figure 33A and Figure 33B This is a circuit diagram illustrating a semiconductor device according to one aspect of the present invention;

[0051] Figure 34 This is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention;

[0052] Figure 35 This is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention;

[0053] Figure 36 This is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention;

[0054] Figure 37A and Figure 37B This is a circuit diagram illustrating a storage device according to one aspect of the present invention;

[0055] Figure 38 This is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention;

[0056] Figure 39 This is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention;

[0057] Figure 40 This is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention;

[0058] Figure 41 This is a circuit diagram illustrating a semiconductor device according to one aspect of the present invention;

[0059] Figure 42 This is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention;

[0060] Figures 43A to 43E This is a circuit diagram illustrating a semiconductor device according to one aspect of the present invention;

[0061] Figure 44A and Figure 44B This is a top view illustrating a semiconductor device according to one aspect of the present invention;

[0062] Figure 45A and Figure 45B This is a block diagram illustrating a semiconductor device according to one aspect of the present invention;

[0063] Figure 46A and Figure 46B This is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention;

[0064] Figure 47A and Figure 47B This is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention;

[0065] Figure 48A1 , Figure 48A2 , Figure 48A3 , Figure 48B1 , Figure 48B2 and Figure 48B3 This is a perspective view and a cross-sectional view illustrating a semiconductor device according to one aspect of the present invention;

[0066] Figure 49 This is a block diagram illustrating a semiconductor device according to one aspect of the present invention;

[0067] Figure 50 This is a circuit diagram illustrating a semiconductor device according to one aspect of the present invention;

[0068] Figures 51A to 51C This is a circuit diagram, top view, and cross-sectional view of a semiconductor device illustrating one aspect of the present invention;

[0069] Figure 52A and Figure 52B This is a circuit diagram and cross-sectional view of a semiconductor device illustrating one aspect of the present invention;

[0070] Figures 53A to 53F This is a perspective view illustrating an electronic device according to one aspect of the present invention;

[0071] Figure 54A and Figure 54B This is a surface state image of a sample from one embodiment of Example 1;

[0072] Figures 55A to 55D A bright-field image of a sample from one embodiment of Example 2, observed using a scanning transmission electron microscope;

[0073] Figures 56A to 56C This is a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. Detailed Implementation

[0074] Embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in various forms. Furthermore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below. Note that when the structure of the invention is illustrated using the accompanying drawings, reference numerals denoteing the same objects are used in the same figures. Additionally, sometimes the same shading patterns are used to denote the same parts without specifically adding reference numerals.

[0075] Note that in the accompanying drawings, dimensions, film (layer) thickness, or areas are sometimes exaggerated for clarity.

[0076] Note that in this specification, for example, when describing the shape of an object, the length of one side of the smallest cube that contains the object or the equivalent circle diameter of the object's cross-section may be interpreted as the object's "diameter," "grain size," "size," "dimension," "width," etc. The equivalent circle diameter of an object's cross-section refers to the diameter of a perfect circle having the same area as one cross-section of the object.

[0077] Voltage generally refers to the potential difference between a certain potential and a reference potential (e.g., ground potential (GND) or source potential). Therefore, voltage can be referred to as potential.

[0078] Furthermore, for convenience, ordinal numbers such as "first," "second," etc., are added, but they do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for description. In addition, the ordinal numbers described in this specification and other documents are sometimes inconsistent with the ordinal numbers used to specify one aspect of the present invention.

[0079] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration of less than 0.1 atomic% are considered impurities. Sometimes, the presence of impurities can lead to the formation of DOS (Density of States) in the semiconductor, decreased carrier mobility, or decreased crystallinity. When the semiconductor is an oxide semiconductor, impurities that alter its properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, especially, for example, hydrogen (in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In oxide semiconductors, the incorporation of impurities such as hydrogen can sometimes lead to the creation of oxygen vacancies. Furthermore, when the semiconductor is silicon, impurities that alter its properties include, for example, oxygen, Group 1 elements (excluding hydrogen), Group 2 elements, Group 13 elements, and Group 15 elements.

[0080] Note that channel length refers, for example, to the distance between the overlapping region of the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on-state) and the gate electrode in a top view of the transistor, or between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region forming the channel. Furthermore, the channel length in a transistor is not necessarily the same in all regions. That is, the channel length of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel length refers to any value, maximum, minimum, or average value in the region forming the channel.

[0081] Channel width refers, for example, to the length of the overlapping region between the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) and the gate electrode, or the portion of the region forming the channel where the source and drain electrodes face each other. Furthermore, the channel width in a transistor is not necessarily the same across all regions. That is, the channel width of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel width refers to any value, maximum, minimum, or average value within the region forming the channel.

[0082] Furthermore, in some transistor structures, the actual channel width (hereinafter referred to as the effective channel width) in the region forming the channel sometimes differs from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in transistors with a three-dimensional structure, the effect cannot be ignored because the effective channel width is sometimes greater than the apparent channel width shown in the top view of the transistor. For example, in transistors with a fine and three-dimensional structure, the proportion of channel regions formed on the semiconductor sidewalls is sometimes large. In this case, the actual effective channel width forming the channel is greater than the apparent channel width shown in the top view.

[0083] In transistors with three-dimensional structures, it is sometimes difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width based on design values, it is necessary to know the assumed shape of the semiconductor beforehand. Therefore, when the shape of the semiconductor is unclear, it is difficult to accurately measure the effective channel width.

[0084] Therefore, in this specification, the length of the portion of the source and drain opposite each other in the overlapping area of ​​the semiconductor and gate electrodes in a top view of a transistor, i.e., the apparent channel width, is sometimes referred to as the "surrounded channel width (SCW)". Furthermore, in this specification, when simply described as "channel width", it sometimes refers to both the surrounding channel width and the apparent channel width. Alternatively, in this specification, when simply described as "channel width", it sometimes refers to the actual channel width. Note that the values ​​of channel length, channel width, actual channel width, apparent channel width, surrounding channel width, etc., can be determined by analysis of cross-sectional TEM images, etc.

[0085] Furthermore, when calculating the field-effect mobility of a transistor or the current value per channel width, the calculation is sometimes performed using the width around the channel. In this case, the value may differ from the value calculated using the actual channel width.

[0086] In this specification, "A has a shape in which its ends protrude beyond the ends of B" sometimes means that in a top view or cross-sectional view, at least one end of A is located outside at least one end of B. Thus, for example, the statement "A has a shape in which its ends protrude beyond the ends of B" can be interpreted as one end of A being located outside one end of B in a top view.

[0087] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, it also includes states where the angle is greater than -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, it also includes states where the angle is greater than 85° and less than 95°.

[0088] Note that in this specification, the hexagonal crystal system includes the trigonal and rhombohedral crystal systems.

[0089] Note that in this specification, when referred to as "semiconductor," it can be replaced with "oxide semiconductor." Semiconductors may include: Group 14 semiconductors such as silicon or germanium; compound semiconductors such as silicon carbide, germanium silicide, gallium arsenide, indium phosphide, zinc selenide, and cadmium sulfide; carbon nanotubes; graphene; and organic semiconductors.

[0090] In this specification, "silicon oxynitride film" refers to a film with more oxygen than nitrogen, while "silicon oxynitride film" refers to a film with more nitrogen than oxygen.

[0091] In this specification and the like, when the accompanying drawings or articles illustrating a particular embodiment show at least one specific example, those skilled in the art can readily understand that the broader concept of that specific example can be derived from it. Therefore, when the accompanying drawings or articles illustrating a particular embodiment show at least one specific example, the broader concept of that specific example is also a mode of the disclosed invention, and can constitute a mode of the invention. Furthermore, it can be said that a mode of the invention is clearly defined.

[0092] Furthermore, in this specification and the like, at least the content shown in the accompanying drawings (or even a portion thereof) is one aspect of the disclosed invention and can constitute one aspect of the invention. Therefore, even if a certain content is not described in the text, if that content is shown in the accompanying drawings, it can be said that that content is one aspect of the disclosed invention and can constitute one aspect of the invention. Similarly, a portion of the accompanying drawings is also one aspect of the disclosed invention and can constitute one aspect of the invention. Furthermore, it can be said that one aspect of the invention is clearly defined.

[0093] Furthermore, regarding content not specified in the text or drawings of the specification, it can be stipulated that one aspect of the invention does not include such content. Additionally, when a numerical range for a certain value is described (upper limit, lower limit, etc.), by arbitrarily narrowing the range or removing a portion of the range, it can be stipulated that one aspect of the invention does not include a part of that range. Thus, for example, it can be stipulated that prior art is not included within the technical scope of one aspect of the present invention.

[0094] Implementation Method 1

[0095] <Transistor Structure 1>

[0096] The structure of the transistor included in a semiconductor device according to one aspect of the present invention will now be described.

[0097] Figure 1A , Figure 1B and Figure 1C This is a top view and a cross-sectional view of a semiconductor device according to one aspect of the present invention. Figure 1A It is a top view. Figure 1B It is along Figure 1A The cross-sectional view shown by the dotted line A1-A2 illustrates the cross-sectional shape along the length of the channel. Figure 1C It is along Figure 1A The cross-sectional view shown by the dotted lines A3-A4 illustrates the cross-sectional shape along the width of the channel. Note that... Figure 1A In the top view, some of the constituent elements are omitted for ease of understanding.

[0098] Figures 1A to 1C The transistor shown includes: a conductor 413 and an insulator 401 on a substrate 400; an insulator 402 on the conductor 413 and the insulator 401; an insulator 406a on the insulator 402; a semiconductor 406b on the insulator 406a; conductors 416a and 416b including a region in contact with the top surface of the semiconductor 406b; an insulator 410 having an opening in contact with the top surface of the insulator 402, the top surface of the conductor 416a, and the top surface of the conductor 416b; an insulator 406c in contact with the side surface of the conductor 416a, the top surface and the side surface of the semiconductor 406b; an insulator 412 in contact with the top surface of the insulator 406c and the side surface of the opening of the insulator 410; and a conductor 404 disposed on the semiconductor 406b with respect to the insulator 412 and the insulator 406c and including conductors 404a and 404b. Furthermore, conductor 404b faces the side of the opening of insulator 410 across conductor 404a and insulator 412. The transistor includes: conductor 420 on conductor 404a and conductor 404b; and insulator 408 on insulator 412 and conductor 420. Additionally, as... Figure 56A , Figure 56Band Figure 56C As shown, conductor 413 and insulator 401 are not essential components, and conductor 413 and insulator 401 may be omitted.

[0099] The insulator 406c preferably contains at least one element other than oxygen found in the semiconductor 406b. This suppresses defect formation at the interface between the semiconductor 406b and the insulator 406c. Furthermore, it improves the crystallinity of the insulator 406c.

[0100] Semiconductor 406b and insulator 406c preferably include CAAC-OS as described below. Additionally, insulator 406a also preferably includes CAAC-OS.

[0101] In this transistor, conductors 404a and 404b function as the first gate electrode. Furthermore, it is preferable that at least one of conductors 404a and 404b is a conductor that is not easily permeable to oxygen. For example, by forming an oxygen-impermeable conductor as the lower conductor 404a, the decrease in conductivity caused by oxidation of conductor 404b can be prevented. Additionally, the insulator 412 functions as the first gate insulator.

[0102] Conductor 413 functions as a second gate electrode. Alternatively, conductor 413 can be a multilayer structure including oxygen-impermeable conductors. By employing a multilayer structure including oxygen-impermeable conductors, the decrease in conductivity caused by oxidation of conductor 413 can be prevented. Insulator 402 functions as a second gate insulator. The threshold voltage of the transistor can be controlled by the potential applied to conductor 413. Furthermore, by electrically connecting the first gate electrode and the second gate electrode, the on-state current can be increased. Note that the functions of the first gate electrode and the second gate electrode can be interchanged.

[0103] In addition, conductors 416a and 416b function as source and drain electrodes, respectively. Note that the conductivity of the conductors can be measured using methods such as the two-terminal method.

[0104] The resistance of semiconductor 406b can be controlled by the potential applied to conductor 404. In other words, the conduction / non-conduction between conductor 416a and conductor 416b can be controlled by the potential applied to conductor 404.

[0105] like Figure 1BAs shown, the top surface of semiconductor 406b is in contact with conductors 416a and 416b. Furthermore, the semiconductor 406b can be surrounded by the electric field of conductor 404, which functions as a gate electrode. A transistor structure in which the semiconductor is surrounded by the electric field of the gate electrode is called a surrounded channel (S-channel) structure. Therefore, a channel is sometimes formed throughout the entire semiconductor 406b. In an S-channel structure, a large current can flow between the source and drain of the transistor, thereby increasing the on-state current. Additionally, since semiconductor 406b is surrounded by the electric field of conductor 404, the off-state current can be reduced.

[0106] Since the region of the transistor used as the gate electrode in this embodiment is formed in a self-aligned manner to fill the opening formed in the insulator 410, the transistor can also be called TGSA s-channel FET (Trench Gate Self Align s-channel FET).

[0107] Here, in Figure 1B In the process, the length between the top surface of the semiconductor 406b and the bottom surface of the conductor 404 in the region overlapping with the conductor 404 is t1. Additionally, in... Figure 1B In this context, the length between the region of semiconductor 406b overlapping the bottom surface of conductor 416a and the region of semiconductor 406b overlapping the bottom surface of conductor 404 is L1. Alternatively, the length between the region of semiconductor 406b overlapping the bottom surface of conductor 416b and the region of semiconductor 406b overlapping the bottom surface of conductor 404 is L1.

[0108] In a transistor, an L1 region is formed between the region in semiconductor 406b where the channel is formed (the region where conductor 404 overlaps with semiconductor 406b) and the source or drain region (the region where conductor 416a or conductor 416b overlaps with semiconductor 406b). By including this region, the off-state current of the transistor can be reduced; however, if this region is too large, the on-state current of the transistor will decrease.

[0109] Furthermore, by covering the region of the semiconductor 406b that forms the channel with insulator 406c, elements other than oxygen (hydrogen, silicon, etc.) constituting the adjacent insulator can be prevented from entering the region of the channel. Therefore, insulator 406c only needs to be formed on semiconductor 406b.

[0110] Therefore, by providing an insulator 406c on the side of the conductor 404 without separating it from the insulator 412, or by making the area of ​​the insulator 406c covering the side of the conductor 404 through the insulator 412 thinner than the area of ​​the insulator 406c overlapping the bottom surface of the conductor 404 through the insulator 412, L1 can be reduced. Therefore, t1 is greater than L1 and L1 / t1 is less than 1.

[0111] exist Figure 1B In this context, the length between conductor 416a or conductor 416b and conductor 420 is t2. Additionally, in... Figure 1B In the figure, the length between conductor 416a and conductor 416b is L2.

[0112] The more miniaturized a transistor becomes, the more significant the parasitic capacitance near the transistor becomes. For example, parasitic capacitance sometimes forms between conductor 420 and conductor 416a or conductor 416b. When the parasitic capacitance near the channel region is large, the time required to charge the parasitic capacitance during transistor operation degrades the transistor's susceptibility and even the susceptibility of the semiconductor device. Furthermore, the power consumption increases in circuits composed of multiple transistors due to the excess power consumed in charging the parasitic capacitance. Therefore, t2 preferably has a sufficient length so that the parasitic capacitance is almost negligible compared to the gate capacitance.

[0113] Furthermore, the more miniaturized the transistor, the smaller L2 becomes, making it difficult to apply sufficient voltage to conductors 404a and 404b. However, by designing t2 to be of sufficient length, the resistance of conductors 404a and 404b can be reduced. Therefore, t2 is at least greater than L2, and preferably t2 / L2 is 1.5 or more and 2 or less.

[0114] As the substrate 400, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used, for example. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium-stabilized zirconium oxide substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of a single material such as silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates can also be used, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples of insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators can also be used. Alternatively, substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0115] Alternatively, a flexible substrate can be used as substrate 400. Another method for forming a transistor on a flexible substrate is to form a transistor on a non-flexible substrate, then peel off the transistor and transfer it to substrate 400 on the flexible substrate. In this case, it is preferable to provide a release layer between the non-flexible substrate and the transistor. Alternatively, a sheet, film, or foil containing fibers can be used as substrate 400. Furthermore, substrate 400 can also be stretchable. Additionally, substrate 400 can have the property of returning to its original shape when bending or stretching stops. Alternatively, it can have the property of not returning to its original shape. Substrate 400, for example, includes a region with a thickness of 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less. By forming substrate 400 thin, the semiconductor device including the transistor can be made lightweight. Furthermore, by forming the substrate 400 thin, even when using glass or the like, the substrate 400 may sometimes exhibit stretchability or the property of returning to its original shape when bending or stretching ceases. Therefore, it is possible to mitigate impacts on the semiconductor device on the substrate 400 caused by drops or other factors. In other words, it is possible to provide a semiconductor device with high durability.

[0116] The substrate 400 of the flexible substrate can be made of, for example, metal, alloy, resin, glass, or its fibers. A lower coefficient of linear expansion of the flexible substrate 400 is preferred, as it suppresses deformation caused by environmental factors. For example, the substrate 400 of the flexible substrate can use a coefficient of linear expansion of 1 × 10⁻⁶. -3 / K or less, 5×10 -5 / K or less or 1×10 -5 Materials with a coefficient of linear expansion of less than / K. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic resin, etc. Aromatic polyamides, in particular, have a low coefficient of linear expansion, therefore, the substrate 400 of the flexible substrate is preferably made of aromatic polyamide.

[0117] Note that by surrounding the transistor with an insulator that blocks impurities such as hydrogen and oxygen, the transistor's electrical characteristics can be stabilized. For example, an insulator that blocks impurities such as hydrogen and oxygen can be used as insulator 408.

[0118] As an insulator that can block impurities such as hydrogen and oxygen, a single layer or stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used.

[0119] Alternatively, insulator 408 can be formed using aluminum oxide, magnesium oxide, silicon oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. In addition, insulator 408 preferably contains aluminum oxide. For example, when insulator 408 is formed using oxygen-containing plasma, oxygen can be added to the insulator 410, which forms the base layer of insulator 408. Alternatively, oxygen can be added to the sidewalls of insulator 412. The added oxygen becomes excess oxygen in insulator 410 or insulator 412. By including aluminum oxide in insulator 408, impurities such as hydrogen can be suppressed from entering semiconductor 406b. Furthermore, by including aluminum oxide in insulator 408, for example, the outward diffusion of excess oxygen added to insulator 410 and insulator 412 can be reduced.

[0120] As the insulator 402, for example, a single layer or a stack of insulators comprising boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. For example, the insulator 402 preferably comprises silicon oxide or silicon oxynitride.

[0121] Note that the insulator 410 preferably comprises an insulator with a low relative permittivity. For example, the insulator 410 preferably comprises silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen, porous silicon oxide, or resin, etc. Alternatively, the insulator 410 preferably has a laminated structure of resin and one of the following materials: silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen, or porous silicon oxide. Because silicon oxide and silicon oxynitride are thermally stable, a thermally stable laminated structure with a low relative permittivity can be obtained by combining them with a resin. Examples of resins include polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, acrylic resins, etc.

[0122] As the insulator 412, for example, a single layer or a stack of insulators comprising boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. For example, the insulator 412 preferably comprises silicon oxide or silicon oxynitride.

[0123] Note that insulator 412 preferably comprises an insulator with a high dielectric constant. For example, insulator 412 preferably comprises gallium oxide, hafnium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, or an oxynitride containing silicon and hafnium. Alternatively, insulator 412 preferably has a stacked structure of silicon oxide or silicon oxynitride and an insulator with a high dielectric constant. Because silicon oxide and silicon oxynitride have thermal stability, a thermally stable and high dielectric constant stacked structure can be achieved by combining them with an insulator with a high dielectric constant. For example, when aluminum oxide, gallium oxide, or hafnium oxide of insulator 412 is located on the side of insulator 406c, silicon contained in silicon oxide or silicon oxynitride can be suppressed from mixing into semiconductor 406b. In addition, for example, when silicon oxide or silicon oxynitride is located on the side of insulator 406c, trap centers may sometimes be formed at the interface between aluminum oxide, gallium oxide, or hafnium oxide and silicon oxide or silicon oxynitride. The trap center can sometimes cause the threshold voltage of a transistor to drift in the positive direction by trapping electrons.

[0124] As conductors 416a and 416b, for example, a single layer or stack of conductors comprising one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, platinum, silver, indium, tin, tantalum, and tungsten can be used. For example, alloy films or compound films can also be used, and conductors comprising aluminum, copper and titanium, copper and manganese, indium, tin and oxygen, or titanium and nitrogen can be used.

[0125] As conductors 404, 413, and 420, single layers or stacks of conductors comprising one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten can be used. For example, alloy films or compound films can also be used, and conductors comprising aluminum, copper and titanium, copper and manganese, indium, tin and oxygen, or titanium and nitrogen can be used.

[0126] As for semiconductor 406b, oxide semiconductors are preferred. Note that silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors may sometimes be used.

[0127] As insulators 406a and 406c, oxides composed of one or more elements other than oxygen constituting semiconductor 406b are preferably used. Note that silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors may sometimes be used.

[0128] Semiconductor 406b is, for example, an oxide semiconductor. For example, when semiconductor 406b contains indium, its carrier mobility (electron mobility) is improved. Furthermore, semiconductor 406b preferably contains element M. Element M is preferably aluminum, gallium, yttrium, or tin. Other elements that can be used as element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that multiple of the above elements can sometimes be combined as element M. Element M is, for example, an element with a high bond energy with oxygen. Element M is an element with a higher bond energy with oxygen than indium. Alternatively, element M is, for example, an element that has the function of increasing the band gap of the oxide semiconductor. Additionally, semiconductor 406b preferably contains zinc. When an oxide semiconductor contains zinc, it is sometimes easier to crystallize.

[0129] Note that semiconductor 406b is not limited to oxide semiconductors. Semiconductor 406b can also be, for example, an oxide semiconductor that does not contain indium but contains zinc, gallium, or tin, such as zinc tin oxide or gallium tin oxide.

[0130] For example, an oxide with a large bandgap is used as the semiconductor 406b. The bandgap of the semiconductor 406b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0131] For example, insulators 406a and 406c are oxides containing one or more elements other than oxygen that constitute semiconductor 406b. Because insulators 406a and 406c contain one or more elements other than oxygen that constitute semiconductor 406b, defect states are not easily formed at the interface between insulator 406a and semiconductor 406b, or at the interface between semiconductor 406b and insulator 406c.

[0132] The semiconductor 406b uses an oxide whose electron affinity is greater than that of the insulators 406a and 406c. For example, the semiconductor 406b uses an oxide whose electron affinity is greater than that of the insulators 406a and 406c by 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less. Note that electron affinity is the energy difference between the vacuum level and the conduction band bottom.

[0133] Thus, if a gate voltage is applied to a transistor in which insulators 406a and 406c are respectively disposed above and below semiconductor 406b, a channel is formed in semiconductor 406b, which has the highest electron affinity among insulators 406a, 406b, and 406c. This can form a so-called buried channel structure.

[0134] Here, sometimes a mixed region of insulator 406a and semiconductor 406b exists between insulator 406a and semiconductor 406b. Additionally, sometimes a mixed region of semiconductor 406b and insulator 406c exists between semiconductor 406b and insulator 406c. The defect state density in the mixed region is low. Therefore, in the stack of insulator 406a, semiconductor 406b, and insulator 406c, the energy at and near the interfaces between the layers changes continuously (also known as continuous bonding). Note that sometimes the interfaces of insulator 406a, semiconductor 406b, and insulator 406c cannot be clearly distinguished.

[0135] At this time, electrons do not move in insulators 406a and 406c, but mainly in semiconductor 406b.

[0136] The fewer obstacles that hinder electron movement, the higher the on-state current of the transistor can be. For example, electron movement can be hindered if there are large physical irregularities in the channel formation region.

[0137] To improve the on-state current of the transistor, for example, the root mean square (RMS) roughness of the top or bottom surface (the formed surface, in this case, the top surface of the insulator 406a) of the semiconductor 406b in the range of 1 μm × 1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. Additionally, its average surface roughness (also known as Ra) in the range of 1 μm × 1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. Its maximum difference (also known as PV) in the range of 1 μm × 1 μm is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and even more preferably less than 7 nm. The RMS roughness, Ra, and PV can be measured using a scanning probe microscope such as the SPA-500 manufactured by SIINano Technology Co., Ltd.

[0138] The three-layer structure described above is merely one example. For instance, a stacked structure may also be used, having any one of the insulators exemplified as insulator 406a or insulator 406c on or under insulator 406a.

[0139] Note that oxide semiconductors, which can be used as semiconductors, are described in detail in other embodiments.

[0140] <Transistor Manufacturing Method 1>

[0141] Below, refer to Figures 7A to 9D For the present invention Figures 1A to 1C The manufacturing method of the transistor shown will be explained.

[0142] First, prepare the substrate 400.

[0143] Next, as Figure 7A and Figure 7B As shown, an insulator 401, which will become an insulator, is formed on a substrate 400. An opening is formed in the insulator 401, and a conductor 413, which will become a conductor, is formed on the insulator 401. The conductor 413 can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD. Alternatively, the conductor 413 can be a multilayer structure including a conductor that is not easily permeable to oxygen (or, in other words, a conductor with high stability against oxidation). The conductor 413 can be embedded into the opening of the insulator 401 using methods such as chemical mechanical polishing (CMP). Alternatively, as another method for forming the conductor 413, the conductor can be formed and processed using methods such as photolithography to form the conductor 413.

[0144] Note that in photolithography, the resist is first exposed through a mask. Next, a developer is used to remove or leave the exposed areas, forming a resist mask. Then, etching is performed through this resist mask to process conductors, semiconductors, or insulators into the desired shape. For example, the resist mask is formed by exposing the resist using KrF stimulated excimer lasers, ArF stimulated excimer lasers, or EUV (Extreme Ultraviolet) light. Alternatively, immersion techniques can be used, where exposure is performed with liquid (e.g., water) filling the space between the substrate and the projection lens. Electron beams or ion beams can also be used instead of the aforementioned light. Furthermore, the resist mask can be removed by performing dry etching (such as ashing) or wet etching, or by performing wet etching after dry etching, or dry etching after wet etching.

[0145] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel planar electrodes can be used. This apparatus can apply a high-frequency power supply to one of the parallel planar electrodes; it can apply multiple different high-frequency power supplies to one of the parallel planar electrodes; it can apply a high-frequency power supply of the same frequency to each of the parallel planar electrodes; or it can apply high-frequency power supplies of different frequencies to each of the parallel planar electrodes. Furthermore, a dry etching apparatus including a high-density plasma source can also be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus including a high-density plasma source.

[0146] Next, as Figure 7A or Figure 7B As indicated by the arrows, high-density plasma treatment can also be performed. High-density plasma treatment is preferably performed in an oxygen atmosphere or a nitrogen atmosphere. An oxygen atmosphere is a gaseous atmosphere containing oxygen atoms, specifically an atmosphere containing oxygen, ozone, or nitrogen oxides (nitric oxide, nitrogen dioxide, nitrous oxide, dinitrogen trioxide, dinitrogen tetroxide, or dinitrogen pentoxide, etc.). Alternatively, the oxygen atmosphere may also contain nitrogen or an inert gas such as a rare gas (helium, argon, etc.). Thus, by performing high-density plasma treatment in an oxygen atmosphere, for example, carbon and hydrogen can be removed. Furthermore, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can be easily removed from the treated material.

[0147] As a high-density plasma treatment under a nitrogen atmosphere, the above-mentioned high-density plasma treatment can be performed, for example, in an atmosphere containing nitrogen and rare gases, in an atmosphere containing nitrogen, hydrogen and rare gases, or in an atmosphere containing ammonia and rare gases. By performing high-density plasma treatment under a nitrogen atmosphere, the surface of the workpiece and its vicinity can be nitrided. An extremely thin nitrided region can be formed on one side of the surface of the workpiece. This nitrided region can suppress the diffusion of impurities.

[0148] High-density plasma treatment can be performed in an oxygen atmosphere followed by high-density plasma treatment in a nitrogen atmosphere, or vice versa. Annealing treatment can also be performed before and after each high-density plasma treatment. Furthermore, to increase the plasma density, it is sometimes preferable to supply a sufficient amount of gas. If the amount of gas is insufficient, the deactivation rate of free radicals may sometimes exceed the generation rate. For example, it is sometimes preferable to supply gas at a density of 100 sccm or higher, 300 sccm or higher, or 800 sccm or higher.

[0149] In high-density plasma processing, microwaves generated by a high-frequency generator with a frequency of 0.3 GHz or higher and 3.0 GHz or lower, 0.7 GHz or higher and 1.1 GHz or lower, or 2.2 GHz or higher and 2.8 GHz or lower (typically 2.45 GHz) can be used. Furthermore, the processing pressure can be 10 Pa or higher and 5000 Pa or lower, preferably 200 Pa or higher and 1500 Pa or lower, more preferably 300 Pa or higher and 1000 Pa or lower, the substrate temperature can be 100 °C or higher and 600 °C or lower (typically 400 °C), and a mixture of oxygen and argon can be used.

[0150] High-density plasma is generated, for example, by using 2.45 GHz microwaves, preferably at a density of 1 × 10⁻⁶ GHz. 11 / cm 3 Above and 1×10 13 / cm 3 The treatment is performed at electron densities below 2 eV, electron temperatures below 2 eV, or ion energies below 5 eV. In such high-density plasma treatment, the kinetic energy of free radicals is low, and the damage caused by plasma is also less compared to conventional plasma treatments. Therefore, films with fewer defects can be formed. The distance from the antenna generating the microwaves to the workpiece is 5 mm or more and 120 mm or less, preferably 20 mm or more and 60 mm or less.

[0151] Alternatively, a plasma power supply that applies an RF (Radio Frequency) bias to the substrate can be used. The RF bias frequency can be, for example, 13.56 MHz or 27.12 MHz. High-density plasma can generate a high density of oxygen ions, and by applying an RF bias to one side of the substrate, the oxygen ions generated by the high-density plasma can be efficiently introduced into the workpiece. Therefore, it is preferable to perform high-density plasma treatment while applying a bias to the substrate.

[0152] After high-density plasma treatment, annealing can be performed continuously without exposure to the atmosphere. Alternatively, high-density plasma treatment can be performed continuously after annealing without exposure to the atmosphere. By continuously performing high-density plasma treatment and annealing, the introduction of impurities during the treatment process can be suppressed. Furthermore, by performing high-density plasma treatment in an oxygen atmosphere followed by annealing, excess oxygen added to the workpiece that was not used to fill oxygen vacancies can be removed. Additionally, the aforementioned annealing process can be, for example, lamp annealing.

[0153] In addition, the processing time for high-density plasma treatment is preferably 30 seconds or more and 120 minutes or less, 1 minute or more and 90 minutes or less, 2 minutes or more and 30 minutes or less, or 3 minutes or more and 15 minutes or less.

[0154] In addition, the annealing temperature is preferably above 250°C and below 800°C, above 300°C and below 700°C, or above 400°C and below 600°C, and the processing time is preferably above 30 seconds and below 120 minutes, above 1 minute and below 90 minutes, above 2 minutes and below 30 minutes, or above 3 minutes and below 15 minutes.

[0155] Next, insulator 402 is formed. Insulator 402 can be formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), etc.

[0156] CVD methods can be categorized into plasma-enhanced CVD (PECVD), thermal CVD (TCVD), and photoCVD. Furthermore, they can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0157] PECVD can produce high-quality films at relatively low temperatures. Furthermore, because thermal CVD does not use plasma, it reduces plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes experience charge buildup by receiving charge from plasma. This charge buildup can sometimes damage the wiring, electrodes, and components. On the other hand, when using thermal CVD without plasma, the aforementioned damage caused by plasma exposure is avoided, thus improving the yield of semiconductor devices. Additionally, because the workpiece is not exposed to plasma during deposition in thermal CVD, films with fewer defects are more easily obtained.

[0158] In addition, the ALD method can reduce plasma damage to the treated material. Furthermore, the ALD method does not generate plasma damage during deposition, thus yielding films with fewer defects.

[0159] Unlike deposition methods that deposit particles released from a target or similar material, CVD and ALD methods form films through reactions on the surface of the workpiece. Therefore, CVD and ALD methods can achieve good step coverage and are less affected by the shape of the workpiece. In particular, ALD achieves good step coverage and thickness uniformity, making it suitable for forming films covering surfaces with high aspect ratio openings. However, because ALD has a relatively slow deposition rate, it is sometimes preferred to combine it with other deposition methods, such as CVD, which has a faster deposition rate.

[0160] CVD and ALD methods allow for control of the film composition by adjusting the source gas flow rate ratio. For example, in CVD and ALD, films with arbitrary compositions can be formed by adjusting the source gas flow rate ratio. Furthermore, in CVD and ALD, films with continuously varying compositions can be formed by changing the source gas flow rate ratio while the film is being formed. When the source gas flow rate ratio is changed simultaneously with deposition, the time required for transport and pressure adjustment can be eliminated, thus reducing the time required for film formation compared to deposition using multiple chambers. Therefore, the productivity of semiconductor devices can be improved.

[0161] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0162] Alternatively, oxygen can be added to the insulator 402. Examples of oxygen addition methods include ion implantation and plasma treatment. However, the oxygen added to the insulator 402 becomes excess oxygen.

[0163] Next, as Figure 7C and Figure 7D As shown, an insulator that will become an insulator 406a, a semiconductor that will become a semiconductor 406b, and a resist mask 430 are formed.

[0164] First, an insulator that will become insulator 406a is formed on insulator 402. The insulator that will become insulator 406a can be formed using sputtering, CVD, MBE, PLD, or ALD methods, etc. In particular, it is preferred to form the insulator using an opposed target sputtering apparatus. Note that in this specification and the like, the deposition method using an opposed target sputtering apparatus can also be referred to as VDSP (vapor deposition sputtering).

[0165] By using a counter-target sputtering apparatus to form insulators, plasma damage during insulator formation can be reduced. This reduces oxygen vacancies in the film. Furthermore, using a counter-target sputtering apparatus allows deposition to be performed under high vacuum. This reduces the concentration of impurities (e.g., hydrogen, rare gases (argon, etc.), water, etc.) in the formed insulator.

[0166] Alternatively, a sputtering apparatus with an inductively coupled antenna conductor plate can be used. This allows for the formation of large-area films with high uniformity at high deposition rates.

[0167] Preferred gases include those containing oxygen, rare gases, and those containing nitrogen. For example, nitrogen (N2), nitrous oxide (N2O), and ammonia (NH3) can be used as nitrogen-containing gases.

[0168] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0169] Alternatively, oxygen can be added to the insulator that will become insulator 406a. Methods for adding oxygen include ion implantation and plasma treatment. Furthermore, the oxygen added to the insulator that will become insulator 406a is excess oxygen.

[0170] Next, a semiconductor 406b is formed on the insulator that will become insulator 406a. The semiconductor can be formed using sputtering, CVD, MBE, PLD, or ALD methods. In particular, it is preferable to form the semiconductor using a facing target sputtering apparatus.

[0171] By using a counter-target sputtering apparatus to form semiconductors, plasma damage during semiconductor formation can be reduced. This reduces oxygen vacancies in the film. Furthermore, using a counter-target sputtering apparatus allows deposition to be performed under high vacuum. This reduces the concentration of impurities (e.g., hydrogen, rare gases (argon, etc.), water, etc.) in the formed semiconductor.

[0172] Alternatively, a sputtering apparatus with an inductively coupled antenna conductor plate can be used. This allows for the formation of large-area films with high uniformity at high deposition rates.

[0173] Preferred gases include those containing oxygen, rare gases, and those containing nitrogen. For example, nitrogen (N2), nitrous oxide (N2O), and ammonia (NH3) can be used as nitrogen-containing gases.

[0174] Next, a first heat treatment is preferably performed. The first heat treatment is performed at a temperature of 250°C or higher and 650°C or lower, preferably 450°C or higher and 600°C or lower. The first heat treatment is performed in an inert gas atmosphere or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. The first heat treatment can also be performed under reduced pressure. Alternatively, in the first heat treatment, heat treatment can be performed in an inert gas atmosphere, and then heat treatment can be performed in an oxidizing gas atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher to replenish the released oxygen. By performing the first heat treatment, the crystallinity of the semiconductor can be improved, and impurities such as hydrogen or water can be removed. Alternatively, in the first heat treatment, plasma treatment containing oxygen can also be performed under reduced pressure. For example, plasma treatment containing oxygen preferably employs a device including a power supply that uses microwaves to generate high-density plasma. Alternatively, a plasma power supply that applies an RF voltage to one side of the substrate can also be included. By using high-density plasma, high-density oxygen radicals can be generated, and by applying an RF voltage to one side of the substrate, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the semiconductor 406b. Alternatively, after plasma treatment with an inert gas using such a device, an oxygen-containing plasma treatment can be performed to replenish the detached oxygen.

[0175] Next, as Figure 7E and Figure 7F As shown, using a resist mask 430, the insulator 406a (which will become the insulator) and the semiconductor 406b (which will become the semiconductor) are processed by photolithography or the like, thereby forming a multilayer film including the insulator 406a and the semiconductor 406b. Note that during the formation of the multilayer film, the insulator 402 is sometimes etched, and a portion of it becomes thinner. That is, the insulator 402 sometimes has protrusions in the areas that contact the multilayer film.

[0176] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0177] Next, as Figure 7G and Figure 7H As shown, an insulator is formed that will become both conductor 416 and insulator 410.

[0178] First, a conductor 416 is formed. The conductor 416 can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0179] Note that the conductor 416 is covered by a multilayer film. When the conductor is formed on this multilayer film, damage is caused to the side surfaces of the insulator 406a, the top surface of the semiconductor 406b, and a portion of the side surfaces of the semiconductor 406b, sometimes resulting in low-resistance regions. Because a portion of the insulator 406a and the semiconductor 406b has low-resistance regions, the contact resistance between the conductor 416 and the semiconductor 406b can be reduced.

[0180] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0181] Next, the conductor 416 is processed using photolithography and other methods to form conductor 416a and conductor 416b.

[0182] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0183] Next, the insulator that will become insulator 410 is formed. The insulator that will become insulator 410 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. Alternatively, it can be formed using spin coating, dip coating, droplet jetting (inkjet, etc.), printing (screen printing, offset printing, etc.), doctor knife coating, roll coating, or curtain coating.

[0184] The insulator that will become insulator 410 can be formed in a manner where its top surface is flat. For example, the top surface of the insulator that will become insulator 410 can be flat immediately after film formation. Alternatively, for example, after film formation, the upper part of the insulator that will become insulator 410 can be removed with its top surface parallel to a reference surface such as the back surface of the substrate. This process is called planarization. Planarization processes include chemical mechanical polishing, dry etching, etc. However, the top surface of the insulator that will become insulator 410 may not be flat.

[0185] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0186] Next, a photoresist mask 431 is formed on the insulator that will become the insulator 410 using photolithography or the like. Here, in order to improve the tightness between the top surface of the insulator that will become the insulator 410 and the photoresist mask 431, for example, an organic coating film can be disposed between the top surface of the insulator that will become the insulator 410 and the photoresist mask 431.

[0187] Next, as Figure 8A and Figure 8B As shown, openings are formed in the insulator 410 and the conductor 416. First, after forming the resist mask 431, the insulator that will become the insulator 410 is first processed using a dry etching method or the like, so that the top surface of the conductor 416 is exposed. The dry etching apparatus described above can be used in the dry etching method, but it is preferable to use a dry etching apparatus that connects high-frequency power supplies of different frequencies to each parallel planar electrode.

[0188] Next, the conductor 416 is further processed by a second process, such as dry etching, to separate it into conductor 416a and conductor 416b. Note that the processing of the insulator 410 and the conductor 416 can be performed in the same photolithography process. By performing these processes in the same photolithography process, the number of steps can be reduced. Therefore, the productivity of semiconductor devices, including transistors, can be improved.

[0189] At this point, the semiconductor 406b includes an exposed area. Through the second processing described above, sometimes a portion of the exposed area of ​​the semiconductor 406b is removed. Additionally, impurity elements such as residual components of the etching gas may sometimes adhere to the exposed semiconductor 406b. For example, when a chlorine-based gas is used as the etching gas, chlorine may sometimes adhere. Furthermore, when a hydrocarbon gas is used as the etching gas, carbon or hydrogen may sometimes adhere. Therefore, it is preferable to reduce the impurity elements adhering to the exposed surface of the semiconductor 406b. For example, this can be reduced by using a washing process with dilute hydrofluoric acid, a washing process with ozone, or a washing process with ultraviolet light. Furthermore, multiple washing processes can be combined. As a result, the exposed surface of the semiconductor 406b, that is, the area where the channel is formed, becomes highly resistive.

[0190] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0191] Next, as Figure 8C and Figure 8DAs shown, an insulator 406c is formed on at least the top and side surfaces of the semiconductor 406b (excluding the side surface of the insulator 410), the side surface of the insulator 406a, the top surface of the insulator 402, and the top surface of the insulator 410. The insulator 406c can be formed using a sputtering method.

[0192] Here, refer to Figure 21 and Figure 22 The sputtering apparatus used to form insulator 406c is described.

[0193] Figure 21 This is a cross-sectional view showing a portion of the sputtering apparatus 101. Figure 21 The sputtering apparatus 101 shown includes: a component 190; a collimator 150 disposed on the component 190; a target holder 120; a pad 110 on the target holder 120; a target 100 on the pad 110; a magnet unit 130 including magnets 130N and 130S disposed below the target 100 across the pad 110; and a magnet holder 132 supporting the magnet unit 130. In this specification, the plurality of magnets are referred to as a magnet unit. A magnet unit may also be referred to as a cathode, cathode magnet, magnetic component, magnetic part, etc.

[0194] The substrate stage 170, arranged facing the target 100, and the substrate 160 supported by the substrate stage 170 are also shown. In addition, magnetic lines of force 180a and magnetic lines of force 180b formed by the magnet unit 130 are also shown.

[0195] The target holder 120 and the pad 110 are fixed together by bolts or the like and are subjected to the same potential. The target holder 120 supports the target 100 across the pad 110.

[0196] The pad 110 has the function of fixing the target 100.

[0197] The sputtering apparatus 101 may also have water channels inside or at the bottom of the pad 110. By allowing fluid (air, nitrogen, rare gas, water, oil, etc.) to flow through the water channels, abnormal discharge caused by the temperature rise of the target 100 during sputtering or damage to the sputtering apparatus 101 caused by deformation of components such as the target 100 can be suppressed. In this case, it is preferable to use an adhesive member to bond the pad 110 and the target 100 together, as the cooling performance is improved.

[0198] By providing a gasket between the target holder 120 and the pad 110, impurities are less likely to enter the sputtering device 101 from the outside or water channels, which is therefore preferred.

[0199] In the magnet unit 130, magnets 130N and 130S are arranged with different polarities facing the target 100. Here, we will describe the case where the N pole of magnet 130N faces the target 100, and the S pole of magnet 130S faces the target 100. Note that the arrangement of magnets and their polarities in the magnet unit 130 is not limited to this configuration. Figure 21 The configuration shown.

[0200] Magnetic field line 180a is one of the magnetic field lines that form a horizontal magnetic field near the top surface of the target 100. Near the top surface of the target 100 refers, for example, to an area with a vertical distance of 0 mm to 10 mm from the top surface of the target 100, especially 0 mm to 5 mm.

[0201] Magnetic field line 180b is one of the magnetic field lines that forms a horizontal magnetic field at a vertical distance d from the top surface of magnet unit 130. The vertical distance d is, for example, 0 mm or more and 20 mm or less, or 5 mm or more and 15 mm or less.

[0202] During deposition, the potential V1 applied to the target holder 120 is, for example, lower than the potential V2 applied to the substrate stage 170. The potential V2 applied to the substrate stage 170 is, for example, a ground potential. The potential V3 applied to the magnet holder 132 is, for example, a ground potential. Note that potentials V1, V2, and V3 are not limited to the aforementioned potentials. It is also possible not to apply potentials to all three components: the target holder 120, the substrate stage 170, and the magnet holder 132. For example, the substrate stage 170 may also be in an electrically floating state.

[0203] exist Figure 21 The diagram shows an example where the pad 110 and target holder 120 are not electrically connected to the magnet unit 130 and magnet holder 132, but this is not a limitation. For example, the pad 110 and target holder 120 can also be electrically connected to the magnet unit 130 and magnet holder 132 and have the same potential applied to them.

[0204] A deposition gas (e.g., a rare gas such as argon, oxygen, nitrogen, etc.) is supplied to the sputtering apparatus 101 at a fixed pressure (e.g., 0.05 Pa or more and 10 Pa or less, preferably 0.1 Pa or more and 0.8 Pa or less). A potential V1 is applied to the target holder 120, thereby forming plasma in the magnetic field formed by the magnet unit 130. The potential Vp of the plasma is higher than the potential V1. At this time, cations in the plasma are accelerated towards the target 100 due to the potential difference between potential Vp and potential V1. When the cations collide with the target 100, sputtered particles are released. Among the released sputtered particles, the sputtered particles that reach the substrate 160 are deposited to form a film.

[0205] Generally, in sputtering apparatuses, sputtered particles do not easily reach the bottom of the opening, which has a large aspect ratio and a small opening. In addition, sputtered particles flying at an angle to the substrate deposit near the top of the opening, narrowing the top of the opening, so sometimes sputtered particles do not form within the opening.

[0206] On the other hand, by using the sputtering apparatus with the above-described structure, sputtering particles flying obliquely towards the surface of the substrate 160 are attached to the collimator 150 among the released sputtered particles. That is, by providing the collimator 150, sputtering particles passing between the target 100 and the substrate 160 and having a component perpendicular to the substrate 160 reach the substrate. Therefore, they are deposited on a surface parallel to the substrate. On the other hand, sputtering particles are not deposited on a surface perpendicular to the substrate, or the amount of sputtering particles deposited on a surface perpendicular to the substrate is less than the amount deposited on a surface parallel to the substrate. Therefore, by using the above-described sputtering apparatus, such as... Figure 8C and Figure 8D As shown, insulator 406c can be formed on a surface other than the surface perpendicular to the substrate.

[0207] Note that the vertical distance between the target 100 and the collimator 150, or the vertical distance between the substrate 160 and the collimator 150, can be appropriately changed according to the quality of the formed film. Therefore, as... Figure 22 As shown, the collimator 150 may also have a movable part 151 and a movable part 152. By having a movable part 151, it is easier to select whether to use the collimator 150. In addition, by having a movable part 152, it is easier to adjust the vertical distance between the collimator 150 and the substrate 160 and between the collimator 150 and the target 100.

[0208] Alternatively, long-range ballistic sputtering can be used. In long-range ballistic sputtering, by increasing the vertical distance between the target 100 and the substrate 160, the incident direction of the sputtered particles onto the substrate 160 can be made nearly perpendicular. Therefore, even without using the collimator 150, an insulator 406c can be formed on a surface other than the one perpendicular to the substrate. Note that the vertical distance between the substrate 160 and the target 100 should be between 150 mm and 500 mm. Alternatively, long-range ballistic sputtering and the collimator 150 can be combined.

[0209] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0210] Next, as Figure 8E and Figure 8F As shown, an insulator that will become an insulator 412, a conductor that will become a conductor 404a, and a conductor that will become a conductor 404b are formed.

[0211] First, an insulator that will become insulator 412 is formed on insulator 410 and insulator 406c. The insulator that will become insulator 412 can be formed using sputtering, CVD, MBE, PLD, or ALD methods.

[0212] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0213] Next, conductive bodies that will become conductor 404a and conductor 404b are formed. The conductive bodies that will become conductor 404a and conductor 404b can be formed using sputtering, CVD, MBE, PLD, or ALD methods. The conductive bodies that will become conductor 404a and conductor 404b are formed by filling openings formed in the insulator 410, etc. Therefore, CVD (especially MCVD) is preferred. Furthermore, to improve the compactness of the conductor formed by MCVD, it is sometimes preferable to use a laminated film of a conductor formed by ALD and a conductor formed by CVD. For example, a laminated film in which titanium nitride and tungsten are sequentially formed can be used.

[0214] Next, as Figure 9A and Figure 9B As shown, conductors 404a and 404b, insulators 412 and 406c, and finally insulator 410 are removed through CMP processing, etc. At this time, insulator 410 can also be used as a stop layer, so sometimes the thickness of insulator 410 becomes thinner. Therefore, by ensuring that the film thickness of insulator 410 has sufficient margin to sufficiently reduce the resistance of conductors 404a and 404b in the completed transistor, multiple transistors with small deviations can be formed.

[0215] Furthermore, CMP treatment can be performed either once or multiple times. When performing multiple CMP treatments, it is preferable to perform a high-polish initial polishing followed by a low-polish fine polishing. In this way, by combining polishing processes with different polishing rates, the flatness of the polished surface can be further improved.

[0216] Next, a conductive material that will become conductor 420 is formed. Conductor 420 can also be a multilayer structure. The conductive material that will become conductor 420 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. Then, conductor 420 is formed by processing methods such as photolithography.

[0217] Next, as Figure 9C and Figure 9DAs shown, an insulator 408 is formed on insulator 410 and conductor 420. Insulator 408 can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD. It is preferable to form alumina using an oxygen-containing plasma as insulator 408, so that the oxygen in the plasma can be added as excess oxygen (exO) to the top surface of insulator 410. Alternatively, oxygen can diffuse through insulator 410 to insulator 408, adding excess oxygen to insulator 408. Therefore, in this case, a mixed region containing a large amount of excess oxygen may sometimes form at and near the interface between insulator 408 and insulator 410.

[0218] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0219] Furthermore, a second heat treatment can be performed at any time after the formation of insulator 408. Through this second heat treatment, excess oxygen contained in insulator 410 and the mixing region 414 migrates to semiconductor 406b via insulators 412, 402, 406c, and 406a. Thus, because excess oxygen migrates to semiconductor 406b, defects (oxygen vacancies) in semiconductor 406b can be reduced.

[0220] Note that the second heat treatment can be performed at a temperature at which excess oxygen contained in the insulator 410 and the mixing region 414 can diffuse to the semiconductor 406b. For example, the second heat treatment can also refer to the description of the first heat treatment. Alternatively, the temperature at which the second heat treatment is performed is preferably lower than the temperature at which the first heat treatment is performed. The temperature difference between the first heat treatment and the second heat treatment is 20°C or more and 150°C or less, preferably 40°C or more and 100°C or less. This can suppress the release of excess oxygen from the insulator 402, etc. Note that when the heat treatment performed during the formation of each film can also serve as the second heat treatment, sometimes the second heat treatment is not necessary.

[0221] Alternatively, although not shown, openings leading to conductors 416a and 416b may be formed in insulators 408 and 410, and conductors used for wiring may be formed in these openings. Alternatively, an opening leading to conductor 404 may be formed in insulator 408, and conductors used for wiring may be formed in these openings.

[0222] Through the above steps, it is possible to form Figures 1A to 1C The transistor shown.

[0223] In this embodiment, one aspect of the invention is described. However, this aspect of the invention is not limited thereto. That is, various inventive methods are described in one and other embodiments of the invention, thus this aspect of the invention is not limited to a specific method. For example, although one aspect of the invention shows an example of using an oxide semiconductor as the semiconductor, this aspect of the invention is not limited thereto. Depending on the circumstances, silicon, germanium, silicon-germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc., may also be used in one aspect of the invention.

[0224] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0225] Implementation Method 2

[0226] <Transistor Structure 2>

[0227] Below, refer to Figures 2A to 2C to and Figures 1A to 1C Different transistor structures and their manufacturing methods are explained. Figures 2A to 2C A top view and a cross-sectional view of a semiconductor device according to one aspect of the present invention are shown. Figure 2A It is a top view. Figure 2B It corresponds to Figure 2A The cross-sectional view of the dotted line A1-A2 shown. Figure 2C It corresponds to Figure 2A The cross-sectional view shown is along the dashed-dot line A3-A4. Note that... Figure 2A In the top view, some of the constituent elements are omitted for clarity.

[0228] exist Figure 2B In this transistor, the side surface of the insulator 410 has an angle θ greater than 0 degrees and less than 90 degrees with respect to the top surface of the conductor 416a, and an insulator 406c is formed on the side surface of the insulator 410. Note that the angle θ is preferably 75 degrees or more and less than 90 degrees, preferably 80 degrees or more and less than 90 degrees, and more preferably 85 degrees or more and less than 90 degrees. Note that the area where the insulator 406c overlaps with the side surface of the conductor 404 across the insulator 412 is set to be thinner than the area where the bottom surface of the insulator 406c overlaps with the bottom surface of the conductor 404. Other constituent elements refer to [reference needed]. Figures 1A to 1C The transistor shown.

[0229] <Transistor Manufacturing Method 2>

[0230] First, proceed to the implementation method shown in Implementation Method 1. Figure 7H The process up to this point.

[0231] Next, the side surface of the insulator 410 is formed at an angle θ greater than 0 degrees and less than 90 degrees relative to the top surface of the conductor 416a. Then, the insulator 406c is formed using the film-forming apparatus described in Embodiment 1. At this time, for example, the smaller the angle θ, the higher the probability of sputtered particle deposition, thereby forming a thicker insulator 406c on the side surface of the insulator 410. Conversely, the larger the angle θ, the thinner the insulator 406c is formed on the side surface of the insulator 410. Therefore, the film thickness of the insulator 406c formed on the side surface of the insulator 410 can be adjusted according to the angle θ. That is, the width L1 of the formed offset region can be reduced. Therefore, t1 is greater than L1, and L1 / t1 is less than 1.

[0232] The following steps are performed in the same manner as those in the transistor manufacturing method 1 shown in Embodiment 1.

[0233] Through the above steps, it is possible to form Figures 2A to 2C The transistor shown.

[0234] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0235] Implementation Method 3

[0236] <Transistor Structure 3 and Transistor Structure 4>

[0237] Below, refer to Figures 3A to 4C to and Figures 1A to 1C Different transistor structures and their manufacturing methods are explained. Figures 3A to 4C A top view and a cross-sectional view of a semiconductor device according to one aspect of the present invention are shown.

[0238] right Figures 3A to 4C The transistor shown is used for illustration. Figure 3A and Figure 4A It is a top view. Figure 3B It corresponds to Figure 3A The cross-sectional view of the dotted line A1-A2 shown. Figure 3C It corresponds to Figure 3A The cross-sectional view shown is along the dashed-dot line A3-A4. Note that... Figure 3A In the top view, some of the constituent elements are omitted for clarity.

[0239] Figure 4B It corresponds to Figure 4A The cross-sectional view of the dotted line A1-A2 shown. Figure 4C It corresponds to Figure 4A The cross-sectional view shown is along the dashed-dot line A3-A4. Note that... Figure 4A In the top view, some of the constituent elements are omitted for clarity.

[0240] exist Figures 3A to 4C In the transistor shown, the insulator 406c2 (in) Figures 4A to 4C Insulator 406c), insulator 412, conductor 404a, and conductor 404b are also formed in a portion of the top surface of insulator 410. Other constituent elements are referenced. Figures 1A to 1C or Figures 2A to 2C The transistor shown.

[0241] exist Figures 3A to 4C In the transistor shown, a portion of conductors 404a and 404b, which serve as gate electrodes, can also function as wiring. That is, a portion of conductors 404a and 404b formed on insulator 410, separated by insulators 406c and 412, corresponds to conductor 420 in transistor structure 1. Therefore, in this structure, t2 is the perpendicular distance between conductor 416a or conductor 416b and a portion of conductor 404a on insulator 410. Furthermore, since insulators 406c2, 412, conductors 404a, and 404b are formed simultaneously, insulator 406c2 is sandwiched between the top surface of insulator 410 and a portion of conductor 404a on insulator 410 (in...). Figures 4A to 4C The middle part consists of insulator 406c and insulator 412. Therefore, due to t2 (the thickness of insulator 410 plus the thickness of insulator 406c2), Figures 4A to 4C The length of the thickness of insulator 406c and insulator 412 is large enough to suppress parasitic capacitance.

[0242] <Transistor Manufacturing Method 3 and Transistor Manufacturing Method 4>

[0243] Below, on Figures 3A to 3C The manufacturing method of the transistor shown will be explained.

[0244] First, proceed to the implementation method shown in Implementation Method 1. Figure 8F The process up to this point.

[0245] Next, insulator 406c, insulator 412, conductor 404a, and conductor 404b are formed using photolithography and other methods. By adopting this structure, conductors equivalent to conductor 420 in transistor structure 1 can be formed simultaneously using conductors 404a and 404b.

[0246] Next, insulator 408 is formed.

[0247] Through the above steps, it is possible to form Figures 3A to 3C The transistor shown.

[0248] In addition, Figures 4A to 4CIn the transistor shown, through with Figures 2A to 2C The transistor shown is formed using the same process as insulator 406c, insulator 412, conductor 404a, and conductor 404b. Then, insulator 406c, insulator 412, conductor 404a, and conductor 404b are formed into the desired shape using photolithography or the like. By employing this structure, conductors 404a and 404b can be used to form a conductor equivalent to conductor 420 in transistor structure 1.

[0249] Through the above steps, it is possible to form Figures 4A to 4C The transistor shown.

[0250] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0251] Implementation Method 4

[0252] <Transistor Structure 5 and Transistor Structure 6>

[0253] Below, refer to Figures 5A to 6C to and Figures 1A to 1C Different transistor structures and their manufacturing methods are explained. Figures 5A to 6C A top view and a cross-sectional view of a semiconductor device according to one aspect of the present invention are shown.

[0254] right Figures 5A to 6C The transistor shown is used for illustration. Figure 5A and Figure 6A It is a top view. Figure 5B It corresponds to Figure 5A The cross-sectional view of the dotted line A1-A2 shown. Figure 5C It corresponds to Figure 5A The cross-sectional view shown is along the dashed-dot line A3-A4. Note that... Figure 5A In the top view, some of the constituent elements are omitted for clarity.

[0255] Figure 6B It corresponds to Figure 6A The cross-sectional view of the dotted line A1-A2 shown. Figure 6C It corresponds to Figure 6A The cross-sectional view shown is along the dashed-dot line A3-A4. Note that... Figure 6A In the top view, some of the constituent elements are omitted for clarity.

[0256] exist Figures 5A to 6C In the transistor shown, conductors 416a and 416b are formed only on semiconductor 406b. Other constituent elements are referenced. Figures 1A to 1C or Figures 2A to 2C The transistor shown.

[0257] <Transistor Manufacturing Method 5 and Transistor Manufacturing Method 6>

[0258] Below, on Figures 5A to 5C The manufacturing method of the transistor shown will be explained.

[0259] First, proceed to the implementation method shown in Implementation Method 1. Figure 7A and Figure 7B The process up to this point.

[0260] Next, after forming the insulator 406a and the semiconductor 406b, a conductor 416 is formed. Then, a photoresist is formed on the conductor 416 using photolithography or the like, and the conductor 416 is etched using the photoresist as a mask. Next, the photoresist is removed, and then a second etching is performed using the conductor 416 as a mask. The second etching is performed on both the insulator 406a and the semiconductor 406b.

[0261] The following procedures are the same as those in Implementation Method 1. Figure 7G and Figure 7H The subsequent processes are the same. Through the above steps, it is possible to form... Figures 5A to 5C The transistor shown.

[0262] In addition, Figures 6A to 6C The transistor shown also has... Figures 5A to 5C The transistor shown similarly forms an insulator 406a, a semiconductor 406b, and a conductor 416. Then, preferably by means of... Figures 2A to 2C The transistor shown is formed using the same process.

[0263] Through the above steps, it is possible to form Figures 6A to 6C The transistor shown.

[0264] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0265] Implementation Method 5

[0266] <Transistor Structure 7>

[0267] The structure of the transistor included in a semiconductor device according to one aspect of the present invention will now be described.

[0268] Figure 10A , Figure 10B and Figure 10C This is a top view and a cross-sectional view of a semiconductor device according to one aspect of the present invention. Figure 10A It is a top view. Figure 10B It is along Figure 10A The cross-sectional view shown by the dotted line A1-A2 illustrates the cross-sectional shape along the length of the channel. Figure 10C It is along Figure 10AThe cross-sectional view shown by the dotted lines A3-A4 illustrates the cross-sectional shape along the width of the channel. Note that... Figure 10A In the top view, some of the constituent elements are omitted for ease of understanding.

[0269] Figures 10A to 10C The transistor shown includes: a conductor 413 and an insulator 401 on a substrate 400; an insulator 402 on the conductor 413 and the insulator 401; an insulator 406a on the insulator 402; a semiconductor 406b on the insulator 406a; a conductor 416a and a conductor 416b including a region contacting the top surface of the semiconductor 406b; and a transistor having an open circuit in contact with the top surface of the insulator 402, the top surface of the conductor 416a, and the top surface of the conductor 416b. An insulator 410 is provided at the opening; an insulator 406c is provided in contact with the side surface of the conductor 416a, the top surface and the side surface of the semiconductor 406b; an insulator 406d is provided on the insulator 406c; an insulator 412 is provided in contact with the top surface of the insulator 406d and the side surface of the opening of the insulator 410; and a conductor 404 is provided on the semiconductor 406b and includes conductors 404a and 404b, which are disposed on the semiconductor 406b with respect to insulators 412, 406c and 406d. Furthermore, conductor 404b faces the side surface of the opening of the insulator 410 with respect to conductors 404a and 412. A conductor 420 is provided on the conductors 404a and 404b; and an insulator 408 is provided on the insulators 412 and 420. Additionally, as... Figure 56A , Figure 56B and Figure 56C As shown, conductor 413 and insulator 401 are not essential components, and conductor 413 and insulator 401 may be omitted.

[0270] Insulators 406c and 406d preferably contain at least one element other than oxygen in semiconductor 406b. This suppresses defect formation at both the interface between semiconductor 406b and insulator 406c, and the interface between insulator 406c and insulator 406d. Furthermore, it improves the crystallinity of insulators 406c and 406d.

[0271] Semiconductor 406b and insulator 406c preferably include CAAC-OS as described below. Insulator 406d also preferably includes CAAC-OS. Insulator 406a also preferably includes CAAC-OS.

[0272] In this transistor, conductors 404a and 404b function as the first gate electrode. Furthermore, it is preferable that at least one of conductors 404a and 404b is a conductor that is not easily permeable to oxygen. For example, by forming an oxygen-impermeable conductor as the lower conductor 404a, the decrease in conductivity caused by oxidation of conductor 404b can be prevented. Additionally, the insulator 412 functions as the first gate insulator.

[0273] Conductor 413 functions as a second gate electrode. Alternatively, conductor 413 can be a stacked structure comprising conductors that are not easily permeable to oxygen. By employing a stacked structure comprising conductors that are not easily permeable to oxygen, the decrease in conductivity caused by oxidation of conductor 413 can be prevented. Insulator 402 functions as a second gate insulator. The threshold voltage of the transistor can be controlled by the potential applied to conductor 413. Furthermore, by electrically connecting the first gate electrode and the second gate electrode, the on-state current can be increased. Note that the functions of the first gate electrode and the second gate electrode can be interchanged.

[0274] In addition, conductors 416a and 416b function as source or drain electrodes. Note that the conductivity of the conductors can be measured using methods such as the two-terminal method.

[0275] The resistance of semiconductor 406b can be controlled by the potential applied to conductor 404. In other words, the conduction / non-conduction between conductor 416a and conductor 416b can be controlled by the potential applied to conductor 404.

[0276] like Figure 10B As shown, the top surface of semiconductor 406b is in contact with conductors 416a and 416b. Furthermore, the semiconductor 406b can be surrounded by the electric field of conductor 404, which functions as a gate electrode. A transistor structure in which the semiconductor is surrounded by the electric field of the gate electrode is called a surrounded channel (S-channel) structure. Therefore, a channel is sometimes formed throughout the entire semiconductor 406b. In an S-channel structure, a large current can flow between the source and drain of the transistor, thereby increasing the on-state current. Additionally, since semiconductor 406b is surrounded by the electric field of conductor 404, the off-state current can be reduced.

[0277] Since the region of the transistor used as the gate electrode in this embodiment is formed in a self-aligned manner to fill the opening formed in the insulator 410, the transistor can also be called TGSA s-channel FET (Trench Gate Self Align s-channel FET).

[0278] Here, in Figure 10B In the process, the length between the top surface of the semiconductor 406b and the bottom surface of the conductor 404 in the region overlapping with the conductor 404 is t1. Additionally, in... Figure 10B In this context, the length between the region of semiconductor 406b overlapping the bottom surface of conductor 416a and the region of semiconductor 406b overlapping the bottom surface of conductor 404 is L1. Alternatively, the length between the region of semiconductor 406b overlapping the bottom surface of conductor 416b and the region of semiconductor 406b overlapping the bottom surface of conductor 404 is L1.

[0279] In a transistor, an L1 region is formed between the region in semiconductor 406b where the channel is formed (the region where conductor 404 overlaps with semiconductor 406b) and the source or drain region (the region where conductor 416a or conductor 416b overlaps with semiconductor 406b). By including this region, the off-state current of the transistor can be reduced; however, if this region is too large, the on-state current of the transistor will decrease.

[0280] Furthermore, by covering the region of the semiconductor 406b that forms a channel with insulators 406c and 406d, elements other than oxygen (hydrogen, silicon, etc.) constituting the adjacent insulators can be prevented from entering the region of the channel. Therefore, insulators 406c and 406d need to be formed at least on the semiconductor 406b.

[0281] Therefore, by providing insulators 406c and 406d on the side of conductor 404 without separating them from insulator 412, or by making the area where insulators 406c and 406d cover the side of conductor 404 through insulator 412 thinner than the area where insulators 406c and 406d overlap with the bottom surface of conductor 404 through insulator 412, L1 can be reduced. Therefore, t1 is greater than L1 and L1 / t1 is less than 1.

[0282] exist Figure 10B and Figure 11A In this context, the length between conductor 416a or conductor 416b and conductor 420 is t2. Additionally, in... Figure 10B In the figure, the length between conductor 416a and conductor 416b is L2.

[0283] The more miniaturized a transistor becomes, the more significant the parasitic capacitance near the transistor becomes. For example, parasitic capacitance sometimes forms between conductor 420 and conductor 416a or conductor 416b. When the parasitic capacitance near the channel region is large, the time required to charge the parasitic capacitance during transistor operation degrades the transistor's susceptibility and even the susceptibility of the semiconductor device. Furthermore, the power consumption increases in circuits composed of multiple transistors due to the excess power consumed in charging the parasitic capacitance. Therefore, t2 preferably has a sufficient length so that the parasitic capacitance is almost negligible compared to the gate capacitance.

[0284] Furthermore, the more miniaturized the transistor, the smaller L2 becomes, making it difficult to apply sufficient voltage to conductors 404a and 404b. However, by designing t2 to be of sufficient length, the resistance of conductors 404a and 404b can be reduced. Therefore, t2 is at least greater than L2, and preferably t2 / L2 is 1.5 or more and 2 or less.

[0285] Figure 11A and Figure 11B An enlarged view of the opening in the insulator 410 of the transistor in this embodiment is shown. The height of the top surface of the insulator 406d should be approximately the same as the top surfaces of the conductors 416a and 416b. Note that the top surface of the insulator 406d refers to the surface near the conductor 404a in the region where the bottom surfaces of the insulator 406d overlap with those of the conductors 404a and 404b. Ideally, as... Figure 11A As shown, the height of the top surface of the insulator 406d is preferably the same as the top surface of the conductors 416a and 416b.

[0286] Furthermore, the height of the top surface of the insulator 406c is preferably approximately the same as the interface between the semiconductor 406b and the conductors 416a and 416b. Note that the top surface of the insulator 406c refers to the surface near the conductor 404a in the region where the bottom surfaces of the insulator 406c overlap with those of the conductors 404a and 404b. Ideally, the height of the top surface of the insulator 406c is preferably the same as the interface between the semiconductor 406b and the conductors 416a and 416b. However, the insulator 406c only needs to fill at least the over-etched portion of the semiconductor 406b, and the top surface of the insulator 406c can also be as follows: Figure 11B As shown, it is above the interface between semiconductor 406b and conductors 416a and 416b.

[0287] Furthermore, although the transistor in this embodiment shows a double-layer structure with insulators 406c and 406d disposed on semiconductor 406b, it is not limited to this and a stacked structure of three or more layers can also be used.

[0288] As the substrate 400, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used, for example. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium-stabilized zirconium oxide substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of a single material such as silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates can also be used, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples of insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators can also be used. Alternatively, substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0289] Alternatively, a flexible substrate can be used as substrate 400. Another method for forming a transistor on a flexible substrate is to form a transistor on a non-flexible substrate, then peel off the transistor and transfer it to substrate 400 on the flexible substrate. In this case, it is preferable to provide a release layer between the non-flexible substrate and the transistor. Alternatively, a sheet, film, or foil containing fibers can be used as substrate 400. Furthermore, substrate 400 can also be stretchable. Additionally, substrate 400 can have the property of returning to its original shape when bending or stretching stops. Alternatively, it can have the property of not returning to its original shape. Substrate 400, for example, includes a region with a thickness of 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less. By forming substrate 400 thin, the semiconductor device including the transistor can be made lightweight. Furthermore, by forming the substrate 400 thin, even when using glass or the like, the substrate 400 may sometimes exhibit stretchability or the property of returning to its original shape when bending or stretching ceases. Therefore, it is possible to mitigate impacts on the semiconductor device on the substrate 400 caused by drops or other factors. In other words, it is possible to provide a semiconductor device with high durability.

[0290] The substrate 400 of the flexible substrate can be made of, for example, metal, alloy, resin, glass, or its fibers. A lower coefficient of linear expansion of the flexible substrate 400 is preferred, as it suppresses deformation caused by environmental factors. For example, the substrate 400 of the flexible substrate can use a coefficient of linear expansion of 1 × 10⁻⁶. -3 / K or less, 5×10 -5 / K or less or 1×10 -5 Materials with a coefficient of linear expansion of less than / K. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic resin, etc. Aromatic polyamides, in particular, have a low coefficient of linear expansion, therefore, the substrate 400 of the flexible substrate is preferably made of aromatic polyamide.

[0291] Note that by surrounding the transistor with an insulator that blocks impurities such as hydrogen and oxygen, the transistor's electrical characteristics can be stabilized. For example, an insulator that blocks impurities such as hydrogen and oxygen can be used as insulator 408.

[0292] As an insulator that can block impurities such as hydrogen and oxygen, a single layer or stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used.

[0293] Alternatively, insulator 408 can be formed using aluminum oxide, magnesium oxide, silicon oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. In addition, insulator 408 preferably contains aluminum oxide. For example, when insulator 408 is formed using oxygen-containing plasma, oxygen can be added to the insulator 410, which forms the base layer of insulator 408. Alternatively, oxygen can be added to the sidewalls of insulator 412. The added oxygen becomes excess oxygen in insulator 410 or insulator 412. By including aluminum oxide in insulator 408, impurities such as hydrogen can be suppressed from entering semiconductor 406b. Furthermore, by including aluminum oxide in insulator 408, for example, the outward diffusion of excess oxygen added to insulator 410 and insulator 412 can be reduced.

[0294] As the insulator 402, for example, a single layer or a stack of insulators comprising boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. For example, the insulator 402 preferably comprises silicon oxide or silicon oxynitride.

[0295] Note that the insulator 410 preferably comprises an insulator with a low relative permittivity. For example, the insulator 410 preferably comprises silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen, porous silicon oxide, or resin, etc. Alternatively, the insulator 410 preferably has a laminated structure of resin and one of the following materials: silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen, or porous silicon oxide. Because silicon oxide and silicon oxynitride are thermally stable, a thermally stable laminated structure with a low relative permittivity can be obtained by combining them with a resin. Examples of resins include polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, acrylic resins, etc.

[0296] As the insulator 412, for example, a single layer or a stack of insulators comprising boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. For example, the insulator 412 preferably comprises silicon oxide or silicon oxynitride.

[0297] Note that insulator 412 preferably comprises an insulator with a high dielectric constant. For example, insulator 412 preferably comprises gallium oxide, hafnium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, or an oxynitride containing silicon and hafnium. Alternatively, insulator 412 preferably has a stacked structure of silicon oxide or silicon oxynitride and an insulator with a high dielectric constant. Because silicon oxide and silicon oxynitride have thermal stability, a thermally stable stacked structure with a high dielectric constant can be achieved by combining them with an insulator with a high dielectric constant. For example, when aluminum oxide, gallium oxide, or hafnium oxide of insulator 412 is located on one side of insulator 406c and insulator 406d, silicon contained in silicon oxide or silicon oxynitride can be suppressed from mixing into semiconductor 406b. Additionally, when silicon oxide or silicon oxynitride is located on one side of insulator 406c and insulator 406d, trap centers sometimes form at the interface between aluminum oxide, gallium oxide, or hafnium oxide and silicon oxide or silicon oxynitride. These trap centers can sometimes cause the threshold voltage of the transistor to drift in the positive direction by trapping electrons.

[0298] As conductors 416a and 416b, for example, a single layer or stack of conductors comprising one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, platinum, silver, indium, tin, tantalum, and tungsten can be used. For example, alloy films or compound films can also be used, and conductors comprising aluminum, copper and titanium, copper and manganese, indium, tin and oxygen, or titanium and nitrogen can be used.

[0299] As conductors 404, 413, and 420, single layers or stacks of conductors comprising one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten can be used. For example, alloy films or compound films can also be used, and conductors comprising aluminum, copper and titanium, copper and manganese, indium, tin and oxygen, or titanium and nitrogen can be used.

[0300] As for semiconductor 406b, oxide semiconductors are preferred. Note that silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors may sometimes be used.

[0301] As insulators 406a, 406c, and 406d, oxides composed of one or more elements other than oxygen constituting semiconductor 406b are preferably used. Note that silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors may sometimes be used.

[0302] Semiconductor 406b is, for example, an indium-containing oxide semiconductor. For example, when semiconductor 406b contains indium, its carrier mobility (electron mobility) is improved. Furthermore, semiconductor 406b preferably contains element M. Element M is preferably aluminum, gallium, yttrium, or tin. Other elements that can be used as element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that multiple of the above elements can sometimes be combined as element M. Element M is, for example, an element with a high bond energy with oxygen. Element M is, for example, an element with a bond energy with oxygen higher than that of indium. Alternatively, element M is, for example, an element that has the function of increasing the band gap of the oxide semiconductor. Additionally, semiconductor 406b preferably contains zinc. When an oxide semiconductor contains zinc, it is sometimes easier to crystallize.

[0303] Note that semiconductor 406b is not limited to indium-containing oxide semiconductors. Semiconductor 406b can also be, for example, zinc tin oxide or gallium tin oxide, or other oxide semiconductors that do not contain indium but contain zinc, gallium, or tin.

[0304] For example, an oxide with a large bandgap is used as the semiconductor 406b. The bandgap of the semiconductor 406b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0305] For example, insulators 406a, 406c, and 406d are oxides containing one or more elements other than oxygen that constitute semiconductor 406b. Because insulators 406a, 406c, and 406d contain one or more elements other than oxygen that constitute semiconductor 406b, defect states are less likely to form at the interfaces between insulator 406a and semiconductor 406b, between semiconductor 406b and insulator 406c, and between insulator 406c and insulator 406d.

[0306] The semiconductor 406b uses an oxide whose electron affinity is greater than that of insulators 406a, 406c, and 406d. For example, the semiconductor 406b uses an oxide whose electron affinity is greater than that of insulators 406a, 406c, and 406d by 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less. Note that electron affinity is the energy difference between the vacuum level and the conduction band bottom. Furthermore, the electron affinity of insulator 406c is preferably greater than that of insulator 406d.

[0307] Thus, if a gate voltage is applied to a transistor in which insulators 406a, 406c, and 406d are respectively disposed above and below semiconductor 406b, a channel is formed in semiconductor 406b, which has the highest electron affinity among insulators 406a, 406b, 406c, and 406d. This can form a so-called buried channel structure.

[0308] Here, sometimes a mixed region of insulator 406a and semiconductor 406b exists between insulator 406a and semiconductor 406b. Additionally, sometimes a mixed region of semiconductor 406b and insulator 406c exists between semiconductor 406b and insulator 406c. Furthermore, sometimes a mixed region of insulator 406c and insulator 406d exists between insulator 406c and insulator 406d. The defect state density in the mixed regions is low. Therefore, in the stack of insulator 406a, semiconductor 406b, insulator 406c, and insulator 406d, the energy at and near the interfaces between the layers changes continuously (also called continuous bonding). Note that sometimes the interfaces of insulator 406a, semiconductor 406b, insulator 406c, and insulator 406d cannot be clearly distinguished.

[0309] At this time, electrons do not move in insulators 406a, 406c, and 406d, but mainly in semiconductor 406b.

[0310] The fewer obstacles that hinder electron movement, the higher the on-state current of the transistor can be. For example, electron movement can be hindered if there are large physical irregularities in the channel formation region.

[0311] To improve the on-state current of the transistor, for example, the root mean square (RMS) roughness of the top or bottom surface (the formed surface, in this case, the top surface of the insulator 406a) of the semiconductor 406b in the range of 1 μm × 1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. Additionally, its average surface roughness (also known as Ra) in the range of 1 μm × 1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. Its maximum difference (also known as PV) in the range of 1 μm × 1 μm is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and even more preferably less than 7 nm. The RMS roughness, Ra, and PV can be measured using a scanning probe microscope such as the SPA-500 manufactured by SIINano Technology Co., Ltd.

[0312] The above four-layer structure is just one example. For example, a stacked structure may also be used with any one of the insulators exemplified as insulators 406a, 406c, and 406d on or under insulator 406a.

[0313] Note that oxide semiconductors, which can be used as semiconductors, are described in detail in other embodiments.

[0314] <Transistor Manufacturing Method 7>

[0315] Below, refer to Figures 18A to 20F For the present invention Figures 10A to 10C The manufacturing method of the transistor shown will be explained.

[0316] First, prepare the substrate 400.

[0317] Next, as Figure 18A and Figure 18BAs shown, an insulator 401, which will become an insulator, is formed on a substrate 400. An opening is formed in the insulator 401, and a conductor 413, which will become a conductor, is formed on the insulator 401. The conductor 413 can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD. Alternatively, the conductor 413 can be a multilayer structure including a conductor that is not easily permeable to oxygen. The conductor 413 can be embedded into the opening of the insulator 401 using methods such as chemical mechanical polishing (CMP). Alternatively, as another method for forming the conductor 413, the conductor can be formed and processed using methods such as photolithography to form the conductor 413.

[0318] Note that in photolithography, the resist is first exposed through a mask. Next, a developer is used to remove or leave the exposed areas, forming a resist mask. Then, etching is performed through this resist mask to process conductors, semiconductors, or insulators into the desired shape. For example, the resist mask is formed by exposing the resist using KrF stimulated excimer lasers, ArF stimulated excimer lasers, or EUV (Extreme Ultraviolet) light. Alternatively, immersion techniques can be used, where exposure is performed with liquid (e.g., water) filling the space between the substrate and the projection lens. Electron beams or ion beams can also be used instead of the aforementioned light. Furthermore, the resist mask can be removed by performing dry etching (such as ashing) or wet etching, or by performing wet etching after dry etching, or dry etching after wet etching.

[0319] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel planar electrodes can be used. This apparatus can apply a high-frequency power supply to one of the parallel planar electrodes; it can apply multiple different high-frequency power supplies to one of the parallel planar electrodes; it can apply a high-frequency power supply of the same frequency to each of the parallel planar electrodes; or it can apply high-frequency power supplies of different frequencies to each of the parallel planar electrodes. Furthermore, a dry etching apparatus including a high-density plasma source can also be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus including a high-density plasma source.

[0320] Next, as Figure 18A or Figure 18BAs indicated by the arrows, high-density plasma treatment can also be performed. High-density plasma treatment is preferably performed in an oxygen atmosphere or a nitrogen atmosphere. An oxygen atmosphere is a gaseous atmosphere containing oxygen atoms, specifically an atmosphere containing oxygen, ozone, or nitrogen oxides (nitric oxide, nitrogen dioxide, nitrous oxide, dinitrogen trioxide, dinitrogen tetroxide, or dinitrogen pentoxide, etc.). Alternatively, the oxygen atmosphere may also contain nitrogen or an inert gas such as a rare gas (helium, argon, etc.). Thus, by performing high-density plasma treatment in an oxygen atmosphere, for example, carbon and hydrogen can be removed. Furthermore, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can be easily removed from the treated material.

[0321] As a high-density plasma treatment under a nitrogen atmosphere, the above-mentioned high-density plasma treatment can be performed, for example, in an atmosphere containing nitrogen and rare gases, in an atmosphere containing nitrogen, hydrogen and rare gases, or in an atmosphere containing ammonia and rare gases. By performing high-density plasma treatment under a nitrogen atmosphere, the surface of the workpiece and its vicinity can be nitrided. An extremely thin nitrided region can be formed on one side of the surface of the workpiece. This nitrided region can suppress the diffusion of impurities.

[0322] High-density plasma treatment can be performed in an oxygen atmosphere followed by high-density plasma treatment in a nitrogen atmosphere, or vice versa. Annealing treatment can also be performed before and after each high-density plasma treatment. Furthermore, to increase the plasma density, it is sometimes preferable to supply a sufficient amount of gas. If the amount of gas is insufficient, the deactivation rate of free radicals may sometimes exceed the generation rate. For example, it is sometimes preferable to supply gas at a density of 100 sccm or higher, 300 sccm or higher, or 800 sccm or higher.

[0323] In high-density plasma processing, microwaves generated by a high-frequency generator with a frequency of 0.3 GHz or higher and 3.0 GHz or lower, 0.7 GHz or higher and 1.1 GHz or lower, or 2.2 GHz or higher and 2.8 GHz or lower (typically 2.45 GHz) can be used. Furthermore, the processing pressure can be 10 Pa or higher and 5000 Pa or lower, preferably 200 Pa or higher and 1500 Pa or lower, more preferably 300 Pa or higher and 1000 Pa or lower, the substrate temperature can be 100 °C or higher and 600 °C or lower (typically 400 °C), and a mixture of oxygen and argon can be used.

[0324] High-density plasma is generated, for example, by using 2.45 GHz microwaves, preferably at a density of 1 × 10⁻⁶ GHz. 11 / cm 3 Above and 1×10 13 / cm 3The treatment is performed at electron densities below 2 eV, electron temperatures below 2 eV, or ion energies below 5 eV. In such high-density plasma treatment, the kinetic energy of free radicals is low, and the damage caused by plasma is also less compared to conventional plasma treatments. Therefore, films with fewer defects can be formed. The distance from the antenna generating the microwaves to the workpiece is 5 mm or more and 120 mm or less, preferably 20 mm or more and 60 mm or less.

[0325] Alternatively, a plasma power supply that applies an RF (Radio Frequency) bias to the substrate can be used. The RF bias frequency can be, for example, 13.56 MHz or 27.12 MHz. High-density plasma can generate a high density of oxygen ions, and by applying an RF bias to one side of the substrate, the oxygen ions generated by the high-density plasma can be efficiently introduced into the workpiece. Therefore, it is preferable to perform high-density plasma treatment while applying a bias to the substrate.

[0326] After high-density plasma treatment, annealing can be performed continuously without exposure to the atmosphere. Alternatively, high-density plasma treatment can be performed continuously after annealing without exposure to the atmosphere. By continuously performing high-density plasma treatment and annealing, the introduction of impurities during the treatment process can be suppressed. Furthermore, by performing high-density plasma treatment in an oxygen atmosphere followed by annealing, excess oxygen added to the workpiece that was not used to fill oxygen vacancies can be removed. Additionally, the aforementioned annealing process can be, for example, lamp annealing.

[0327] In addition, the processing time for high-density plasma treatment is preferably 30 seconds or more and 120 minutes or less, 1 minute or more and 90 minutes or less, 2 minutes or more and 30 minutes or less, or 3 minutes or more and 15 minutes or less.

[0328] In addition, the annealing temperature is preferably above 250°C and below 800°C, above 300°C and below 700°C, or above 400°C and below 600°C, and the processing time is preferably above 30 seconds and below 120 minutes, above 1 minute and below 90 minutes, above 2 minutes and below 30 minutes, or above 3 minutes and below 15 minutes.

[0329] Next, insulator 402 is formed. Insulator 402 can be formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), etc.

[0330] CVD methods can be classified into plasma-enhanced CVD (PECVD), thermal TCVD (TCVD), and photoCVD (PhotoCVD). Furthermore, they can be categorized based on the source gas used, such as metal CVD (MCVD) and organometallic CVD (MOCVD).

[0331] PECVD can produce high-quality films at relatively low temperatures. Furthermore, because thermal CVD does not use plasma, it reduces plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes experience charge buildup by receiving charge from plasma. This charge buildup can sometimes damage the wiring, electrodes, and components. On the other hand, when using thermal CVD without plasma, the aforementioned damage caused by plasma exposure is avoided, thus improving the yield of semiconductor devices. Additionally, because the workpiece is not exposed to plasma during deposition in thermal CVD, films with fewer defects are more easily obtained.

[0332] In addition, the ALD method can reduce plasma damage to the treated material. Furthermore, the ALD method does not generate plasma damage during deposition, thus yielding films with fewer defects.

[0333] Unlike deposition methods that deposit particles released from a target or similar material, CVD and ALD methods form films through reactions on the surface of the workpiece. Therefore, CVD and ALD methods can achieve good step coverage and are less affected by the shape of the workpiece. In particular, ALD achieves good step coverage and thickness uniformity, making it suitable for forming films covering surfaces with high aspect ratio openings. However, because ALD has a relatively slow deposition rate, it is sometimes preferred to combine it with other deposition methods, such as CVD, which has a faster deposition rate.

[0334] CVD and ALD methods allow for control of the film composition by adjusting the source gas flow rate ratio. For example, in CVD and ALD, films with arbitrary compositions can be formed by adjusting the source gas flow rate ratio. Furthermore, in CVD and ALD, films with continuously varying compositions can be formed by changing the source gas flow rate ratio while the film is being formed. When the source gas flow rate ratio is changed simultaneously with deposition, the time required for transport and pressure adjustment can be eliminated, thus reducing the time required for film formation compared to deposition using multiple chambers. Therefore, the productivity of semiconductor devices can be improved.

[0335] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0336] Alternatively, oxygen can be added to the insulator 402. Examples of oxygen addition methods include ion implantation and plasma treatment. However, the oxygen added to the insulator 402 becomes excess oxygen.

[0337] Next, as Figure 18C and Figure 18D As shown, an insulator that will become an insulator 406a, a semiconductor that will become a semiconductor 406b, and a resist mask 430 are formed.

[0338] First, an insulator that will become insulator 406a is formed on insulator 402. The insulator that will become insulator 406a can be formed using sputtering, CVD, MBE, PLD, or ALD methods, etc. In particular, it is preferred to form the insulator using a facing target sputtering apparatus. Note that in this specification and the like, the deposition method using a facing target sputtering apparatus can also be referred to as VDSP.

[0339] By using a counter-target sputtering apparatus to form insulators, plasma damage during insulator formation can be reduced. This reduces oxygen vacancies in the film. Furthermore, using a counter-target sputtering apparatus allows deposition to be performed under high vacuum. This reduces the concentration of impurities (e.g., hydrogen, rare gases (argon, etc.), water, etc.) in the formed insulator.

[0340] Alternatively, a sputtering apparatus with an inductively coupled antenna conductor plate can be used. This allows for the formation of large-area films with high uniformity at high deposition rates.

[0341] Preferred gases include those containing oxygen, rare gases, and those containing nitrogen. For example, nitrogen (N2), nitrous oxide (N2O), and ammonia (NH3) can be used as nitrogen-containing gases.

[0342] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0343] Alternatively, oxygen can be added to the insulator that will become insulator 406a. Methods for adding oxygen include ion implantation and plasma treatment. Furthermore, the oxygen added to the insulator that will become insulator 406a is excess oxygen.

[0344] Next, a semiconductor 406b is formed on the insulator that will become insulator 406a. The semiconductor can be formed using sputtering, CVD, MBE, PLD, or ALD methods. In particular, it is preferable to form the semiconductor using a facing target sputtering apparatus.

[0345] By using a counter-target sputtering apparatus to form semiconductors, plasma damage during semiconductor formation can be reduced. This reduces oxygen vacancies in the film. Furthermore, using a counter-target sputtering apparatus allows deposition to be performed under high vacuum. This reduces the concentration of impurities (e.g., hydrogen, rare gases (argon, etc.), water, etc.) in the formed semiconductor.

[0346] Alternatively, a sputtering apparatus with an inductively coupled antenna conductor plate can be used. This allows for the formation of large-area films with high uniformity at high deposition rates.

[0347] Preferred gases include those containing oxygen, rare gases, and those containing nitrogen. For example, nitrogen (N2), nitrous oxide (N2O), and ammonia (NH3) can be used as nitrogen-containing gases.

[0348] Next, a first heat treatment is preferably performed. The first heat treatment is performed at a temperature of 250°C or higher and 650°C or lower, preferably 450°C or higher and 600°C or lower. The first heat treatment is performed in an inert gas atmosphere or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. The first heat treatment can also be performed under reduced pressure. Alternatively, in the first heat treatment, heat treatment can be performed in an inert gas atmosphere, and then heat treatment can be performed in an oxidizing gas atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher to replenish the released oxygen. By performing the first heat treatment, the crystallinity of the semiconductor can be improved, and impurities such as hydrogen or water can be removed. Alternatively, in the first heat treatment, plasma treatment containing oxygen can also be performed under reduced pressure. For example, plasma treatment containing oxygen preferably employs a device including a power supply that uses microwaves to generate high-density plasma. Alternatively, a plasma power supply that applies an RF voltage to one side of the substrate can also be included. By using high-density plasma, high-density oxygen radicals can be generated, and by applying an RF voltage to one side of the substrate, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the semiconductor 406b. Alternatively, after plasma treatment with an inert gas using such a device, an oxygen-containing plasma treatment can be performed to replenish the detached oxygen.

[0349] Next, as Figure 18E and Figure 18FAs shown, using a resist mask 430, the insulator 406a (which will become the insulator) and the semiconductor 406b (which will become the semiconductor) are processed by photolithography or the like, thereby forming a multilayer film including the insulator 406a and the semiconductor 406b. Note that during the formation of the multilayer film, the insulator 402 is sometimes etched, and a portion of it becomes thinner. That is, the insulator 402 sometimes has protrusions in the areas that contact the multilayer film.

[0350] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0351] Next, as Figure 18G and Figure 18H As shown, an insulator is formed that will become both conductor 416 and insulator 410.

[0352] First, a conductor 416 is formed. The conductor 416 can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0353] Note that the conductor 416 is covered by a multilayer film. When the conductor is formed on this multilayer film, damage is caused to the side surfaces of the insulator 406a, the top surface of the semiconductor 406b, and a portion of the side surfaces of the semiconductor 406b, sometimes resulting in low-resistance regions. Because a portion of the insulator 406a and the semiconductor 406b has low-resistance regions, the contact resistance between the conductor 416 and the semiconductor 406b can be reduced.

[0354] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0355] Next, the conductor 416 is processed using photolithography and other methods to form conductor 416a and conductor 416b.

[0356] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0357] Next, the insulator that will become insulator 410 is formed. The insulator that will become insulator 410 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. Alternatively, it can be formed using spin coating, dip coating, droplet jetting (inkjet, etc.), printing (screen printing, offset printing, etc.), doctor knife coating, roll coating, or curtain coating.

[0358] The insulator that will become insulator 410 can be formed in a manner where its top surface is flat. For example, the top surface of the insulator that will become insulator 410 can be flat immediately after film formation. Alternatively, for example, after film formation, the upper part of the insulator that will become insulator 410 can be removed with its top surface parallel to a reference surface such as the back surface of the substrate. This process is called planarization. Planarization processes include chemical mechanical polishing, dry etching, etc. However, the top surface of the insulator that will become insulator 410 may not be flat.

[0359] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0360] Next, a photoresist mask 431 is formed on the insulator that will become the insulator 410 using photolithography or the like. Here, in order to improve the tightness between the top surface of the insulator that will become the insulator 410 and the photoresist mask 431, for example, an organic coating film can be disposed between the top surface of the insulator that will become the insulator 410 and the photoresist mask 431.

[0361] Next, as Figure 19A and Figure 19B As shown, openings are formed in the insulator 410 and the conductor 416. First, the insulator, which will become the insulator 410, is first processed using a dry etching method or the like until the top surface of the conductor 416 is exposed. The dry etching apparatus described above can be used in the dry etching method, but it is preferable to use a dry etching apparatus that connects high-frequency power supplies of different frequencies to each parallel planar electrode.

[0362] Next, the conductor 416 is further processed by a second process, such as dry etching, to separate it into conductor 416a and conductor 416b. Note that the processing of the insulator 410 and the conductor 416 can be performed in the same photolithography process. By performing these processes in the same photolithography process, the number of steps can be reduced. Therefore, the productivity of semiconductor devices, including transistors, can be improved.

[0363] At this point, the semiconductor 406b includes an exposed area. Through the second processing described above, sometimes a portion of the exposed area of ​​the semiconductor 406b is removed. Additionally, impurity elements such as residual components of the etching gas may sometimes adhere to the exposed semiconductor 406b. For example, when a chlorine-based gas is used as the etching gas, chlorine may sometimes adhere. Furthermore, when a hydrocarbon gas is used as the etching gas, carbon or hydrogen may sometimes adhere. Therefore, it is preferable to reduce the impurity elements adhering to the exposed surface of the semiconductor 406b. For example, this can be reduced by using a washing process with dilute hydrofluoric acid, a washing process with ozone, or a washing process with ultraviolet light. Furthermore, multiple washing processes can be combined. As a result, the exposed surface of the semiconductor 406b, that is, the area where the channel is formed, becomes highly resistive.

[0364] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0365] Next, as Figure 19C and Figure 19D As shown, insulator 406c is formed at least on the top and side surfaces of semiconductor 406b (excluding the side surface of insulator 410), the side surface of insulator 406a, the top surface of insulator 402, and the top surface of insulator 410. Furthermore, insulator 406c is preferably formed by filling the depressions formed in semiconductor 406b. Insulator 406c can be formed using a sputtering method.

[0366] Here, refer to Figure 21 and Figure 22 The sputtering apparatus used to form insulators 406c and 406d is described.

[0367] Figure 21 This is a cross-sectional view showing a portion of the sputtering apparatus 101. Figure 21 The sputtering apparatus 101 shown includes: a component 190; a collimator 150 disposed on the component 190; a target holder 120; a pad 110 on the target holder 120; a target 100 on the pad 110; a magnet unit 130 including magnets 130N and 130S disposed below the target 100 across the pad 110; and a magnet holder 132 supporting the magnet unit 130. In this specification, the plurality of magnets are referred to as a magnet unit. A magnet unit may also be referred to as a cathode, cathode magnet, magnetic component, magnetic part, etc.

[0368] The substrate stage 170, arranged facing the target 100, and the substrate 160 supported by the substrate stage 170 are also shown. In addition, magnetic lines of force 180a and magnetic lines of force 180b formed by the magnet unit 130 are also shown.

[0369] The target holder 120 and the pad 110 are fixed together by bolts or the like and are subjected to the same potential. The target holder 120 supports the target 100 across the pad 110.

[0370] The pad 110 has the function of fixing the target 100.

[0371] The sputtering apparatus 101 may also have water channels inside or at the bottom of the pad 110. By allowing fluid (air, nitrogen, rare gas, water, oil, etc.) to flow through the water channels, abnormal discharge caused by the temperature rise of the target 100 during sputtering or damage to the sputtering apparatus 101 caused by deformation of components such as the target 100 can be suppressed. In this case, it is preferable to use an adhesive member to bond the pad 110 and the target 100 together, as the cooling performance is improved.

[0372] By providing a gasket between the target holder 120 and the pad 110, impurities are less likely to enter the sputtering device 101 from the outside or water channels, which is therefore preferred.

[0373] In the magnet unit 130, magnets 130N and 130S are arranged with different polarities facing the target 100. Here, we will describe the case where the N pole of magnet 130N faces the target 100, and the S pole of magnet 130S faces the target 100. Note that the arrangement of magnets and their polarities in the magnet unit 130 is not limited to this configuration. Figure 21 The configuration shown.

[0374] Magnetic field line 180a is one of the magnetic field lines that form a horizontal magnetic field near the top surface of the target 100. Near the top surface of the target 100 refers, for example, to an area with a vertical distance of 0 mm or more and less than 10 mm from the target 100, especially 0 mm or more and less than 5 mm.

[0375] Magnetic field line 180b is one of the magnetic field lines that forms a horizontal magnetic field at a vertical distance d from the top surface of magnet unit 130. The vertical distance d is, for example, 0 mm or more and 20 mm or less, or 5 mm or more and 15 mm or less.

[0376] During deposition, the potential V1 applied to the target holder 120 is, for example, lower than the potential V2 applied to the substrate stage 170. The potential V2 applied to the substrate stage 170 is, for example, a ground potential. The potential V3 applied to the magnet holder 132 is, for example, a ground potential. Note that potentials V1, V2, and V3 are not limited to the aforementioned potentials. It is also possible not to apply potentials to all three components: the target holder 120, the substrate stage 170, and the magnet holder 132. For example, the substrate stage 170 may also be in an electrically floating state.

[0377] exist Figure 21The diagram shows an example where the pad 110 and target holder 120 are not electrically connected to the magnet unit 130 and magnet holder 132, but this is not a limitation. For example, the pad 110 and target holder 120 can also be electrically connected to the magnet unit 130 and magnet holder 132 and have the same potential applied to them.

[0378] A deposition gas (e.g., a rare gas such as argon, oxygen, nitrogen, etc.) is supplied to the sputtering apparatus 101 at a fixed pressure (e.g., 0.05 Pa or more and 10 Pa or less, preferably 0.1 Pa or more and 0.8 Pa or less). A potential V1 is applied to the target holder 120, thereby forming plasma in the magnetic field formed by the magnet unit 130. The potential Vp of the plasma is higher than the potential V1. At this time, cations in the plasma are accelerated towards the target 100 due to the potential difference between potential Vp and potential V1. When the cations collide with the target 100, sputtered particles are released. Among the released sputtered particles, the sputtered particles that reach the substrate 160 are deposited to form a film.

[0379] Generally, in sputtering apparatuses, sputtered particles do not easily reach the bottom of the opening, which has a large aspect ratio and a small opening. In addition, sputtered particles flying at an angle to the substrate deposit near the top of the opening, narrowing the top of the opening, so sometimes sputtered particles do not form within the opening.

[0380] On the other hand, by using the sputtering apparatus with the above-described structure, sputtering particles flying obliquely towards the surface of the substrate 160 are attached to the collimator 150 among the released sputtered particles. That is, by providing the collimator 150, sputtering particles passing between the target 100 and the substrate 160 and having a component perpendicular to the substrate 160 reach the substrate. Therefore, they are deposited on a surface parallel to the substrate. On the other hand, sputtering particles are not deposited on a surface perpendicular to the substrate, or the amount of sputtering particles deposited on a surface perpendicular to the substrate is less than the amount deposited on a surface parallel to the substrate. Therefore, by using the above-described sputtering apparatus, such as... Figure 19C and Figure 19D As shown, insulator 406c can be formed on a surface other than the surface perpendicular to the substrate.

[0381] Note that the vertical distance between the target 100 and the collimator 150, or the vertical distance between the substrate 160 and the collimator 150, can be appropriately changed according to the quality of the formed film. Therefore, as... Figure 22 As shown, the collimator 150 may also have a movable part 151 and a movable part 152. By having a movable part 151, it is easier to select whether to use the collimator 150. In addition, by having a movable part 152, it is easier to adjust the vertical distance between the collimator 150 and the substrate 160 and between the collimator 150 and the target 100.

[0382] Alternatively, long-range ballistic sputtering can be used. In long-range ballistic sputtering, by increasing the vertical distance between the target 100 and the substrate 160, the incident direction of the sputtered particles onto the substrate 160 can be made nearly perpendicular. Therefore, even without using the collimator 150, an insulator 406c can be formed on a surface other than the one perpendicular to the substrate. Note that the vertical distance between the substrate 160 and the target 100 should be between 150 mm and 500 mm. Alternatively, long-range ballistic sputtering and the collimator 150 can be combined.

[0383] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0384] Next, as Figure 19E and Figure 19F As shown, insulator 406d is formed. Insulator 406d can be formed by the same process as insulator 406c.

[0385] Next, as Figure 20A and Figure 20B As shown, an insulator that will become an insulator 412, a conductor that will become a conductor 404a, and a conductor that will become a conductor 404b are formed.

[0386] First, an insulator that will become insulator 412 is formed on insulator 410 and insulator 406d. The insulator that will become insulator 412 can be formed using sputtering, CVD, MBE, PLD, or ALD methods, etc.

[0387] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0388] Next, conductive bodies that will become conductor 404a and conductor 404b are formed. The conductive bodies that will become conductor 404a and conductor 404b can be formed using sputtering, CVD, MBE, PLD, or ALD methods. The conductive bodies that will become conductor 404a and conductor 404b are formed by filling openings formed in the insulator 410, etc. Therefore, CVD (especially MCVD) is preferred. Furthermore, to improve the compactness of the conductor formed by MCVD, it is sometimes preferable to use a laminated film of a conductor formed by ALD and a conductor formed by CVD. For example, a laminated film in which titanium nitride and tungsten are sequentially formed can be used.

[0389] Next, as Figure 20C and Figure 20D As shown, conductors 404a and 404b, insulators 412, 406c, and 406d are removed through CMP processing, exposing insulator 410. In this case, insulator 410 can also be used as a stop layer, thus sometimes the thickness of insulator 410 becomes thinner. Therefore, by ensuring sufficient thickness of the insulator 410 film to sufficiently reduce the resistance of conductors 404a and 404b in the completed transistor, multiple transistors with small deviations can be formed.

[0390] Furthermore, CMP treatment can be performed either once or multiple times. When performing multiple CMP treatments, it is preferable to perform a high-polish initial polishing followed by a low-polish fine polishing. In this way, by combining polishing processes with different polishing rates, the flatness of the polished surface can be further improved.

[0391] Next, a conductive material that will become conductor 420 is formed. Conductor 420 can also be a multilayer structure. The conductive material that will become conductor 420 can be formed using sputtering, CVD, MBE, PLD, or ALD methods. Then, conductor 420 is formed by processing methods such as photolithography.

[0392] Next, as Figure 20E and Figure 20F As shown, an insulator 408 is formed on insulator 410 and conductor 420. Insulator 408 can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD. It is preferable to form alumina using an oxygen-containing plasma as insulator 408, so that the oxygen in the plasma can be added as excess oxygen (exO) to the top surface of insulator 410. Alternatively, oxygen can diffuse through insulator 410 to insulator 408, adding excess oxygen to insulator 408. Therefore, in this case, a mixed region containing a large amount of excess oxygen may sometimes form at and near the interface between insulator 408 and insulator 410.

[0393] Next, carbon and hydrogen can be removed by performing the high-density plasma treatment described above. Additionally, by performing high-density plasma treatment in an oxygen atmosphere, organic compounds such as hydrocarbons can also be removed from the treated material.

[0394] Furthermore, a second heat treatment can be performed at any time after the formation of insulator 408. Through this second heat treatment, excess oxygen contained in insulator 410 and the mixing region 414 migrates to semiconductor 406b via insulators 412, 402, 406d, 406c, and 406a. Thus, because excess oxygen migrates to semiconductor 406b, defects (oxygen vacancies) in semiconductor 406b can be reduced.

[0395] Note that the second heat treatment can be performed at a temperature at which excess oxygen contained in the insulator 410 and the mixing region 414 can diffuse to the semiconductor 406b. For example, the second heat treatment can also refer to the description of the first heat treatment. Alternatively, the temperature at which the second heat treatment is performed is preferably lower than the temperature at which the first heat treatment is performed. The temperature difference between the first heat treatment and the second heat treatment is 20°C or more and 150°C or less, preferably 40°C or more and 100°C or less. This can suppress the release of excess oxygen from the insulator 402, etc. Note that when the heat treatment performed during the formation of each film can also serve as the second heat treatment, sometimes the second heat treatment is not necessary.

[0396] Alternatively, although not shown, openings leading to conductors 416a and 416b may be formed in insulators 408 and 410, and conductors used for wiring may be formed in these openings. Alternatively, an opening leading to conductor 404 may be formed in insulator 408, and conductors used for wiring may be formed in these openings.

[0397] Through the above steps, it is possible to form Figures 10A to 10C The transistor shown.

[0398] In this embodiment, one aspect of the invention is described. However, this aspect of the invention is not limited thereto. That is, various inventive methods are described in one and other embodiments of the invention, thus this aspect of the invention is not limited to a specific method. For example, although one aspect of the invention shows an example of using an oxide semiconductor as the semiconductor, this aspect of the invention is not limited thereto. Depending on the circumstances, silicon, germanium, silicon-germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc., may also be used in one aspect of the invention.

[0399] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0400] Implementation Method 6

[0401] <Transistor Structure 8>

[0402] Below, refer to Figures 12A to 13B to and Figures 10A to 10C Different transistor structures and their manufacturing methods are explained. Figures 12A to 12C A top view and a cross-sectional view of a semiconductor device according to one aspect of the present invention are shown. Figure 12A It is a top view. Figure 12B It corresponds to Figure 12A The cross-sectional view of the dotted line A1-A2 shown. Figure 12C It corresponds to Figure 12AThe cross-sectional view shown is along the dashed-dot line A3-A4. Note that... Figure 12A In the top view, for clarity, some constituent elements have been omitted. Additionally, Figure 13A and Figure 13B yes Figures 12A to 12C An enlarged view of the cross-sectional diagram shown.

[0403] exist Figure 12B In this transistor, the side surface of the insulator 410 has an angle θ greater than 0 degrees and less than 90 degrees with respect to the top surface of the conductor 416a, and an insulator 406d is formed on the side surface of the insulator 410, with respect to the insulator 406c. Note that the angle θ is preferably 75 degrees or more and less than 90 degrees, preferably 80 degrees or more and less than 90 degrees, and more preferably 85 degrees or more and less than 90 degrees. Note that the area where the insulator 406c and the insulator 406d overlap with the side surface of the conductor 404 with respect to the insulator 412 is set to be thinner than the area where the insulator 406c and the insulator 406d overlap with the bottom surface of the conductor 404. Other constituent elements refer to [reference needed]. Figures 10A to 10C The transistor shown.

[0404] Furthermore, as long as t1 is greater than L1 and L1 / t1 is less than 1, the region covering the side of insulator 410 of only one of insulators 406c and 406d can be formed thin. Alternatively, only one of insulators 406c and 406d can be formed in the region covering the side of insulator 410 without forming the other.

[0405] Figure 13A and Figure 13B An enlarged view of the opening in the insulator 410 of the transistor in this embodiment is shown. The height of the top surface of the insulator 406d should be approximately the same as the top surfaces of the conductors 416a and 416b. Note that the top surface of the insulator 406d refers to the surface near the conductor 404a in the region where the bottom surfaces of the insulator 406d overlap with those of the conductors 404a and 404b. Ideally, as... Figure 13A As shown, the height of the top surface of the insulator 406d is preferably the same as the top surface of the conductors 416a and 416b.

[0406] Furthermore, the height of the top surface of the insulator 406c is preferably approximately the same as the interface between the semiconductor 406b and the conductors 416a and 416b. Note that the top surface of the insulator 406c refers to the surface near the conductor 404a in the region where the bottom surfaces of the insulator 406c overlap with those of the conductors 404a and 404b. Ideally, the height of the top surface of the insulator 406c is preferably the same as the interface between the semiconductor 406b and the conductors 416a and 416b. However, the insulator 406c only needs to fill at least the over-etched portion of the semiconductor 406b, and the top surface of the insulator 406c can also be as follows: Figure 13B As shown, it is above the interface between semiconductor 406b and conductors 416a and 416b.

[0407] Furthermore, although the transistor in this embodiment shows a double-layer structure with insulators 406c and 406d disposed on semiconductor 406b, it is not limited to this and a stacked structure of three or more layers can also be used.

[0408] <Transistor Manufacturing Methods 8>

[0409] First, proceed to the implementation method shown in Implementation Method 5. Figure 18H The process up to this point.

[0410] Next, the side surface of the insulator 410 is formed at an angle θ greater than 0 degrees and less than 90 degrees relative to the top surface of the conductor 416a. Then, insulators 406c and 406d are formed using the film-forming apparatus described in Embodiment 5. At this time, for example, the smaller the angle θ, the higher the probability of sputtered particle deposition, thereby forming thicker insulators 406c and 406d on the side surface of the insulator 410. Conversely, the larger the angle θ, the thinner insulators 406c and 406d are formed on the side surface of the insulator 410. Therefore, the film thickness of insulators 406c and 406d formed on the side surface of the insulator 410 can be adjusted according to the angle θ. That is, the width L1 of the formed offset region can be reduced. t1 is greater than L1, and L1 / t1 is less than 1.

[0411] The following steps are performed in the same manner as those in the transistor manufacturing method 1 shown in Embodiment 5.

[0412] Through the above steps, it is possible to form Figures 12A to 12C The transistor shown.

[0413] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0414] Implementation Method 7

[0415] <Transistor Structure 9 and Transistor Structure 10>

[0416] Below, refer to Figures 14A to 15C to and Figures 10A to 10C Different transistor structures and their manufacturing methods are explained. Figures 14A to 15C A top view and a cross-sectional view of a semiconductor device according to one aspect of the present invention are shown.

[0417] right Figures 14A to 15C The transistor shown is used for illustration. Figure 14A and Figure 15AIt is a top view. Figure 14B It corresponds to Figure 14A The cross-sectional view of the dotted line A1-A2 shown. Figure 14C It corresponds to Figure 14A The cross-sectional view shown is along the dashed-dot line A3-A4. Note that... Figure 14A In the top view, some of the constituent elements are omitted for clarity.

[0418] Figure 15B It corresponds to Figure 15A The cross-sectional view of the dotted line A1-A2 shown. Figure 15C It corresponds to Figure 15A The cross-sectional view shown is along the dashed-dot line A3-A4. Note that... Figure 15A In the top view, some of the constituent elements are omitted for clarity.

[0419] exist Figures 14A to 15C In the transistor shown, the insulator 406c2 (in) Figures 4A to 4C The middle is insulator 406c), insulator 406d2 (in Figures 4A to 4C Insulator 406d), insulator 412, conductor 404a, and conductor 404b are also formed in a portion of the top surface of insulator 410. Other constituent elements are referenced. Figures 10A to 10C or Figures 12A to 12C The transistor shown.

[0420] exist Figures 14A to 15C In the transistor shown, a portion of conductors 404a and 404b, which serve as gate electrodes, can also function as wiring. That is, separated by insulator 406c2 (in... Figures 4A to 4C The middle is insulator 406c), insulator 406d2 (in Figures 4A to 4C The conductors 404a and 404b formed on the insulator 410 (insulator 406d) and insulator 412 are equivalent to conductor 420 in transistor structure 1. Therefore, in this structure, t2 is the perpendicular distance between conductor 416a or conductor 416b and conductor 404a on the insulator 410. In addition, since insulator 406c2 (in Figures 4A to 4C The middle is insulator 406c), insulator 406d2 (in Figures 4A to 4C Insulator 406d), insulator 412, conductor 404a, and conductor 404b are formed simultaneously. Therefore, insulator 406c and insulator 406d2 are sandwiched between the top surface of insulator 410 and a portion of conductor 404a on insulator 410. Figures 4A to 4C The middle part consists of insulator 406d and insulator 412. Therefore, due to t2 (the thickness of insulator 410 plus the thickness of insulator 406c2), Figures 4A to 4CThe middle is insulator 406c), insulator 406d2 (in Figures 4A to 4C The thickness (length) of the insulator (406d) is large enough to suppress parasitic capacitance.

[0421] <Transistor Manufacturing Method 9 and Transistor Manufacturing Method 10>

[0422] Below, on Figures 14A to 14C The manufacturing method of the transistor shown will be explained.

[0423] First, proceed to the implementation method shown in Implementation Method 5. Figure 19F The process up to this point.

[0424] Next, insulators 406c, 406d, and 412, conductors 404a and 404b are formed using photolithography and other methods. By employing this structure, conductors equivalent to conductor 420 in transistor structure 1 can be formed simultaneously using conductors 404a and 404b.

[0425] Next, insulator 408 is formed.

[0426] Through the above steps, it is possible to form Figures 14A to 14C The transistor shown.

[0427] In addition, Figures 15A to 15C In the transistor shown, through with Figures 12A to 12C The transistor shown is formed using the same process as insulators 406c, 406d, 412, conductors 404a, and 404b, each with the desired shape. Then, insulators 406c, 406d, 412, conductors 404a, and 404b are formed using photolithography or similar methods. By employing this structure, conductors 404a and 404b can simultaneously form a conductor equivalent to conductor 420 in transistor structure 1.

[0428] Through the above steps, it is possible to form Figures 15A to 15C The transistor shown.

[0429] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0430] Implementation Method 8

[0431] <Transistor Structure 11 and Transistor Structure 12>

[0432] Below, refer to Figures 16A to 17C to and Figures 10A to 10C Different transistor structures and their manufacturing methods are explained. Figures 16A to 17C A top view and a cross-sectional view of a semiconductor device according to one aspect of the present invention are shown.

[0433] right Figures 16A to 17C The transistor shown is used for illustration. Figure 16A and Figure 17A It is a top view. Figure 16B It corresponds to Figure 16A The cross-sectional view of the dotted line A1-A2 shown. Figure 16C It corresponds to Figure 16A The cross-sectional view shown is along the dashed-dot line A3-A4. Note that... Figure 16A In the top view, some of the constituent elements are omitted for clarity.

[0434] Figure 17B It corresponds to Figure 17A The cross-sectional view of the dotted line A1-A2 shown. Figure 17C It corresponds to Figure 17A The cross-sectional view shown is along the dashed-dot line A3-A4. Note that... Figure 17A In the top view, some of the constituent elements are omitted for clarity.

[0435] exist Figures 16A to 17C In the transistor shown, conductors 416a and 416b are formed only on semiconductor 406b. Other constituent elements are referenced. Figures 10A to 10C or Figures 12A to 12C The transistor shown.

[0436] <Transistor Manufacturing Method 11 and Transistor Manufacturing Method 12>

[0437] Below, on Figures 16A to 16C The manufacturing method of the transistor shown will be explained.

[0438] First, proceed to the implementation method shown in Implementation Method 5. Figure 18A and Figure 18B The process up to this point.

[0439] Next, after forming the insulator 406a and the semiconductor 406b, a conductor 416 is formed. Then, a photoresist is formed on the conductor 416 using photolithography or the like, and the conductor 416 is etched using the photoresist as a mask. Next, the photoresist is removed, and then a second etching is performed using the conductor 416 as a mask. The second etching is performed on both the insulator 406a and the semiconductor 406b.

[0440] The next steps and Figure 18G and Figure 18H The subsequent processes are the same. Through the above steps, it is possible to form... Figures 16A to 16C The transistor shown.

[0441] In addition, Figures 17A to 17C The transistor shown also has... Figures 16A to 16CThe transistor shown similarly forms an insulator 406a, a semiconductor 406b, and a conductor 416. Then, preferably by means of... Figures 12A to 12C The transistor shown is formed using the same process.

[0442] Through the above steps, it is possible to form Figures 17A to 17C The transistor shown.

[0443] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0444] Implementation Method 9

[0445] <Deposition Device>

[0446] The structure of the deposition apparatus, including the sputtering device described above, will now be described. (Refer to...) Figures 23 to 24C The structure of a deposition apparatus with minimal impurities mixed into the film during deposition is described.

[0447] Figure 23 A schematic top view of a single-wafer multi-chamber deposition apparatus 1700 is shown. The deposition apparatus 1700 includes: an atmospheric-side substrate supply chamber 1701 having a cassette port 1761 for receiving a substrate and an alignment port 1762 for substrate alignment; an atmospheric-side substrate transfer chamber 1702 for transferring a substrate from the atmospheric-side substrate supply chamber 1701; a loading lock chamber 1703a for loading a substrate and switching the pressure in the chamber from atmospheric pressure to depressurization or vice versa; an unloading lock chamber 1703b for unloading a substrate and switching the pressure in the chamber from depressurization to atmospheric pressure or vice versa; a transfer chamber 1704 for transferring a substrate in a vacuum; a substrate heating chamber 1705 for heating the substrate; and deposition chambers 1706a, 1706b, and 1706c for deposition. All or part of the deposition chambers 1706a, 1706b and 1706c may employ the above-described sputtering apparatus 101.

[0448] In addition, such as Figure 23 As shown, multiple box-type interfaces 1761 can also be set (in Figure 23 (There are three in the middle).

[0449] The substrate transfer chamber 1702 on the atmospheric side is connected to the loading lock chamber 1703a and the unloading lock chamber 1703b. The loading lock chamber 1703a and the unloading lock chamber 1703b are connected to the transfer chamber 1704. The transfer chamber 1704 is connected to the substrate heating chamber 1705, the deposition chamber 1706a, the deposition chamber 1706b and the deposition chamber 1706c.

[0450] A gate valve 1764 is provided at the connection of each chamber, which can independently control the pressure of each chamber except for the substrate supply chamber 1701 and the substrate transfer chamber 1702 on the atmospheric side. The substrate transfer chamber 1702 and the transfer chamber 1704 on the atmospheric side are respectively equipped with transfer robots 1763a and 1763b, thereby enabling the transfer of substrates.

[0451] The substrate heating chamber 1705 preferably also serves as a plasma chamber. The deposition apparatus 1700 can transfer the substrate between processes without exposure to the atmosphere, thereby suppressing the adhesion of impurities from the atmosphere to the substrate. Furthermore, the order of deposition, heat treatment, etc., can be freely determined. The structures of the transfer chamber, deposition chamber, loading lock chamber, unloading lock chamber, and substrate heating chamber are not limited to the structures described above and can be appropriately determined according to the space or process conditions in which they are installed.

[0452] then, Figures 24A to 24C Show along Figure 23 The cross-sections of the deposition apparatus 1700 shown are defined by dashed lines X1-X2, Y1-Y2, and Y2-Y3.

[0453] Figure 24A The diagram shows a cross-section of a substrate heating chamber 1705 and a transfer chamber 1704. The substrate heating chamber 1705 has multiple heating stages 1765 capable of receiving a substrate. Figure 24A The diagram shows a structure with seven heating stages 1765, but it is not limited to this; one or more, but fewer than seven or more, heating stages can also be provided. By increasing the number of heating stages 1765, multiple substrates can be heated simultaneously, thus increasing productivity. The substrate heating chamber 1705 is connected to a vacuum pump 1770 via a valve. The vacuum pump 1770 can be, for example, a drying pump, a mechanical booster pump, etc.

[0454] As the substrate heating chamber 1705, heating can also be performed using a resistance heating element, for example. Alternatively, as the heating mechanism, heat conduction or thermal radiation from a medium such as the gas being heated can be used. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) and LRTA (Lamp Rapid Thermal Annealing) can be used. LRTA heats the workpiece by the radiation of light (electromagnetic waves) emitted by lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. GRTA utilizes a high-temperature gas for heating treatment. An inert gas is used as the gas.

[0455] The substrate heating chamber 1705 is connected to the purifier 1781 via a mass flow controller 1780. Note that although the number of mass flow controllers 1780 and purifiers 1781 depends on the number of gas types, only one mass flow controller 1780 and one purifier are shown for ease of understanding. The gas introduced into the substrate heating chamber 1705 can be a gas with a dew point below -80°C, preferably below -100°C, such as oxygen, nitrogen, and rare gases (argon, etc.).

[0456] The transfer chamber 1704 includes a transfer robot 1763b. The transfer robot 1763b has multiple movable parts and an arm for holding the substrate, thereby enabling the transfer of the substrate to each chamber. The transfer chamber 1704 is connected to a vacuum pump 1770 and a cryogenic pump 1771 via valves. With this structure, when the pressure inside the transfer chamber 1704 is atmospheric pressure to a low or medium vacuum (approximately 0.1 Pa to several hundred Pa), the vacuum pump 1770 can be used to vent the air, and then the valves can be switched to adjust the pressure inside the transfer chamber 1704 to a medium to high or ultra-high vacuum (0.1 Pa to 1 × 10⁻⁶ Pa). -7 When the pressure is Pa), a cryogenic pump 1771 can be used for venting.

[0457] For example, two or more cryogenic pumps 1771 can be connected in parallel with the transfer chamber 1704. By adopting the above structure, even when one cryogenic pump is undergoing regeneration, other cryogenic pumps can be used for venting. Note that the above regeneration refers to the process of releasing molecules (or atoms) accumulated in the cryogenic pump. When too many molecules (or atoms) accumulate in the cryogenic pump, its venting capacity decreases, thus requiring periodic regeneration.

[0458] Figure 24B Cross-sections of sedimentation chamber 1706b, transfer chamber 1704, and loading lock chamber 1703a are shown.

[0459] Here, refer to Figure 24BEach sedimentation chamber is described in detail. Note that for information on the structure of each sedimentation chamber, please refer to [link / reference needed]. Figure 21 The description of the sputtering apparatus 101 shown is appropriately combined with the following description. Figure 24B The deposition chamber 1706b shown includes a target 100, a substrate stage 170, and a collimator 150 disposed between the target and the substrate stage. Here, a substrate is disposed on the substrate stage 170. Although not shown, the substrate stage 170 may also include a substrate holding mechanism for holding the substrate or a back-side heater for heating the substrate from the back side.

[0460] The deposition chamber 1706b is connected to the mass flow controller 1780 via a gas heating mechanism 1782, which in turn is connected to the purifier 1781 via the mass flow controller 1780. The gas heating mechanism 1782 can heat the deposition gas to a temperature of 40°C or higher and 400°C or lower, preferably 50°C or higher and 200°C or lower. Note that although the number of gas heating mechanisms 1782, mass flow controllers 1780, and purifiers 1781 depends on the number of gas types, only one gas heating mechanism 1782, one mass flow controller 1780, and one purifier 1781 are shown for ease of understanding. As the deposition gas, a gas with a dew point of -80°C or lower is preferred, and more preferably -100°C or lower.

[0461] Parallel flat plate sputtering devices and ion beam sputtering devices can also be installed in deposition chamber 1706b.

[0462] When a purifier is installed near the gas inlet, the length of the pipe from the purifier 1781 to the deposition chamber 1706b is set to 10m or less, preferably 5m or less, and more preferably 1m or less. By setting the pipe length to 10m or less, 5m or less, or 1m or less, the impact of released gas from the pipe can be reduced depending on the pipe length. Furthermore, the gas pipe is preferably a metal pipe with an internal coating of iron fluoride, alumina, or chromium oxide. For example, compared to SUS316L-EP pipes, the above pipes release less gas containing impurities, thus reducing the mixing of impurities into the deposition gas. As for the pipe fittings, high-performance ultra-miniature metal gasket fittings (UPG fittings) are preferred. By using metal to constitute the entire pipe, the impact of released gas and external leakage can be reduced compared to using resin or the like, which is therefore preferred.

[0463] The deposition chamber 1706b is connected to the turbomolecular pump 1772 and the vacuum pump 1770 via valves. The deposition chamber 1706b preferably includes a cryogenic cold trap.

[0464] The cryogenic cold trap 1751 is a mechanism capable of adsorbing molecules (or atoms) with high melting points, such as water. The turbomolecular pump 1772 can stably discharge large molecules (or atoms) and has a low maintenance frequency, thus offering advantages in productivity; however, its capacity for hydrogen and water discharge is relatively low. Therefore, to improve the capacity for discharging water, a structure connecting the cryogenic cold trap 1751 to the deposition chamber 1706b is adopted. The temperature of the refrigerator in the cryogenic cold trap 1751 is below 100K, preferably below 80K. When the cryogenic cold trap 1751 has multiple refrigerators, it is preferable to set different temperatures for each refrigerator to efficiently discharge gases. For example, the temperature of the refrigerator in the first compartment can be set below 100K, and the temperature of the refrigerator in the second compartment can be set below 20K.

[0465] The venting method for sedimentation chamber 1706b is not limited to the method described above, and can be the same as the venting method for transfer chamber 1704 (the venting method using a cryogenic pump and a vacuum pump). Of course, the venting method for transfer chamber 1704 can also be the same as the venting method for sedimentation chamber 1706b (the venting method using a turbomolecular pump and a vacuum pump).

[0466] Preferably, the back pressure (total pressure) of the transfer chamber 1704, the substrate heating chamber 1705, and the deposition chamber 1706b, as well as the partial pressure of each gas molecule (atom), are set as follows. In particular, since impurities may be mixed into the formed film, attention needs to be paid to the back pressure of the deposition chamber 1706b and the partial pressure of each gas molecule (atom).

[0467] The back pressure (total pressure) of each of the above chambers is 1×10 -4 Pa or less, preferably 3×10 Pa -5 Pa or less, more preferably 1×10 Pa -5 Below Pa. The partial pressure of gas molecules (atoms) in each of the above chambers is 3 × 10⁸, with a mass-to-charge ratio (m / z) of 18. -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 Pa -6 Below Pa. Furthermore, the partial pressure of gas molecules (atoms) with an m / z of 28 in each of the above chambers is 3 × 10⁻⁸. -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 Pa -6 Below Pa. The partial pressure of gas molecules (atoms) in each of the above chambers with an m / z of 44 is 3 × 10⁻⁴. -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 Pa -6 Below Pa.

[0468] The total pressure and partial pressure within the vacuum chamber can be measured using a mass analyzer. For example, a quadrupole mass analyzer (also known as a Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. can be used.

[0469] Preferably, the external and internal leakage of the above-mentioned transfer chamber 1704, substrate heating chamber 1705 and deposition chamber 1706b is minimal.

[0470] For example, the leakage rate of the aforementioned transfer chamber 1704, substrate heating chamber 1705, and deposition chamber 1706b is 3 × 10⁻⁶. -6 Pa·m 3 Below / s, preferably 1×10 -6 Pa·m 3 Below / s. The leakage rate of gas molecules (atoms) with a m / z of 18 is 1×10 -7 Pa·m 3 Below / s, preferably 3×10 -8 Pa·m 3 Below / s. The leakage rate of gas molecules (atoms) with a m / z of 28 is 1×10 -5 Pa·m 3 Below / s, preferably 1×10 -6 Pa·m 3 Below / s. The leakage rate of gas molecules (atoms) with a m / z of 44 is 3 × 10⁻⁶. -6 Pa·m 3 Below / s, preferably 1×10 -6 Pa·m 3 / s or less.

[0471] The leakage rate can be calculated based on the total pressure and partial pressure measured using the aforementioned mass analyzer.

[0472] The leakage rate depends on both external and internal leakage. External leakage refers to the inflow of gas from the outside of the vacuum system through tiny holes or poor seals. Internal leakage occurs due to leaks through valves or other baffles in the vacuum system, or from released gas from internal components. To keep the leakage rate below these values, measures need to be taken to address both external and internal leakage.

[0473] For example, a metal gasket is preferably used to seal the opening and closing parts of the deposition chamber 1706b. The metal gasket is preferably made of a metal coated with iron fluoride, alumina, or chromium oxide. The metal gasket has a higher tightness than an O-ring, thus reducing external leakage. By utilizing a passivated metal coated with iron fluoride, alumina, chromium oxide, etc., the release of gases containing impurities from the metal gasket can be suppressed, thereby reducing internal leakage.

[0474] As components constituting the deposition apparatus 1700, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which contain few released gases and contain impurities, are used. Alternatively, alloys containing iron, chromium, and nickel can be used to coat the components. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and easy to process. Here, by reducing the surface roughness of the components through polishing or other methods to decrease the surface area, the released gases can be reduced.

[0475] Alternatively, iron fluoride, aluminum oxide, chromium oxide, etc., can be used to cover the components of the above-mentioned deposition device 1700.

[0476] The components of the preferred deposition apparatus 1700 are preferably made of metal. For example, when a viewing window made of quartz or the like is provided, in order to suppress the release of gas, it is preferable to cover the surface of the viewing window with a thin layer of iron fluoride, aluminum oxide, or chromium oxide.

[0477] The deposits present in the sedimentation chamber adhere to the inner wall and do not affect the pressure of the sedimentation chamber, but these deposits become the cause of gas release when the sedimentation chamber is vented. Therefore, although the leakage rate is not related to the venting rate, it is very important to use a pump with a high venting capacity to remove the deposits present in the sedimentation chamber as much as possible and to vent them in advance. To promote the removal of deposits, the sedimentation chamber can also be baked. Baking can increase the removal rate of deposits by about 10 times. Baking can be carried out at a temperature of 100°C or higher and 450°C or lower. At this time, by introducing inert gas into the sedimentation chamber while removing deposits, the removal rate of water and other substances that are not easily removed by venting alone can be further improved. By heating the inert gas to a temperature similar to the baking temperature, the removal rate of deposits can be further improved. Here, rare gases are preferably used as inert gases. Depending on the type of film being deposited, oxygen or the like can also be used instead of inert gases. For example, when depositing oxides, oxygen, the main component of oxides, is sometimes preferred.

[0478] Furthermore, it is preferable to increase the pressure inside the sedimentation chamber by using an inert gas such as a heated rare gas or oxygen, and then vent the sedimentation chamber again after a certain period of time. The heated gas can detach the deposits inside the sedimentation chamber, thereby reducing the impurities present inside the sedimentation chamber. Effective results can be obtained by repeating this process 2 to 30 times, preferably 5 to 15 times. Specifically, by introducing an inert gas or oxygen at a temperature of 40°C to 400°C, preferably 50°C to 200°C, the pressure inside the sedimentation chamber can be maintained at 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa, for a period of 1 to 300 minutes, preferably 5 to 120 minutes. Then, the sedimentation chamber is vented for 5 to 300 minutes, preferably 10 to 120 minutes.

[0479] Furthermore, spoofing can further improve the detachment rate of deposited material. Spoofing refers to depositing a film on a spoofed substrate and the walls of the deposition chamber using methods such as sputtering, thereby encapsulating impurities and deposited material within the deposition chamber. A substrate with low gas release is preferred as the spoofed substrate. Spoofing can reduce the impurity concentration in the subsequently deposited film. Additionally, spoofing can be performed simultaneously with the baking process of the deposition chamber.

[0480] Next, the explanation Figure 24B The transfer chamber 1704 and the loading lock chamber 1703a shown are as follows: Figure 24C The detailed structure of the substrate transfer chamber 1702 on the atmospheric side and the substrate supply chamber 1701 on the atmospheric side is shown. Figure 24C The cross-sections of the substrate transfer chamber 1702 on the atmospheric side and the substrate supply chamber 1701 on the atmospheric side are shown.

[0481] about Figure 24B The teleportation room 1704 shown is referenced. Figure 24A The record shows the teleportation room 1704.

[0482] The loading lock chamber 1703a has a substrate transfer stage 1752. When the pressure in the loading lock chamber 1703a rises from depressurization to atmospheric pressure, the substrate transfer stage 1752 receives the substrate from the transfer robot 1763a located in the substrate transfer chamber 1702 on the atmospheric side. Then, after the loading lock chamber 1703a is evacuated and placed in a depressurized state, the transfer robot 1763b located in the transfer chamber 1704 receives the substrate from the substrate transfer stage 1752.

[0483] The loading lock chamber 1703a is connected to the vacuum pump 1770 and the cryogenic pump 1771 via valves. The connection method for the exhaust systems of the vacuum pump 1770, cryogenic pump 1771, etc., can be referred to the connection method of the transfer chamber 1704, so it is omitted here. Figure 23 The unloading lock chamber 1703b shown can adopt the same structure as the loading lock chamber 1703a.

[0484] The substrate transfer chamber 1702 on the atmospheric side has a transfer robot 1763a. The transfer robot 1763a can deliver the substrate between the cassette interface 1761 and the loading lock chamber 1703a. Mechanisms such as HEPA filters (High Efficiency Particulate Air Filters) can also be provided above the substrate transfer chamber 1702 and the substrate supply chamber 1701 on the atmospheric side to prevent the entry of dust or particles.

[0485] The substrate supply chamber 1701 on the atmospheric side has multiple cassette interfaces 1761. The cassette interfaces 1761 can accommodate multiple substrates.

[0486] The surface temperature of the target material is below 100°C, preferably below 50°C, and more preferably at room temperature (typically 25°C). Sputtering apparatuses for large-area substrates mostly use large-area targets. However, it is difficult to manufacture targets with sizes corresponding to large areas without seams. In actual manufacturing, multiple targets are arranged in a large shape with as few gaps as possible, but there will always be tiny gaps. When the surface temperature of the target material increases, zinc and other materials may volatilize from these tiny gaps, causing the gaps to gradually widen. When the gaps widen, metals used for backing and bonding may also be sputtered, which is a major cause of increased impurity concentration. Therefore, it is preferable to adequately cool the target material.

[0487] Specifically, a metal with high electrical conductivity and high heat dissipation (specifically copper) is used as the backing plate. By forming water channels within the backing plate and allowing a sufficient amount of cooling water to flow through these channels, the target material can be cooled efficiently.

[0488] When the target material contains zinc, plasma damage is reduced by deposition in an oxygen atmosphere, thereby obtaining an oxide semiconductor that is less prone to zinc volatilization.

[0489] By using the above-described deposition apparatus, impurities can be prevented from mixing into the formed film.

[0490] Implementation Method 10

[0491] <Manufacturing Equipment>

[0492] The manufacturing apparatus for high-density plasma processing according to one aspect of the present invention will now be described.

[0493] First, refer to Figure 25 , Figure 26 and Figure 27 The structure of a manufacturing apparatus that minimizes the introduction of impurities during the manufacture of semiconductor devices is described.

[0494] Figure 25 This is a schematic top view of a monolithic multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes: an atmospheric-side substrate supply chamber 2701 having a cassette interface 2761 for receiving substrates and an alignment interface 2762 for performing substrate alignment; an atmospheric-side substrate transfer chamber 2702 for transferring substrates from the atmospheric-side substrate supply chamber 2701; a loading lock chamber 2703a for loading substrates and switching the pressure in the chamber from atmospheric pressure to depressurization or from depressurization to atmospheric pressure; an unloading lock chamber 2703b for unloading substrates and switching the pressure in the chamber from depressurization to atmospheric pressure or from atmospheric pressure to depressurization; a transfer chamber 2704 for transferring substrates in a vacuum; chambers 2706a, 2706b, 2706c; and 2706d.

[0495] The substrate transfer chamber 2702 on the atmospheric side is connected to the loading lock chamber 2703a and the unloading lock chamber 2703b. The loading lock chamber 2703a and the unloading lock chamber 2703b are connected to the transfer chamber 2704. The transfer chamber 2704 is connected to the chambers 2706a, 2706b, 2706c and 2706d.

[0496] Gate valves GV are installed at the connection points of each chamber, allowing each chamber except for the substrate supply chamber 2701 and substrate transfer chamber 2702 on the atmospheric side to be independently maintained in a vacuum state. Furthermore, a transfer robot 2763a is installed in the substrate transfer chamber 2702 on the atmospheric side, and a transfer robot 2763b is installed in the transfer chamber 2704. The substrate can be transferred within the manufacturing apparatus 2700 by the transfer robots 2763a and 2763b.

[0497] The back pressure (total pressure) of transfer chamber 2704 and chambers 2706a to 2706d is, for example, 1 × 10⁻⁶. -4 Pa or less, preferably 3×10 Pa -5 Pa or less, more preferably 1×10 Pa -5 Below Pa. The mass-to-charge ratio (m / z) of the gas molecules (atoms) in the transfer chamber 2704 and chambers 2706a to 2706d is 18, and the partial pressure is, for example, 3 × 10⁻⁶. -5 Pa or less, preferably 1×10 -5Pa or less, more preferably 3×10 Pa -6 Below Pa. Furthermore, the partial pressures of gas molecules (atoms) with m / z of 28 in the transfer chamber 2704 and chambers 2706a to 2706d are, for example, 3 × 10⁻⁸. -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 Pa -6 Below Pa. The partial pressure of gas molecules (atoms) with m / z of 44 in transmission chamber 2704 and chambers 2706a to 2706d is, for example, 3 × 10⁻⁴. -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 Pa -6 Below Pa.

[0498] The total pressure and partial pressure within transfer chamber 2704 and chambers 2706a to 2706d can be measured using a mass analyzer. For example, a four-pole mass analyzer (also known as a Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. can be used.

[0499] Furthermore, the transfer chamber 2704 and chambers 2706a to 2706d preferably have a structure with minimal external or internal leakage. For example, the leakage rate of the transfer chamber 2704 and chambers 2706a to 2706d is 3 × 10⁻⁶. -6 Pa·m 3 Below / s, preferably 1×10 - 6 Pa·m 3 Below / s. Additionally, for example, the leakage rate of gas molecules (atoms) with an m / z of 18 is 1 × 10⁻⁶. -7 Pa·m 3 Below / s, preferably 3×10 -8 Pa·m 3 Below / s. For example, the leakage rate of gas molecules (atoms) with m / z of 28 is 1×10 -5 Pa·m 3 Below / s, preferably 1×10 -6 Pa·m 3 Below / s. For example, the leakage rate of gas molecules (atoms) with m / z of 44 is 3 × 10⁻⁶. -6 Pa·m 3 Below / s, preferably 1×10 -6 Pa·m 3 / s or less.

[0500] The leakage rate can be calculated based on the total pressure and partial pressure measured using the aforementioned mass analyzer. The leakage rate depends on both external and internal leakage. External leakage refers to the inflow of gas from outside the vacuum system through tiny holes or poor seals. Internal leakage occurs due to leaks through valves or other baffles in the vacuum system, or from released gas from internal components. To keep the leakage rate below the aforementioned values, measures need to be taken to address both external and internal leakage.

[0501] For example, metal gaskets are preferably used to seal the opening and closing portions of the transfer chamber 2704 and chambers 2706a to 2706d. The metal gaskets are preferably made of metal coated with iron fluoride, alumina, or chromium oxide. Metal gaskets offer higher tightness than O-rings, thus reducing external leakage. By utilizing a passivated metal coated with iron fluoride, alumina, chromium oxide, etc., the release of impurity-containing gases from the metal gasket can be suppressed, thereby reducing internal leakage.

[0502] As components constituting the manufacturing apparatus 2700, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which contain few impurities and release gases, are used. Alternatively, alloys containing iron, chromium, and nickel can be used as coatings. Alloys containing iron, chromium, and nickel are rigid, heat-resistant, and easy to process. Here, by reducing the surface roughness of the component through polishing or other methods to decrease the surface area, the release of gases can be reduced.

[0503] Alternatively, ferric fluoride, alumina, chromium oxide, etc., can be used to cover the components of the manufacturing apparatus 2700.

[0504] The components of the preferred manufacturing apparatus 2700 are preferably made of metal. For example, when a viewing window made of quartz or the like is provided, in order to suppress the release of gas, it is preferable to cover the surface of the viewing window with a thin layer of iron fluoride, aluminum oxide or chromium oxide.

[0505] The deposits present in the transfer chambers 2704 and chambers 2706a to 2706d adhere to the inner walls, and therefore do not affect the pressure in the transfer chambers 2704 and chambers 2706a to 2706d. However, these deposits become the cause of gas release during venting of the transfer chambers 2704 and chambers 2706a to 2706d. Therefore, although the leakage rate is not related to the venting rate, it is very important to use a pump with a high venting capacity to remove the deposits present in the transfer chambers 2704 and chambers 2706a to 2706d as much as possible and to vent them in advance. To promote the removal of deposits, the transfer chambers 2704 and chambers 2706a to 2706d can also be baked. Baking can increase the removal rate of deposits by about 10 times. Baking can be carried out at a temperature of 100°C or higher and 450°C or lower. At this time, by introducing inert gas into the transfer chamber 2704 and chambers 2706a to 2706d while removing the adhering substances, the removal speed of substances such as water that are not easily removed by exhaust alone can be further improved. The removal speed of the adhering substances can be further improved by heating the introduced inert gas to a temperature similar to the baking temperature. Here, a rare gas is preferably used as the inert gas.

[0506] Alternatively, it is preferable to increase the pressure within the transfer chambers 2704 and cavities 2706a to 2706d by introducing heated inert gases such as rare gases or oxygen, and then exhaust the gas from the transfer chambers 2704 and cavities 2706a to 2706d again after a certain period of time. The introduction of heated gas can cause deposits to detach from the transfer chambers 2704 and cavities 2706a to 2706d, thereby reducing impurities present in these chambers. Effective results can be obtained by repeating this process more than twice and less than 30 times, preferably more than five times and less than 15 times. Specifically, by introducing an inert gas or oxygen at a temperature of 40°C or higher and 400°C or lower, preferably 50°C or higher and 200°C or lower, the pressure in the transfer chamber 2704 and chambers 2706a to 2706d can be maintained at 0.1 Pa or higher and 10 kPa or lower, preferably 1 Pa or higher and 1 kPa or lower, more preferably 5 Pa or higher and 100 Pa or lower, for a period of 1 to 300 minutes, preferably 5 minutes or higher and 2706d. Then, the transfer chamber 2704 and chambers 2706a to 2706d are vented for 5 to 300 minutes, preferably 10 to 120 minutes.

[0507] Next, refer to Figure 26 The cross-sectional schematic diagram shown illustrates chambers 2706b and 2706c.

[0508] Chambers 2706b and 2706c are, for example, chambers capable of performing high-density plasma treatment on the workpiece. Note that the only difference between chambers 2706b and 2706c is the atmosphere used for high-density plasma treatment. Other structural features are common and will therefore be described below.

[0509] Chambers 2706b and 2706c include a slotted antenna plate 2808, a dielectric plate 2809, a substrate stage 2812, and an exhaust port 2819. Additionally, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are disposed on the outside of chambers 2706b and 2706c.

[0510] A high-frequency generator 2803 is connected to a mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slotted antenna plate 2808 via a waveguide 2807. The slotted antenna plate 2808 is grounded in contact with a dielectric plate 2809. A gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is supplied to chambers 2706b and 2706c via a gas pipe 2806 passing through the mode converter 2805, waveguide 2807, and dielectric plate 2809. A vacuum pump 2817 can discharge gas from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. A high-frequency power supply 2816 is connected to a substrate stage 2812 via a matching adapter 2815.

[0511] The substrate stage 2812 is capable of holding the substrate 2811. For example, the substrate 2811 can be held electrostatically or mechanically. In addition, it can also be used as an electrode to which power is supplied from the high-frequency power supply 2816. Furthermore, the substrate stage 2812 includes a heating mechanism 2813, which is capable of heating the substrate 2811.

[0512] As the vacuum pump 2817, for example, a drying pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryogenic pump, or a turbomolecular pump can be used. In addition to the vacuum pump 2817, a cryogenic cold trap can also be used. When using a cryogenic pump and a cryogenic cold trap, water can be efficiently discharged, making them particularly preferred.

[0513] As the heating mechanism 2813, a heating mechanism that uses a resistance heating element or the like for heating can be used. Alternatively, a heating mechanism that uses heat conduction or heat radiation from a medium such as a gas to be heated can also be used. For example, RTAs such as GRTA and LRTA can be used. GRTA uses a high-temperature gas for heating. An inert gas is used as the gas.

[0514] Alternatively, the gas supply source 2801 can also be connected to the purifier via a mass flow controller. Preferably, a gas with a dew point below -80°C, and more preferably below -100°C, is used. For example, oxygen gas, nitrogen gas, and rare gases (such as argon) can be used.

[0515] For example, silicon dioxide (quartz), aluminum oxide, or yttrium oxide can be used as the dielectric plate 2809. Alternatively, a protective layer can be formed on the surface of the dielectric plate 2809. Magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide can be used as the protective layer. Since the dielectric plate 2809 will be exposed to the high-density plasma 2810, especially the high-density region, as described later, the protective layer can mitigate damage. As a result, the increase of particles during processing can be suppressed.

[0516] The high-frequency generator 2803 is capable of generating microwaves, for example, at frequencies above 0.3 GHz and below 3.0 GHz, above 0.7 GHz and below 1.1 GHz, and above 2.2 GHz and below 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to a mode converter 2805 via a waveguide 2804. In the mode converter 2805, the microwaves transmitted in TE mode are converted to TEM mode. The microwaves are then transmitted to a slotted antenna plate 2808 via a waveguide 2807. Multiple slots are provided in the slotted antenna plate 2808, through which the microwaves pass and through a dielectric plate 2809. An electric field is generated below the dielectric plate 2809, thereby generating a high-density plasma 2810. The high-density plasma 2810 contains ions and free radicals corresponding to the types of gas supplied from the gas supply source 2801. For example, oxygen free radicals or nitrogen free radicals are present.

[0517] At this time, the ions and free radicals generated in the high-density plasma 2810 can alter the properties of the film, etc., on the substrate 2811. Furthermore, it is sometimes preferable to apply a bias voltage to the substrate 2811 using a high-frequency power supply 2816. For example, an RF power supply with a frequency of 13.56 MHz or 27.12 MHz can be used as the high-frequency power supply 2816. By applying a bias voltage to the substrate, ions in the high-density plasma 2810 can efficiently reach the depth of openings in the film, etc., on the substrate 2811.

[0518] For example, in chamber 2706b, oxygen radical treatment can be performed using high-density plasma 2810 by introducing oxygen from gas supply source 2801, while in chamber 2706c, nitrogen radical treatment can be performed using high-density plasma 2810 by introducing nitrogen from gas supply source 2801.

[0519] Next, refer to Figure 27 The cross-sectional schematic diagram shown illustrates chambers 2706a and 2706d.

[0520] Chambers 2706a and 2706d, for example, are capable of irradiating the object being treated with electromagnetic waves. Note that the only difference between chambers 2706a and 2706d is the type of electromagnetic wave. Since the other structures are common, they will be described below.

[0521] Chambers 2706a and 2706d include one or more lamps 2820, a substrate stage 2825, a gas inlet 2823, and an exhaust port 2830. Additionally, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are disposed outside chambers 2706a and 2706d.

[0522] A gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. A vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. A lamp 2820 is configured opposite to a substrate stage 2825. The substrate stage 2825 is capable of holding a substrate 2824. Furthermore, the substrate stage 2825 includes a heating mechanism 2826 internally, capable of heating the substrate 2824.

[0523] As for lamp 2820, a light source capable of emitting electromagnetic waves such as visible light or ultraviolet light can be used. For example, a light source capable of emitting electromagnetic waves with peak values ​​in the wavelength range of 10 nm to 2500 nm, 500 nm to 2000 nm, and 40 nm to 340 nm can be used.

[0524] For example, halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps can be used as light sources for lamp 2820.

[0525] For example, some or all of the electromagnetic waves emitted from lamp 2820 are absorbed by substrate 2824, thereby altering the properties of films, etc., on substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. Furthermore, by emitting electromagnetic waves while heating substrate 2824, defects can be generated or reduced, or impurities can be removed efficiently.

[0526] Alternatively, for example, electromagnetic waves emitted from lamp 2820 can be used to heat the substrate stage 2825, thereby heating the substrate 2824. In this case, the heating mechanism 2826 may not be required inside the substrate stage 2825.

[0527] Regarding vacuum pump 2828, refer to the description of vacuum pump 2817. Regarding heating mechanism 2826, refer to the description of heating mechanism 2813. Regarding gas supply source 2821, refer to the description of gas supply source 2801.

[0528] By using the manufacturing apparatus described above, it is possible to suppress the mixing of impurities into the workpiece while altering the properties of the membrane.

[0529] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0530] Implementation Method 11

[0531] <Structure of Oxide Semiconductors>

[0532] The structure of oxide semiconductors will be described below.

[0533] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include: CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous like oxide semiconductor), and amorphous oxide semiconductors.

[0534] From another perspective, oxide semiconductors are divided into amorphous oxide semiconductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include: single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS.

[0535] It is known that amorphous structures are generally defined as being in a metastable state and not fixed, exhibiting isotropy but not inhomogeneity. In other words, the bond angles of amorphous structures are not fixed, and they possess short-range order but not long-range order.

[0536] This means that substantially stable oxide semiconductors cannot be called completely amorphous oxide semiconductors. Furthermore, oxide semiconductors that are not isotropic (e.g., oxide semiconductors with periodic structures in small regions) cannot be called completely amorphous oxide semiconductors. Note that a-like OS has periodic structures in small regions, but also has voids and an unstable structure. Therefore, a-like OS exhibits properties close to those of amorphous oxide semiconductors.

[0537] <caac-os>

[0538] First, let's explain CAAC-OS.

[0539] CAAC-OS is one of the oxide semiconductors that contains multiple c-axis oriented crystalline regions (also known as particles).

[0540] In the composite analysis image of the bright-field image and diffraction pattern of CAAC-OS obtained using transmission electron microscopy (TEM), also known as a high-resolution TEM image, multiple particles were observed. However, in the high-resolution TEM image, the clear boundaries between particles, i.e., grain boundaries, were not observed. Therefore, in CAAC-OS, the reduction in electron mobility caused by grain boundaries is not easily observed.

[0541] The following section describes the CAAC-OS observed using TEM. Figure 28A This shows a high-resolution TEM image of the CAAC-OS cross-section as viewed from a direction approximately parallel to the sample plane. This high-resolution TEM image was obtained using the spherical aberration corrector function. High-resolution TEM images obtained using the spherical aberration corrector function are specifically referred to as Cs-corrected high-resolution TEM images. For example, Cs-corrected high-resolution TEM images can be obtained using an atomic resolution analytical electron microscope (JEM-ARM200F) manufactured by Nippon Electron Ltd.

[0542] Figure 28B yes Figure 28A A magnified Cs-corrected high-resolution TEM image of region (1) in the image. Figure 28B The diagram shows that the metal atoms in the particles are arranged in layers. Each layer of metal atoms has a convex-concave configuration that reflects the surface (hereinafter also referred to as the forming surface) or the top surface of the CAAC-OS, and is arranged in a manner parallel to the forming surface or the top surface of the CAAC-OS.

[0543] like Figure 28B As shown, CAAC-OS has a unique atomic arrangement. Figure 28C In the diagram, auxiliary lines are used to indicate the unique atomic arrangement. Figure 28B and Figure 28C The particles shown have a size of 1 nm or more, or 3 nm or more, and the gaps created by the tilt between the particles are approximately 0.8 nm in size. Therefore, the particles can also be referred to as nanocrystals (nc). Note that CAAC-OS can also be referred to as an oxide semiconductor with CANC (c-axis aligned nanocrystals).

[0544] Here, based on Cs-corrected high-resolution TEM images, the configuration of CAAC-OS particles 5100 on substrate 5120 is schematically represented as a structure of stacked bricks or blocks (see reference). Figure 28D ).exist Figure 28C The tilted portion of the particles observed in the middle corresponds to Figure 28D The area shown is 5161.

[0545] Figure 29A This shows a Cs-corrected high-resolution TEM image of the CAAC-OS plane obtained by viewing from a direction approximately perpendicular to the sample surface. Figure 29B , Figure 29C and Figure 29D They are Figure 29A Cs-corrected high-resolution TEM images of regions (1), (2), and (3) in the image. Figure 29B , Figure 29C and Figure 29D The diagram shows that the metal atoms in the particles are arranged in triangular, square, or hexagonal shapes. However, the arrangement of metal atoms is not regular between different particles.

[0546] Next, the analysis of CAAC-OS using X-ray diffraction (XRD) will be explained. For example, when analyzing the structure of CAAC-OS containing InGaZnO4 crystals using the out-of-plane method, such as... Figure 30A As shown, a peak appears near the diffraction angle (2θ) of 31°. This peak originates from the (009) plane of the InGaZnO4 crystal, indicating that the crystals in CAAC-OS have a c-axis orientation, and that the c-axis is oriented approximately perpendicular to the formation plane or top surface of CAAC-OS.

[0547] Note that in the structural analysis of CAAC-OS using the out-of-plane method, in addition to the peak value near 2θ 31°, a peak value sometimes also appears near 2θ 36°. The peak value near 2θ 36° indicates that a portion of the CAAC-OS contains crystals that do not have c-axis orientation. Preferably, in the analysis of CAAC-OS using the out-of-plane method, a peak value appears near 2θ 31° but no peak value appears near 2θ 36°.

[0548] On the other hand, in the CAAC-OS structural analysis using the in-plane method with X-rays incident on the sample from a direction approximately perpendicular to the c-axis, a peak appears around 2θ is 56°. This peak originates from the (110) plane of the InGaZnO4 crystal. In CAAC-OS, when the analysis (φ scan) is performed with 2θ fixed around 56° and the sample rotated about the normal vector of the sample plane as the axis (φ axis), as shown... Figure 30B As shown, no clear peak is observed. In contrast, in single-crystal oxide semiconductors of InGaZnO4, when φ is scanned with 2θ fixed at around 56°, as... Figure 30C As shown, six peaks originating from the crystal plane equivalent to (110) were observed. Therefore, structural analysis using XRD indicates that the orientations of the a-axis and b-axis in CAAC-OS are irregular.

[0549] Next, the analysis using CAAC-OS via electron diffraction will be explained. For example, when an electron beam with a diameter of 300 nm is incident on a CAAC-OS containing InGaZnO4 crystals in a direction parallel to the sample plane, the following results can be obtained: Figure 31A The diffraction pattern shown is also known as a selected area transmission electron diffraction pattern. This diffraction pattern contains spots originating from the (009) plane of InGaZnO4 crystallization. Therefore, electron diffraction also indicates that the particles contained in CAAC-OS have a c-axis orientation, and that the c-axis is oriented approximately perpendicular to the formation plane or top surface of CAAC-OS. On the other hand, Figure 31B The diagram shows the diffraction pattern obtained when an electron beam with a diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample plane. (Example:) Figure 31B As shown, a ring-shaped diffraction pattern was observed. Therefore, electron diffraction also indicates that the a-axis and b-axis of the particles contained in CAAC-OS are not oriented. It can be considered that... Figure 31B The first ring in the crystal originates from the (010) and (100) planes of InGaZnO4 crystals. It can be considered that... Figure 31B The second ring in the middle is caused by (110) surface, etc.

[0550] As mentioned above, CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors can sometimes be reduced due to the incorporation of impurities or the formation of defects. This means that CAAC-OS has fewer impurities and defects (e.g., oxygen vacancies).

[0551] In addition, impurities refer to elements other than the main components of an oxide semiconductor, such as hydrogen, carbon, silicon, or transition metals. For example, elements such as silicon, which have a stronger bonding force with oxygen than the metals contained in the oxide semiconductor, can remove oxygen from the oxide semiconductor, thereby disrupting the atomic arrangement and leading to decreased crystallinity. Because heavy metals such as iron or nickel, argon, carbon dioxide, etc., have large atomic radii (or molecular radii), they can also disrupt the atomic arrangement of oxide semiconductors, leading to decreased crystallinity.

[0552] The properties of oxide semiconductors containing impurities or defects can sometimes change due to light or heat. For example, impurities in oxide semiconductors can sometimes act as carrier traps or carrier sources. In addition, oxygen vacancies in oxide semiconductors can sometimes act as carrier traps or carrier sources when they capture hydrogen.

[0553] CAAC-OS with low impurities and oxygen vacancies is an oxide semiconductor with low carrier density (specifically, below 8 × 10⁻⁶). 11 pcs / cm 3 Preferably less than 1×10 11 pcs / cm 3 More preferably, less than 1×10 10 pcs / cm 3 And it is 1×10 -9 pcs / cm 3 (Above). Such oxide semiconductors are called high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. CAAC-OS has low impurity concentration and defect state density. Therefore, CAAC-OS can be called an oxide semiconductor with stable properties.

[0554] <nc-os>

[0555] Next, we will explain nc-OS.

[0556] In high-resolution TEM images of nc-OS, there are regions where crystalline regions are observable and regions where crystalline regions are not clearly observable. In most cases, the crystalline regions contained in nc-OS have a size greater than 1 nm and less than 10 nm, or greater than 1 nm and less than 3 nm. Note that oxide semiconductors with crystalline regions larger than 10 nm and less than 100 nm are sometimes referred to as microcrystalline oxide semiconductors. For example, grain boundaries are sometimes not clearly observable in high-resolution TEM images of nc-OS. Note that the origin of nanocrystals may be the same as that of particles in CAAC-OS. Therefore, the crystalline regions of nc-OS are sometimes referred to as particles below.

[0557] In nc-OS, the atomic arrangement in tiny regions (e.g., regions larger than 1 nm and smaller than 10 nm, particularly regions larger than 1 nm and smaller than 3 nm) exhibits periodicity. There is no regularity in the crystalline orientation between different particles in nc-OS. Therefore, no orientation is observed in the overall film. Thus, depending on the analytical method, nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when nc-OS is analyzed using out-of-plane X-rays with a beam diameter larger than the particles, no peaks representing crystalline planes are detected. Furthermore, when nc-OS is electron diffracted using electron beams with a beam diameter larger than the particles (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when irradiated with electron beams with a beam diameter close to or smaller than the particles, spots are observed in the nanobeam electron diffraction of nc-OS. Additionally, circular (ring-shaped) high-brightness regions are sometimes observed in the nanobeam electron diffraction pattern of nc-OS. Multiple spots are sometimes also observed within ring-shaped regions in the nanobeam electron diffraction pattern of nc-OS.

[0558] Thus, since there is no regularity in the crystallization orientation between particles (nanocrystals), nc-OS can also be called an oxide semiconductor containing RANC (random aligned nanocrystals) or an oxide semiconductor containing NANC (non-aligned nanocrystals).

[0559] nc-OS is an oxide semiconductor with higher regularity than amorphous oxide semiconductors. Therefore, the defect state density of nc-OS is lower than that of a-like OS and amorphous oxide semiconductors. Note that there is no regularity in crystal orientation among different particles in nc-OS. Therefore, the defect state density of nc-OS is higher than that of CAAC-OS.

[0560] <a-like OS>

[0561] a-like OS has a structure that falls between nc-OS and amorphous oxide semiconductor.

[0562] Voids are sometimes observed in high-resolution TEM images of a-like OS. Additionally, high-resolution TEM images show areas where crystallization is clearly visible and areas where it is not.

[0563] Because a-like OS contains voids, its structure is unstable. To demonstrate that a-like OS has an unstable structure compared to CAAC-OS and nc-OS, the structural changes caused by electron irradiation are shown below.

[0564] As samples for electron irradiation, a-like OS (referred to as sample A), nc-OS (referred to as sample B), and CAAC-OS (referred to as sample C) were prepared. Each sample was an In-Ga-Zn oxide.

[0565] First, high-resolution cross-sectional TEM images of each sample were obtained. These high-resolution cross-sectional TEM images show that each sample has a crystalline structure.

[0566] Note that the determination of which part is considered the crystalline region is as follows. It is known that the unit lattice of InGaZnO4 crystals has a structure consisting of nine layers stacked in a layered manner along the c-axis, comprising three In-O layers and six Ga-Zn-O layers. The spacing between these closely spaced layers is equal to the lattice surface spacing (also known as the d-value) of the (009) plane, which is determined to be 0.29 nm by crystal structure analysis. Therefore, the portion with a lattice fringe spacing greater than 0.28 nm and less than 0.30 nm can be considered the InGaZnO4 crystalline region. Each lattice fringe corresponds to the ab plane of the InGaZnO4 crystal.

[0567] Figure 32 The variation in the average size of the crystalline portions (from 22 to 45 portions) of each sample is shown. Note that the crystalline portion size corresponds to the length of the lattice fringes described above. Figure 32 This indicates that the crystalline region in an a-like OS gradually increases in size based on the cumulative amount of electron irradiation. Specifically, such as... Figure 32 As shown in (1), in the initial observation using TEM, the crystal portion (also known as the initial nucleus) with a size of about 1.2 nm was observed with a cumulative irradiation dose of 4.2 × 10⁻⁶. 8 e - / nm 2 The growth rate reached approximately 2.6 nm. On the other hand, the cumulative electron irradiation dose for both nc-OS and CAAC-OS from the start of electron irradiation to the present was 4.2 × 10⁻⁶. 8 e - / nm 2 Within this range, the size of the crystallized portion remained unchanged. Specifically, such as Figure 32 As shown in (2) and (3), regardless of the cumulative electron irradiation, the average crystal size of nc-OS and CAAC-OS is about 1.4 nm and about 2.1 nm, respectively.

[0568] Thus, electron irradiation can sometimes induce the growth of crystalline regions in a-like OS. On the other hand, in nc-OS and CAAC-OS, there is almost no growth of crystalline regions induced by electron irradiation. Therefore, a-like OS has an unstable structure compared to nc-OS and CAAC-OS.

[0569] Because a-like OS contains voids, its density is lower than that of nc-OS and CAAC-OS. Specifically, the density of a-like OS is more than 78.6% and less than 92.3% of that of single-crystal oxide semiconductors with the same composition. The densities of nc-OS and CAAC-OS are more than 92.3% and less than 100% of those of single-crystal oxide semiconductors with the same composition. Note that it is difficult to deposit oxide semiconductors with a density less than 78% of that of single-crystal oxide semiconductors.

[0570] For example, in oxide semiconductors with an atomic ratio of In:Ga:Zn = 1:1:1, the density of a single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm³. 3 Therefore, for example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the density of a-like OS is 5.0 g / cm³. 3 Above and less than 5.9 g / cm 3 For example, in oxide semiconductors with an atomic ratio of In:Ga:Zn = 1:1:1, the densities of nc-OS and CAAC-OS are 5.9 g / cm³. 3 Above and less than 6.3 g / cm 3 .

[0571] Note that sometimes there is no single-crystalline oxide semiconductor having the same composition. In this case, by combining single-crystalline oxide semiconductors having different compositions in an arbitrary ratio, the density of a single-crystalline oxide semiconductor equivalent to a desired composition can be estimated. The density of the single-crystalline oxide semiconductor having the desired composition can be calculated using a weighted average based on the combination ratio of the single-crystalline oxide semiconductors having different compositions. Note that it is preferable to calculate the density by minimizing the types of single-crystalline oxide semiconductors used as much as possible.

[0572] As described above, the oxide semiconductor has various structures and various characteristics. Note that the oxide semiconductor can be, for example, a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0573] Embodiment 12

[0574] In this embodiment, an example of a circuit of a semiconductor device such as a transistor using one aspect of the present invention will be described.

[0575] <CMOS inverter>

[0576] Figure 33A The circuit diagram shown shows the structure of a so-called CMOS inverter, in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series, and their gates are connected.

[0577] <Structure 1 of semiconductor device>

[0578] Figure 34 corresponds to Figure 33A a cross-sectional view of a semiconductor device. Figure 34 The semiconductor device shown includes a transistor 2200 and a transistor 2100. The transistor 2100 is disposed above the transistor 2200. Note that the transistor described in the above embodiment can be used as the transistor 2100. Therefore, the description of the transistor above can be appropriately referred to for the transistor 2100.

[0579] Figure 34 The transistor 2200 shown is a transistor using a semiconductor substrate 450. The transistor 2200 includes a region 472a in the semiconductor substrate 450, a region 472b in the semiconductor substrate 450, an insulator 462, and a conductor 454.

[0580] In transistor 2200, regions 472a and 472b function as source and drain regions, respectively. Additionally, insulator 462 functions as a gate insulator. Furthermore, conductor 454 functions as a gate electrode. Therefore, the resistance of the channel forming region can be controlled by the potential applied to conductor 454. In other words, the conduction / non-conduction between regions 472a and 472b can be controlled by the potential applied to conductor 454.

[0581] The semiconductor substrate 450 can be, for example, a single-material semiconductor substrate made of silicon or germanium, or a semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Preferably, a single-crystal silicon substrate is used as the semiconductor substrate 450.

[0582] The semiconductor substrate 450 uses a semiconductor substrate containing impurities that impart n-type conductivity. Note that the semiconductor substrate 450 can also use a semiconductor substrate containing impurities that impart p-type conductivity. In this case, a well containing impurities that impart n-type conductivity can be disposed in the region where the transistor 2200 is formed. Alternatively, the semiconductor substrate 450 can also be i-type.

[0583] The top surface of the semiconductor substrate 450 preferably has a (110) surface. This improves the on-state characteristics of the transistor 2200.

[0584] Regions 472a and 472b are regions containing impurities that impart p-type conductivity. Thus, transistor 2200 has a p-channel structure.

[0585] Note that transistor 2200 is separated from adjacent transistors by region 460, etc. Region 460 is insulating.

[0586] Figure 34 The semiconductor device shown includes insulator 464, insulator 466, insulator 468, conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b, conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, insulator 489, insulator 490, insulator 492, insulator 493, insulator 494, and insulator 495.

[0587] Insulator 464 is disposed on transistor 2200. Insulator 466 is disposed on insulator 464. Insulator 468 is disposed on insulator 466. Insulator 489 is disposed on insulator 468. Transistor 2100 is disposed on insulator 489. Insulator 493 is disposed on transistor 2100. Insulator 494 is disposed on insulator 493.

[0588] The insulator 464 includes an opening reaching region 472a, an opening reaching region 472b, and an opening reaching conductor 454. Conductors 480a, 480b, and 480c respectively fill the respective openings.

[0589] Insulator 466 includes an opening leading to conductor 480a, an opening leading to conductor 480b, and an opening leading to conductor 480c. Conductors 478a, 478b, and 478c respectively fill the respective openings.

[0590] The insulator 468 includes an opening leading to the conductor 478b and an opening leading to the conductor 478c. Conductors 476a and 476b respectively fill the respective openings.

[0591] Insulator 489 includes an opening overlapping the channel forming region of transistor 2100, an opening leading to conductor 476a, and an opening leading to conductor 476b. Conductors 474a, 474b, and 474c respectively fill the respective openings.

[0592] Conductor 474a may also function as the gate electrode of transistor 2100. Alternatively, for example, the electrical characteristics of transistor 2100, such as the threshold voltage, can be controlled by applying a predetermined potential to conductor 474a. Alternatively, for example, conductor 474a may be electrically connected to conductor 504, which functions as the gate electrode of transistor 2100. This increases the on-state current of transistor 2100. Furthermore, since punch-through can be suppressed, the electrical characteristics in the saturation region of transistor 2100 can be stabilized. Note that since conductor 474a corresponds to conductor 413 shown in the above embodiment, details regarding it can be found in the description of conductor 413.

[0593] Additionally, the insulator 490 includes an opening leading to the conductor 474b. Note that since the insulator 490 is equivalent to the insulator 402 shown in the above embodiment, for details regarding it, please refer to the description of the insulator 402.

[0594] Insulator 495 includes an opening through a conductor 507b passing through one of the source and drain electrodes of transistor 2100 to conductor 474b, an opening through a conductor 507a passing through the other of the source and drain electrodes of transistor 2100, an opening through a conductor 504 passing through the gate electrode of transistor 2100, and an opening through conductor 474c. Note that since insulator 495 is equivalent to insulator 410 shown in the above embodiment, its details can be found in the description of insulator 410.

[0595] Insulator 493 includes an opening through conductor 507b passing through one of the source and drain electrodes of transistor 2100 to conductor 474b, an opening through conductor 507a passing through the other of the source and drain electrodes of transistor 2100, an opening through conductor 504 passing through the gate electrode of transistor 2100, and an opening through conductor 474c. Conductors 496a, 496b, 496c, and 496d fill each of the openings. Note that openings provided in components such as transistor 2100 are sometimes located between openings provided in other components.

[0596] The insulator 494 includes an opening leading to conductor 496a, an opening leading to conductors 496b and 496d, and an opening leading to conductor 496c. Conductors 498a, 498b, and 498c respectively fill the respective openings.

[0597] As insulators 464, 466, 468, 489, 493 and 494, for example, a single layer or stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used.

[0598] At least one of insulators 464, 466, 468, 489, 493, and 494 preferably includes an insulator that functions to block impurities such as hydrogen and oxygen. By placing an insulator that functions to block impurities such as hydrogen and oxygen near transistor 2100, the electrical characteristics of transistor 2100 can be stabilized.

[0599] As an insulator that can block impurities such as hydrogen and oxygen, a single layer or stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used.

[0600] As conductors 480a, 480b, 480c, 478a, 478b, 478c, 476a, 476b, 474a, 474b, 474c, 496a, 496b, 496c, 496d, 498a, 498b, and 498c, for example, a single layer or stack of conductors comprising one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten can be used. For example, alloys or compounds containing the above-mentioned elements may also be used, as well as conductors containing aluminum, copper and titanium, copper and manganese, indium, tin and oxygen, titanium and nitrogen, etc.

[0601] Notice, Figure 35 The semiconductor device shown is Figure 34 The only difference in the semiconductor device shown is the structure of transistor 2200. Therefore, regarding Figure 35 The semiconductor device shown is referenced. Figure 34 The semiconductor device shown is described. Specifically, in Figure 35 In the semiconductor device shown, transistor 2200 is a Fin-type transistor. By making transistor 2200 a Fin-type transistor, the effective channel width is increased, thereby improving the on-state characteristics of transistor 2200. Furthermore, since the influence of the gate electrode electric field can be increased, the off-state characteristics of transistor 2200 can be improved.

[0602] in addition, Figure 36 The semiconductor device shown is Figure 34 The only difference in the semiconductor device shown is the structure of transistor 2200. Therefore, regarding Figure 36 The semiconductor device shown is referenced. Figure 34 The semiconductor device shown is described. Specifically, in Figure 36 In the semiconductor device shown, transistor 2200 is disposed in semiconductor substrate 450, which serves as SOI substrate. Figure 36 The diagram shows a structure where region 456 and semiconductor substrate 450 are separated by insulator 452. By using an SOI substrate as semiconductor substrate 450, punch-through phenomena can be suppressed, thus improving the off-state characteristics of transistor 2200. Note that insulator 452 can be formed by insulating semiconductor substrate 450. For example, silicon oxide can be used as insulator 452.

[0603] exist Figures 34 to 36 In the semiconductor device shown, since a p-channel transistor is formed using a semiconductor substrate and an n-channel transistor is formed on top of it, the area occupied by the components can be reduced. In other words, the integration density of the semiconductor device can be increased. Furthermore, compared to forming both n-channel and p-channel transistors using the same semiconductor substrate, the manufacturing process can be simplified, thus improving the productivity of the semiconductor device. Additionally, the yield rate of the semiconductor device can be increased. Moreover, p-channel transistors can sometimes omit complex processes such as the formation of the LDD (Lightly Doped Drain) region, the formation of shallow trench structures, or bending designs. Therefore, compared to semiconductor devices that use a semiconductor substrate to form n-channel transistors, Figures 34 to 36 The semiconductor devices shown can sometimes improve productivity and yield.

[0604] <CMOS Analog Switch>

[0605] Figure 33B The circuit diagram shown illustrates a structure in which the sources of transistors 2100 and 2200 are connected to each other, and the drains of transistors 2100 and 2200 are connected to each other. By employing this structure, the transistors can be used as so-called CMOS analog switches.

[0606] <Storage Device 1>

[0607] Figure 37A and Figure 37B An example of a semiconductor device (memory device) is shown, in which a transistor of one aspect of the present invention is used, which is able to retain stored data even without a power supply and has no limit on the number of writes.

[0608] Figure 37A The semiconductor device shown includes a transistor 3200 using a first semiconductor, a transistor 3300 using a second semiconductor, and a capacitor 3400. Alternatively, the same transistor as transistor 2100 described above can be used as transistor 3300.

[0609] Transistor 3300 is preferably a transistor with low off-state current. For example, transistor 3300 can be a transistor containing oxide semiconductor. Because of the low off-state current of transistor 3300, predetermined nodes of the semiconductor device can retain stored data for extended periods. That is, because refresh operations are not required or can be performed at extremely low frequencies, a low-power semiconductor device can be realized.

[0610] exist Figure 37A In this configuration, the first wiring 3001 is electrically connected to the source of transistor 3200, and the second wiring 3002 is electrically connected to the drain of transistor 3200. Furthermore, the third wiring 3003 is electrically connected to one of the source and drain of transistor 3300, and the fourth wiring 3004 is electrically connected to the gate of transistor 3300. Additionally, the gate of transistor 3200 and the other of the source and drain of transistor 3300 are electrically connected to one electrode of capacitor 3400, and the fifth wiring 3005 is electrically connected to the other electrode of capacitor 3400.

[0611] Figure 37A The semiconductor device shown can be used to write, hold, and read information as follows, by having the feature of maintaining the potential of the gate of transistor 3200.

[0612] The writing and retention of information are explained. First, the potential of the fourth wiring 3004 is set to the potential that turns on transistor 3300, thus putting transistor 3300 in the on state. Consequently, the potential of the third wiring 3003 is applied to node FG, where the gate of transistor 3200 is electrically connected to one electrode of capacitor 3400. In other words, a predetermined charge is applied to the gate of transistor 3200 (writing). Here, either a charge of two different levels (hereinafter referred to as low-level charge and high-level charge) is applied. Then, by setting the potential of the fourth wiring 3004 to the potential that turns off transistor 3300, the transistor is turned off, and node FG retains the charge (retention).

[0613] Because the off-state current of transistor 3300 is small, the charge at node FG is maintained for a long time.

[0614] Next, the information readout will be explained. When an appropriate potential (readout potential) is applied to the fifth wiring 3005 while a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 has a potential corresponding to the amount of charge held in node FG. This is because, in the case where transistor 3200 is an n-channel transistor, the apparent threshold voltage V when a high-level charge is applied to the gate of transistor 3200... th_H The apparent threshold voltage V is lower than the voltage V that is applied to the gate of transistor 3200 when a low-level charge is applied. th_L Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 required to make transistor 3200 "on". Therefore, by setting the potential of the fifth wiring 3005 to V... th_H With V th_L The potential V0 between these values ​​can be used to identify the charge applied to node FG. For example, if node FG is supplied with a high-level charge during writing, and the potential of the fifth wiring 3005 is V0 (>V0), then... th_H When transistor 3200 is in the "conducting state", it becomes "on". On the other hand, when node FG is supplied with a low-level charge, even if the potential of the fifth wiring 3005 is V0 ( <V th_L Transistor 3200 remains in the "off state". Therefore, by identifying the potential of the second wiring 3002, the information held by node FG can be read.

[0615] Note that when the memory cells are configured in an array, the information of the desired memory cell must be read during readout. For example, in a memory cell where no information is read out, a potential (i.e., below V) is applied to the fifth wiring 3005 to make transistor 3200 "off" regardless of the charge applied to node FG. th_H Alternatively, in a memory cell where no information is read, a potential higher than V can be applied to the fifth wiring 3005 that makes the transistor 3200 "on" regardless of the charge applied to node FG. th_L The potential of the storage unit is used to form a structure that allows only the information of the desired storage unit to be read.

[0616] Note that although an example of two charges being held at node FG has been shown above, the semiconductor device according to the present invention is not limited to this. For example, three or more charges can be held at node FG of the semiconductor device. By adopting the above structure, the semiconductor device can be multi-valued, thereby increasing the storage capacity.

[0617] <Structure of Storage Device 1>

[0618] Figure 38 It corresponds to Figure 37A A cross-sectional view of a semiconductor device. Figure 38 The semiconductor device shown includes transistor 3200, transistor 3300, and capacitor 3400. Transistor 3300 and capacitor 3400 are disposed above transistor 3200. Transistor 3300 refers to the description of transistor 2100 above. Transistor 3200 refers to... Figure 34 The transistor 2200 is shown in the description. In Figure 34 In the diagram, transistor 2200 is a p-channel transistor, but transistor 3200 can also be an n-channel transistor.

[0619] Figure 38 The transistor 2200 shown is a transistor using a semiconductor substrate 450. The transistor 2200 includes a region 472a in the semiconductor substrate 450, a region 472b in the semiconductor substrate 450, an insulator 462, and a conductor 454.

[0620] Figure 38 The semiconductor device shown includes insulator 464, insulator 466, insulator 468, conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b, conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d, conductor 498a, conductor 498b, conductor 498c, insulator 489, insulator 490, insulator 492, insulator 493, insulator 494, and insulator 495.

[0621] Insulator 464 is disposed on transistor 3200. Insulator 466 is disposed on insulator 464. Insulator 468 is disposed on insulator 466. Insulator 489 is disposed on insulator 468. Transistor 2100 is disposed on insulator 489. Insulator 493 is disposed on transistor 2100. Insulator 494 is disposed on insulator 493.

[0622] The insulator 464 includes an opening reaching region 472a, an opening reaching region 472b, and an opening reaching conductor 454. Conductors 480a, 480b, and 480c respectively fill the respective openings.

[0623] Insulator 466 includes an opening leading to conductor 480a, an opening leading to conductor 480b, and an opening leading to conductor 480c. Conductors 478a, 478b, and 478c respectively fill the respective openings.

[0624] The insulator 468 includes an opening leading to the conductor 478b and an opening leading to the conductor 478c. Conductors 476a and 476b respectively fill the respective openings.

[0625] Insulator 489 includes an opening overlapping the channel forming region of transistor 3300, an opening leading to conductor 476a, and an opening leading to conductor 476b. Conductors 474a, 474b, and 474c respectively fill the respective openings.

[0626] Conductor 474a may also function as the bottom gate electrode of transistor 3300. Alternatively, for example, the electrical characteristics of transistor 3300, such as the threshold voltage, can be controlled by applying a predetermined potential to conductor 474a. Alternatively, for example, conductor 474a may be electrically connected to conductor 504 of the top gate electrode of transistor 3300. This increases the on-state current of transistor 3300. Furthermore, since punch-through can be suppressed, the electrical characteristics in the saturation region of transistor 3300 can be stabilized.

[0627] The insulator 490 includes an opening leading to the conductor 474b and an opening leading to the conductor 474c. Note that since the insulator 490 is equivalent to the insulator 402 shown in the above embodiment, its details can be found in the description of the insulator 402.

[0628] Insulator 495 includes an opening through a conductor 507b passing through one of the source and drain terminals of transistor 3300 to conductor 474b, an opening through a conductor 507a passing through the other of the source and drain terminals of transistor 3300 to conductor 515, and an opening through a conductor 507a passing through the other of the source and drain terminals of transistor 3300 to conductor 474c. Note that since insulator 495 is equivalent to insulator 410 shown in the above embodiment, its details can be found in the description of insulator 410.

[0629] The insulator 493 includes an opening leading to a conductor 514 that overlaps with the conductor 515 across the insulator 511, an opening leading to a conductor of the gate electrode of the transistor 3300, and an opening leading to a conductor 516 electrically connected to a conductor 507b that is electrically connected to one of the source and drain electrodes of the transistor 3300. Conductors 496e, 496b, and 496f fill each of the openings. Note that openings provided in the components of the transistor 3300, etc., sometimes penetrate other components.

[0630] The insulator 494 includes an opening leading to the conductor 496e, an opening leading to the conductor 496b, and an opening leading to the conductor 496f. Conductors 498a, 498b, and 498c respectively fill the respective openings.

[0631] At least one of insulators 464, 466, 468, 489, 493, and 494 preferably has the function of blocking impurities such as hydrogen and oxygen. By arranging an insulator with the function of blocking impurities such as hydrogen and oxygen near transistor 3300, the electrical characteristics of transistor 3300 can be stabilized.

[0632] The source or drain of transistor 3200 is electrically connected to conductor 507b of one of the source and drain of transistor 3300 via conductors 480b, 478b, 476a, 474b, and 496c. The gate electrode conductor 454 of transistor 3200 is electrically connected to conductor 507a of the other of the source and drain of transistor 3300 via conductors 480c, 478c, 476b, 474c, and 496d.

[0633] The capacitor 3400 includes a conductor 515, a conductor 514, and an insulator 511.

[0634] The structure of other constituent elements can be appropriately referenced from the relevant provisions. Figure 34 Records such as those of [etc.]

[0635] Notice, Figure 39 The semiconductor device shown is Figure 38 The only difference in the semiconductor device shown is the structure of transistor 3200. Therefore, Figure 39 The semiconductor device shown is referenced Figure 38 The semiconductor device shown is described. Specifically, in Figure 39 In the semiconductor device shown, transistor 3200 is a Fin type. Fin type transistor 3200 is referenced. Figure 35 The transistor 2200 is shown in the description. In Figure 35 In the diagram, transistor 2200 is a p-channel transistor, but transistor 3200 can also be an n-channel transistor.

[0636] in addition, Figure 40 The semiconductor device shown is Figure 38 The only difference in the semiconductor device shown is the structure of transistor 3200. Therefore, Figure 40 The semiconductor device shown is referenced Figure 38 The semiconductor device shown is described. Specifically, in Figure 40 In the semiconductor device shown, transistor 3200 is disposed in semiconductor substrate 450, which serves as an SOI substrate. The transistor 3200 disposed in semiconductor substrate 450 (SOI substrate) is shown in reference. Figure 36 The transistor 2200 is shown in the description. In Figure 36 In the diagram, transistor 2200 is a p-channel transistor, but transistor 3200 can also be an n-channel transistor.

[0637] <Storage Device 2>

[0638] Figure 37B The semiconductor device shown is, excluding transistor 3200, with Figure 37A The semiconductor device shown is different. In this case, it can also be compared with... Figure 37A The semiconductor device shown performs the same tasks of writing and retaining data.

[0639] illustrate Figure 37B Data readout from the semiconductor device shown. When transistor 3300 is turned on, the floating third wiring 3003 and capacitor 3400 are turned on, and charge is redistributed between the third wiring 3003 and capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 varies depending on the potential of one electrode of capacitor 3400 (or the charge accumulated in capacitor 3400).

[0640] For example, if the potential of one electrode of capacitor 3400 is V, the capacitance of capacitor 3400 is C, and the capacitive component of the third wiring 3003 is C... B The potential of the third wiring 3003 before the charge is redistributed is V. B0 At that time, the potential of the third wiring 3003 after the charge is redistributed is (C B ×V B0 +C×V) / (C B +C). Therefore, assuming that the storage cell is in one of two states at the potential of one electrode of its capacitor 3400, namely V1 and V0 (V1>V0), it can be determined that the potential of the third wiring 3003 when holding potential V1 is (=(C)). B ×V B0 +C×V1) / (C B +C)) is higher than the potential of the third wiring 3003 when the holding potential V0 (=(C) B ×V B0 +C×V0) / (C B +C)).

[0641] Furthermore, data can be read by comparing the potential of the third wiring 3003 with a predetermined potential.

[0642] In this case, the transistor using the first semiconductor can be used in a drive circuit to drive the memory cell, and the transistor using the second semiconductor as transistor 3300 can be stacked on the drive circuit.

[0643] The aforementioned semiconductor device can utilize transistors with low off-state current using oxide semiconductors to retain stored data for extended periods. That is, because refresh operations are unnecessary or can be performed at extremely low frequencies, a low-power semiconductor device can be achieved. Furthermore, stored data can be retained for extended periods even without a power supply (but preferably at a fixed potential).

[0644] Furthermore, because this semiconductor device does not require high voltage when writing data, component degradation is less likely to occur. For example, unlike existing non-volatile memories, it does not require injecting or extracting electrons from the floating gate, thus avoiding problems such as insulator degradation. In other words, in the semiconductor device of one aspect of the present invention, the number of rewrites, which is a problem in existing non-volatile memories, is not limited, and its reliability is greatly improved. Moreover, since data is written based on the on / off state of the transistor, high-speed operation is possible.

[0645] <Storage Device 3>

[0646] Reference Figure 41 The circuit diagram shown is for Figure 37A A modified example of the semiconductor device (memory device) shown will be explained.

[0647] Figure 41 The semiconductor device shown includes transistors 4100, 4200, 4300, and 4400, capacitors 4500 and 4600. Here, transistor 4100 can be the same transistor as transistor 3200 described above, and transistors 4200, 4300, and 4400 can be the same transistors as transistor 3300 described above. Note that in... Figure 41 Not shown in the image, but multiple Figure 41 The semiconductor devices shown are arranged in a matrix. Figure 41 The semiconductor device shown can control the writing and reading of data voltage based on the signals or potentials supplied to wirings 4001, 4003, and 4005 to 4009.

[0648] One of the source and drain of transistor 4100 is connected to wiring 4003. The other of the source and drain of transistor 4100 is connected to wiring 4001. Note that although in Figure 41 Transistor 4100 is a p-channel transistor, but it can also be an n-channel transistor.

[0649] Figure 41 The illustrated semiconductor device includes two data holding units. For example, the first data holding unit holds charge between one of the source and drain terminals of transistor 4400 connected to node FG1, one electrode of capacitor 4600, and one of the source and drain terminals of transistor 4200. The second data holding unit holds charge between the gate of transistor 4100 connected to node FG2, the other of the source and drain terminals of transistor 4200, one of the source and drain terminals of transistor 4300, and one electrode of capacitor 4500.

[0650] The other electrode of transistor 4300 is connected to wiring 4003. The other electrode of transistor 4400 is connected to wiring 4001. The gate of transistor 4400 is connected to wiring 4005. The gate of transistor 4200 is connected to wiring 4006. The gate of transistor 4300 is connected to wiring 4007. The other electrode of capacitor 4600 is connected to wiring 4008. The other electrode of capacitor 4500 is connected to wiring 4009.

[0651] Transistors 4200, 4300, and 4400 function as switches controlling the writing of data voltage and the retention of charge. Note that transistors 4200, 4300, and 4400 are preferably transistors with low off-state current (current flowing between the source and drain in the off state). As for transistors with low off-state current, transistors comprising oxide semiconductor (OS transistors) in their channel formation region are preferred. OS transistors, for example, have low off-state current and can be fabricated in a manner overlapping with silicon-containing transistors. Note that although in Figure 41 Transistors 4200, 4300 and 4400 are n-channel transistors, but they can also be p-channel transistors.

[0652] Even if transistors 4200, 4300, and 4400 are oxide semiconductor transistors, it is preferable to place them in different layers. That is, as... Figure 41 As shown, Figure 41 The semiconductor device shown is preferably composed of a first layer 4021 including transistor 4100, a second layer 4022 including transistors 4200 and 4300, and a third layer 4023 including transistor 4400. By stacking layers including transistors, the circuit area can be reduced, thereby enabling miniaturization of the semiconductor device.

[0653] Next, explain the... Figure 41 The semiconductor device shown is performing a data writing operation.

[0654] First, the writing operation of the data voltage to the data holding section connected to node FG1 will be explained (hereinafter referred to as write operation 1). Note that the data voltage written to the data holding section connected to node FG1 below is V. D1 The threshold voltage of transistor 4100 is V. th .

[0655] In writing operation 1, the potential of wiring 4003 is set to V. D1 After setting the potential of wiring 4001 to ground, wiring 4001 is placed in a floating state. Furthermore, the potentials of wirings 4005 and 4006 are set to high level. Additionally, the potentials of wirings 4007 to 4009 are set to low level. As a result, the potential of node FG2, which is in a floating state, rises, causing current to flow through transistor 4100. When current flows through transistor 4100, the potential of wiring 4001 rises. Furthermore, transistors 4400 and 4200 are turned on. Therefore, as the potential of wiring 4001 rises, the potentials of nodes FG1 and FG2 rise. When the potential of node FG2 rises, the voltage between the gate and source of transistor 4100 (V) increases. gs The threshold voltage V of transistor 4100 becomes th At this time, the current flowing through transistor 4100 decreases. Therefore, the potential rise of wiring 4001, nodes FG1, and FG2 stops, and remains fixed at a value greater than V. D1 Low out V th The "V" D1 -V th ".

[0656] In other words, when current flows through transistor 4100, the V applied to wiring 4003 D1 An application is made to wiring 4001, causing the potentials of nodes FG1 and FG2 to rise. When the potential rise causes the potential of node FG2 to become "V". D1 -V th "At that time, the V of transistor 4100 gs Become V th Therefore, the current stops flowing.

[0657] Next, the writing operation of the data voltage to the data holding section connected to node FG2 will be explained (hereinafter referred to as write operation 2). Note that the data voltage written to the data holding section connected to node FG2 is V. D2 The situation.

[0658] In writing operation 2, the potential of wiring 4001 is set to V. D2 After setting the potential of wiring 4003 to ground, wiring 4003 is placed in a floating state. Furthermore, the potential of wiring 4007 is set to a high level. Additionally, the potentials of wirings 4005, 4006, 4008, and 4009 are set to a low level. Transistor 4300 is turned on, and the potential of wiring 4003 is set to a low level. Therefore, the potential of node FG2 also drops to a low level, allowing current to flow through transistor 4100. When current flows, the potential of wiring 4003 rises. Furthermore, transistor 4300 is turned on. Therefore, as the potential of wiring 4003 rises, the potential of node FG2 rises. When the potential of node FG2 rises, the V of transistor 4100... gs V becomes transistor 4100 th At this time, the current flowing through transistor 4100 decreases. Therefore, the potential rise of wiring 4003 and node FG2 stops and becomes fixed at V. D2 The decrease corresponds to V th The "V" D2 -V th ".

[0659] In other words, when current flows through transistor 4100, the V applied to wiring 4001 D2 A voltage is applied to wiring 4003, causing the potential of node FG2 to rise. When the potential of node FG2 becomes "V" due to the rise in potential... D2 -V th "At that time, the V of transistor 4100 gs Become V th Therefore, the current stops flowing. At this time, transistors 4200 and 4400 are both in the off state, while node FG1 remains in the "V" state written in write operation 1. D1 -V th ".

[0660] exist Figure 41 In the semiconductor device shown, after writing data voltage to multiple data holding sections, the potential of wiring 4009 is set to a high level, causing the potentials of nodes FG1 and FG2 to rise. Then, each transistor is turned off to stop charge movement, thereby maintaining the written data voltage.

[0661] As described above, by writing data voltages to nodes FG1 and FG2, the data voltage can be maintained in multiple data holding sections. Note that although "V" is given as an example of the written potential... D1 -V th "and "V D2 -V th However, these potentials correspond to data voltages for multi-valued data. Therefore, when holding 4 bits of data in each data holding section, it is possible to obtain 16-valued "V". D1 -V th "and 16 values ​​of "V" D2 -V th ".

[0662] Next, explain the... Figure 41 The semiconductor device shown performs data readout operations.

[0663] First, the data voltage readout operation performed on the data holding unit connected to node FG2 will be explained (hereinafter referred to as readout operation 1).

[0664] In readout operation 1, wiring 4003, which is in a electrically floating state after pre-charging, is discharged. Furthermore, the potentials of wirings 4005 to 4008 are set to low. Additionally, the potential of wiring 4009 is set to low, while the potential of node FG2, which is in a electrically floating state, is set to "V". D2 -V th "When the potential of node FG2 decreases, current flows through transistor 4100. As current flows, the potential of the electrically floating wiring 4003 decreases. As the potential of wiring 4003 decreases, the Vt of transistor 4100..." gs It becomes smaller. When the V of transistor 4100... gs V becomes transistor 4100 th At this time, the current flowing through transistor 4100 decreases. That is, the potential of wiring 4003 becomes lower than the potential of node FG2 by a factor of V. D2 -V th "Higher than V" th The value of "V" D2 The potential of wiring 4003 corresponds to the data voltage of the data holding section connected to node FG2. The read analog value of the data voltage is converted by an A / D converter to obtain the data of the data holding section connected to node FG2.

[0665] In other words, the pre-charged wiring 4003 is made to float, while the potential of wiring 4009 is switched from high to low, thereby allowing current to flow through transistor 4100. When current flows, the potential of the floating wiring 4003 decreases and becomes "V". D2 In transistor 4100, due to the "V" of node FG2 D2 -V th "V" of wiring 4003 D2 V between " gs Become V th Therefore, the current stops flowing. Then, V is written in writing operation 2. D2 It was read out to wiring 4003.

[0666] After acquiring data from the data holding section connected to node FG2, transistor 4300 is turned on, thereby enabling the "V" signal of node FG2. D2 -V th "Discharge."

[0667] Next, the charge held at node FG1 is distributed between node FG1 and node FG2, and the data voltage of the data holding section connected to node FG1 is moved to the data holding section connected to node FG2. Here, the potentials of wirings 4001 and 4003 are set to low level. Furthermore, the potential of wiring 4006 is set to high level. Additionally, the potentials of wirings 4005, 4007 to 4009 are set to low level. By turning on transistor 4200, the charge at node FG1 is distributed between node FG1 and node FG2.

[0668] Here, the potential after charge distribution is from the written potential "V". D1 -V th "Reduced. Therefore, the capacitance value of capacitor 4600 is preferably greater than the capacitance value of capacitor 4500. Alternatively, the potential written to node FG1"V D1 -V th "Preferred potential is greater than the potential representing the same data"V D2 -V th Thus, by changing the capacitance ratio to increase the pre-written potential, the potential drop after charge distribution can be suppressed. The potential fluctuations caused by charge distribution will be explained later.

[0669] Next, the reading operation of the data voltage of the data holding unit connected to node FG1 will be explained (hereinafter referred to as reading operation 2).

[0670] In readout operation 2, wiring 4003, which is in a electrically floating state after pre-charging, is discharged. Furthermore, the potentials of wirings 4005 to 4008 are set to low. Additionally, the potential of wiring 4009 is set to high during pre-charging and then low. By setting the potential of wiring 4009 to low, the potential of node FG2, which is in a electrically floating state, becomes potential "V". D1 -V th "When the potential of node FG2 decreases, current flows through transistor 4100. As current flows, the potential of the electrically floating wiring 4003 decreases. As the potential of wiring 4003 decreases, the Vt of transistor 4100..." gs It becomes smaller. When the V of transistor 4100... gs V becomes transistor 4100 th At this time, the current flowing through transistor 4100 decreases. That is, the potential of wiring 4003 becomes lower than the potential of node FG2 by a factor of V. D1 -V th "Higher than V" th The value of "V" D1 The potential of wiring 4003 corresponds to the data voltage of the data holding section connected to node FG1. The read analog value of the data voltage is converted by an A / D converter to obtain the data of the data holding section connected to node FG1. The above describes the reading of the data voltage of the data holding section connected to node FG1.

[0671] In other words, the pre-charged wiring 4003 is made to float, while the potential of wiring 4009 is switched from high to low, thereby allowing current to flow through transistor 4100. When current flows, the potential of the floating wiring 4003 decreases to V. D1 In transistor 4100, due to the "V" of node FG2 D1 -V th "V" of wiring 4003 D1 V between " gs Become V th Therefore, the current stops flowing. Then, the "V" written in writing operation 1... D1 "Read out to wiring 4003."

[0672] As described above, by reading the data voltage from nodes FG1 and FG2, the data voltage can be read from multiple data holding sections. For example, by holding 4 bits (16 values) of data in each of nodes FG1 and FG2, a total of 8 bits (256 values) of data can be held. Furthermore, although in Figure 41 The structure consists of a first layer 4021 to a third layer 4023. However, by forming more layers, the storage capacity can be increased without increasing the area of ​​the semiconductor device.

[0673] Note that the read voltage can be considered as being V higher than the written data voltage. th The voltage is read. Therefore, it can be offset by canceling the "V" written during the write operation. D1 -V th "and "V D2 -V th "V" th And then, reading. As a result, while improving the storage capacity per storage unit, the read data can also be made close to the correct data, thus achieving high data reliability.

[0674] Figure 42 Showing the corresponding Figure 41 A cross-sectional view of a semiconductor device. Figure 42 The semiconductor device shown includes transistors 4100, 4200, 4300, and 4400, capacitors 4500 and 4600. Here, transistor 4100 is formed in a first layer 4021, transistors 4200, 4300, and capacitor 4500 are formed in a second layer 4022, and transistor 4400 and capacitor 4600 are formed in a third layer 4023.

[0675] Here, reference can be made to the description of transistor 3300 for transistors 4200, 4300, and 4400, and to the description of transistor 3200 for transistor 4100. Additionally, reference can be made appropriately to other wiring and insulators, etc. Figure 38 The records.

[0676] Note that in Figure 38 In capacitor 3400 of the semiconductor device shown, a conductive layer is disposed parallel to the substrate to form the capacitor. However, in capacitors 4500 and 4600, the conductive layer is configured as a trench shape to form the capacitor. By adopting this structure, a larger capacitance value can be ensured even with the same area.

[0677] <fpga>

[0678] One aspect of this invention can be applied to LSIs such as FPGAs (Field Programmable Gate Arrays).

[0679] Figure 43A An example block diagram of an FPGA is shown. The FPGA consists of a switching element 521 and a logic element 522. Furthermore, the logic element 522 can change the function of logic circuits such as combinational circuits or sequential circuits based on the configuration data stored in the configuration memory.

[0680] Figure 43B This is a schematic diagram illustrating the function of the routing switch element 521. The routing switch element 521 can switch the connections between logic elements 522 based on the configuration data stored in the configuration memory 523. Note that in... Figure 43B The diagram shows a switch that toggles the connection between terminal IN and terminal OUT, but in reality, multiple switches are provided between multiple logic elements 522.

[0681] Figure 43C An example of the circuit structure used as configuration memory 523 is shown. Configuration memory 523 is composed of transistor M11 using OS transistors and transistor M12 using silicon (Si) transistors. For node FN SW Configuration data D is applied via transistor M11. SW The configuration data D can be maintained by keeping transistor M11 in the off state. SW The potential. Due to the maintained configuration data D SW The potential of the transistor M12 is used to switch the on / off state, thereby switching the connection between the IN terminal and the OUT terminal.

[0682] Figure 43D This is a schematic diagram illustrating the function of logic element 522. Logic element 522 can switch the OUT terminal based on the configuration data stored in the configuration memory 527. mem The potential. Look up Table 524 according to terminal OUT. mem The potential of the signal at terminal IN can change the function of the combinational circuit that processes the signal at terminal IN. Additionally, logic element 522 includes a timing circuit register 525 and a selector 526 for switching the signal at terminal OUT. Selector 526 selects the signal at terminal OUT output from configuration memory 527. mem The potential can be selected to look up the output of the signal in table 524 or the output of the signal in register 525.

[0683] Figure 43E An example of the circuit structure used as configuration memory 527 is shown. Configuration memory 527 is composed of transistors M13 and M14 using OS transistors and transistors M15 and M16 using Si transistors. For node FN LE Configuration data D is applied via transistor M13. LE For node FNB LE Configuration data DB is applied via transistor M14. LE Configuration data DB LE This is equivalent to reversing the configuration data D. LE The logic potential. This configuration data D can be maintained by turning off transistors M13 and M14. LE Configuration data D BLE The potential. Due to the maintained configuration data D LE and configuration data DB LE The potential of transistor M15 and transistor M16 is used to switch the on / off state of one of them, thereby controlling the OUT terminal. mem Apply a potential VDD or a potential VSS.

[0684] The structure shown in the above embodiments can be applied to Figures 43A to 43E The structure is shown. For example, transistors M12, M15, and M16 are constructed using Si transistors, while transistors M11, M13, and M14 are constructed using OS transistors. In this case, a low-resistance conductive material can be used to form the wiring connecting the underlying Si transistors. This allows for a circuit with improved access speed and low power consumption.

[0685] The structure shown in this embodiment can be used in appropriate combinations with the structures shown in other embodiments.

[0686] Implementation Method 13

[0687] In this embodiment, an example of a camera device using a transistor or the like according to one aspect of the present invention will be described.

[0688] <Structure of the Camera Device>

[0689] Figure 44A This is a plan view illustrating an example of an imaging device 200 according to one aspect of the present invention. The imaging device 200 includes a pixel unit 210 and peripheral circuitry (peripheral circuitry 260, 270, 280, and 290) for driving the pixel unit 210. The pixel unit 210 includes a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). Peripheral circuitry 260, 270, 280, and 290 are respectively connected to the plurality of pixels 211, and signals for driving the plurality of pixels 211 are supplied. Furthermore, in this specification and the like, peripheral circuitry 260, 270, 280, and 290 are sometimes collectively referred to as "peripheral circuitry" or "driving circuitry." For example, peripheral circuitry 260 can also be considered a part of peripheral circuitry.

[0690] The camera device 200 preferably includes a light source 291. The light source 291 is capable of emitting detection light P1.

[0691] The peripheral circuitry includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, or a conversion circuit. Alternatively, the peripheral circuitry may be fabricated on the substrate forming the pixel portion 210. Furthermore, semiconductor devices such as ICs may be used for part or all of the peripheral circuitry. Note that one or more of peripheral circuits 260, 270, 280, and 290 may be omitted.

[0692] like Figure 44B As shown, the pixel units 210 included in the imaging device 200 can also be arranged with the pixels 211 tilted. By arranging the pixels 211 in a tilted manner, the pixel spacing (interval) in the row direction and column direction can be shortened. As a result, the imaging quality of the imaging device 200 can be improved.

[0693] <Example 1 of pixel structure>

[0694] By making the pixels 211 included in the camera device 200 consist of a plurality of sub-pixels 212, and by combining each sub-pixel 212 with a filter (color filter) that allows light in a specific wavelength region to pass through, data for displaying color images can be obtained.

[0695] Figure 45A This is a top view showing an example of pixel 211 used to obtain a color image. Figure 45A The pixel 211 shown includes a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") with a color filter that allows light in the red (R) wavelength region to pass through, a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") with a color filter that allows light in the green (G) wavelength region to pass through, and a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212B") with a color filter that allows light in the blue (B) wavelength region to pass through. The sub-pixel 212 can be used as a photoelectric sensor.

[0696] Sub-pixels 212 (sub-pixels 212R, 212G, and 212B) are electrically connected to wirings 231, 247, 248, 249, and 250. Furthermore, sub-pixels 212R, 212G, and 212B are each connected to independently provided wirings 253. In this specification, for example, wirings 248 and 249 connected to the pixel 211 in the nth row are referred to as wiring 248[n] and wiring 249[n], respectively. Furthermore, for example, wiring 253 connected to the pixel 211 in the mth column is referred to as wiring 253[m]. Furthermore, in... Figure 45A In this circuit, the wiring 253 connecting the sub-pixel 212R included in the m-th column pixel 211 is called wiring 253[m]R, the wiring 253 connecting the sub-pixel 212G is called wiring 253[m]G, and the wiring 253 connecting the sub-pixel 212B is called wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit through the above wiring.

[0697] The camera device 200 has a structure in which adjacent pixels 211 are arranged and sub-pixels 212 with color filters that allow light of the same wavelength region to pass through are electrically connected to each other by a switch. Figure 45B This illustrates an example of the connection between a sub-pixel 212 in pixel 211 located in row n (n is an integer greater than 1 and less than p) and column m (m is an integer greater than 1 and less than q), and a sub-pixel 212 located in the adjacent pixel 211 located in row (n+1) and column m. Figure 45B In the configuration, sub-pixel 212R configured in row n, column m and sub-pixel 212R configured in row (n+1), column m are connected via switch 201. Furthermore, sub-pixel 212G configured in row n, column m and sub-pixel 212G configured in row (n+1), column m are connected via switch 202. Additionally, sub-pixel 212B configured in row n, column m and sub-pixel 212B configured in row (n+1), column m are connected via switch 203.

[0698] The color filter used for sub-pixel 212 is not limited to red (R) filter, green (G) filter, and blue (B) filter; color filters that allow cyan (C), yellow (Y), and magenta (M) light to pass through can also be used. By setting a sub-pixel 212 in a single pixel 211 that detects light in three different wavelength regions, a full-color image can be obtained.

[0699] Alternatively, a pixel 211 can be used that includes sub-pixels 212 that are respectively provided with color filters that allow red (R), green (G), and blue (B) light to pass through, as well as sub-pixels 212 that are provided with color filters that allow yellow (Y) light to pass through. Alternatively, a pixel 211 can be used that includes sub-pixels 212 that are respectively provided with color filters that allow cyan (C), yellow (Y), and magenta (M) light to pass through, as well as sub-pixels 212 that are provided with color filters that allow blue (B) light to pass through. By providing sub-pixels 212 that detect light in four different wavelength regions within a single pixel 211, the color reproduction of the obtained image can be further improved.

[0700] For example, in Figure 45A In this design, the pixel ratio (or light-receiving area ratio) of the sub-pixels 212 that detect light in the red wavelength region, the green wavelength region, and the blue wavelength region is not limited to 1:1:1. For example, a Bayer arrangement with a pixel ratio (light-receiving area ratio) of red:green:blue = 1:2:1 can also be used. Alternatively, the pixel ratio (light-receiving area ratio) can also be red:green:blue = 1:6:1.

[0701] The number of sub-pixels 212 set in pixel 211 can be one, but preferably two or more. For example, by setting two or more sub-pixels 212 that detect light in the same wavelength region, redundancy can be improved, thereby improving the reliability of the imaging device 200.

[0702] Furthermore, an infrared light detection camera 200 can be realized by using an IR (Infrared) filter that reflects or absorbs visible light and allows infrared light to pass through.

[0703] By using neutral density (ND) filters, output saturation can be prevented when a large amount of light is incident on the photoelectric conversion element (light-receiving element). By combining ND filters with different light reduction values, the dynamic range of the camera device can be increased.

[0704] In addition to the aforementioned filter, a lens can also be provided in pixel 211. Here, refer to... Figure 46A and Figure 46B The cross-sectional diagram illustrates an example of the configuration of pixel 211, filter 254, and lens 255. By configuring lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown... Figure 46A As shown, light 256 can pass through the lens 255, filter 254 (filter 254R, filter 254G and filter 254B) and pixel circuit 230 formed in the pixel 211 and be incident on the photoelectric conversion element 220.

[0705] Note that, as shown in the area surrounded by the dotted line, sometimes a portion of the light 256 indicated by the arrow is obscured by a portion of the wiring 257. Therefore, as... Figure 46B As shown, a preferred structure is one in which a lens 255 and a filter 254 are arranged on one side of the photoelectric conversion element 220, thereby enabling the photoelectric conversion element 220 to efficiently receive light 256. By incident light 256 onto the photoelectric conversion element 220 from one side, a camera device 200 with high detection sensitivity can be provided.

[0706] As Figure 46A and Figure 46B The photoelectric conversion element 220 shown can also be a photoelectric conversion element with a pn junction or a pin junction.

[0707] The photoelectric conversion element 220 can also be formed using a material that has the function of absorbing radiation and generating electric charge. Examples of materials that have the function of absorbing radiation and generating electric charge include selenium, lead iodide, mercuric iodide, gallium arsenide, cadmium telluride, and cadmium-zinc alloy.

[0708] For example, when selenium is used in photoelectric conversion element 220, a photoelectric conversion element 220 with a light absorption coefficient in a wide wavelength range such as visible light, ultraviolet light, infrared light, X-rays, and gamma rays can be realized.

[0709] Here, the pixel 211 included in the camera device 200, in addition to Figure 45A and Figure 45B In addition to the sub-pixel 212 shown, it may also include a sub-pixel 212 having a first filter.

[0710] <Example 2 of pixel structure>

[0711] Below, an example of a pixel including transistors using silicon and transistors using oxide semiconductors will be described.

[0712] Figure 47A and Figure 47B It is a cross-sectional view of the components that make up the camera device. Figure 47A The imaging device shown includes a silicon-based transistor 351 disposed on a silicon substrate 300, transistors 352 and 353 disposed on the transistor 351 and disposed in the silicon substrate 300, and a photodiode 360 ​​disposed in the silicon substrate 300. Each transistor and photodiode 360 ​​is electrically connected to various connectors 370 and wiring 371. Furthermore, the anode 361 of the photodiode 360 ​​is electrically connected to the connector 370 through a low-resistance region 363.

[0713] The camera device includes: a layer 310 comprising a transistor 351 disposed on a silicon substrate 300 and a photodiode 360 ​​disposed in the silicon substrate 300; a layer 320 disposed in contact with the layer 310 and including wiring 371; a layer 330 disposed in contact with the layer 320 and including transistor 352 and transistor 353; and a layer 340 disposed in contact with the layer 330 and including wiring 372 and wiring 373.

[0714] exist Figure 47A In one example of a cross-sectional view, a light-receiving surface of a photodiode 360 ​​is provided on the side of the silicon substrate 300 opposite to the side where the transistor 351 is formed. By employing this structure, the optical path can be ensured unaffected by various transistors and wiring. Therefore, a pixel with a high aperture ratio can be formed. Alternatively, the light-receiving surface of the photodiode 360 ​​can also be the same as the side where the transistor 351 is formed.

[0715] When a pixel includes only transistors using oxide semiconductors, layer 310 is a layer that includes transistors using oxide semiconductors. Alternatively, a pixel may include only transistors using oxide semiconductors and omit layer 310.

[0716] Layer 330 can also be omitted when the pixel only includes transistors using silicon. Figure 47B An example of a cross-sectional view of layer 330 is shown.

[0717] The silicon substrate 300 can also be an SOI substrate. Alternatively, a substrate containing germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor can be used instead of the silicon substrate 300.

[0718] Here, an insulator 380 is provided between layer 310, which includes transistor 351 and photodiode 360, and layer 330, which includes transistor 352 and transistor 353. Note that the location of the insulator 380 is not limited to this.

[0719] Hydrogen in the insulator near the channel formation region of transistor 351 terminates the dangling bonds in silicon, thereby improving the reliability of transistor 351. On the other hand, hydrogen in the insulator near transistors 352 and 353 can potentially contribute to the generation of charge carriers in the oxide semiconductor. Therefore, hydrogen can sometimes cause a decrease in the reliability of transistors 352 and 353. Therefore, when stacking transistors using oxide semiconductors on top of transistors using silicon semiconductors, it is preferable to place an insulator 380 that blocks hydrogen between them. By enclosing hydrogen under the insulator 380, the reliability of transistor 351 can be improved. Furthermore, since the diffusion of hydrogen from under the insulator 380 to the insulator 380 can be suppressed, the reliability of transistors 352 and 353 can also be improved.

[0720] For example, an insulator 380 is used as an insulator that has the function of blocking oxygen or hydrogen.

[0721] exist Figure 47A In the cross-sectional view, the photodiode 360 ​​disposed in layer 310 and the transistor disposed in layer 330 can be formed in an overlapping manner. Therefore, the pixel integration density can be improved. That is to say, the resolution of the camera device can be improved.

[0722] like Figure 48A1 and Figure 48B1 As shown, it can bend part or all of the camera device. Figure 48A1 The image shows the camera device bent in the direction of the dashed lines X1-X2 in the accompanying drawing. Figure 48A2 It is along Figure 48A1 The cross-sectional view of the portion indicated by the dashed lines X1-X2 in the figure. Figure 48A3 It is along Figure 48A1 The cross-sectional view of the portion indicated by the dashed lines Y1-Y2 in the figure.

[0723] Figure 48B1 The image shows a state in which the camera device is bent in the direction of the dashed line X3-X4 in the figure and in the direction of the dashed line Y3-Y4 in the figure. Figure 48B2 It is along Figure 48B1 The cross-sectional view of the portion indicated by the dashed lines X3-X4 in the figure. Figure 48B3 It is along Figure 48B1 The cross-sectional view of the section indicated by the dashed lines Y3-Y4 in the figure.

[0724] By bending the imaging device, field curvature or astigmatism can be reduced. Therefore, the optical design of a lens or the like used in combination with the imaging device can be made easier. For example, since the number of lenses for aberration correction can be reduced, miniaturization or weight reduction of an electronic device or the like using the imaging device can be achieved. In addition, the quality of the captured image can be improved.

[0725] The structure shown in this embodiment can be used in appropriate combination with the structures shown in other embodiments.

[0726] Embodiment 14

[0727] In this embodiment, an example of a CPU of a semiconductor device such as a transistor or the above-described storage device including one aspect of the present invention will be described.

[0728] <Structure of CPU>

[0729] Figure 49 is a block diagram showing an example of the structure of a CPU in which a part thereof uses the above-described transistor.

[0730] Figure 49 The CPU shown has, on a substrate 1190: an ALU 1191 (ALU: Arithmetic Logic Unit: arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, a bus interface 1198, a rewritable ROM 1199, and a ROM interface 1189. As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may also be provided on different chips. Of course, Figure 49 The CPU shown is merely an example showing a simplified structure thereof, so an actual CPU has various structures depending on its use. For example, it may also include Figure 49 The structure of the CPU or arithmetic circuit shown as a core, and a plurality of such cores may be provided and operated simultaneously. In addition, the number of bits that can be processed in the internal arithmetic circuit or data bus of the CPU can be, for example, 8, 16, 32, 64, or the like.

[0731] An instruction input to the CPU through the bus interface 1198 is input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

[0732] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals to control the operation of the ALU 1191. Furthermore, the interrupt controller 1194, during CPU program execution, determines and processes interrupt requests from external input / output devices or peripheral circuits based on their priority or mask state. The register controller 1197 generates the address of register 1196 and reads or writes data to register 1196 according to the CPU's state.

[0733] Additionally, the timing controller 1195 generates signals to control the operating timing of the ALU 1191, ALU controller 1192, instruction decoder 1193, interrupt controller 1194, and register controller 1197. For example, the timing controller 1195 has an internal clock generator that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0734] exist Figure 49 In the CPU shown, a storage unit is provided in register 1196. The aforementioned transistors or storage devices can be used in the storage unit of register 1196.

[0735] exist Figure 49 In the CPU shown, the register controller 1197 selects the holding operation in register 1196 according to instructions from ALU 1191. In other words, the register controller 1197 selects whether data is held by flip-flops or by capacitors within the memory locations of register 1196. When flip-flops are selected, power supply voltage is supplied to the memory locations in register 1196. When capacitors are selected, the data is overwritten to the capacitors, and power supply voltage to the memory locations in register 1196 can be stopped.

[0736] Figure 50 This is an example of a circuit diagram for a storage element 1200 that can be used as register 1196. Storage element 1200 includes a circuit 1201 that loses stored data when power is cut off, a circuit 1202 that does not lose stored data when power is cut off, switches 1203 and 1204, a logic element 1206, a capacitor 1207, and a selection circuit 1220. Circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Additionally, storage element 1200 may include other components such as diodes, resistors, or inductors as needed.

[0737] Here, the aforementioned storage device can be used as circuit 1202. When the power supply voltage to the storage element 1200 is stopped, GND (0V), or a potential that turns off transistor 1209, is continuously input to the gate of transistor 1209 in circuit 1202. For example, the gate of transistor 1209 is grounded through a load such as a resistor.

[0738] This example illustrates a transistor 1213 with a conductivity type (e.g., n-channel) as switch 1203, and a transistor 1214 with the opposite conductivity type (e.g., p-channel) as switch 1204. Here, the first terminal of switch 1203 corresponds to one of the source and drain terminals of transistor 1213, and the second terminal of switch 1203 corresponds to the other of the source and drain terminals of transistor 1213. The on / off state of transistor 1213 is selected by a control signal RD input to the gate of transistor 1213. Similarly, the first terminal of switch 1204 corresponds to one of the source and drain terminals of transistor 1214, and the second terminal of switch 1204 corresponds to the other of the source and drain terminals of transistor 1214. The on / off state of transistor 1214 is also selected by a control signal RD input to the gate of transistor 1214.

[0739] One of the source and drain of transistor 1209 is electrically connected to one of the electrodes of capacitor 1208 and the gate of transistor 1210. This connection is ...

Claims

1. A semiconductor device having a first transistor and a second transistor, the semiconductor device comprising: Substrate; The first insulator above the substrate; The channel formation region of the first transistor above the first insulator; A second insulator above the channel formation region of the first transistor; The first conductor above the second insulator; A third insulator above the first conductor and the second insulator; The second conductor above the third insulator; The fourth insulator above the second conductor; The semiconductor above the fourth insulator that contains the channel forming region of the second transistor; A third conductor and a fourth conductor having a region in contact with the top surface of a semiconductor containing the channel forming region of the second transistor; A fifth insulator above the semiconductor containing the channel formation region of the second transistor; The fifth conductor is located above the fifth insulator and overlaps with the channel region of the second transistor. The sixth insulator above the fifth conductor; as well as The sixth conductor above the sixth insulator The channel region of the first transistor contains silicon. The first conductor serves as the gate electrode of the first transistor. The second conductor serves as the first gate electrode of the second transistor. The channel formation region of the second transistor has an oxide semiconductor comprising indium, gallium, and zinc. The third conductor serves as one of the source and drain electrodes of the second transistor. The fourth conductor serves as the other of the source and drain electrodes of the second transistor. The fifth conductor serves as the second gate electrode of the second transistor. The sixth conductor serves as the first electrode of the capacitor. In the cross-sectional view along the channel length of the second transistor, the first conductor and the second conductor do not overlap. The third conductor is electrically connected to one of the source and drain terminals of the first transistor. The fourth conductor is electrically connected to the gate electrode of the first transistor. The sixth conductor has a region that overlaps with the first gate electrode of the first transistor and a region that overlaps with the semiconductor containing the channel forming region of the second transistor.

2. A semiconductor device, comprising: Semiconductors on a substrate; The first conductor and the second conductor on the semiconductor; The first conductor and the first insulator on the second conductor; The second insulator on the semiconductor; A third insulator on the second insulator; The third conductor on the third insulator; as well as The first insulator and the fourth conductor on the third conductor, The third insulator includes a region that contacts the side surface of the first insulator. The semiconductor includes a first region overlapping with the bottom surface of the first conductor, a second region overlapping with the bottom surface of the second conductor, and a third region overlapping with the bottom surface of the third conductor. The length between the top surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region. The length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first region and the second region.

3. A semiconductor device having a first transistor and a second transistor, the semiconductor device comprising: Substrate; The first insulator above the substrate; The channel formation region of the first transistor above the first insulator; A second insulator above the channel formation region of the first transistor; The first conductor above the second insulator; A third insulator above the first conductor and the second insulator; The second conductor above the third insulator; The fourth insulator above the second conductor; The semiconductor above the fourth insulator that contains the channel forming region of the second transistor; A third conductor and a fourth conductor having a region in contact with the top surface of a semiconductor containing the channel forming region of the second transistor; A fifth insulator above the semiconductor containing the channel formation region of the second transistor; The fifth conductor is located above the fifth insulator and overlaps with the channel region of the second transistor. The sixth insulator above the fifth conductor; as well as The sixth conductor above the sixth insulator The channel region of the first transistor contains silicon. The first conductor serves as the gate electrode of the first transistor. The second conductor serves as the first gate electrode of the second transistor. The channel formation region of the second transistor has an oxide semiconductor comprising indium, gallium, and zinc. The third conductor serves as one of the source and drain electrodes of the second transistor. The fourth conductor serves as the other of the source and drain electrodes of the second transistor. The fifth conductor serves as the second gate electrode of the second transistor. The sixth conductor serves as the first electrode of the capacitor. In the cross-sectional view along the channel length of the second transistor, the first conductor and the second conductor do not overlap. The third conductor is electrically connected to one of the source and drain terminals of the first transistor. The fourth conductor is electrically connected to the gate electrode of the first transistor. The sixth conductor has a region that overlaps with the first gate electrode of the first transistor and a region that overlaps with the semiconductor containing the channel forming region of the second transistor. In a cross-sectional view along the channel width of the second transistor, the bottom surface of the fifth conductor is lower than the bottom surface of the semiconductor containing the channel forming region of the second transistor.

4. A semiconductor device, comprising: Semiconductors on a substrate; The first conductor and the second conductor on the semiconductor; The first conductor and the first insulator on the second conductor; The second insulator on the semiconductor; A third insulator on the second insulator; The fourth insulator on the third insulator; The third conductor on the fourth insulator; as well as The first insulator and the fourth conductor on the third conductor, The fourth insulator includes a region that contacts the side surface of the first insulator. The semiconductor includes a first region overlapping with the bottom surface of the first conductor, a second region overlapping with the bottom surface of the second conductor, and a third region overlapping with the bottom surface of the third conductor. The length between the top surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region. The length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first region and the second region.

5. The semiconductor device according to claim 2 or claim 4, wherein, The length between the first conductor or the second conductor and the fourth conductor is more than 1.5 times and less than 2 times the length between the first region and the second region.

6. A semiconductor device, comprising: Semiconductors on a substrate; The first conductor and the second conductor on the semiconductor; The first conductor and the first insulator on the second conductor; The second insulator on the semiconductor; A third insulator on the second insulator; The third conductor on the third insulator; as well as The first insulator and the fourth conductor on the third conductor, The second insulator includes a region that contacts the side of the first insulator. The side surface of the first insulator has an angle θ greater than 0 degrees and less than 90 degrees with respect to the top surface of the first conductor or the second conductor. The semiconductor includes a first region overlapping with the bottom surface of the first conductor, a second region overlapping with the bottom surface of the second conductor, and a third region overlapping with the bottom surface of the third conductor. The length between the top surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region. The length between the first conductor or the second conductor and the fourth conductor is greater than the length between the first region and the second region.

7. The semiconductor device according to claim 6, wherein, The length between the first conductor or the second conductor and the fourth conductor is more than 1.5 times and less than 2 times the length between the first region and the second region.

8. The semiconductor device according to claim 6, wherein, The semiconductor is an oxide semiconductor.

9. A semiconductor device having a first transistor and a second transistor, the semiconductor device comprising: Substrate; The first insulator above the substrate; The channel formation region of the first transistor above the first insulator; A second insulator above the channel formation region of the first transistor; The first conductor above the second insulator; A third insulator above the first conductor and the second insulator; The semiconductor containing the channel forming region of the second transistor above the third insulator; A second conductor having a region overlapping with a semiconductor containing a channel forming region of the second transistor; A third conductor and a fourth conductor having a region in contact with the top surface of a semiconductor containing the channel forming region of the second transistor; The third conductor and the fourth insulator above the fourth conductor; and The fifth conductor above the fourth insulator, The channel region of the first transistor contains silicon. The first conductor serves as the gate electrode of the first transistor. The second conductor serves as the gate electrode of the second transistor. The channel region of the second transistor has an indium-containing oxide semiconductor. The third conductor serves as one of the source and drain electrodes of the second transistor. The fourth conductor serves as the other of the source and drain electrodes of the second transistor. The fifth conductor serves as the first electrode of the capacitor. In the cross-sectional view along the channel length of the second transistor, the first conductor and the second conductor do not overlap. The third conductor is electrically connected to one of the source and drain terminals of the first transistor. The fourth conductor is electrically connected to the first conductor.

10. A semiconductor device having a first transistor and a second transistor, the semiconductor device comprising: Substrate; The first insulator above the substrate; The channel formation region of the first transistor above the first insulator; A second insulator above the channel formation region of the first transistor; The first conductor above the second insulator; A third insulator above the first conductor and the second insulator; The semiconductor containing the channel forming region of the second transistor above the third insulator; A second conductor having a region overlapping with a semiconductor containing a channel forming region of the second transistor; A third conductor and a fourth conductor having a region in contact with the top surface of a semiconductor containing the channel forming region of the second transistor; The third conductor and the fourth insulator above the fourth conductor; and The fifth conductor above the fourth insulator, The channel region of the first transistor contains silicon. The first conductor serves as the gate electrode of the first transistor. The second conductor serves as the gate electrode of the second transistor. The channel region of the second transistor has an indium-containing oxide semiconductor. The third conductor serves as one of the source and drain electrodes of the second transistor. The fourth conductor serves as the other of the source and drain electrodes of the second transistor. The fifth conductor serves as the first electrode of the capacitor. In the cross-sectional view along the channel length of the second transistor, the first conductor and the second conductor do not overlap. The third conductor is electrically connected to one of the source and drain terminals of the first transistor. The fourth conductor is located on the same layer as the second conductor, and the fourth conductor is electrically connected to the first conductor via a sixth conductor containing the same material as the second conductor.

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