Arithmetic devices and multiply-accumulate systems

Abstract

An arithmetic device includes a plurality of input lines and one or more multiplication-accumulation devices. Each of the electrical signals corresponding to the input values ​​is input into the plurality of input lines within a predetermined input cycle. The plurality of multiplication units of the multiplication-accumulation device generates a charge corresponding to a product value obtained by multiplying the input value by a weight value based on the electrical signal input into each of the plurality of input lines. The accumulation unit of the multiplication-accumulation device accumulates the charge corresponding to the product value generated by each of the plurality of multiplication units. The charging unit of the multiplication-accumulation device charges the accumulation unit in which the charge corresponding to the product value is accumulated after the input cycle. The output unit of the multiplication-accumulation device outputs a multiplication-accumulation signal indicating the sum of the product values ​​by performing threshold determination on the voltage held by the accumulation unit using a predetermined threshold value after charging starts through the charging unit. In the one or more multiplication-accumulation devices, charging through the charging unit is performed in a common charging mode, and the common threshold value is set to a predetermined threshold value.

Description

Technical Field

[0001] The present technology relates to an arithmetic device and a multiply-accumulate system applicable to a multiply-accumulate operation using an analog method. Background Art

[0002] Conventionally, a technique for performing a multiplication-accumulation operation has been developed. The multiplication-accumulation operation is an operation of multiplying each of a plurality of input values ​​by a weight and adding the multiplication results to each other, and is used, for example, in processing for recognizing an image, a voice, or the like by a neural network or the like.

[0003] For example, patent document 1 describes an analog circuit in which a multiplication-accumulation process is performed in an analog manner. In the analog circuit, a weight corresponding to each of a plurality of electrical signals is set. In addition, charges according to the corresponding electrical signals and weights are output respectively, and the output charges are appropriately accumulated in a capacitor. The value representing the multiplication-accumulation result to be calculated is calculated based on the voltage of the capacitor in which the charges are accumulated. Therefore, compared with, for example, digital processing, the power consumption required for the multiplication-accumulation operation can be reduced (paragraphs

[0003] ,

[0049] to

[0053] , and

[0062] of the specification of patent document 1, Figure 3 wait).

[0004] Citation List

[0005] Patent Literature

[0006] Patent Document 1: WO 2018 / 034163 Summary of the invention

[0007] Technical issues

[0008] It is expected that the use of such analog circuits will lead to lower power consumption in neural networks, etc., and that a technology for achieving efficient and high-speed calculation processing will be provided.

[0009] In view of the above circumstances, an object of the present technology is to provide an arithmetic device, a multiplication-accumulation system, and a setting method by which efficient and high-speed operation processing can be realized in an analog circuit that performs multiplication-accumulation operations.

[0010] Solution to the problem

[0011] In order to achieve the above-mentioned object, an arithmetic device according to an embodiment of the present technology includes a plurality of input lines and one or more multiplication-accumulation devices.

[0012] Each of the electrical signals corresponding to the input values ​​is input into the plurality of input lines within a predetermined input period.

[0013] The one or more multiplication-accumulation devices each include a plurality of multiplication units, an accumulation unit, a charging unit, and an output unit.

[0014] The plurality of multiplication units generate charges corresponding to a product value obtained by multiplying the input value by the weight value based on an electrical signal input to each of the plurality of input lines.

[0015] The accumulation unit accumulates charges corresponding to the product value generated by each of the plurality of multiplication units.

[0016] After the input period, the charging unit charges the accumulation unit in which the charge corresponding to the product value is accumulated.

[0017] After charging is started by the charging unit, the output unit outputs a multiplication-accumulation signal indicating a sum of product values ​​by performing threshold determination on the voltage held by the accumulation unit using a predetermined threshold.

[0018] Furthermore, in one or more of the multiplication-accumulation devices, charging by the charging unit is performed in a common charging mode, and the common threshold is set to a predetermined threshold.

[0019] In the arithmetic device, charging is performed in a common charging mode with respect to one or more multiplication-accumulation means, and threshold determination is performed by using a common threshold value. Therefore, efficient and high-speed arithmetic processing can be realized in an analog circuit that performs multiplication-accumulation operations.

[0020] The one or more multiply-accumulate devices may be a plurality of multiply-accumulate devices connected in parallel to a plurality of input lines.

[0021] The common charging mode may include charging with the same charging signal supplied during a common charging cycle.

[0022] The common charging mode may include charging at a common charging speed.

[0023] The common charging mode may include charging according to a common time constant.

[0024] The sum of absolute values ​​of weight values ​​set in the plurality of multiplication units is defined as a weight sum value, and the common charging mode may include charging based on a maximum value of the weight sum value in one or more multiplication-accumulation devices.

[0025] Each of the one or more multiplication-accumulation devices may include a charge output line. In this case, the plurality of multiplication units may output the charge corresponding to the product value to the charge output line. In addition, the common charging mode may include charging in which a time constant associated with outputting the charge corresponding to the product value to the charge output line by the plurality of multiplication units is used as a common time constant, and the weight sum value of the plurality of multiplication units is a maximum value.

[0026] The common threshold may be set based on the duration of the input cycle.

[0027] The sum of absolute values ​​of weight values ​​set in a plurality of multiplication units is defined as a weight sum value, and the common threshold may be set based on a maximum value of the weight sum values ​​in one or more multiplication-accumulation devices.

[0028] The common charging mode may include charging with the same charging signal supplied during the common charging cycle. In this case, the charging unit may include a charging line connected to the accumulation unit and providing the same charging signal to the accumulation unit during the common charging cycle.

[0029] The common charging mode may include charging with the same charging signal supplied during the common charging cycle. In this case, the charging unit may supply the same charging signal to the accumulation unit via a plurality of input lines during the common charging cycle.

[0030] The plurality of multiplication units may include at least one of a positive weight multiplication unit and a negative weight multiplication unit, the positive weight multiplication unit generating a positive weight charge corresponding to a product value obtained by multiplying an input value by a positive weight value, and the negative weight multiplication unit generating a negative weight charge corresponding to a product value obtained by multiplying an input value by a negative weight value. In this case, the accumulation unit may include a positive charge accumulation unit capable of accumulating the positive weight charge generated by the positive weight multiplication unit and a negative charge accumulation unit capable of accumulating the negative weight charge generated by the negative weight multiplication unit. In addition, the charging unit may charge the positive charge accumulation unit and the negative charge accumulation unit in a common charging mode. In addition, the output unit may output a multiplication-accumulation signal by thresholding each of the positive charge accumulation unit and the negative charge accumulation unit using a common threshold.

[0031] The sum of the positive weight values ​​set in multiple multiplication units is defined as a positive sum value, and the sum of the absolute values ​​of the negative weight values ​​is defined as a negative sum value, and the common charging mode may include charging based on the maximum value of the positive sum value and the negative sum value in one or more multiplication-accumulation devices.

[0032] Each of the one or more multiplication-accumulation devices may include a positive charge output line and a negative charge output line. In this case, the positive charge multiplication unit may output a positive weighted charge to the positive charge output line. In addition, the negative charge multiplication unit may output a negative weighted charge to the negative charge output line. In addition, assuming that the maximum value of the positive sum value and the negative sum value in the one or more multiplication-accumulation devices is the maximum sum value, the positive weighted charge or negative weighted charge associated with the maximum sum value is the maximum weighted charge, and the positive charge output line or negative charge output line from which the maximum weighted charge is output is the maximum charge output line; the time constant associated with the output of the maximum weighted charge to the maximum charge output line is defined as a common time constant, and the common charging mode may include charging according to the common time constant.

[0033] The sum of the positive weight values ​​set in multiple multiplication units is defined as a positive sum value, and the sum of the absolute values ​​of the negative weight values ​​is defined as a negative sum value, and the common threshold can be set based on the maximum value of the positive sum value and the negative sum value in one or more multiplication-accumulation devices.

[0034] The absolute values ​​of the positive weight value and the negative weight value can be fixed to the same value, set to any one of a plurality of values ​​different from each other, or set randomly. In this case, in one or more multiplication-accumulation devices, the value obtained by adding the positive sum value and the negative sum value can be a common value.

[0035] The absolute values ​​of the positive weight value and the negative weight value can be fixed to the same value, set to any one of a plurality of values ​​different from each other, or set randomly. In this case, in one or more multiplication-accumulation devices, the value obtained by adding the positive sum value and the negative sum value can be a random value.

[0036] The common charging mode may include charging with the same charging signal supplied during the common charging cycle. In this case, the charging unit may include a charging line connected to the positive charge accumulation unit and the negative charge accumulation unit, and the same charging signal is supplied to the positive charge accumulation unit and the negative charge accumulation unit during the common charging cycle.

[0037] The common charging mode may include charging with the same charging signal supplied during the common charging cycle. In this case, the charging unit may supply the same charging signal to the positive charge accumulation unit and the negative charge accumulation unit via a plurality of input lines during the common charging cycle.

[0038] A multiply-accumulate system according to an embodiment of the present technology includes a plurality of input lines, one or more analog circuits, and a network circuit.

[0039] The one or more analog circuits include a plurality of multiplication units, accumulation units, charging units, and output units.

[0040] A network circuit is configured by connecting multiple analog circuits.

[0041] Furthermore, in one or more analog circuits, charging by the charging unit is performed in a common charging mode, and the common threshold is set to a predetermined threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] [ Figure 1 ] shows a schematic diagram of a configuration example of an arithmetic device according to an embodiment of the present technology.

[0043] [ Figure 2 ] shows a schematic diagram of an example of an electrical signal to be input into an analog circuit.

[0044] [ Figure 3 ] shows a schematic diagram of a specific configuration example of an arithmetic device.

[0045] [ Figure 4 ] shows a schematic diagram of an example configuration of a neuron circuit.

[0046] [ Figure 5 ] shows a schematic circuit diagram of an analog circuit example of the PWM method.

[0047] [ Figure 6 ] is used to describe Figure 5 Graph showing an example of calculation of a multiply-accumulate signal for the illustrated analog circuit.

[0048] [ Figure 7 ] shows an example of the calculation of the multiplication-accumulation signal and a schematic diagram of the entire multiplication-accumulation result.

[0049] [ Figure 8 ] shows a schematic circuit diagram of an example of an analog circuit according to the TACT method.

[0050] [ Fig. 9 ] is a schematic graph describing the potential of each output line at the end of an input cycle.

[0051] [ Fig.10 ] is a diagram showing a configuration example of an arithmetic device including a plurality of analog circuits according to a PWM method.

[0052] [ Fig.11 ] is a diagram showing a configuration example of an arithmetic device including a plurality of analog circuits according to a PWM method.

[0053] [ Fig.12 ] is a diagram showing a configuration example of an arithmetic device including a plurality of analog circuits according to the TACT method.

[0054] [ Fig.13 ] is a diagram showing a configuration example of an arithmetic device including a plurality of analog circuits according to the TACT method.

[0055] [ Fig.14 ] shows a schematic diagram of a configuration example of a neural network.

[0056] [ Fig.15 ] shows a schematic circuit diagram of another example of an analog circuit according to the PWM method.

[0057] [ Fig.16 ] shows a schematic circuit diagram of another example of an analog circuit according to the PWM method.

[0058] [ Fig.17 ] is used to describe Fig.16 Graph showing an example of calculation of a multiply-accumulate signal for the illustrated analog circuit. DETAILED DESCRIPTION

[0059] Hereinafter, embodiments according to the present technology will be described with reference to the drawings.

[0060] [Arithmetic device configuration]

[0061] Figure 1 1 is a schematic diagram showing a configuration example of an arithmetic device according to an embodiment of the present technology. The arithmetic device 100 is an analog arithmetic device that performs predetermined arithmetic processing including multiplication-accumulation operations. For example, by using the arithmetic device 100, arithmetic processing can be performed according to a mathematical model such as a neural network.

[0062] The arithmetic device 100 includes a plurality of signal lines 1, a plurality of input units 2, and a plurality of analog circuits 3. Each of the signal lines 1 is a line that transmits a predetermined type of electrical signal. For example, an analog signal that represents a signal value by using analog quantities such as pulse timing and pulse width is used as the electrical signal. The direction of electrical signal transmission is Figure 1 In the present embodiment, the analog circuit 3 corresponds to a multiplication-accumulation device.

[0063] For example, a plurality of signal lines 1 are connected to one analog circuit 3. A signal line 1 that transmits an electric signal to the analog circuit 3 is an input signal line into which the electric signal is input for the analog circuit 3 connected to the signal line 1. In addition, a signal line 1 that transmits an electric signal output from the analog circuit 3 is an output signal line from which the electric signal is output for the analog circuit 3 connected to the signal line 1. In the present embodiment, the input signal line corresponds to the input line.

[0064] The plurality of input units 2 each generate a plurality of electrical signals corresponding to the input data 4. The input data 4 is, for example, data to be processed using a neural network or the like implemented by the arithmetic device 100. Therefore, it can also be said that the respective signal values ​​of the plurality of electrical signals corresponding to the input data 4 are input values ​​of the arithmetic device 100.

[0065] For example, arbitrary data such as image data, audio data, and statistical data to be processed by the arithmetic device 100 is used as the input data 4. For example, in the case where image data is used as the input data 4, an electric signal using a pixel value (RGB value, brightness value, etc.) of each pixel of the image data as a signal value is generated. In addition, an electric signal corresponding to the input data 4 can be appropriately generated according to the type of the input data 4 and the content of the processing performed by the arithmetic device 100.

[0066] The analog circuit 3 is an analog circuit that performs multiplication-accumulation operations based on input electrical signals. The multiplication-accumulation operation is, for example, an operation of adding multiple product values ​​obtained by multiplying multiple input values ​​by weight values ​​corresponding to the input values. Therefore, it can also be said that the multiplication-accumulation operation is a process of calculating the sum of the product values ​​(hereinafter referred to as the multiplication-accumulation result).

[0067] like Figure 1 As shown, a plurality of input signal lines are connected to one analog circuit 3 and a plurality of electrical signals are provided thereto. According to the present embodiment, a plurality of input signal lines and the analog circuit constitute a multiplication-accumulation operation circuit. In addition, a plurality of electrical signals are input from each of the input signal lines, so the multiplication-accumulation method according to the present embodiment is performed by the multiplication-accumulation operation circuit (analog circuit 3).

[0068] Hereinafter, it is assumed that the total number of electrical signals input to one analog circuit 3 is N. It should be noted that the number N of electrical signals to be input to each analog circuit 3 is appropriately set for each circuit according to, for example, a model, accuracy, etc. of arithmetic processing.

[0069] In analog circuit 3, for example, w is calculated i *x i , which is the signal value x represented by the electrical signal input by the i-th input signal line i and corresponds to the signal value x i The weight value w i Here, i represents a natural number equal to or less than N (i=1, 2, ..., N). A product value operation is performed on each electrical signal (input signal line), and N product values ​​are calculated. The value obtained by adding the N product values ​​is calculated as a multiplication-accumulation result (the sum of the N product values). Therefore, the multiplication-accumulation result calculated by one analog circuit 3 is represented by the following expression.

[0070] [Formula 1]

[0071]

[0072] Weight value w i is set, for example, at -α≤w i ≤+α. Here, α represents any real value. Therefore, the weight value w i can include positive weight values ​​w i , negative weight value w i , zero weight value w i As mentioned above, by setting the weight value w i By setting it within a predetermined range, it is possible to avoid the situation where the multiplication-accumulation result diverges.

[0073] In addition, for example, the weight value w can be set i In this case, the weight value w i Set at -1≤w i ≤ 1. Therefore, for example, the maximum value, the minimum value, etc. of the multiplication-accumulation result can be adjusted, and the multiplication-accumulation operation can be performed with desired accuracy.

[0074] In neural networks and the like, a method called binary connection can be used, which converts the weight value w i Set to +α or -α. Binary connections are used in various fields, such as image recognition using deep neural networks (multi-layer neural networks). Using binary connections can simplify the weight value w i The setting of the positive weight value and the negative weight value is fixed to the same value in the binary connection.

[0075] As mentioned above, in a binary connection, the weight value w i is binarized into binary values ​​(±α). Therefore, for example, the weight value w i Change to positive or negative to easily set the desired weight value w i Optionally, the binary weight value w i can be normalized and the weight value w i Can be set to ±1.

[0076] In addition, the weight value w i Can be multi-valued. In this case, the weight value w is set by selecting from multiple discrete weight value candidates i Examples of weight value candidates include (-3, -2, -1, 0, 1, 2, 3) and (1, 2, 5, 10). In addition, standardized weight value candidates (-1, -0.5, 0, 0.5, 1) and the like may be used. A value is selected from these weight value candidates and is set as the weight value w. iThe number of weight value candidates, the method of setting the candidate values, etc. are not limited. i Multi-valued, highly versatile neural networks can be constructed.

[0077] In addition, the weight value w i The setting range, setting value, etc. of are not limited, and can be appropriately set to achieve the desired processing accuracy, for example. For example, the weight value w can be randomly set. i .

[0078] Signal value x i For example, the electric signal output from the input unit 2 and the multiplication-accumulation result output from the analog circuit 3. In this way, it can also be said that the input unit 2 and the analog circuit 3 play the role of outputting the signal value x i The role of the signal source.

[0079] exist Figure 1 In the example shown, a single electrical signal (single signal value x) is output from a signal source (input unit 2, analog circuit 3). i ). Therefore, the same electric signal is input to each of the plurality of signal lines 1 connected to the output side of one signal source. In addition, one signal source and the analog circuit 3 into which the electric signal output from the signal source is input are connected to each other through a single input signal line.

[0080] Thus, for example, M input signal lines are connected to analog circuit 3, which is connected to Figure 1 In the arithmetic device 100 shown in FIG. 1 , there are M signal sources. In this case, the total number N of electrical signals input to the analog circuit 3 is N=M. It should be noted that a pair of electrical signals (a pair of signal values ​​x ) corresponding to positive and negative values ​​are output from one signal source. i + 、x i - ) configuration is possible.

[0081] like Figure 1 As shown, the arithmetic device 100 has a layered structure in which a plurality of analog circuits 3 are provided in each of a plurality of layers. By configuring the layer structure of the analog circuits 3, for example, a multilayer perceptron type neural network or the like is constructed. For example, the number of analog circuits provided in each layer, the number of layers, etc. are appropriately designed so that desired processing can be performed. In the following, the number of analog circuits 3 provided in the jth layer is sometimes referred to as N. j .

[0082] For example, N electrical signals generated by N input units 2 are input to each analog circuit 3 provided in the first-level layer (lowest layer). The analog circuit 3 of the first level calculates the signal value x corresponding to the input data. iThe related multiplication-accumulation result is not subjected to a linear conversion process and the calculated multiplication-accumulation result is output to the analog circuit 3 of the next layer (second level).

[0083] N1 electrical signals representing the corresponding multiplication-accumulation results calculated in the first stage are input to the corresponding analog circuits 3 provided in the second layer (upper layer). Therefore, from the perspective of the analog circuits 3 of the second layer, the nonlinear conversion processing results of the corresponding multiplication-accumulation results calculated in the first stage are the signal values ​​x of the electrical signals. i The analog circuit 3 of the second stage calculates the signal value x output from the first stage i The multiplication-accumulation result is calculated and the calculated multiplication-accumulation result is output to the upper-layer analog circuit 3.

[0084] In this way, in the arithmetic device 100, the multiplication-accumulation result of the analog circuit 3 in the upper layer is calculated based on the multiplication-accumulation result calculated by the analog circuit 3 in the lower layer. Such processing is performed multiple times, and the processing results are obtained from the top layer ( Figure 1 The analog circuit 3 in the third-level layer in FIG. 1 is output. Therefore, for example, processing such as image recognition to determine that an object is a cat can be performed based on image data (input data 4) obtained by imaging a cat.

[0085] As described above, a desired network circuit can be configured by appropriately connecting a plurality of analog circuits 3. The network circuit is used as a data flow processing system that performs arithmetic processing by, for example, passing a signal therethrough. In the network circuit, various processing functions can be realized by appropriately setting, for example, weight values ​​(synaptic connections). Through this network circuit, the multiplication-accumulation system of the present embodiment is constructed.

[0086] It should be noted that there is no limitation on the method of connecting the analog circuits 3 to each other, and for example, a plurality of analog circuits 3 may be appropriately connected to each other so that the desired processing can be performed. For example, even in the case where the analog circuits 3 are connected to each other to configure another structure different from the hierarchical structure, the present technology can be applied.

[0087] In the above description, a configuration has been described in which the multiplication-accumulation result calculated in the lower layer is input to the upper layer as it is. The present technology is not limited to this, and for example, conversion processing or the like may be performed on the multiplication-accumulation result. For example, in a neural network model, a process is performed in which, for example, the multiplication-accumulation result of each analog circuit 3 is nonlinearly converted by using an activation function and the conversion result is input to the upper layer.

[0088] In the arithmetic device 100, a function circuit 5 or the like that performs nonlinear conversion on an electric signal using, for example, an activation function is used. The function circuit 5 is, for example, a circuit that is provided between a lower layer and an upper layer and appropriately converts a signal value of an input electric signal and outputs an electric signal according to the conversion result. For example, a function circuit 5 is provided for each of the signal lines 1. The number of function circuits 5, the arrangement of the function circuits 5, etc. are appropriately set according to, for example, a mathematical model implemented in the arithmetic device 100.

[0089] For example, a ReLU function (ramp function) or the like is used as an activation function. The ReLU function is, for example, i If the value is 0 or greater, the signal value x is output as is. i , otherwise 0 is output. For example, a function circuit 5 that implements a ReLU function is appropriately connected to each of the signal lines 1. Thus, the processing of the arithmetic device 100 can be implemented.

[0090] Figure 2 3 is a schematic diagram showing an example of an electrical signal input to the analog circuit 3. Figure 2 A and B schematically show a graph showing the waveforms of a plurality of electrical signals in each of FIG. The horizontal axis of the graph represents the time axis, and the vertical axis represents the voltage of the electrical signal.

[0091] Figure 2 An exemplary waveform of an electrical signal according to a pulse width modulation (PWM) method is shown in A. For example, the PWM method is to use a pulse width τ of a pulse waveform. i To represent the signal value x i That is, in the PWM method, the pulse width τ of the electrical signal i is dependent on the signal value x i Length.

[0092] Usually, the pulse width τ i The longer the signal value x i The higher.

[0093] In addition, the electric signal is input into the analog circuit 3 within a predetermined input cycle T. More specifically, the corresponding electric signal is input into the analog circuit 3 so that the pulse waveform of the electric signal falls within the input cycle T. Therefore, the maximum value of the pulse width of the electric signal is similar to the input cycle T. It should be noted that the timing of each pulse waveform (electric signal) input and the like are not limited as long as the pulse waveform falls within the input cycle T.

[0094] In the PWM method, for example, the pulse width τ can be used i The duty cycle R of the input period T i (=τ i / T) to normalize the signal value x iThat is, the normalized signal value x i is represented as the signal value x i =R i It should be noted that the signal value x i With pulse width τ i The associated method is not restricted, for example, the signal value x can be appropriately set i The pulse width τ i , thereby making it possible to perform calculation processing and the like with desired accuracy.

[0095] In the case of using an electric signal according to the PWM method, a time axis analog multiplication-accumulation operation using the analog circuit 3 according to the PWM method can be performed.

[0096] exist Figure 2 In FIG. 1B, an exemplary waveform of an electrical signal of a spike timing method (hereinafter referred to as a TACT method) is shown. For example, the TACT method is to express a signal value x by using the rising timing of a pulse. i For example, by using a predetermined timing as a reference, a pulse is input at a timing corresponding to an input value.

[0097] The electrical signal is input to the analog circuit 3 within a predetermined input period T. The signal value x i It is represented by the pulse input timing within the input cycle T. For example, the maximum signal value x i Indicated by a pulse input simultaneously with the start of input cycle T. Minimum signal value x i Indicated by a pulse input simultaneously with the end of input cycle T.

[0098] In other words, the signal value x i It is represented by the duration from the input timing of the pulse to the end timing of the input cycle T. For example, the maximum signal value x i It is represented by a pulse whose duration from the input timing of the pulse to the end timing of the input cycle T is equal to the input cycle T. The minimum signal value x i Represented by one pulse, its duration from the input timing of the pulse to the end timing of the input cycle T is 0.

[0099] It should be noted that in Figure 2 In B, a continuous pulse signal that rises to a timing corresponding to the input value and maintains an ON level until a multiplication-accumulation result is obtained is used as an electrical signal according to the TACT method. The present technology is not limited thereto, and a rectangular pulse having a predetermined pulse width or the like can be used as an electrical signal according to the TACT method.

[0100] In the case of using an electric signal according to the TACT method, a time axis analog multiplication-accumulation operation using the analog circuit 3 according to the TACT method can be performed.

[0101] like Figure 2 As shown in A and B, a pulse signal whose duration of ON time relative to the input cycle T corresponds to the input value can be used as an electrical signal corresponding to the input value. It should be noted that the following will assume that the signal value x represented by each electrical signal i Describe the variable that is greater than or equal to 0 and less than or equal to 1.

[0102] Figure 3 is a schematic diagram showing a specific configuration example of the arithmetic device 100 . Figure 3 It is used to implement, for example Figure 1 The illustrated arrangement example of the circuit of the arithmetic device 100 schematically shows a plurality of analog circuits 3 provided in one layer of the arithmetic device 100 .

[0103] Each analog circuit 3 includes a pair of output lines 7, a plurality of synapse circuits 8 and a neuron circuit 9. Figure 3 As shown in the figure, one analog circuit 3 is configured to extend in a predetermined direction (vertical direction in the figure). A plurality of such analog circuits 3 extending in the vertical direction are arranged side by side in the horizontal direction to form a layer. It is assumed below that the analog circuit 3 on the far left in the figure is the first analog circuit 3. In addition, the direction in which the analog circuit 3 extends is sometimes referred to as the extension direction.

[0104] The pair of output lines 7 are spaced apart from each other in the extending direction. The pair of output lines 7 includes a positive charge output line 7a and a negative charge output line 7b. Each of the positive charge output line 7a and the negative charge output line 7b is connected to a neuron circuit 9 via a plurality of synapse circuits 8.

[0105] The synaptic circuit 8 calculates the signal value x represented by the electrical signal i With weight value w i The product value (w i *x i ). Specifically, the charge (current) corresponding to the product value is output to the positive charge output line 7a or the negative charge output line 7b.

[0106] As will be described later, a positive weight value w i + Or negative weight value w i - is set to the synaptic circuit 8. For example, corresponding to a positive weight value w i + The positive weight charge corresponding to the product value of w is output to the positive charge output line 7a. In addition, for example, i -The negative weighted charge of the product value is output to the negative charge output line 7b.

[0107] It should be noted that in the synaptic circuit 8, regardless of the weight value w i Whether it is positive or negative, the charge with the same sign (for example, positive charge) is output as the charge corresponding to the product value. That is, the positive weight charge and the negative weight charge become charges with the same sign.

[0108] In this way, each of the synaptic circuits 8 is configured to i The sign of the multiplication result is output to a different output line 7a or 7b. The specific configuration of the synapse circuit 8 will be described in detail later. In this embodiment, the plurality of synapse circuits 8 are used as a plurality of multiplication units that generate charges corresponding to product values ​​obtained by multiplying the input value by the weight value based on the electrical signal input to each of the plurality of input lines.

[0109] In this embodiment, a single input signal line 6 and a pair of output lines 7 are connected to a single synapse circuit 8. That is, a single electrical signal is input to the single synapse circuit 8, and a charge corresponding to a product value calculated based on the input electrical signal is output to the output line 7a or 7b. Therefore, the synapse circuit 8 is a single-input dual-output circuit connected to a single input signal line 6 and a pair of output lines 7 (a positive charge output line 7a and a negative charge output line 7b).

[0110] In one analog circuit 3, a plurality of synapse circuits 8 are arranged along a pair of output lines 7. Each synapse circuit 8 is connected in parallel to a positive charge output line 7a (negative charge output line 7b). In the following, it is assumed that the synapse circuit 8 disposed on the most downstream side (the side connected to the neuron circuit 9) is the first synapse circuit.

[0111] like Figure 3 As shown, a plurality of input signal lines 6 are wired to intersect with a pair of output lines 7 of each of a plurality of analog circuits 3. Typically, the input signal lines 6 are arranged to be orthogonal to each output line 7. That is, the arithmetic device 100 has a crossbar configuration in which the input signal lines 6 and the output lines 7 cross each other. By the crossbar configuration, for example, the analog circuits 3 and the like can be integrated at a high density.

[0112] Furthermore, in the arithmetic device 100, the j-th synapse circuit 8 included in the corresponding analog circuit 3 is connected in parallel to the j-th input signal line 6. Therefore, similar electric signals are input to the synapse circuits 8 connected to the same input signal line 6. Therefore, a configuration in which one signal source included in the lower layer is connected to a plurality of analog circuits 3 included in the upper layer can be realized.

[0113] It should be noted that in Figure 3In the example shown, the analog circuit 3 (front neuron) included in the lower layer is schematically shown as a signal source that inputs an electric signal into each input signal line 6. The present technology is not limited thereto, and for example, a crossbar configuration may also be used where the input unit 2 is used as a signal source.

[0114] As described above, in the arithmetic device 100, a plurality of analog circuits 3 are connected in parallel to each of the plurality of input signal lines 6. Therefore, for example, an electrical signal can be input in parallel to each analog circuit 3 (each synapse circuit 8) and high-speed arithmetic processing can be achieved. Therefore, excellent operation performance can be exhibited.

[0115] The neuron circuit 9 calculates the multiplication-accumulation result shown in the expression (Formula 1) based on the product value calculated by the synaptic circuit 8. Specifically, the neuron circuit 9 outputs an electrical signal representing the multiplication-accumulation result (multiplication-accumulation signal) based on the charge input via the pair of output lines 7.

[0116] Figure 4 is a schematic diagram showing a configuration example of the neuron circuit 9. The neuron circuit 9 includes an accumulation unit 11 and a signal output unit 12. Figure 4 A dual-input single-output neuron circuit 9 is shown connected to a pair of output lines 7 and a single output signal line 10. It should be noted that a dual-input dual-output circuit or the like may be used as the neuron circuit 9 in some cases.

[0117] The accumulation unit 11 accumulates the charges outputted to the pair of output lines 7 by the plurality of synaptic circuits 8. The accumulation unit 11 includes two capacitors 13a and 13b. The capacitor 13a is connected between the positive charge output line 7a and GND. In addition, the capacitor 13b is connected between the negative charge output line 7b and GND. Therefore, the charges flowing in from the positive charge output line 7a and the negative charge output line 7b are accumulated in the capacitors 13a and 13b accordingly.

[0118] For example, when the input period T of the electric signal has elapsed, the charge accumulated in the capacitor 13a is the sum of the positive weight charges σ + , each positive weight charge corresponds to a positive weight value w i + In addition, the charge accumulated in capacitor 13b corresponds to the negative weight value w i - The sum of the negative weighted charges of the product value σ - .

[0119] For example, when positive weight charges are accumulated in the capacitor 13a, the potential of the positive charge output line 7a with respect to GND rises. Therefore, the potential of the positive charge output line 7a depends on the voltages corresponding to the positive weight values ​​w i+ The total charge of the product value σ + It should be noted that the potential of the positive charge output line 7a corresponds to the voltage held by the capacitor 13a.

[0120] Similarly, when negative weight charges are accumulated in capacitor 13b, the potential of negative charge output line 7b rises with reference to GND. Therefore, the potential of negative charge output line 7b depends on the voltages corresponding to the negative weight values ​​w i - The total charge of the product value σ - It should be noted that the potential of the negative charge output line 7b corresponds to the voltage held by the capacitor 13b.

[0121] The signal output unit 12 outputs a signal representing a product value (w i + *x i The multiplication-accumulation signal is, for example, a signal representing the total multiplication-accumulation result, which is all positive and negative weight values ​​w i With the signal value x i The sum of the product values ​​of . For example, the multiplication-accumulation result represented by the expression (Formula 1) can be written as follows.

[0122] [Formula 2]

[0123]

[0124] Here, N + and N - are the positive weight values ​​w i + The total number and negative weight value w i - As shown in the expression (Formula 2), the total multiplication-accumulation result can be calculated as the multiplication-accumulation result of the positive weight charge (i.e., the positive weight value w i + The product value (w i + *x i )) and the multiplication-accumulation result of the negative weight charge (i.e. the negative weight value w i - The product value (|w i - |*x i ) and the difference between the sum of ).

[0125] exist Figure 4In the example shown, the signal output unit 12 generates a signal representing the total multiplication-accumulation result, for example, as a multiplication-accumulation signal. Specifically, by appropriately referring to the charge accumulated in the accumulation unit 11 (capacitors 13a and 13b), the positive multiplication-accumulation result and the negative multiplication-accumulation result are calculated, and the total multiplication-accumulation result is calculated based on the difference between them. In addition, for example, two signals, a positive multiplication-accumulation signal and a negative multiplication-accumulation signal, which respectively represent the positive multiplication-accumulation result and the negative multiplication-accumulation result, can be generated as the multiplication-accumulation signal.

[0126] The method of referring to the charge accumulated in the accumulation unit 11 is not limited. As an example, a method of detecting the charge accumulated in one capacitor 13 will be described. Figure 2 In the case of the electric signal of the PWM method shown in A, charges each corresponding to the product value are accumulated in the capacitor 13 within the input period T. That is, before and after the input period T, accumulation of charges each corresponding to the product value does not occur.

[0127] For example, after the input cycle T ends, the capacitor 13 is charged at a predetermined charging speed. At this time, a comparator or the like is used to detect the timing at which the potential of the output line connected to the capacitor 13 reaches a predetermined threshold potential. For example, as more charge is accumulated at the beginning of charging, the time when the potential reaches the threshold potential becomes earlier. Therefore, the charge accumulated within the input cycle T (multiplication-accumulation result) can be expressed based on the timing. It should be noted that the charging speed can be expressed, for example, by the amount of charge per unit time, which can also be called a charging rate.

[0128] It should be noted that this threshold determination corresponds to increasing the voltage held by the capacitor 13 by charging and detecting the timing at which the threshold voltage is reached.

[0129] In use according to Figure 2 In the case of the electrical signal of the TACT method shown in B, since the ON level is maintained even after the input cycle T ends, the charge is accumulated in the capacitor 13. For this charge accumulation, the timing at which the potential of the output line connected to the capacitor 13 reaches a predetermined threshold potential is detected by using a comparator or the like. For example, as more charge is accumulated at the end of the input cycle T, the time when the potential reaches the threshold potential becomes earlier. Therefore, the charge accumulated within the input cycle T (the multiplication-accumulation result) can be expressed based on the timing.

[0130] It should be noted that this threshold determination corresponds to the timing at which the voltage held by the detection capacitor 13 reaches the threshold voltage.

[0131] For example, by performing such a threshold determination, the timing representing the multiplication-accumulation result is detected. Based on the detection result, a multiplication-accumulation signal of positive weighted charge, a multiplication-accumulation signal of negative weighted charge, or a total multiplication-accumulation signal is appropriately generated. In addition, each multiplication-accumulation result can be calculated, for example, by directly reading the potential of the capacitor 13 at the end of the input cycle T.

[0132] It should be noted that the voltage depending on the accumulated positive weight charge and the voltage depending on the accumulated negative weight charge can be amplified separately to generate a multiplication-accumulation signal. In addition, the multiplication-accumulation signal can be generated by amplifying the differential voltage between the voltage depending on the accumulated positive weight charge and the voltage depending on the accumulated negative weight charge. For example, a differential amplifier or the like having an arbitrary configuration can be provided in the neuron circuit 9.

[0133] In the present embodiment, the neuron circuit 9 is used as an output unit that accumulates the charges corresponding to the product values ​​generated by the plurality of multiplication units and outputs a multiplication-accumulation signal representing the sum of the product values ​​based on the accumulated charges. In addition, the capacitor 13a and the capacitor 13b are used as a positive charge accumulation unit and a negative charge accumulation unit. The neuron circuit 9 accumulates at least one of the positive weighted charges generated by the positive weighted multiplication unit and the negative weighted charges generated by the negative weighted multiplication unit, thereby outputting a multiplication-accumulation signal.

[0134] Furthermore, as will be described in detail later, in the present embodiment, a charging unit is configured, and the accumulating unit 11 (capacitor 13) in which the charge corresponding to the product value is accumulated is charged after the input period T. It should be noted that charging according to the present technology includes accumulating the charge in the capacitor 13 by a pulse signal maintaining an ON level in the case of using an electric signal according to the TACT method.

[0135] The signal output unit 12 functions as an output unit for outputting a multiplication-accumulation signal indicating the sum of product values ​​by performing threshold determination using a predetermined threshold value on the voltage held by the accumulation unit 11 after the charging unit starts charging. The signal output unit 12 outputs the multiplication-accumulation signal by performing threshold determination for each of the positive charge accumulation unit and the negative charge accumulation unit.

[0136] [Analog circuit based on PWM method]

[0137] Figure 5 is a schematic circuit diagram showing an example of an analog circuit according to the present embodiment. Figure 5 , an example of an analog circuit 3 according to the PWM method is shown. The analog circuit 3 is arranged to extend in a direction orthogonal to the plurality of input signal lines 6. Figure 5 In the example shown, a portrait and landscape configuration is used.

[0138] The analog circuit 3 includes a pair of output lines (a positive charge output line 7a and a negative charge output line 7b), a plurality of synaptic circuits (a plurality of multiplication units) 8, a neuron circuit 9, and a charging unit 15. Figure 5 In the example shown, the neuron circuit 9 includes an accumulation unit 11, a signal output unit 12, and switches 16a and 16b.

[0139] Each has the same signal value x i Pulse signals (PWM signals) of corresponding pulse widths are input to the plurality of input signal lines 6 as input signals in1 to in6. Figure 5 In the example shown, six input signal lines 6 are shown, but the number of input signal lines 6 is not limited. Input signals in1 to in6 are input within an input cycle T having a predetermined duration (see Figure 6 ).

[0140] The positive charge output line 7a outputs the signal value x i Multiply by the positive weight w i + The obtained product value (w i + *x i ) corresponding to the positive weight charge. The negative charge output line 7b outputs the signal value x i Multiply by the negative weight w i - The obtained product value (|w i - |*x i ) corresponding to the negative weighted charge. In this embodiment, a pair of output lines 7 corresponds to one or more output lines.

[0141] A plurality of synapse circuits 8 are provided to be associated with the plurality of input signal lines 6, respectively. In this embodiment, one synapse circuit 8 is provided in one input signal line 6. Each of the plurality of synapse circuits 8 includes a resistor 17 connected between a corresponding input signal line 6 among the plurality of input signal lines 6 and any one of the positive charge output line 7a or the negative charge output line 7b. The resistor 17 may have a nonlinear characteristic and may have a function of preventing current from flowing back. Corresponding to the product value (w i + *x i )(or(|w i - |*x i )) is output to the output line 7a (or 7b) to which the resistor 17 is connected.

[0142] For example, in order to convert the signal value x in each synaptic circuit 8 i Multiply by the positive weight wi + , the resistor 17 is connected between the input signal line 6 and the positive charge output line 7a and causes the positive charge output line 7a to output positive weighted charges. Figure 5 In the example shown, the synapse circuit 8 to which the input signals in1, in3, and in6 are input is a synapse circuit 8a configured as a positive weight multiplication unit that generates positive weight charges. It can also be said that the synapse circuit 8a is a multiplication unit to which positive weights are set.

[0143] In order to convert the signal value x into i Multiply by the negative weight w i - , the resistor 17 is connected between the input signal line 6 and the negative charge output line 7b and causes the negative charge output line 7b to output negative weighted charges. Figure 5 In the example shown, the synapse circuit 8 to which the input signals in2, in4, and in5 are input is a synapse circuit 8b configured as a negative weight multiplication unit that generates negative weight charges. It can also be said that the synapse circuit 8b is a multiplication unit with a negative weight set.

[0144] Hereinafter, the synaptic circuits 8a and 8b will sometimes be referred to as the positive weight multiplication unit 8a and the negative weight multiplication unit 8b. In addition, the resistor 17 connected between the input signal line 6 and the positive charge output line 7a will sometimes be referred to as the positive resistor 17a. In addition, the resistor 17 connected between the input signal line 6 and the negative charge output line 7b will sometimes be referred to as the negative resistor 17b.

[0145] It should be noted that will have the same weight value w as will be set i A resistor of a corresponding resistance value is used as the resistor 17. That is, the resistor 17 is used to define the weight value w in the arithmetic device 100 that performs the multiplication-accumulation operation at the analog circuit 3. i components.

[0146] For example, a fixed resistor element, a variable resistor element, a MOS transistor operating in a subthreshold region, or the like is used as the resistor 17. For example, power consumption can be reduced by using a MOS transistor operating in a subthreshold region as the resistor 17. Of course, any other resistor may be used.

[0147] The accumulating unit 11 accumulates the product values ​​(w i *x i In this embodiment, two capacitors 13a and 13b are provided as the accumulation unit 11.

[0148] Capacitor 13a is connected to positive charge output line 7a via switch 16a to accumulate positive weight charge generated by synaptic circuit 8a. Capacitor 13b is connected to negative charge output line 7b via switch 16b to accumulate negative weight charge generated by synaptic circuit 8b.

[0149] The charging unit 15 accumulates the product value (w i *x i ) is charged by the accumulating unit 11 of the charge sum corresponding to the charge sum. In this embodiment, the charging unit 15 includes a signal source (not shown), a charging line 19 and two resistors 20.

[0150] The charging line 19 is arranged in parallel with the input signal line 6. The resistor 20a of the two resistors 20 is connected between the charging line 19 and the positive charge output line 7a. The other resistor 20b is connected between the charging line 19 and the negative charge output line 7b. Therefore, the charging line 19 is connected to the capacitor 13a via the resistor 20a. In addition, the charging line 19 is connected to the capacitor 13a via the resistor 20b.

[0151] Resistors 20a and 20b having the same resistance value are used. Although the same resistor is generally used, different types of resistors having the same resistance value may be used. The specific configuration of resistors 20a and 20b is not limited, and various configurations such as in resistor 17 may be used. In addition, resistors the same as resistor 17 or resistors different from resistor 17 may be used as resistors 20a and 20b.

[0152] The charging is performed after the input period T ends. In the present embodiment, the charging signal CH is input via the charging line 19 after the input period T ends. That is, the same charging signal CH is supplied to the capacitors 13a and 13b from the charging line 19. Therefore, charges based on the high level value of the charging signal CH and the resistance values ​​of the resistors 20a and 20b are accumulated in the capacitors 13a and 13b.

[0153] Since the resistance values ​​of the resistors 20a and 20b are equal to each other, the capacitors 13a and 13b are charged at the same charging speed. By charging the charging unit 15, the potential V of the positive charge output line 7a is + (the voltage held by capacitor 13a) and the potential V of negative charge output line 7b - (The voltage held by capacitor 13b) is both stepped up.

[0154] After the charging unit 15 starts charging, the signal output unit 12 performs threshold determination on the voltage held by the accumulating unit 11 based on a predetermined threshold, thereby outputting a value indicating the product value (w i *x iIn this embodiment, two comparators 22a and 22b and a signal generating unit 23 are provided as the signal output unit 12.

[0155] Comparator 22a detects the timing when the voltage held by capacitor 13a exceeds a predetermined threshold. It should be noted that the magnitude of the voltage held by capacitor 13a is determined by the total amount of positive weighted charges accumulated in capacitor 13a and the charge amount (charging speed x time).

[0156] Comparator 22b detects the timing when the voltage held by capacitor 13b exceeds a predetermined threshold. It should be noted that the magnitude of the voltage held by capacitor 13b is determined by the total amount of negative weight charges accumulated in capacitor 13b and the charge amount (charging speed×time).

[0157] It should be noted that in the present embodiment, a multiplication-accumulation signal is output by threshold determination for each of the capacitors 13a and 13b having a common threshold value θ. Therefore, the efficiency and speed of the operation can be improved. Of course, a multiplication-accumulation operation is also possible when different threshold values ​​are used.

[0158] The signal generating unit 23 outputs a signal indicating the product value (w i *x i In other words, the signal generating unit 23 outputs a multiplication-accumulation signal based on the timing when the voltage held by the capacitor 13a reaches the threshold value θ and the timing when the voltage held by the capacitor 13b reaches the threshold value θ.

[0159] In this embodiment, a PMW signal which is a pulse signal whose pulse width has been modulated is output as a multiplication-accumulation signal. The specific circuit configuration and the like of the signal generating unit 23 are not limited and can be arbitrarily designed.

[0160] Figure 6 and Figure 7 Is used to describe Figure 5 3 is a diagram of an example of calculation of a multiplication-accumulation signal of the analog circuit 3 shown in . In this embodiment, based on the positive weight charge multiplication-accumulation result based on the positive weight charge accumulated in the capacitor 13a and the negative weight charge multiplication-accumulation result based on the negative weight charge accumulated in the capacitor 13b, a signal representing the total multiplication-accumulation result including positive and negative values ​​is calculated.

[0161] The calculation of the multiplication-accumulation result of the positive weighted charge and the calculation of the multiplication-accumulation result of the negative weighted charge are the same process. Figure 6A method of calculating a multiplication-accumulation result from the charge accumulated in the capacitor 13 without distinguishing between positive and negative values ​​(multiplication-accumulation method) is described.

[0162] Will describe Figure 6 Parameters described in. "t" represents time. "T" represents each of the input cycle and the output cycle. "t n " indicates the end timing of input cycle T, "t m " indicates the end timing of the output cycle T.

[0163] In this embodiment, the duration of the input cycle T and the duration of the output cycle T are set equal to each other. In addition, the output cycle T starts at the end timing t of the input cycle T. n Therefore, the end timing of the input cycle T is t n Corresponds to the start timing of the output cycle T.

[0164] Furthermore, in the present embodiment, the charging unit 15 performs charging in the output period T following the input period T. Therefore, the output period T corresponds to the charging period.

[0165] “θ” represents a common threshold value used for threshold value determination performed by the signal output unit 12 (comparator 22 ).

[0166] “S i (t)” represents the input signal (PWM signal) input to the i-th input signal line 6. “τ i ” indicates the input signal S i (t) is the pulse width. i (t)” means Figure 5 The amount of change in the internal state (potential) in each synaptic circuit 8 is shown. i ” represents the weight value and is represented by Figure 5 The resistance value of the resistor 17 is shown as defined.

[0167] “V n (t)” means “P i (t)” and corresponds to the total amount of charge accumulated in capacitor 13. n (t)” represents a multiplication-accumulation signal (PWM signal), which represents the multiplication-accumulation result. n " represents the pulse width of the multiplication-accumulation signal to be output. Specifically, "τ n " represents the period from the timing when the voltage held by the capacitor 13 exceeds the threshold value θ in the output cycle T to the end timing t of the output cycle T. m The value corresponding to the duration.

[0168] "CH(t)" is a charging signal input to the charging line 19 in the output period T as a charging period. Figure 6 As shown, in this embodiment, a pulse signal that becomes ON level during the output period T is input as a charging signal. Therefore, the pulse width τ of the charging signal CH Equal to the pulse width of the charging signal within the output period T.

[0169] In this example, the switches 16 a and 16 b are provided, and in particular, the reduction in power consumption can be improved by disconnecting the output line via the switches.

[0170] Here, as shown in the following expression, the input value (signal value) x i By the input signal S i (t) is the pulse width τ i Duty cycle R relative to input period T i (=τ / T) is given.

[0171] [Formula 3]

[0172]

[0173] Figure 5 The synaptic circuit 8 shown in FIG. 8 generates the signal value x by i Multiply by the weight w i Specifically, the resistance of resistor 17 is at a constant slope w i Increase the internal state (potential).

[0174] The end timing t of the input cycle T n The change amount P of the internal potential of each synaptic circuit 8 when i (t n ) is given by the following expression. It should be noted that the input signal S i The high level value of (t) is set to 1.

[0175] [Formula 4]

[0176] P i (t n )=w i R i T=w i x i T

[0177] The total amount of charge V accumulated in capacitor 13 n (t n ) is Pi(t n ), and is therefore given by the following expression.

[0178] [Formula 5]

[0179]

[0180] At the end timing t of the input cycle T n When the output period T is equal to the charging period, the charging unit 15 (current source 18) starts charging. As described above, in this embodiment, the output period T corresponds to the charging period.

[0181] By being charged by the charging unit 15, the internal potential of each synaptic circuit 8 is increased from the end timing t of the input cycle T to the internal potential t of the synaptic circuit 8. n The charging speed α is determined by the high level value of the charging signal and the resistance value of the resistor 20. It should be noted that Figure 6 The diagram omits the change in the internal potential of each synapse circuit 8 within the output cycle T (the value of the internal potential at the end of the input cycle T is schematically shown by a dotted line).

[0182] A pulse signal whose high level value is equal to the high level value of the input signal can be used as a charging signal. Of course, a pulse signal whose high level value is different from the high level value of the input signal can also be used. Any other electrical signal different from the input signal can be used as a charging signal.

[0183] The time interval from the timing when the voltage held by the capacitor 13 exceeds the threshold value θ in the output cycle T to the end timing t of the output cycle T is generated. m The duration of the multiplication-accumulation signal (PWM signal) corresponds to the pulse width τn.

[0184] Assume that the pulse width τ of the multiplication-accumulation signal n The duty cycle of the output period T is R n (=τ n / T), R n It is given by the following expression. It should be noted that the threshold value θ is equal to or greater than the total charge V n (t n ).

[0185] [Formula 6]

[0186]

[0187] Therefore, the signal value x i With weight value w i The product value obtained by multiplication (w i *x i The multiplication-accumulation result obtained by adding ) is given by the following expression.

[0188] [Formula 7]

[0189]

[0190] That is, the multiplication-accumulation result is obtained by n =α·(τ n / T) minus a constant defined by the charging speed α, the threshold θ, and the output cycle T. In this way, a multiplication-accumulation signal indicating a multiplication-accumulation result can be output based on the timing at which the voltage held by the accumulation unit 11 exceeds the threshold θ in the output cycle T having a predetermined duration.

[0191] Figure 7 is a schematic diagram showing an example of calculation of a multiplication-accumulation signal representing a total multiplication-accumulation result based on multiplication-accumulation results of both positive weighted charges and negative weighted charges. Figure 7 In the example, the multiplication-accumulation signal representing the multiplication-accumulation result of the positive weighted charge is denoted by “S n + (t)”, and its pulse width is represented by “τ n + In addition, the multiplication-accumulation signal representing the multiplication-accumulation result of the negative weight charge is represented by “S n - (t)”, and its pulse width is represented by “τ n - In addition, the multiplication-accumulation signal representing the total multiplication-accumulation result is represented by “S n (t)”, and its pulse width is represented by “τ n "express.

[0192] At the end timing t of the input cycle T n The total amount of positive weighted charge V accumulated in capacitor 13a at n + (t n ) is given by the following expression. It should be noted that w i + Indicates a positive weight value.

[0193] [Formula 8]

[0194]

[0195] At the end timing t of the input cycle T n The total amount of negative weight charge V accumulated in capacitor 13b at n - (t n ) is given by the following expression. It should be noted that w i - Represents a negative weight value.

[0196] [Formula 9]

[0197]

[0198] Multiply-accumulate signal S n + (t) is R n + (=τ n + / T), will be passed through the signal value x i Multiply by the positive weight w i + The obtained product value (w i + *x i ) is given by the following expression. It should be noted that assuming that the threshold value θ is equal to or greater than the total amount of positive weighted charge V n + (t n ).

[0199] [Formula 10]

[0200]

[0201] In the negative multiplication-accumulation signal S n - The duty cycle of (t) is R n - (=τ n - / T) will be converted to the input value x i Multiply by the negative weight w i - The obtained product value (|w i - |*x i ) is given by the following expression. It should be noted that the charging speed α and the threshold value θ are equal to the values ​​used in the expression (Formula 10). In addition, it is assumed that the threshold value θ is equal to or greater than the total amount of negative weighted charge V n - (t n ).

[0202] [Formula 11]

[0203]

[0204] Therefore, using the above expression (Formula 2), the total multiplication-accumulation result is given by the following expression.

[0205] [Formula 12]

[0206]

[0207] That is, the total multiplication-accumulation result is obtained by the charging speed α, the multiplication-accumulation signal Sn + (t) is the pulse width τ n + , multiplication-accumulation signal S n - (t) is the pulse width τ n - And the output period T is obtained. That is, the multiplication-accumulation result can be easily calculated based on the timing detected by the comparator 22a and the timing detected by the comparator 22b.

[0208] like Figure 7 As shown, it is easy to output a pulse with a width of "τ n The multiplication-accumulation signal "S n (t)” as a multiplication-accumulation signal representing the total multiplication-accumulation result. It should be noted that the multiplication-accumulation signal S can be determined n + (t) is the pulse width τ n + Sum multiplication-accumulation signal S n - (t) is the pulse width τ n - Which of the two is larger? n + The multiply-accumulate signal "S n (t)” can be output as a positive multiplication-accumulation signal, and the pulse width τ n - The multiply-accumulate signal "S n (t)" can also be output as a negative multiplication-accumulation signal. It is used to compare the pulse width τ n + and pulse width τ n - The circuit can be realized by appropriately using an AND circuit, a NOT circuit, etc.

[0209] It is also possible to configure such that, in the case of using a ReLU function (ramp function) or the like, for example, when a positive multiplication-accumulation signal "S n (t)”, the signal is output as is, and when the negative multiplication-accumulation signal “S n (t)”, the output is 0.

[0210] When the charging speed α and the threshold value θ are set, α=θ / T is set for the output period T. Therefore, the constants determined by the charging speed α, the threshold value θ, and the output period T included in the expressions (Formula 6), (Formula 7), (Formula 10), and (Formula 11) can be set to zero, and the processing can be simplified.

[0211] For example, the high level value of the charging signal and the resistance value of the resistor 20 are appropriately set to adjust the charging speed α. The threshold θ is set based on the duration of the input period T. Therefore, an advantageous effect can be exerted.

[0212] [Simulation circuit based on TACT method]

[0213] Figure 8 is a schematic circuit diagram showing an example of an analog circuit 3 according to the TACT method. i At corresponding timings, pulse signals (TACT signals) are input to the plurality of input signal lines 6 as input signals in1 to in6.

[0214] Here, if Figure 2 As shown in B, the input rises to a timing corresponding to the input value and maintains a continuous pulse signal at the ON level. Regarding the pulse signal, the duration of the ON time relative to the input cycle T corresponds to the input value in the input cycle T. In the following, the duration of the ON time in the input cycle T is sometimes referred to as the pulse width in the input cycle T.

[0215] At the timing of the input cycle T, the charge accumulated in the capacitor 13a is equal to the positive weight value w i + The product value corresponds to the sum of positive weighted charges σ + Similarly, the charge accumulated in capacitor 13b is equal to the negative weight value w i - The product value corresponds to the sum of negative weight charges σ - .

[0216] Since the ON level of the electric signal is maintained even after the input cycle T ends, charge is accumulated in capacitors 13a and 13b. Based on the timing when the voltage held by capacitor 13a exceeds threshold θ, a multiplication-accumulation signal (PWM signal) representing the multiplication-accumulation result of positive weighted charge is generated.

[0217] In addition, based on the timing when the voltage held by capacitor 13b exceeds threshold value θ, a multiplication-accumulation signal (PWM signal) representing the multiplication-accumulation result of negative weighted charge is generated. A multiplication-accumulation signal representing the total multiplication-accumulation result can be generated based on these positive and negative multiplication-accumulation signals.

[0218] exist Figure 8 In the illustrated analog circuit 3 according to the TACT method, the output period T corresponds to the charging period. In addition, the input signals in1 to in6 input to the plurality of input signal lines 6 in the output period T correspond to the charging signals.

[0219] therefore, Figure 8In the analog circuit 3 according to the TACT method shown in the figure, the same charging signal is supplied to the capacitors 13a and 13b via the plurality of input signal lines 6. Although not shown in the figure, the configuration for inputting the input signals in1 to in6 to the plurality of input signal lines 6 during the output period T corresponds to the charging unit 15. Therefore, the configuration for inputting the input signals in1 to in6 also serves as the charging unit 15. Figure 8 As shown, the plurality of input signal lines 6 themselves can also be regarded as part of the charging unit 15 .

[0220] Here, the inventors have considered the time constant as a parameter associated with the charge accumulation of the capacitor 13 in the input period T and the output period (charging period) T. In the above, the charge accumulation in the input period T and the output period T is approximated as a linear change and the “slope w i ” and “slope α” to describe, such as Figure 6 Of course, based on this approximation, it is possible to realize an analog type arithmetic device 100 capable of accurately executing predetermined arithmetic processing including multiplication-accumulation operations.

[0221] On the other hand, considering that the charge (potential) of capacitor 13 is Figure 5 and Figure 8 The circuit configuration of the analog circuit 3 shown determines that the time constant is accumulated in the input period T and the output period (charging period) T. Therefore, the inventors believe that by appropriately designing the circuit configuration, more accurate multiplication-accumulation operations can be achieved based on accumulating charges according to the time constant.

[0222] Hereinafter, the charge (electrical potential) of the capacitor 13 will sometimes be described as the (charge) electric potential of the output line 7 for outputting the charge to the capacitor 13 .

[0223] The inventors have found a configuration that makes the time constant of the output line 7 independent of the number of resistors 17 provided between the output line 7 and the plurality of input signal lines 6 .

[0224] First, it is assumed that the capacitors 13a and 13b functionally include parasitic capacitance (not shown) generated in the output lines 7a and 7b. In this case, the minimum value of the capacitance that the capacitors 13a and 13b can take is the parasitic capacitance generated in the output line 7. For example, even in the case where the capacitor 13 is not provided, charges can be accumulated based on the parasitic capacitance generated in the output lines 7a and 7b, and a multiplication-accumulation signal can be generated based on the threshold determination. The same applies to Figure 5 The simulation circuit of the PWM method is shown in Figure 3.

[0225] The time constant of the output line 7 changes continuously according to the number of input signals inputted sequentially with time and the number of resistors 17 (on-resistance) in a state capable of transmitting the signal to the output line 7. Here, emphasis is placed on the time constant at the end of the input cycle T. In the analog circuit 3 of the TACT method according to the present embodiment, a signal is inputted to all input signal lines 6 at the end of the input cycle T. Therefore, the number of input signals at the end of the input cycle T takes a maximum value and a constant value. As a result, the time constant at the end of the input cycle T changes continuously according to the number of on-resistances.

[0226] Here, the resistance value of the resistor 17 is set to the same resistance value R. In other words, a binary connection configuration is adopted. In addition, the parasitic capacitance of each synapse circuit 8 is designed to be a constant capacitance C. Since the resistor 17 is connected in parallel to one output line 7, the combined resistance is R / N in the case where N resistors 17 are connected (the number of on-resistances is N). On the other hand, since the number of synapse circuits 8 is N, which is equal to the number of resistors 17, the combined capacitance is NC.

[0227] For example, in the case where the capacitor 13 is not provided, a multiplication-accumulation signal is generated based on the parasitic capacitance of each synaptic circuit 8. In this case, the value of the combined resistance×combined capacitance is RC regardless of the number of resistors 17 (the number of on-resistances), and therefore, the time constant of the output line 7 at the end of the input cycle T is also RC regardless of the number of resistors 17.

[0228] In the case where the capacitor 13 is mounted, the capacitance of the capacitor 13 is set to a value obtained by multiplying a predetermined constant C0 by the number of resistors 17 (the number of on-resistances) (the number of resistors 17×C0). Therefore, the time constant is R / N×(NC+NC0)=R×(C+C0), and is independent of the number of resistors 17. Therefore, the time constant can be made constant regardless of the number of resistors 17.

[0229] Therefore, the potential V of each output line 7 at the end of the input period T can be approximated by the following expression.

[0230] [Formula 13]

[0231]

[0232] Fig. 9 is a schematic graph for describing the potential V of each output line 7 at the end of the input cycle T. Referring to the expression (Formula 13) and Fig. 9 Describes the potential V of each output line 7 at the end of the input period T. It should be noted that Fig. 9 The time constant curve in the graph of is a curve corresponding to the expression (Formula 13).

[0233] “Vc” represents a constant and is a value corresponding to a converged value of the potential after a time equal to or longer than the time constant has passed.

[0234] “t ave ” represents the average value of the pulse width of the pulse signal input to the input signal line 6 within the input period T.

[0235] It should be noted that the change in charge of each output line 7 until the end of the input period T is not always in accordance with Fig. 9 The time constant curve shown occurs. It is found that the potential V of each output line 7 at least at the end of the input period T can be approximated by the expression (Formula 13).

[0236] On the other hand, in the output cycle (charging period) T, the input signals in1 to in6 (charging signals) at the ON level are input to all the input signal lines 6. Therefore, it can be considered that the charge change in the output cycle (charging period) T is based on Fig. 9 The time constant curves shown are carried out.

[0237] Here, it is assumed that the end timing t of the input cycle T n The potential V of each output line 7 at the time of n In addition, from the end timing t of the input cycle T n The time from the start of the output (the time in the output cycle T) is set to t. Then, the potential “V out ” can be approximated by the following equation.

[0238] [Formula 14]

[0239]

[0240] Here, if Fig. 9 As shown, the input period T and the threshold value θ are determined according to the time constant curve corresponding to the expression (Formula 13). That is, the input period T is substituted into the "t ave " is set to the threshold value θ. Therefore, when the maximum pulse with the largest pulse width within the input cycle T is input to all input signal lines 6, at the end timing of the input cycle T (the start timing of the output cycle T), the potential of the output line 7 exceeds the threshold value.

[0241] On the other hand, in the case where a pulse having a pulse width of 0 within the input cycle T is input to all the input signal lines 6, the potential of the output line 7 exceeds the threshold value at the end timing of the output cycle T. Therefore, the multiplication-accumulation signal can be accurately calculated with high resolution within the output cycle T. That is, by setting the threshold value θ based on the duration of the input cycle T, an advantageous effect can be exhibited.

[0242] like Fig. 9 As shown, threshold determination is performed on each of the capacitors 13a and 13b based on the threshold θ. Therefore, the “t ave " as the pulse width "τ n The multiplication-accumulation signal "S n (t)". ​​Therefore, it is found that the multiplication-accumulation signal "S n The pulse width “τ (t)” n " can also be approximated by the expression (Formula 13).

[0243] Regardless of how the number of resistors 17 for connecting the input signal line 6 and the positive charge output line 7a (i.e., the number of positive weight multiplication units) and the number of resistors 17 for connecting the input signal line 6 and the negative charge output line 7b (i.e., the number of negative weight multiplication units) are combined in each analog circuit 3, the potential V of the positive charge output line 7a is + and the potential V of the negative charge output line 7b - accomplish Fig. 9 The multiply-accumulate operation shown.

[0244] Therefore, if Figure 7 As shown, the multiplication-accumulation signal S n + (t) is the pulse width τ n + and the multiplication-accumulation signal S n - (t) is the pulse width τ n - To calculate the multiplication-accumulation signal "S" representing the total multiplication-accumulation result n (t)”.

[0245] It should be noted that even in the case of adopting other configurations, the analog circuit 3 is designed so that the time constant of the positive charge output line 7a is equal to the time constant of the negative charge output line 7. Therefore, the potential V + and the potential V of the negative charge output line 7b - Achieved Fig. 9 The multiply-accumulate operation shown.

[0246] Of course, the present technique is not limited to the case of binary connection configurations, where the positive weight value w i + and negative weight w i - The absolute value of is fixed to the same value.

[0247] For example, a positive weight value w i + and negative weight w i - The absolute value of is multi-valued. That is, the positive weight value w i + and negative weight w i - The absolute value of is set to any one of a plurality of values ​​different from each other. Alternatively, a positive weight value w is randomly set i + and negative weight w i - The absolute value of .

[0248] Also in this case, the analog circuit 3 is designed so that the time constant of the positive charge output line 7a is equal to the time constant of the negative charge output line 7. Therefore, the potential V + and the potential V of the negative charge output line 7b - Achieved Fig. 9 The multiply-accumulate operation shown.

[0249] In the present disclosure, the time constant of the output line 7 is included in the time constant associated with outputting the charge corresponding to the product value to the output line 7 through the plurality of synapse circuits 8. The time constant of the positive charge output line 7a is included in the time constant associated with outputting the positive charge to the positive charge output line 7a through the plurality of positive weight multiplication units 8a. The time constant of the negative charge output line 7b is included in the time constant associated with outputting the weighted charge to the negative charge output line 7b through the plurality of weight multiplication units 8b.

[0250] Next, consider Figure 5 The analog circuit 3 according to the PWM method is shown. Figure 5 In the illustrated analog circuit 3 according to the PWM method, input signals in1 to in6 are input to the plurality of input signal lines 6 within an input period T. Then, a charging signal CH is input via the charging line 19 within an output period T.

[0251] Here, the potential V of the output line 7 at the end of the input cycle T can be approximated by the expression (Formula 13) as in the TACT method. That is, Fig. 9As shown, the time constant curve can be used to approximate the time constant of the output line 7. Thereafter, the resistance values ​​of the charging line 19 and the resistor 20 are designed so that the charging unit 15 is charged according to the same time constant curve. Fig. 9 The multiply-accumulate operation shown.

[0252] For example, in Figure 5 In the configuration shown, the combined resistance of the positive resistor 17a and the resistance value of the resistor 20a connected to the charging line 19 are made equal. Therefore, a positive charge output line 7a is achieved. Fig. 9 In addition, the combined resistance of the negative resistor 17b and the resistance value of the resistor 20b connected to the charging line 19 are made equal. Therefore, the negative charge output line 7b is realized. Fig. 9 The multiply-accumulate operation shown.

[0253] For example, the analog circuit 3 is designed so that the time constant of the positive charge output line 7a and the time constant of the negative charge output line 7b are equal in the input period T. Then, the combined resistance of the positive resistor 17a and the resistance value of the resistor 20a are made equal, and the combined resistance of the negative resistor 17b and the resistance value of the resistor 20b are made equal.

[0254] Therefore, according to the potential V relative to the positive charge output line 7a + and the potential V of the negative charge output line 7b - The same time constant is achieved Fig. 9 Therefore, the average value of the pulse widths of the corresponding pulse signals in the input period T can be accurately generated and output as the pulse width "τ n The multiplication-accumulation signal "S n (t)”.

[0255] Of course, the application of this technology is not limited to achieving Fig. 9 As the analog circuit 3 according to the PWM method and the analog circuit 3 according to the TACT method, other configurations and other multiplication-accumulation operations may be performed. In any case, the result of the multiplication-accumulation operation may be based on the potential V of the positive charge output line 7a (the voltage held in the capacitor 13a). + and the potential of the negative charge output line 7b (the voltage held in the capacitor 13b) V - To obtain.

[0256] In the present embodiment, the analog circuit 3 according to the PWM method and the analog circuit 3 according to the TACT method each include a plurality of input signal lines 6 , a plurality of synapse circuits 8 , an accumulation unit 11 , a charging unit 15 , and a signal output unit 12 .

[0257] The accumulation unit 11 includes a capacitor 13a capable of accumulating positive weight charges generated by the synapse circuit (positive weight multiplication unit) 8a and a capacitor 13b capable of accumulating negative weight charges generated by the synapse circuit (negative weight multiplication unit) 8b.

[0258] The charging unit 15 charges the capacitors 13a and 13b after the input period T. The signal output unit 12 may output a multiplication-accumulation signal by thresholding each of the capacitors 13a and 13b using a predetermined threshold. It should be noted that the predetermined threshold may be set based on the duration of the input period.

[0259] Figures 10 to 13 are schematic diagrams each showing an example of the configuration of the arithmetic device 100 .

[0260] Figures 10 to 13 The arithmetic device 100 shown includes a plurality of input signal lines 6 and a plurality of analog circuits 3 connected in parallel to the plurality of input signal lines 6. By adopting such a configuration, electric signals can be input in parallel to each analog circuit 3, and the arithmetic processing speed can be increased. Therefore, excellent operation performance can be exhibited.

[0261] exist Fig.10 and Fig.11 In the arithmetic device 100 shown, reference is made to Figures 5 to 7 The analog circuit 3 according to the PWM method described is arranged as a plurality of analog circuits 3. Fig.12 and 13 In the arithmetic device 100 shown, reference is made to Figure 8 and 9 The analog circuit 3 according to the TACT method is described as being arranged as a plurality of analog circuits 3 .

[0262] In the present embodiment, the charging unit 15 performs charging in a common charging mode on a plurality of analog circuits 3. In addition, a common threshold is set as a predetermined threshold for threshold determination of the signal output unit 12 in the neuron circuit 9. That is, charging is performed in the same charging mode in each analog circuit 3 and threshold determination is performed using the same threshold.

[0263] In the analog circuit 3, a common charging mode is performed on each of the capacitors 13a and 13b. That is, charging is performed in the common charging mode on a plurality of capacitors 13a and 13b included in the plurality of analog circuits 3. Then, threshold determination is performed at the plurality of analog circuits 3 by using a common threshold, and a multiplication-accumulation signal is output.

[0264] The common charging mode may be charging in which a charging signal is supplied to each analog circuit 3 in a common charging cycle. In addition, the common charging mode also includes a mode in which the same charging signal is supplied to each analog circuit 3. In addition, the common charging mode includes charging at a common charging speed (charging rate), charging according to a common time constant, etc. Of course, the present technology is not limited thereto.

[0265] For example, Fig.10 and Fig.11 As shown, a common charging line 19 is arranged for a plurality of analog circuits 3. The charging line 19 is arranged in parallel with a plurality of input signal lines 6. A resistor 20a is connected between the charging line 19 of each analog circuit 3 and the positive charge output line 7a. A resistor 20b is connected between the charging line 19 of each analog circuit 3 and the negative charge output line 7b.

[0266] The charging signal that becomes the ON level during the output period (charging period) T is input via the charging line 19. Therefore, the same charging signal can be provided in the common charging period. All resistors having the same resistance value are arranged as resistors 20a and 20b. Therefore, charging can be performed at a common charging speed and a common charging rate.

[0267] For example, it is assumed that charging is performed at a common charging speed in a common charging cycle. In this case, the potential of the positive charge output line 7a and the potential of the negative charge output line 7b of each analog circuit 3 rise according to the charging speed α, as shown in FIG. Figure 6 shown.

[0268] Therefore, if Figure 7 As shown, the multiplication-accumulation signal S in each analog circuit 3 can be n + (t) is the pulse width τ n + and the multiplication-accumulation signal S n - (t) is the pulse width τ n - To calculate the multiplication-accumulation signal "S" representing the total multiplication-accumulation result n (t)”.

[0269] Furthermore, each analog circuit 3 and charging unit 15 are designed so that the time constant of each output line 7 (positive charge output line 7a or negative charge output line 7b) in the output period T is a common value. In this case, charging according to the common time constant can be achieved.

[0270] Each analog circuit 3 is designed so that the time constant of the positive charge output line 7a and the time constant of the negative charge output line 7b in the input cycle T are equal in each of the plurality of analog circuits 3 and so that the value of the time constant is a common value in all analog circuits 3. Then, the charging unit 15 is designed so that the time constant of the positive charge output line 7a and the time constant of the negative charge output line 7b in the output cycle T are equal to the time constant in the input cycle T. Therefore, the charging unit 15 is realized in each analog circuit 3. Fig. 9 It should be noted that the threshold is determined according to the time constant curve based on the input period T and is set as a common threshold.

[0271] In addition, if Fig.12 and Fig.13 As shown, the input signal is input so as to maintain the ON state in the output period T. Therefore, charging in which the same charging signal is supplied during the common charging period is performed.

[0272] In addition, each analog circuit 3 and the charging unit are designed so that the time constant of each output line 7 (positive charge output line 7a, negative charge output line 7b) is a common value. In this case, charging according to the common time constant can be achieved. Therefore, it is possible to achieve in each analog circuit 3 Fig. 9 It should be noted that the threshold is determined based on the input period T according to the time constant curve and is used as a common threshold.

[0273] Here, the inventors also considered the output of the multiplication-accumulation signal of the analog circuit 3 when performing charging according to the common charging mode and when performing threshold determination using the common threshold. Then, the inventors found that the accuracy of the multiplication-accumulation operation is improved by appropriately outputting the multiplication-accumulation signal from each analog circuit 3 in the common output period T. In other words, the inventors found that the accuracy of the multiplication-accumulation operation is improved by increasing the number of analog circuits that can output the multiplication-accumulation signal within the common output period T.

[0274] For example, suppose in Fig.10 and Fig.11 The arithmetic device 100 shown adopts a binary connection configuration. In the binary connection, the absolute values ​​of the positive weight value and the negative weight value are fixed to the same value. That is, the resistance values ​​of the resistors 17 are all fixed to the same value.

[0275] exist Fig.10 In the configuration shown, at each analog circuit 3, the sum of the number of positive resistors 17a and the number of negative resistors 17b is set to a common value (seven). Fig.10In the configuration shown, in multiple analog circuits 3, the value obtained by adding the sum of the positive weight values ​​set in the multiple synapse circuits 8 (hereinafter referred to as the positive sum value) and the sum of the absolute values ​​of the negative weight values ​​set in the multiple synapse circuits 8 (hereinafter referred to as the negative sum value) is a common value.

[0276] It should be noted that the value obtained by adding the positive sum value and the negative sum value corresponds to the sum of the absolute values ​​of the weight values ​​set in the plurality of synapse circuits 8 , and will be referred to as a weight sum value hereinafter.

[0277] exist Fig.11 In the configuration shown, at each analog circuit 3, the sum of the number of positive resistors 17a and the number of negative resistors 17b is not set to a common value. For example, the total number of resistors 17 can be set to any number among a plurality of numbers different from each other. Alternatively, the total number of resistors 17 can be set randomly.

[0278] Therefore, using Fig.11 In the configuration shown, in the plurality of analog circuits 3, the value (weight sum value) obtained by adding the positive sum value and the negative sum value is not a common value. For example, a configuration in which the weight sum value is any one of a plurality of values ​​different from each other can be implemented. Alternatively, a configuration in which the weight sum value is a random value can also be implemented.

[0279] It should be noted that in Fig.11 In the configuration shown, there is a synaptic circuit 8 in which both the positive resistor 17a and the negative resistor 17b are not provided. Such a synaptic circuit 8 can be said to be a multiplication unit corresponding to a term having a weight value of zero in a multiplication-accumulation operation.

[0280] about Fig.10 and Fig.11 The configuration shown in , assumes that a configuration other than binary connection is adopted. The absolute values ​​of the positive weight value and the negative weight value are multi-valued. Alternatively, the absolute values ​​of the positive weight value and the negative weight value are randomly set.

[0281] For the value (weighted sum value) obtained by adding the positive sum value and the negative sum value, any of a configuration in which the value is a common value, a configuration in which the value is any one of a plurality of values ​​different from each other, and a configuration in which the value is a random value can be realized.

[0282] For example, Fig.10 and Fig.11 The arithmetic device 100 shown in can be implemented using the resistor 17 having a multi-valued resistance value or the resistor 17 having a random resistance value as appropriate under the condition that the weight sum value is a common value or the weight sum value is any one of a plurality of values ​​different from each other.

[0283] The same applies to Fig.12 and Fig.13 For example, in the case of a binary connection configuration, using Fig.12 The configuration shown, the weights and the total values ​​are common values ​​in the plurality of simulation circuits 3. Fig.13 In the configuration shown, the weight sum value is not a common value in the plurality of analog circuits 3. For example, a configuration in which the weight sum value is any one of a plurality of values ​​different from each other can be realized. Alternatively, a configuration in which the weight sum value is a random value can also be realized.

[0284] about Fig.12 and Fig.13 The configuration shown in , assuming that a configuration other than binary connection is adopted. In this case, any of a configuration in which the weight sum value is a common value, a configuration in which the weight sum value is any value among multiple values ​​different from each other, and a configuration in which the weight sum value is a random value can be implemented.

[0285] Charging according to the common charging mode and threshold determination using a common threshold are performed on the multi-input×multi-output arithmetic device 100 having such various configurations, so that each analog circuit 3 appropriately outputs a multiplication-accumulation signal. To this end, the inventors focused on the weight sum value, the positive sum value, and the negative sum value in each analog circuit 3.

[0286] Then, the inventor newly designed a technique for performing charging based on the maximum value of the weight sum value among multiple analog circuits 3 and performing threshold determination using a threshold value based on the maximum value of the total weight sum value among multiple analog circuits 3. That is, the inventor newly designed a technique for performing charging based on the maximum value among the weight sum values ​​in multiple analog circuits 3 and performing threshold determination using a threshold value based on the maximum value.

[0287] For example, in Fig.10 and Fig.11 In the configuration shown, the combined resistance in the case of connecting all the resistors 17 included in the analog circuit 3 having the largest weight sum value in parallel is used as a common resistance value. Then, the resistance values ​​of all the resistors 20a and 20b are unified to the common resistance value. In this case, charging according to a common time constant is achieved within the output period T.

[0288] This charging corresponds to charging in which a time constant associated with outputting the charge corresponding to the product value to the output line 7 through the plurality of synapse circuits 8 whose weight sum value is the maximum value is used as a common time constant.

[0289] The threshold value is determined based on the input period T according to the time constant curve, which is defined by the resistance value. Therefore, each analog circuit 3 can output a multiplication-accumulation signal within the common output period T. Therefore, the accuracy of the multiplication-accumulation operation can be improved. It should be noted that the threshold value corresponds to a threshold value based on the maximum value.

[0290] Furthermore, the inventors have newly designed that charging is performed based on the maximum value among the positive sum values ​​and the negative sum values ​​in the plurality of analog circuits 3, and threshold determination is performed using a threshold value based on the maximum value among the positive sum values ​​and the negative sum values ​​in the plurality of analog circuits 3. That is, the inventors have designed that the positive sum value and the negative sum value of each analog circuit 3 are compared over all the plurality of analog circuits 3, charging is performed based on the maximum value among them, and threshold determination is performed using a threshold value based on the maximum value.

[0291] Here, the maximum value among the positive total values ​​and the negative total values ​​in the plurality of analog circuits 3 is defined as the maximum total value.

[0292] The positive weight charge or negative weight charge associated with the maximum sum value is defined as the maximum weight charge. For example, assuming that the positive sum value of one analog circuit 3 among the multiple analog circuits 3 is the maximum sum value. Then in the input cycle T, the positive charge output from the positive charge output line 7a in the analog circuit 3 is the maximum weight charge.

[0293] Alternatively, assuming that the negative sum value of one analog circuit 3 is the maximum sum value, then in the input period T, the negative charge output from the negative charge output line 7 b in the analog circuit 3 is the maximum weight charge.

[0294] It should be noted that the maximum weight charge is a parameter that is independent of the level of the input signal, etc. That is, no matter what signal is input as the input signal, the positive weight charge or negative weight charge (the maximum sum value) output from the positive weight output line or the negative weight output line is the maximum weight charge.

[0295] The positive charge output line or the negative charge output line from which the maximum weight charge is output is defined as the maximum charge output line.

[0296] exist Fig.12 and Fig.13 In the configuration shown, the combined resistance of the resistors 17 connected to the maximum charge output line is used as a common resistance value. Then, the resistance values ​​of all resistors 20a and 20b are unified to the common resistance value. In this case, charging according to a common time constant is achieved within the output period T. It should be noted that the combined resistance of the resistors 17 connected to the maximum charge output line is a parameter corresponding to the maximum sum value.

[0297] This charging corresponds to charging using the time constant associated with outputting the maximum weight charge to the maximum charge output line as a common time constant.

[0298] The threshold value is determined based on the input period T according to the time constant curve, which is defined by the resistance value. Therefore, each analog circuit 3 can output a multiplication-accumulation signal within the common output period T. Therefore, the accuracy of the multiplication-accumulation operation can be improved. It should be noted that the threshold value corresponds to a threshold value based on the maximum sum value.

[0299] It should be noted that the weight sum value of the analog circuit 3 assuming that all resistors 17 are connected to only one of the positive charge output line and the negative charge output line is the maximum value among the plurality of analog circuits 3. In this case, the maximum value of the weight sum value is also the maximum sum value, which is the maximum value of the positive sum value and the negative sum value. Therefore, charging is performed in the same charging mode, and the same threshold value is used for threshold determination.

[0300] exist Fig.12 and Fig.13 In the configuration shown, when the charging signal in the output period T is input to the output line to which all the resistors 17 included in the analog circuit 3 are connected in parallel, the threshold value is set according to the time constant curve, and the weight sum value of the analog circuit is the maximum value. It should be noted that in practice, there is not always an output line to which all the resistors 17 included in the analog circuit 3 are connected in parallel, whose weight sum value is the maximum.

[0301] By setting such a threshold value, a multiplication-accumulation signal can be output in each analog circuit 3 during the common output period T. Therefore, the accuracy of the multiplication-accumulation operation can be improved. It should be noted that the threshold value corresponds to a threshold value based on a maximum value.

[0302] In addition, in the case where a charging signal is input in the output period T, the threshold value is set to the maximum charge output line according to the time constant curve. Therefore, a multiplication-accumulation signal can be output in each analog circuit 3 during the common output period T. Therefore, the accuracy of the multiplication-accumulation operation can be improved. It should be noted that the threshold value corresponds to a threshold value based on the maximum sum value.

[0303] It should be noted that it is assumed that the weight sum value of the analog circuit 3 in which all resistors 17 are connected to only one of the positive charge output line and the negative charge output line is the maximum value among the plurality of analog circuits 3. In this case, the maximum value of the weight sum value is also the maximum sum value of the maximum values ​​of the positive sum value and the negative sum value. Therefore, the threshold determination is performed with the same threshold value.

[0304] Of course, the present technology is not limited to such charging modes and threshold settings. Any configuration and method for implementing charging according to a common charging mode and determining a threshold using a common threshold may be used. In addition, these configurations and methods may be used in conjunction with the above-mentioned Fig. 9 Combinations of configurations and methods of multiplication-accumulation operations shown.

[0305] Fig.14 is a schematic diagram showing an example of a configuration of a neural network. Fig.14 As shown, the neural network is implemented by performing multiple multiplication-accumulation operations, multiple normalization processes, and multiple pooling processes.

[0306] Here, the multiplication-accumulation operation corresponds to outputting a plurality of multiplication-accumulation results by the arithmetic device 100 including a plurality of analog circuits 3. Normalization processing is a process of normalizing input signals for input to the multiplication-accumulation operation of the next stage. Pooling processing is a process of reducing the number of input signals according to the number of inputs to the multiplication-accumulation operation of the next stage. Through normalization processing and pooling processing, processing can be simplified and processing time can be shortened.

[0307] It should be noted that in Fig.14 , a case where the arithmetic device 100 that performs each of the multiplication-accumulation operations 1 to 8 is composed of a plurality of analog circuits 3 designed with a common time constant is shown. That is, charging according to the common time constant is performed in each arithmetic device 100 in a common charging mode.

[0308] In each arithmetic device 100, the common input period T and the common threshold value θ are set based on the common time constant curve. Fig.14 In the example shown, different input cycles T and different thresholds are set for different arithmetic devices 100. The present technology is not limited thereto, and a common input cycle T and a common threshold θ may be set for all arithmetic devices 100.

[0309] Of course, the arithmetic device 100 is composed of analog circuits 3 each having another configuration and capable of performing multiplication-accumulation operations. In this case as well, efficient and high-speed arithmetic processing can be achieved by setting a common charging mode and a common threshold in each analog circuit 3.

[0310] As described above, in the arithmetic device 100 according to the present embodiment, a common charging mode is performed for one or more analog circuits 3 and a common threshold is set. Therefore, efficient and high-speed arithmetic processing can be achieved in the analog circuit that performs multiplication-accumulation operations. That is, by arranging multiple groups of multiple analog circuits 3 in parallel, it is possible to perform parallel operations simultaneously with one input, and achieve high-speed operations and efficient operations.

[0311] <Other embodiments>

[0312] The present technology is not limited to the above-described embodiments, and various other embodiments can be implemented.

[0313] Fig.15 is a schematic circuit diagram showing another example of the analog circuit 3 according to the PWM method. Fig.15 In the illustrated analog circuit 3 , two current sources 25 a and 25 b are provided as the charging unit 15 .

[0314] The current source 25a is connected to the side of the capacitor 13a connected to the positive charge output line 7a (the side opposite to GND) via the switch 16c. The current source 25b is connected to the side of the capacitor 13b connected to the negative charge output line 7b (the side opposite to GND) via the switch 16d.

[0315] exist Fig.15 In the analog circuit 3 shown, capacitors 13a and 13b are charged at the same rate by current sources 25a and 25b. Therefore, the potential V of the positive charge output line 7a is + (the voltage held by capacitor 13a) and the potential V of negative charge output line 7b - The specific configuration of the current source 25 is not limited and can be arbitrarily designed.

[0316] Even in the case of adopting such a configuration, charging according to a common charging mode and threshold determination using a common threshold value can be performed on one or more analog circuits 3. For example, in the case where a plurality of analog circuits 3 are arranged in parallel, charging according to a common charging mode and threshold determination using a common threshold value are performed. Therefore, efficient and high-speed arithmetic processing can be achieved.

[0317] Fig.16 is a schematic circuit diagram showing another example of the analog circuit 3 according to the PWM method. Fig.17 Is used to describe Fig.16 A diagram showing an example of the calculation of a multiply-accumulate signal of the analog circuit 3 is shown.

[0318] exist Fig.16 In the analog circuit 3 shown in FIG. 1 , the differential amplifier circuit 26 outputs a charge (V + -V - ), and the charge (V + -V - ) is stored in the capacitor 13 included in the accumulating unit 11. The specific structure of the differential amplifier circuit 26 is not limited and can be arbitrarily designed.

[0319] At the start timing of the input cycle T, switches 16a, 16b, and 16c are turned on and switch 16d is turned off. Then, the input signal is input during the input cycle T. The charge (V + -V - ) is accumulated in capacitor 13. It should be noted that Fig.17 The illustration of the charge accumulation state in the input period T is omitted.

[0320] At the end timing t of the input cycle T n , switch 16c is turned off and switch 16d is turned on. Then, Fig.17 As shown, at the end timing t of the input cycle T n Charging of the charging unit 15 (current source 25) is started.

[0321] Furthermore, the comparator 22 of the signal output unit 12 detects the timing at which the voltage held by the capacitor 13 exceeds the threshold value θ. Based on the detected timing, the signal generation unit 23 calculates the multiplication-accumulation signal (PWM signal) “S n (t)”.

[0322] Therefore, the difference between the total amount of positive weighted charge and the total amount of negative weighted charge (V + -V - ) corresponding to the charge threshold value to output the multiplication-accumulation signal "S n (t)". ​​In addition, charging according to a common charging mode and threshold determination using a common threshold value can be performed on one or more analog circuits 3. For example, when multiple analog circuits 3 are arranged in parallel, charging according to a common charging mode and threshold determination using a common threshold value are performed. Therefore, efficient and high-speed arithmetic processing can be achieved.

[0323] In the above description, the case where multiple analog circuits are arranged in parallel is mainly described. The technology of the present invention is not limited to this, and can also be applied to a single analog circuit. For example, the positive weight value accumulation unit and the negative weight accumulation unit are charged in a common charging mode. Then, a common threshold is used to determine the threshold of the positive weight charge and the negative weight charge. Therefore, efficient and high-speed arithmetic processing can be achieved.

[0324] In the above description, the case where a multiplication-accumulation signal is output based on the timing at which the voltage maintained by the accumulation unit increases beyond the threshold value has been illustrated. However, a configuration in which a multiplication-accumulation signal is output based on the timing at which the voltage maintained by the accumulation unit decreases beyond the threshold voltage can be adopted. For example, charging is performed in advance until the voltage of the capacitor used as the accumulation unit reaches a predetermined preset value. After the sum of the charges corresponding to the product values ​​of the signal value and the weight value is accumulated, the capacitor is discharged at a predetermined rate. In this case, a multiplication-accumulation signal can be output based on the timing at which the voltage maintained by the capacitor decreases beyond the threshold value. Of course, the present technology is not limited to this configuration. It should be noted that in the present disclosure, charging a capacitor with a negative charge includes discharging the capacitor.

[0325] In the above description, the case of using a pair of output lines has been described. The present invention technology is not limited to this, and three or more output lines may be provided. That is, the above-mentioned present invention technology can also be applied to the case of using one or more output lines of any number. For example, the multiplication unit includes a resistor, which is connected between the associated input line and any one of the one or more output lines and defines a weight value, and outputs a charge corresponding to the product value to the output line to which the resistor is connected. Of course, the present technology is not limited to this.

[0326] The configurations of the arithmetic device, multiplication-accumulation device, analog circuit, synaptic circuit, neuron circuit, etc., the method of generating the multiplication-accumulation signal, etc. described above with reference to the accompanying drawings are merely embodiments and can be arbitrarily modified without departing from the gist of the present technology. That is, any other configuration, method, etc. for performing the technology of the present invention can be adopted.

[0327] In the present disclosure, concepts such as “same”, “equal”, “orthogonal”, and “parallel” include “substantially the same”, “substantially equal”, “substantially orthogonal”, “substantially parallel”, etc. For example, a state within a predetermined range (e.g., a range of ±10%) of reference to “exactly the same”, “completely equal”, “completely orthogonal”, “completely parallel”, etc. is also included.

[0328] It is also possible to combine at least two features of the present technology described above. In other words, the various features described in the various embodiments can be arbitrarily combined regardless of the embodiments. In addition, the various effects described above are not restrictive but merely illustrative, and other effects may be provided.

[0329] It should be noted that the present technology can also adopt the following configurations.

[0330] (1) An arithmetic device comprising:

[0331] a plurality of input lines, an electrical signal corresponding to an input value being input to each input line within a predetermined input period; and

[0332] One or more multiply-accumulate devices, each multiply-accumulate device comprising

[0333] a plurality of multiplication units that generate charges corresponding to product values ​​obtained by multiplying the input value by a weight value based on the electrical signal input to each of the plurality of input lines,

[0334] an accumulation unit that accumulates the charge corresponding to the product value generated by each of the plurality of multiplication units,

[0335] a charging unit that charges the accumulating unit in which the charge corresponding to the product value is accumulated after the input period, and

[0336] an output unit that, after charging is started by the charging unit, performs threshold determination on the voltage held by the accumulating unit using a predetermined threshold value, outputting a multiplication-accumulation signal indicating the sum of the product values, wherein

[0337] In the one or more multiplication-accumulation devices, charging by the charging unit is performed in a common charging mode, and a common threshold is set as the predetermined threshold.

[0338] (2) The arithmetic device according to (1), wherein

[0339] The one or more multiply-accumulate devices are a plurality of multiply-accumulate devices connected in parallel to the plurality of input lines.

[0340] (3) The arithmetic device according to (1) or (2), wherein

[0341] The common charging mode includes charging with the same charging signal supplied during a common charging period.

[0342] (4) The arithmetic device according to any one of (1) to (3), wherein

[0343] The common charging mode includes charging at a common charging speed.

[0344] (5) The arithmetic device according to any one of (1) to (4), wherein

[0345] The common charging mode includes charging according to a common time constant.

[0346] (6) The arithmetic device according to any one of (1) to (5), wherein

[0347] A sum of absolute values ​​of the weight values ​​set in the plurality of multiplication units is defined as a weight sum value, and the common charging mode includes charging based on a maximum value of the weight sum value in the one or more multiplication-accumulation devices.

[0348] (7) The arithmetic device according to (5) or (6), wherein

[0349] Each of the one or more multiply-accumulate devices includes a charge output line,

[0350] The plurality of multiplication units output charges corresponding to the product values ​​to the charge output lines, and

[0351] The common charging mode includes charging in which a time constant associated with outputting the charge corresponding to the product value to the charge output line through the plurality of multiplication units having the maximum weight sum value is used as the common time constant.

[0352] (8) The arithmetic device according to any one of (1) to (7), wherein

[0353] The common threshold is set based on a duration of the input cycle.

[0354] (9) The arithmetic device according to any one of (1) to (8), wherein

[0355] A sum of absolute values ​​of the weight values ​​set in the plurality of multiplication units is defined as a weight sum value, and the common threshold is set based on a maximum value of the weight sum values ​​in the one or more multiplication-accumulation devices.

[0356] (10) The arithmetic device according to any one of (1) to (9), wherein

[0357] The common charging mode includes charging with the same charging signal supplied during the common charging cycle, and

[0358] The charging unit comprises a charging line which is connected to the accumulating unit and supplies the same charging signal to the accumulating unit during the common charging cycle.

[0359] (11) The arithmetic device according to any one of (1) to (9), wherein

[0360] The common charging mode includes charging with the same charging signal supplied during the common charging cycle, and

[0361] The charging unit supplies the same charging signal to the accumulation unit via the plurality of input lines during the common charging cycle.

[0362] (12) The arithmetic device according to any one of (1) to (11), wherein

[0363] The plurality of multiplication units include at least one of a positive weight multiplication unit that generates a positive weight charge corresponding to a product value obtained by multiplying the input value by the positive weight value and a negative weight multiplication unit that generates a negative weight charge corresponding to a product value obtained by multiplying the input value by the negative weight value,

[0364] The accumulation unit includes a positive charge accumulation unit and a negative charge accumulation unit, wherein the positive charge accumulation unit can accumulate the positive weight charge generated by the positive weight multiplication unit, and the negative charge accumulation unit can accumulate the negative weight charge generated by the negative weight multiplication unit.

[0365] The charging unit charges the positive charge accumulation unit and the negative charge accumulation unit in the common charging mode, and

[0366] The output unit outputs the multiplication-accumulation signal by threshold-determining each of the positive charge accumulation unit and the negative charge accumulation unit using the common threshold value.

[0367] (13) The arithmetic device according to (12), wherein

[0368] The sum of the positive weight values ​​set in the multiple multiplication units is defined as a positive sum value, and the sum of the absolute values ​​of the negative weight values ​​is defined as a negative sum value, and the common charging mode includes charging based on the maximum value of the positive sum value and the negative sum value in the one or more multiplication-accumulation devices.

[0369] (14) The arithmetic device according to (13), wherein

[0370] Each of the one or more multiply-accumulate devices includes a positive charge output line and a negative charge output line,

[0371] The positive charge multiplication unit outputs the positive weighted charge to the positive charge output line,

[0372] The negative charge multiplication unit outputs the negative weighted charge to the negative charge output line, and

[0373] Assuming that the maximum value among the positive sum value and the negative sum value in the one or more multiplication-accumulation devices is the maximum sum value, then

[0374] The positive weighted charge or the negative weighted charge associated with the maximum sum value is a maximum weighted charge, and

[0375] The positive charge output line or the negative charge output line from which the maximum weighted charge is output is a maximum charge output line,

[0376] A time constant associated with output of the maximum weight charge to the maximum charge output line is defined as a common time constant, and the common charging mode includes charging according to the common time constant.

[0377] (15) The arithmetic device according to any one of (12) to (14), wherein

[0378] The sum of the positive weight values ​​set in the multiple multiplication units is defined as a positive sum value, and the sum of the absolute values ​​of the negative weight values ​​is defined as a negative sum value, and the common threshold is set based on the maximum value of the positive sum value and the negative sum value in the one or more multiplication-accumulation devices.

[0379] (16) The arithmetic device according to any one of (12) to (15), wherein

[0380] The absolute values ​​of the positive weight value and the negative weight value are fixed to the same value, set to any one of a plurality of values ​​different from each other, or randomly set, and

[0381] In the one or more multiplication-accumulation devices, a value obtained by adding the positive sum value and the negative sum value is a common value.

[0382] (17) The arithmetic device according to any one of (12) to (15), wherein

[0383] The absolute values ​​of the positive weight value and the negative weight value are fixed to the same value, set to any one of a plurality of values ​​different from each other, or randomly set, and

[0384] In the one or more multiplication-accumulation devices, a value obtained by adding the positive sum value and the negative sum value is a random value.

[0385] (18) The arithmetic device according to any one of (12) to (17), wherein

[0386] The common charging mode includes charging with the same charging signal supplied during the common charging cycle, and

[0387] The charging unit includes a charging line connected to the positive charge accumulation unit and the negative charge accumulation unit and supplies the same charging signal to the positive charge accumulation unit and the negative charge accumulation unit during the common charging period.

[0388] (19) The arithmetic device according to any one of (12) to (18), wherein

[0389] The common charging mode includes charging with the same charging signal supplied during the common charging cycle, and

[0390] The charging unit supplies the same charging signal to the positive charge accumulation unit and the negative charge accumulation unit via the plurality of input lines during the common charging period.

[0391] (20) A multiplication-accumulation system, comprising:

[0392] a plurality of input lines, an electrical signal corresponding to an input value being input to each input line within a predetermined input cycle;

[0393] One or more analog circuits, each analog circuit comprising

[0394] a plurality of multiplication units that generate charges corresponding to product values ​​obtained by multiplying the input value by a weight value based on the electrical signal input to each of the plurality of input lines,

[0395] an accumulation unit that accumulates the charge corresponding to the product value generated by each of the plurality of multiplication units,

[0396] a charging unit that charges the accumulating unit in which the charge corresponding to the product value is accumulated after the input period, and

[0397] an output unit that outputs a multiplication-accumulation signal indicating the sum of the product values ​​by performing threshold determination on the voltage held by the accumulation unit using a predetermined threshold value after charging is started by the charging unit; and

[0398] A network circuit configured by connecting a plurality of analog circuits, wherein

[0399] In the one or more analog circuits, charging by the charging unit is performed in a common charging mode, and a common threshold is set as the predetermined threshold.

[0400] (21) The arithmetic device according to any one of (1) to (19), wherein

[0401] The electrical signal corresponding to the input value is a pulse signal whose ON time with respect to the input cycle corresponds to the input value.

[0402] (22) The arithmetic device according to any one of (1) to (19) and (21), wherein

[0403] The duration of the common charging cycle is equal to the input cycle.

[0404] Reference numerals list

[0405] T Input cycle

[0406] θ threshold

[0407] 1 Signal line

[0408] 3 Analog Circuit

[0409] 6 Input signal line

[0410] 7 A pair of output wires

[0411] 7a Positive charge output line

[0412] 7b Negative charge output line

[0413] 8 Synaptic circuit (multiplication unit)

[0414] 8a Synaptic circuit (positive weight multiplication unit)

[0415] 8b Synaptic circuit (negative weight multiplication unit)

[0416] 9 Neuronal Circuits

[0417] 10 Output signal line

[0418] 11 Accumulation Unit

[0419] 12 Signal output unit

[0420] 13. Capacitor

[0421] 15 Charging unit

[0422] 17 Resistors

[0423] 17a Positive resistor

[0424] 17b Negative resistor

[0425] 19 Charging cable

[0426] 20, 20a, 20b Resistor in charging unit

[0427] 22, 22a, 22b Comparator

[0428] 23 Signal generation unit

[0429] 25, 25a, 25b Current source

[0430] 26 Differential amplifier circuit

[0431] 100 Arithmetic equipment.

Claims

1. An arithmetic device comprising: a plurality of input lines, an electrical signal corresponding to an input value being input to each input line within a predetermined input cycle; as well as One or more multiply-accumulate devices, each multiply-accumulate device comprising a plurality of multiplication units that generate charges corresponding to product values ​​obtained by multiplying the input value by a weight value based on the electrical signal input to each of the plurality of input lines, an accumulation unit that accumulates the charge corresponding to the product value generated by each of the plurality of multiplication units, a charging unit that charges the accumulating unit in which the charge corresponding to the product value is accumulated after the input period, and an output unit that, after charging is started by the charging unit, performs threshold determination on the voltage held by the accumulating unit using a predetermined threshold value, outputting a multiplication-accumulation signal indicating the sum of the product values, wherein In the one or more multiplication-accumulation devices, charging by the charging unit is performed in a common charging mode, and a common threshold is set to the predetermined threshold; defining a sum of absolute values ​​of the weight values ​​set in the plurality of multiplication units as a weight sum value; Each of the one or more multiply-accumulate devices includes a charge output line, The plurality of multiplication units output charges corresponding to the product values ​​to the charge output lines, and The common charging mode includes charging in which a time constant associated with outputting the charge corresponding to the product value to the charge output line through the plurality of multiplication units having the maximum weight sum value is used as a common time constant.

2. An arithmetic device according to claim 1, wherein The one or more multiply-accumulate devices are a plurality of multiply-accumulate devices connected in parallel to the plurality of input lines.

3. The arithmetic device according to claim 1, wherein The common charging mode includes charging with the same charging signal supplied during a common charging period.

4. The arithmetic device according to claim 1, wherein The common charging mode includes charging at a common charging speed.

5. The arithmetic device according to claim 1, wherein The common charging mode includes charging according to a common time constant.

6. The arithmetic device according to claim 1, wherein The common charging mode includes charging based on a maximum value of the weight sum values ​​in the one or more multiply-accumulate devices.

7. The arithmetic device according to claim 1, wherein The common threshold is set based on a duration of the input cycle.

8. The arithmetic device according to claim 1, wherein A sum of absolute values ​​of the weight values ​​set in the plurality of multiplication units is defined as a weight sum value, and the common threshold is set based on a maximum value of the weight sum values ​​in the one or more multiplication-accumulation devices.

9. The arithmetic device according to claim 1, wherein The common charging mode includes charging with the same charging signal supplied during a common charging cycle, and The charging unit comprises a charging line which is connected to the accumulating unit and supplies the same charging signal to the accumulating unit during the common charging cycle.

10. The arithmetic device according to claim 1, wherein The common charging mode includes charging with the same charging signal supplied during a common charging cycle, and The charging unit supplies the same charging signal to the accumulation unit via the plurality of input lines during the common charging cycle.

11. The arithmetic device according to claim 1, wherein The plurality of multiplication units include at least one of a positive weight multiplication unit that generates a positive weight charge corresponding to a product value obtained by multiplying the input value by the positive weight value and a negative weight multiplication unit that generates a negative weight charge corresponding to a product value obtained by multiplying the input value by the negative weight value, The accumulation unit includes a positive charge accumulation unit and a negative charge accumulation unit, wherein the positive charge accumulation unit can accumulate the positive weight charge generated by the positive weight multiplication unit, and the negative charge accumulation unit can accumulate the negative weight charge generated by the negative weight multiplication unit. The charging unit charges the positive charge accumulation unit and the negative charge accumulation unit in the common charging mode, and The output unit outputs the multiplication-accumulation signal by threshold-determining each of the positive charge accumulation unit and the negative charge accumulation unit using the common threshold value.

12. The arithmetic device according to claim 11, wherein The sum of the positive weight values ​​set in the multiple multiplication units is defined as a positive sum value, and the sum of the absolute values ​​of the negative weight values ​​is defined as a negative sum value, and the common charging mode includes charging based on the maximum value of the positive sum value and the negative sum value in the one or more multiplication-accumulation devices.

13. The arithmetic device according to claim 12, wherein Each of the one or more multiply-accumulate devices includes a positive charge output line and a negative charge output line, The positive charge multiplication unit outputs the positive weighted charge to the positive charge output line, The negative charge multiplication unit outputs the negative weighted charge to the negative charge output line, and Assuming that the maximum value among the positive sum value and the negative sum value in the one or more multiplication-accumulation devices is the maximum sum value, then The positive weighted charge or the negative weighted charge associated with the maximum sum value is a maximum weighted charge, and The positive charge output line or the negative charge output line from which the maximum weighted charge is output is a maximum charge output line, A time constant associated with output of the maximum weight charge to the maximum charge output line is defined as a common time constant, and the common charging mode includes charging according to the common time constant.

14. The arithmetic device according to claim 11, wherein The sum of the positive weight values ​​set in the multiple multiplication units is defined as a positive sum value, and the sum of the absolute values ​​of the negative weight values ​​is defined as a negative sum value, and the common threshold is set based on the maximum value of the positive sum value and the negative sum value in the one or more multiplication-accumulation devices.

15. The arithmetic device according to claim 11, wherein The absolute values ​​of the positive weight value and the negative weight value are fixed to the same value, set to any one of a plurality of values ​​different from each other, or randomly set, and In the one or more multiplication-accumulation devices, a value obtained by adding the positive sum value and the negative sum value is a common value.

16. The arithmetic device according to claim 11, wherein The absolute values ​​of the positive weight value and the negative weight value are fixed to the same value, set to any one of a plurality of values ​​different from each other, or randomly set, and In the one or more multiplication-accumulation devices, a value obtained by adding the positive sum value and the negative sum value is a random value.

17. The arithmetic device according to claim 11, wherein The common charging mode includes charging with the same charging signal supplied during a common charging cycle, and The charging unit includes a charging line connected to the positive charge accumulation unit and the negative charge accumulation unit and supplies the same charging signal to the positive charge accumulation unit and the negative charge accumulation unit during the common charging period.

18. The arithmetic device according to claim 11, wherein The common charging mode includes charging with the same charging signal supplied during a common charging cycle, and The charging unit supplies the same charging signal to the positive charge accumulation unit and the negative charge accumulation unit via the plurality of input lines during the common charging period.

19. A multiplication-accumulation system comprising: a plurality of input lines, an electrical signal corresponding to an input value being input to each input line within a predetermined input cycle; One or more analog circuits, each analog circuit comprising a plurality of multiplication units that generate charges corresponding to product values ​​obtained by multiplying the input value by a weight value based on the electrical signal input to each of the plurality of input lines, an accumulation unit that accumulates the charge corresponding to the product value generated by each of the plurality of multiplication units, a charging unit that charges the accumulating unit in which the charge corresponding to the product value is accumulated after the input period, and an output unit that outputs a multiplication-accumulation signal indicating a sum of the product values ​​by performing threshold determination on the voltage held by the accumulation unit using a predetermined threshold value after charging is started by the charging unit; as well as A network circuit configured by connecting a plurality of analog circuits, wherein In the one or more analog circuits, charging by the charging unit is performed in a common charging mode, and a common threshold is set to the predetermined threshold; defining a sum of absolute values ​​of the weight values ​​set in the plurality of multiplication units as a weight sum value; Each of the one or more analog circuits includes a charge output line, The plurality of multiplication units output charges corresponding to the product values ​​to the charge output lines, and The common charging mode includes charging in which a time constant associated with outputting the charge corresponding to the product value to the charge output line through the plurality of multiplication units having the maximum weight sum value is used as a common time constant.

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