Multi-chip package with high thermal conductivity die attachment

Abstract

A packaged semiconductor device (200) includes a metal substrate (120) having first and second through-hole apertures (120a, 120b), and a metal pad (125b) surrounding the apertures on a dielectric pad (125a), the through-hole apertures (120a, 120b) having an outer ring. First and second semiconductor dies (180a, 180b) have a back surface metallization (BSM) layer (186) on their bottom surface and are mounted top-side up on the top portion of the apertures. A die attachment layer (187) is located directly between the BSM layer and a wall of the metal substrate defining the apertures to provide die attachment for the first and second semiconductor dies filling the bottom portion of the apertures. Leads (126) contact the metal pads, wherein the leads include a distal portion extending beyond the metal substrate. Bonding wires (133) are located between the metal pads and bonding pads on the first and second semiconductor dies, and a molding compound provides encapsulation for the packaged semiconductor device.

Description

Technical Field

[0001] This disclosure relates to the assembly of semiconductor devices, and more specifically to the attachment of metal dies to substrates. Background Technology

[0002] Packaged semiconductor devices typically include an integrated circuit (IC) die, which is usually a silicon die mounted on die pads of a component such as a leadframe using die-attach adhesive. Other components include an interposer, a printed circuit board (PCB), and another IC die. For IC dies assembled with the top (active) side up and the back side down, the die-attach adhesive provides mechanical attachment and typically also provides electrical and / or thermal pathways to the die pads. Die-attach adhesives typically comprise polymers, such as polyimide or epoxy-based adhesives. Silver is often added as a filler in the form of granular flakes to improve both the electrical and thermal conductivity of the polymer material. Summary of the Invention

[0003] This summary of the invention provides a simplified overview of the disclosed concepts, which are further described below in detail with reference to the accompanying drawings. This summary is not intended to limit the scope of the claimed subject matter.

[0004] It is recognized that conventional die attachment solutions, including those using metal particle-filled polymers, exhibit significant thermal resistance and resistivity. As thermal management becomes increasingly important with the trend towards smaller features and higher operating currents in more compact and highly integrated electronic systems, die attachment arrangements with higher thermal conductivity, while also providing low resistance, are required when using back-side electrical contacts with semiconductor dies. While solder molding attachments, such as eutectic gold and tin (AuSn), are known to provide back-side electrical contacts with semiconductor dies with relatively good thermal and resistivity performance compared to metal particle-filled polymers, solder molding attachments are relatively expensive and limited to solderable die surfaces. Furthermore, the solder molding attachment process involves an inert reflow process, the temperature of which can introduce temperature-induced stresses on the metal interconnects of the semiconductor die.

[0005] The disclosed aspect includes a packaged semiconductor device comprising a metal substrate having first and second through-hole apertures, and metal pads surrounding the apertures on dielectric pads on the metal substrate, each through-hole aperture having an outer ring. First and second semiconductor dies are mounted top-side up on top portions of the apertures, having a back surface metal (BSM) layer on their bottom surfaces. A metal die attachment layer is located between the BSM layer and a wall of the metal substrate defining the apertures to provide die attachment for the first and second semiconductor dies filling the bottom portions of the apertures. Leads contact the metal pads, wherein the leads include distal portions extending beyond the metal substrate. Bonding wires are located between the metal pads and bonding pads on the first and second semiconductor dies, and a molding compound provides device packaging for the packaged semiconductor device. Attached Figure Description

[0006] Now refer to the accompanying drawings, which are not necessarily drawn to scale, in which:

[0007] Figures 1A to 1F The assembly process flow is shown according to the components used in the example aspect and the assembly process for forming the disclosed multi-chip packaged semiconductor device, which has first and second semiconductor dies on a metal substrate having raised metal pads including metal pads on dielectric pads on the surface of the metal substrate, wherein each semiconductor die having a BSM layer is directly attached to the metal substrate by a disclosed electroplated (coated) metal die attachment layer.

[0008] Figure 2A An example leaded multi-chip semiconductor device is shown, which has first and second semiconductor dies on a metal substrate, after sizing, then wire bonding the bonding pads on the respective semiconductor dies to the raised metal pads connected to the leads, and wire bonding the bonding pads between the respective semiconductor dies.

[0009] Figure 2B The molded product is shown. Figure 2A The leaded multi-chip packaged semiconductor device shown is used to form a molding compound to provide a molded leaded multi-chip packaged semiconductor device. Detailed Implementation

[0010] Referring to the accompanying drawings, similar reference numerals are used to indicate similar or equivalent elements. The illustrated order of actions or events should not be considered limiting, as some actions or events may occur in a different order and / or simultaneously with other actions or events. Furthermore, implementing the method according to this disclosure may not require certain illustrated actions or events.

[0011] The disclosed aspects include multi-chip semiconductor packaging, wherein die attachment of the first and at least the second semiconductor dies is established by plating a metal layer, such as copper, nickel, cobalt, or alloys thereof, as opposed to conventional soldering. Therefore, the void problem associated with solder die attachment processes related to the formation of Sn-Cu intermetallic compounds is eliminated in the disclosed multi-chip packaging.

[0012] Figure 1A A diagram is shown for covering a metal substrate (see Figure 1B An example dielectric cap 130 is formed by a metal substrate 120 in which a covered substrate stack is formed, wherein the dielectric cap 130 has a repeating pattern, each pattern including a pair of recesses 130a, 130b, the recesses including a first recess 130a and a second recess 130b. The covered substrate stack is configured for immersion in the substrate below. Figure 1E The plating container shown as 150 is a plating bath for providing an electroplating bath.

[0013] The dielectric cap 130 may comprise plastic. A first recess 130a is used to cover a first semiconductor die, and a second recess 130b is used to cover a second semiconductor die; both are shown, for example, as rectangles, shaped and sized to match the dimensions of the respective semiconductor dies to be covered. The recesses 130a and 130b have slightly larger areas than the first and second semiconductor dies to accommodate the respective semiconductor dies. Although shown as having the same size and shape, the first and second recesses 130a and 130b may be sized and shaped differently relative to each other to match the respective dimensions of the first and second semiconductor dies.

[0014] Alternatively, a UV-curable plating solution resistant tape can be used as the dielectric cap 130. When the tape replaces the dielectric cap, a groove is not required. The dielectric caps on the top surfaces of the first and second semiconductor dies prevent the dies from detaching from the plating solution.

[0015] Figure 1B An example metal substrate 120 is shown, with an enlarged portion of the illustration to show corresponding components of the raised pads 125, each component including a metal pad 125b on a dielectric pad 125a (e.g., polyimide) on the surface of the metal substrate 120. The metal substrate 120 is typically in the form of a substrate sheet / panel having a plurality of dual-die location via apertures, including a first aperture 120a and a second aperture 120b, configured for use with… Figure 1CThe first and second semiconductor dies 180a and 180b shown are positioned with their top surfaces facing upwards within apertures 120a and 120b. The metal substrate / panel may have approximately 50 to 1,000 dual-die positions. The thickness of the metal substrate 120 is typically from approximately 0.1 mm (3.94 mils) to 0.3 mm (11.81 mils).

[0016] The metal substrate 120 may include copper, such as a copper alloy. Other example metals for the metal substrate 120 may include nickel, cobalt, tin, or alloys thereof. The first and second apertures 120a and 120b are arranged in a repeating pattern, and their positions are consistent with... Figure 1A The recesses of the dielectric cap 130 shown match the dimensions and repeating patterns of one or more of the vias 130a and 130b. Apertures 120a and 120b each have outer rings 120a1 and 120b1 for seating the first and second semiconductor dies, with raised pads 125 located on the sides generally surrounding the via apertures 120a and 120b. Metal pads 125b can be printed onto the dielectric pads 125a. Printing is typically aligned using alignment marks on the metal substrate 120.

[0017] Figure 1C The first and second semiconductor dies 180a and 180b are shown, with their top (active) surfaces facing up and their back surfaces facing down, seated within outer rings 120a1 and 120b1 within apertures 120a and 120b of a metal substrate 120. Figure 1B (As shown in the diagram). Bonding pads 181 coupled to nodes in circuits 170a and 170b are shown on the active top surfaces of semiconductor dies 180a and 180b. Circuits 170a and 170b include circuit elements (including transistors, and typically diodes, resistors, capacitors, etc.) formed in a semiconductor layer (an epitaxial layer on a bulk substrate), which are configured together to typically perform at least a circuit function. Example circuit functions include analog (e.g., amplifiers or power converters), radio frequency (RF), digital, or non-volatile memory functions.

[0018] The first and second semiconductor dies 180a and 180b have a BSM layer 186, which may include, for example, copper. Although not shown, an optional refractory metal barrier layer (e.g., TiW, TaN, or Cr) may be present beneath the BSM layer 186. Bonding pads 181 may include copper pillars or solder bumps thereon.

[0019] Figure 1DA dielectric cap 130 is shown after the metal substrate 120 placed above semiconductor dies 180a and 180b. The view is inverted to look down at the bottom of the metal substrate 120, showing the portions of apertures 120a and 120b not occupied by semiconductor dies 180a and 180b. A BSM layer 186 is shown on the back side of semiconductor dies 180a and 180b.

[0020] Figure 1E The illustration shows the immersion of a covered substrate stack, including a dielectric cap 130, on a metal substrate 120 having first and second semiconductor dies (not shown) therein, into a plating container 150 providing an electroplating bath. These components are immersed in a plating solution 145 comprising an electrolyte containing one or more dissolved metal salts, including the metal of interest for electroplating, and other ions in the solution that allow current flow.

[0021] In the case of a dielectric cap, a sealant, such as a plating solution resistant tape, is typically present between the dielectric cap 130 and the metal substrate 120 to prevent plating of the plating metal die attachment layer on the top surface of the semiconductor dies 180a, 180b. For plating, the metal substrate 120 is connected to the negative terminal (cathode) of the power supply 190, and conductive structures spaced apart from the metal substrate 120 (such as a metal block shown as an anode 135 spaced apart from the metal substrate 120) are connected to the positive terminal (anode) of the power supply 190.

[0022] Electroplating is typically performed at temperatures between 15°C and 30°C to avoid introducing temperature-induced stresses, such as those introduced into interconnects on semiconductor dies. At the cathode, metal ions (e.g., Cu) dissolved in the plating solution 145... +2 The metals are reduced at the interface between the solution and the cathode, causing them to be plated onto the cathode as zero-valent metals (e.g., Cu). Electroplating is typically performed using direct current (DC), but it can also be done as pulsed electroplating.

[0023] Electroplated deposited metal die attachment layer, which is shown herein as including Figure 1F A single layer (such as including copper) of 187 is used to fill the volume between the BSM layer 186 on the bottom surfaces of semiconductor dies 180a and 180b and the walls of the metal substrate 120 defining apertures 120a and 120b to provide die attachment. The electroplating process time can be calculated by dividing the desired thickness of the metal die attachment layer 187 by the deposition rate. The thickness of the plated metal die attachment layer 187 is designed to fill apertures 120a and 120b, such as 10 to 250 μm thick, for example, 40 to 250 μm thick.

[0024] Figure 1FThe portions of apertures 120a and 120b not occupied by the semiconductor die 180 (below the die) are shown, now filled with a plated metal die attachment layer 187, which is deposited as a sheet over the entire bottom surface of the metal substrate 120. Although the plated metal die attachment layer 187 is shown as planar, there is typically a slight indentation above the corresponding apertures 120a and 120b.

[0025] Even compared to other layers of the same metallic material deposited by other methods (such as sputtered metal layers), the plated metal die attachment layer 187, as a plated metal layer, is a unique layer. Unlike sputtered layers, electrodeposited layers are known to fill areas outside the line of sight. Electrodeposited layers are also known to have unique microstructures, including an initially deposited Nernst diffusion layer whose density and microstructure differ from those of the bulk portion of the electrodeposited layer.

[0026] Figure 2A This illustration shows a single leaded multi-chip semiconductor device 200 after the covered substrate stack is removed from the plating solution 145, the dielectric cap 130 is removed, the metal substrate 120 is cut, and leads 126 are added to the metal pads 125b of the raised pads 125, such as by soldering. The leaded multi-chip semiconductor device 200 can be viewed as an 18-lead package. The leads 126 comprise strips of metal (e.g., the same metal as the lead frame), such as commercially available or internally produced copper, copper alloys, or tin-plated leads 126. For example, a sheet of metal can be cut into strips for the leads 126.

[0027] Lead 126 has at least one bend and includes a distal portion extending beyond the metal substrate 120. Although not shown, lead 126 may be in a gull-wing arrangement. Lead 126 is typically soldered to metal pad 125b, but may also be attached via soldering or by means of a conductive adhesive material. Bonding wires 133 and 134 shown are added prior to dicing and include bonding wire 133 connecting the metal pad 125b of the raised pad 125 to bonding pads 181 on the semiconductor dies 180a, 180b. Optional bonding wire 134 is also shown connecting the bonding pads 181 on the respective semiconductor dies 180a, 180b. Figure 2B A leaded multi-chip packaged semiconductor device, now shown as 250, is shown after molding compound 290 is formed to provide a package for the packaged semiconductor device.

[0028] The disclosed aspects can be integrated into various assembly processes to form a variety of different multi-chip semiconductor packaged devices and related products. The semiconductor die may include various components therein and / or layers thereon, including barrier layers, dielectric layers, device structures, active components, and passive components (including source regions, drain regions, bit lines, bases, emitters, collectors, wires, conductive vias, etc.). Furthermore, the semiconductor die can be formed using various processes, including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS, and MEMS.

[0029] Those skilled in the art will understand that many variations of the disclosed aspects are possible within the scope of the claimed invention, and that further additions, deletions, substitutions, and modifications can be made to the above aspects without departing from the scope of this disclosure.

Claims

1. A packaged semiconductor device comprising: A metal substrate having a first aperture via and a second aperture via, and a plurality of metal pads surrounding the first aperture via and the second aperture via on dielectric pads, each aperture via having an outer ring; The first semiconductor die and the second semiconductor die are mounted top-up on the top portion of the corresponding aperture through-hole, and each die has a back metal layer, namely a BSM layer, on its bottom surface. A metal die attachment layer is located directly between the BSM layer and the wall of the metal substrate, the wall of the metal substrate defining vias of corresponding diameter to provide die attachment for the first semiconductor die and the second semiconductor die, which fill the bottom portion of the vias of corresponding diameter. Leads that contact the plurality of metal pads, wherein the leads include a distal portion extending beyond the metal substrate; Bonding wires, located between the plurality of metal pads and the bonding pads on the first semiconductor die and the second semiconductor die, and Molded compounds that provide encapsulation.

2. The packaged semiconductor device of claim 1, wherein the dielectric pad comprises a polymer.

3. The packaged semiconductor device according to claim 1, wherein the metal die attachment layer consists of a single layer.

4. The packaged semiconductor device according to claim 1, wherein the BSM layer, the metal substrate, and the metal die attachment layer all comprise copper.

5. The packaged semiconductor device according to claim 1, wherein the metal die attachment layer is an electroplated metal layer.

6. The packaged semiconductor device of claim 1, further comprising additional bonding lines between other bonding pads on the first semiconductor die and other bonding pads on the second semiconductor die.

7. The packaged semiconductor device according to claim 1, wherein the thickness of the metal die attachment layer is from 40 μm to 250 μm.

8. The packaged semiconductor device according to claim 1, wherein the thickness of the metal substrate is 0.1 mm to 0.3 mm.

9. A packaged semiconductor device comprising: A metal substrate having a first aperture via and a second aperture via, and a plurality of metal pads surrounding the first aperture via and the second aperture via on dielectric pads, each aperture via having an outer ring; The first semiconductor die and the second semiconductor die are mounted top-up on the top portion of the corresponding aperture through-hole, and each die has a back metal layer, namely a BSM layer, on its bottom surface. A metal die attachment layer is located directly between the BSM layer and the wall of the metal substrate, the wall of the metal substrate defining vias of corresponding diameter to provide die attachment for the first semiconductor die and the second semiconductor die, which fill the bottom portion of the vias of corresponding diameter. Leads that contact the plurality of metal pads, wherein the leads include a distal portion extending beyond the metal substrate; Bonding wires, located between the plurality of metal pads and the bonding pads on the first semiconductor die and the second semiconductor die, and Molded compounds, which provide encapsulation, The metal core attachment layer consists of a single layer, and The BSM layer, the metal substrate, and the metal die attachment layer all contain copper.

10. The packaged semiconductor device of claim 9, further comprising additional bonding lines between other bonding pads on the first semiconductor die and the second semiconductor die.

11. The packaged semiconductor device of claim 9, wherein the thickness of the metal die attachment layer is from 40 μm to 250 μm.

12. A semiconductor assembly method for multi-chip packaging, comprising: A metal substrate is provided, the metal substrate comprising a repeating pattern of first aperture vias and second aperture vias, each having an outer ring, and a plurality of metal pads surrounding the corresponding aperture vias on dielectric pads, the outer rings being positioned to match a first semiconductor die and a second semiconductor die, both the first semiconductor die and the second semiconductor die having a back metal layer, i.e., a BSM layer. The first semiconductor die and the second semiconductor die, each having a bonding pad, are inserted with their top surfaces facing upwards into the corresponding apertures of a plurality of aperture vias to be seated on the outer ring. The top surfaces of the first semiconductor die and the second semiconductor die are sealed to fix the first semiconductor die and the second semiconductor die in the first aperture via and the second aperture via to provide a plurality of covered substrate stacks; The plurality of covered substrate stacks are immersed in a metal plating solution within a solution container, wherein the metal substrate is connected to the negative terminal of a power supply, and conductive structures spaced apart from the metal substrate are connected to the positive terminal of the power supply. Electroplating is used to deposit an electroplated metal die attachment layer to fill the volume between the walls of the BSM layer and the metal substrate defining corresponding aperture vias, thereby providing die attachment for the first semiconductor die and the second semiconductor die.

13. The method of claim 12, wherein a dielectric cap is used for sealing, the method further comprising removing the dielectric cap after the electroplating, and then performing wire bonding between the plurality of metal pads and the bonding pads on the first semiconductor die and the second semiconductor die.

14. The method of claim 12, wherein the UV-curable tape is used for the seal.

15. The method of claim 12, further comprising printing dielectric pads on the metal substrate and then printing the metal pads on the dielectric pads.

16. The method of claim 12, wherein the metal plating solution comprises a copper plating solution, and wherein the BSM layer, the metal substrate, and the metal die attachment layer all comprise copper.

17. The method of claim 12, wherein the dielectric pad comprises a polymer.

18. The method of claim 13, wherein the wire bonding further comprises placing the bonding wire between other bonding pads on the first semiconductor die and other bonding pads on the second semiconductor die.

19. The method of claim 12, further comprising forming a molding compound for encapsulating the semiconductor device of the package.

20. A packaged semiconductor device comprising: A metal substrate comprising a repeating pattern of first-diameter vias and second-diameter vias, each having an outer ring, and a plurality of metal pads surrounding the corresponding vias on dielectric pads, wherein the outer rings are positioned to match a first semiconductor die and a second semiconductor die, and both the first semiconductor die and the second semiconductor die have a back metal layer, i.e., a BSM layer. The first semiconductor die and the second semiconductor die each have bonding pads on their top surfaces, and the first semiconductor die and the second semiconductor die are mounted so as to be inserted top-up into corresponding apertures in a plurality of aperture vias; The top surfaces of the first semiconductor die and the second semiconductor die are sealed to fix the first semiconductor die and the second semiconductor die in the first aperture through hole and the second aperture through hole; as well as An electroplated metal die attachment layer fills the volume between the walls of the BSM layer and the metal substrate defining corresponding aperture vias.

21. The packaged semiconductor device of claim 20, wherein the dielectric pad comprises a polymer.

22. The packaged semiconductor device of claim 21, wherein the metal die attachment layer consists of a single layer.

23. The packaged semiconductor device of claim 21, wherein the BSM layer, the metal substrate, and the metal die attachment layer all comprise copper.

24. The packaged semiconductor device of claim 21, wherein the metal die attachment layer is an electroplated metal layer.

25. The packaged semiconductor device of claim 21, further comprising additional bonding lines between other bonding pads on the first semiconductor die and other bonding pads on the second semiconductor die.

26. The packaged semiconductor device of claim 21, wherein the thickness of the metal die attachment layer is from 40 μm to 250 μm.

27. The packaged semiconductor device of claim 21, wherein the thickness of the metal substrate is from 0.1 mm to 0.3 mm.

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