A boundary scan circuit

Abstract

The present invention discloses a boundary scan circuit, comprising: a test access port controller, which provides data to be tested for a boundary scan chain and receives test results output by the boundary scan chain; a user-defined register, which provides selection control signals for a plurality of multiplexers; wherein the boundary scan chain has a plurality of stages connected in series, each stage includes a scan sub-chain, a scan bypass register and a multiplexer, and the multiplexer determines the output mode of input data according to the selection control signal; the output ends of the multiplexers of the previous-stage boundary scan chain are respectively connected to the input ends of the scan sub-chain and the scan bypass register of the next-stage boundary scan chain. The boundary scan circuit of the present invention can support multiple package test scenarios, improve test coverage and reduce test costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor digital integrated circuit design and testing, and particularly to a boundary scan circuit applicable to multiple package testing scenarios. Background Art

[0002] With the increasing scale of digital integrated circuits, the number of chip pins has increased sharply. Printed circuit boards are developing in the direction of being smaller, more micro, and thinner in terms of production scale. The traditional integrated circuit testing method using a multimeter and an oscilloscope with probes (abbreviation: ICT) can no longer meet the testing requirements for high-density chip pins. Subsequently, a new pin testing technology has emerged. The Joint Test Action Group (JTAG) defines it as boundary scan test and names it the IEEE 1149.1 specification, the JTAG standard. The boundary scan test is mainly realized by inserting a boundary scan cell and some additional test control logics between each input and output pin of the chip and the internal logic. The boundary scan test has two major advantages: one advantage is that it is convenient for fault location of the chip, quickly and accurately tests whether the connection between two chip pins is reliable, and improves the test and inspection efficiency; another advantage is that for chips with a JTAG interface, a pre-defined functional mode is built-in, and the chip can be made to be in a certain specific functional mode through the boundary scan channel to improve the flexibility of system control and facilitate system design.

[0003] In order to adapt to the applications of multiple chip products and make the same chip design scheme meet different packaging requirements, in the multiple packaging designs of the chip, different requirements for boundary scan testing in board-level testing need to be considered, so that the same boundary scan circuit can support multiple packaging application scenarios. Therefore, there is an urgent need to provide a flexible and adjustable boundary scan chain. However, in the application background of multiple packages, it has always been difficult to balance between improving test coverage and reducing test costs in the prior art. Therefore, there is no boundary scan test scheme that can ensure both high test coverage and reduced test costs. Summary of the Invention

[0004] In view of this, the present invention provides a boundary scan circuit applicable to multiple packages, which can improve test coverage and reduce test costs without adding extra pins, and meet the requirements of multiple usage scenarios.

[0005] On the one hand, the present invention provides a boundary scan circuit, including:

[0006] A test access port controller, connected to the boundary scan chain, is used to provide serial input data to be tested for the boundary scan chain and receive serial test result data output by the boundary scan chain;

[0007] A user-defined register is used to provide selection control signals for the selection terminals of multiple multiplexers;

[0008] The boundary scan chain has multiple stages connected in series, and each stage further includes:

[0009] A scan sub-chain includes multiple boundary scan cells connected in series, and each boundary scan cell corresponds to one or more pads;

[0010] Scan bypass registers are respectively connected in parallel with the scan sub-chain;

[0011] A multiplexer, whose input terminals are respectively connected to the output terminals of the scan sub-chain and the scan bypass register, is used to determine the output mode of the serial input data according to the selection control signal;

[0012] Among them, the input terminals of the scan sub-chain and the scan bypass register of the first-stage boundary scan chain receive the serial input data to be tested, and the output terminals of the multiplexers of each stage of the boundary scan chain are respectively connected to the input terminals of the scan sub-chain and the scan bypass register of the next-stage boundary scan chain, and the output of the multiplexer of the last-stage boundary scan chain is used as the serial test result data.

[0013] Preferably, the test access port controller has a test signal input terminal and a test signal output terminal. The test signal input terminal provides serial input data to be tested for the boundary scan chain, and the test signal output terminal receives the serial test result data output by the boundary scan chain.

[0014] Preferably, when the selection control signal of the multiplexer at the same stage of the scan sub-chain is a first preset signal, the scan sub-chain receives the input data of the test signal input terminal and outputs its own data to the test signal output terminal.

[0015] Preferably, the scan bypass register is used to receive the input data of the test signal input terminal and output its own data to the test signal output terminal when the selection control signal of the multiplexer at the same stage is a second preset signal.

[0016] Preferably, the user-defined register is associated with a user input signal to set the selection control signal of the multiplexer at each stage according to the packaging requirements.

[0017] Preferably, when the packaging requirement specifies that a scan test needs to be performed on the first pad, determine the first scan sub-chain where the first pad is located, and connect the first scan sub-chain to the boundary scan chain.

[0018] Preferably, when the packaging requirement specifies that a scan test does not need to be performed on the second pad, determine the second scan sub-chain where the second pad is located, and bypass the second scan sub-chain from the boundary scan chain.

[0019] Preferably, the scan bypass register includes a bypass enable signal terminal, where the bypass enable signal and the selection control signal of the same-level multiplexer have the same input terminal.

[0020] Preferably, the type of the boundary scan unit is selected according to the direction or attribute of the corresponding pad.

[0021] Preferably, the boundary scan units included in the same-level scan sub-chain correspond to pads with the same packaging requirements.

[0022] Another aspect of the present invention provides a boundary scan test method for a boundary scan circuit based on the foregoing aspect, including:

[0023] Step S1: According to the predefined packaging requirements, divide multiple boundary scan units corresponding to one or more pads into different scan sub-chains;

[0024] Step S2: Determine the arrangement order of the multiple scan sub-chains in the boundary scan chain;

[0025] Step S3: Construct a boundary scan chain according to the determined division method of the scan sub-chains and the arrangement order;

[0026] Step S4: Provide the serial input data to be tested to the boundary scan chain, perform a boundary scan test on one or more scan sub-chains, and receive the test results output by the boundary scan chain.

[0027] It can be seen that compared with the traditional boundary scan circuit, the boundary scan test circuit of the present invention has stronger controllability. Only by using a fixed number of serial test data ports (TDI / TDO), a boundary scan circuit that meets various packaging scenarios can be obtained, achieving full coverage of all PADs packaged under different packages. At the same time, the PADs that are not packaged will not appear on the boundary scan chain in this scenario, effectively shortening the test time and reducing the test cost. Description of the Drawings

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0029] Figure 1 It is a schematic structural diagram of multiple boundary scan test chains according to the present invention.

[0030] Figure 2 It is a schematic structural diagram of a single boundary scan test chain according to the present invention.

[0031] Figure 3 It is a schematic structural diagram of a boundary scan test circuit applicable to multiple packages according to the present invention.

[0032] Figure 4 It is a schematic internal structure diagram of the scan sub-chain bscan chain according to the present invention.

[0033] Figure 5 It is a schematic internal structure diagram of the scan bypass register bscan bypass segment according to the present invention.

[0034] Figure 6 It is a flowchart of the implementation method and test process of the boundary scan test circuit according to the present invention. Specific embodiments

[0035] To better understand the above technical solutions, the following will make a detailed description of the above technical solutions in combination with the drawings in the specification and specific embodiments.

[0036] It should be clear that the described embodiments are only some embodiments of the present invention, not all of them. To more clearly illustrate the present invention, numerous technical details are described in the following specific embodiments. Those skilled in the art should understand that the present invention can also be implemented without some of these details. In addition, to highlight the inventive concept of the present invention, some methods, means, components and their applications well known to those skilled in the art are not described in detail, but this does not affect the implementation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0037] The present invention aims to analyze the types and packaging information of each PAD according to all packaging test scenarios of the chip, and adopt segmented bypass of part of the boundary scan chain to implement the entire chip boundary scan chain circuit. Furthermore, in various packaging test scenarios, it supports flexible selection of the content and length of the boundary scan chain to meet various test requirements.

[0038] Embodiment 1

[0039] In order to adapt to multiple packages and multiple test requirements, the present invention designs two construction methods for the boundary scan test chain in one aspect. The first method is to prepare multiple boundary scan test chains (multi-boundary scanchain) in the design. Each boundary scan chain covers different test pins. During the test by an Automatic Test Equipment (ATE), according to the packaging information, the test vector (test pattern) of the boundary scan chain to be tested is provided. The specific structure is as Figure 1 shown.

[0040] Among them, TAP is the Test Access Port controller (Test Access Port): The test access port includes a test data input port (TDI), a test data output port (TDO), a test mode selection port (TMS), a test clock port (TCK), and a test reset signal port (TRSTN, this signal is optional). The TAP controller controls multiple states by controlling these ports, thereby controlling the operations on all instruction registers and data registers. By adopting the above chain construction method, it is possible to avoid increasing the length of the scan chain, reduce the time for serial data input and output, and reduce the test cost.

[0041] Optionally, the second construction method of the boundary scan test chain is to insert all the PADs (pads) that can plug in boundary scan cells into the boundary scan chain (boundary scan chain) to form a longer single chain (single-boundary scan chain test). When providing the test vector (test pattern) subsequently, according to the packaging information, multiple test patterns are provided. For the PADs that are not packaged out in a certain packaging scenario, no boundary scan test is performed. The specific structure is as Figure 2 shown. By adopting the above chain construction method, the required number of I / Os can be reduced, and the demand for test pins can be reduced.

[0042] Embodiment 2

[0043] In another embodiment, the present invention provides an enhanced boundary scan test adaptable to multi-packaging, hereinafter referred to as AdaptiveBST, whose main structure is as Figure 3 shown.

[0044] The Adaptive BST according to the present invention mainly includes the following parts:

[0045] (1) A test access port controller, namely the TAP controller, is connected to the boundary scan chain and is used to provide serial input data to be tested for the boundary scan chain and receive serial test result data output by the boundary scan chain. As Figure 3 shown, the TAP controller is connected to the boundary scan chain through a test signal input terminal Bsr_Tdi and a test signal output terminal Bsr_Tdo. The test signal input terminal Bsr_Tdi provides serial input data for the boundary scan chain, and the test signal output terminal Bsr_Tdo receives the serial test result data output by the boundary scan chain. Since all boundary scan cells are connected in series on a boundary scan chain, the design of the entire circuit only requires one serial test input data line and one serial test output data line, thus reducing the overhead of the test circuit on the input and output pins.

[0046] Optionally, the TAP controller may further be provided with signals Bsr_Tck, Bsr_capture, Bsr_shift, Bsr_update (not shown), where Bsr_Tck provides a clock signal homologous to the JTAG test clock signal JTAG_TCK for the bscan chain (scan sub-chain) and the bscan bypass segment (scan bypass register), and is clamped by the Bsr_mode signal; Bsr_capture is used as a control signal for the boundary scan cell to implement data sampling of the bscan cell, Bsr_shift is used as a control signal for the boundary scan cell to implement data shifting of the bscan cell, and Bsr_update is used as a control signal for the boundary scan cell to implement data update of the bscan cell. Those skilled in the art should understand that if AC JTAG needs to be supported, signals such as Bsr_Hystclk, Bsr_Actest, and Bsr_Acmode may also be provided.

[0047] (2) User-defined register TDR, which is used to provide selection control signals for the selection terminals of multiple multiplexers in the boundary scan chain; the user-defined register is associated with user input signals to set the selection control signals of each stage of the multiplexer according to packaging requirements. Specifically, the register TDR is connected to the control signal tdr_ctrl, and this register provides selection control signals for the selection terminals of the multiplexer MUX. Each bscan chain corresponds to a multiplexer MUX. In the present invention, when the selection control signal of MUX_X is the first preset signal (X represents the serial number of the MUX), the corresponding bscanchainX at the same level is connected to the total boundary scan chain, and the serial data at the input terminal Bsr_Tdi is shifted into bscan chainX, and the data in bscan chainX is shifted out to the output terminal Bsr_Tdo. The first preset signal can be 0 or low level; when the selection control signal of MUX_X is the second preset signal, the corresponding bscan chainX at the same level is not connected to the total boundary scan chain, and the serial data at the input terminal Bsr_Tdi is shifted into bscan bypass segmentX, and the data in bscan bypass segmentX is shifted out to the output terminal Bsr_Tdo. The second preset signal can be 1 or high level.

[0048] In addition, although the above exemplary embodiments use the user-defined register TDR to implement the control signals of the MUX and bscan bypass segment, it is not limited thereto. Other types of circuits capable of providing static configuration signals can also provide control signals for the MUX and bscan bypass segment. At the same time, the MUX plays a selection role in the entire solution, so it can also be implemented by any other element with a selection function, such as including combinational logic or other circuits.

[0049] (3) Boundary scan chain. The boundary scan chain has multiple stages connected in series, and each stage further includes: a scan sub-chain bscan chain, and the scan sub-chain further includes multiple boundary scan cells BSC (Boundary scan cell) connected in series. Each boundary scan cell corresponds to one or more pads PAD; a scan bypass register bscan bypass segment, which is respectively connected in parallel with the scan sub-chain; a multiplexer MUX, whose input terminals are respectively connected to the output terminals of the scan sub-chain and the scan bypass register, and is used to determine the output mode of the serial input data according to the selection control signal;

[0050] The multiplexer MUX, the scan sub-chain bscan chain, and the scan bypass register bscan bypass segment constitute one level of the boundary scan chain. That is, MUX_X, bscan chainX, and bscan bypass segmentX constitute the X-th level of the boundary scanchain (X represents the serial number of the MUX). Each scan sub-chain bscan chain is formed by connecting in series one or more boundary scan cells corresponding to PADs. Among them, the input ends of the scan sub-chain bscan chain1 and the scan bypass register bscan bypass segment 1 of the first-level boundary scan chain receive the serial input data to be tested, and then the output ends of the multiplexers of each level of the boundary scan chain are respectively connected to the input ends of the scan sub-chain bscan chain n and the scan bypass register bscan bypass segment n of the next level of the boundary scan chain, and the output of the multiplexer MUX_X of the last-level boundary scan chain is used as the serial test result data;

[0051] In a preferred embodiment, the boundary scan cells corresponding to the PADs with the same packaging requirements are placed on the same bscan chain. The packaging requirements of the PADs are specified by the user. In the set of all PADs, if it is desired to include a certain PAD combination or not include a certain PAD combination in a certain package, then the multiple PADs in the PAD combination can be regarded as having the same packaging requirements. For example, there are 10 PADs in the design PAD, PAD1 - PAD10, where the user specifies that there are two packages that do not output PAD3 and PAD7, and there is one package that does not output PAD4, PAD5, and PAD6. Therefore, the BSCs (Boundary scan cell) corresponding to PAD1 - PAD10 need to be divided into 3 scan sub-chains bscan chain. Among them, the BSCs corresponding to PAD3 and PAD7 are bscan chain1, the BSCs corresponding to PAD4, PAD5, and PAD6 are bscan chain2, and the BSCs corresponding to the remaining PADs are bscan chain3.

[0052] As Figure 3 shown, each bscan chain corresponds to a set of bscan bypass segments and a MUX. When the selection terminal of the MUX is 0, the bscan chain is connected in series to the total boundary scan chain.

[0053] The internal connection of each scan sub-chain bscan chain is asFigure 4 As shown, the type of boundary scan cell_n (n represents the serial number of the scan cell) is selected according to the direction or attribute of the corresponding PAD. For example, when the attribute of the PAD is an input signal for clock, reset, or mode selection, the corresponding boundary scan cell generally selects the bc_4 type; when the direction of the PAD is input, output, or bidirectional, the boundary scan cell can select the bc_1, bc_2, and bc_7 types respectively. Among them:

[0054] The serial input of the boundary scan cell_1 at the head of the chain, the serial input, serves as the serial input test data and is connected to Bsr_Tdi or the output of the boundary scan cell at the end of the previous bscan chain;

[0055] The serial output of the boundary scan cell_n at the end of the chain, the serial output, serves as the serial output test data and is connected to Bsr_Tdo or the input of the boundary scan cell at the head of the next bscan chain;

[0056] The CSU includes three control signals, Bsr_capture, Bsr_shift, and Bsr_update, which are connected to the outputs of the corresponding signals of the TAP controller; as described above, the CSU is used to implement data sampling, data shifting, and data updating of the bscan cell respectively.

[0057] Clock provides the working clock for the registers in the boundary scan cell and is homologous to JTAG_TCK;

[0058] Mode serves as the mode control signal and is jointly controlled by the instructions of IEEE 1149.1 or 1149.6;

[0059] Parallel_input is the functional data input, which is connected to the data output of the PAD input direction and / or the functional output of the chip. After passing through the boundary scan cell, the output data is connected to the data input of the PAD output direction;

[0060] Parallel_output is the functional data output, which is connected to the data input of the PAD output direction and / or the functional input of the chip. The input data comes from the output of the PAD input direction and is connected to the functional input of the chip after passing through the boundary scan cell;

[0061] Figure 4Each of the PAD_1, PAD_2, … PAD_n shown can represent one PAD or multiple PADs.

[0062] For the bscan bypass segment, i.e., the scan bypass register of the bscan chain, the present invention provides an exemplary basic structure as Figure 5 shown. The source of the bypass enable signal segment_bypass_en can be the same as the source of the selection control signal of the current same-level multiplexer, i.e., from the user-defined register TDR; the serial input terminal serial input can be connected to Bsr_Tdi or the output terminal of the previous-level MUX; the serial output terminal serial output can be connected to Bsr_Tdo or the input terminal of the current MUX; Bsr_tck is of the same origin as JTAG_TCK and is clamped by the IEEE 1149.1 or 1149.6 instruction. In Figure 5 the structure shown, the bscan bypass segment includes two registers reg1 and reg2, but is not limited thereto. The entire scan bypass register can also be implemented by one or more register units or in other ways.

[0063] Through the combined structure of the above multiplexer MUX, scan sub-chain bscan chain, and scan bypass register bscan bypass segment, the length of the boundary scan test link can be flexibly adjusted according to the actual packaging requirements. For example, when the user's packaging requirement specifies that PAD_1 needs to be scanned and tested, determine the scan sub-chain bscan chain 1 where PAD_1 is located and connect bscan chain 1 to the boundary scan chain. When the user's packaging requirement specifies that PAD_2 does not need to be scanned and tested, determine the scan sub-chain bscan chain 2 where PAD_2 is located and bypass the scan sub-chain bscan chain 2 from the boundary scan chain. That is to say, when certain PADs need to be located during the test, the test pattern can only select the scan sub-chain bscan chainX where the PAD is located, and the remaining scan sub-chains bscan chain are in the bypass mode due to the action of the scan bypass register bscan bypass segment, realizing precise scan testing for the packaging requirements and shortening the test time.

[0064] Embodiment III

[0065] Refer to Figure 6 , based on the above circuit structure, the implementation method and test process of the Adaptive BST circuit of the present invention are as follows, including:

[0066] Step S1: According to the predefined encapsulation requirements, divide multiple boundary scan cells corresponding to one or more pads into different scan sub-chains bscan chain.

[0067] Since there is an inherent association between the PAD and the boundary scan cell, the user first determines the division method of bscan chainX according to the encapsulation of the design PAD. For example, there are 10 PADs in the design, PAD1 - PAD10, where the user specifies that two encapsulations do not have PAD3 and PAD7, and one encapsulation does not have PAD4, PAD5, and PAD6. Therefore, the BSCs (Boundary scan cells) corresponding to all PAD1 - PAD10 need to be divided into 3 scan sub-chains bscan chain. Among them, the BSCs corresponding to PAD3 and PAD7 are bscan chain1, the BSCs corresponding to PAD4, PAD5, and PAD6 are bscan chain2, and the BSCs corresponding to the remaining PADs are bscan chain3.

[0068] It should be noted that if there are features such as power domains or partition good in the design, the division of the scan sub-chain bscan chain of the PAD BSC needs to be considered comprehensively.

[0069] Step S2: Determine the arrangement order of multiple scan sub-chains bscan chain in the boundary scan chain.

[0070] Specifically, according to the content of bscan chainX that has been divided in Step S1, the DFT engineer and the physical implementation engineer can negotiate and confirm the order (pad order) of the entire boundary scan chain formed by all PADs on the layout (floorplan), and complete the series connection of bscan chain according to the order of pad order.

[0071] Step S3: Construct the boundary scan chain according to the determined division method and the arrangement order of the scan sub-chain bscan chain.

[0072] In the circuit implementation stage, according to the established bscan chain content and sequence in step S2, and with reference to the circuit structure of the above Adaptive BST, provide clock, control signals, mode signals, etc., connect the bscan chains of each level of scan sub-chains in sequence, and connect each level of multiplexer MUX and scan bypass register bscan bypass segment to the bscan chains of each level according to the structure of the above embodiment and implement the corresponding configuration, so as to obtain a boundary scan test circuit that meets the design package requirements.

[0073] Step S4: Provide the serial input data to be tested to the boundary scan chain, perform boundary scan testing on one or more bscan chains of scan sub-chains, and receive the test results output by the boundary scan chain.

[0074] Since there can be multiple packages in chip design and there are also multiple usage scenarios for corresponding products, DFT engineers can provide different boundary scan description language (BSDL) files according to the package requirement information to accurately cover the test coverage of all PADs in different scenarios. Specifically, the boundary scan test vectors required by the Automatic Test Equipment (ATE) can be provided to test all PADs in each scenario. Referring to the above example, when it is necessary to test PAD3 and PAD7, only the corresponding bscanchain1 needs to be specified for testing. Because bscan chain1 only includes the boundary scan cells BSC corresponding to PAD3 and PAD7, and does not include the BSCs of other PADs.

[0075] It can be seen that the above technical solution of the present invention has good controllability. First, the length of the boundary scan chain can be flexibly adjusted. According to the actual packaging situation, the pins to be tested are selected to shorten the actual length of the scan sub-chain and reduce the test time. At the same time, the technical solution of the present invention is also beneficial to debugging the boundary scan test. When it is necessary to locate certain input / output pins during the test, the test pattern can only select the scan sub-chain bscan chainX where the PAD is located, and the remaining scan sub-chains bscan chain are in the bypass mode, which can greatly reduce the total length of the boundary scan chain and accelerate the debugging progress. And the present invention can implement the boundary scan circuit that meets various packaging scenarios by using a fixed number of serial test data ports (TDI / TDO), which can ensure full coverage of all PADs packaged under different packages. At the same time, the PADs that are not packaged will not appear on the boundary scan chain in this scenario, which can effectively reduce the test time and test cost.

[0076] The above describes multiple embodiment solutions provided by the embodiments of the present invention. Each optional manner introduced in each embodiment solution can be combined and cross-referenced with each other without conflict, so as to extend a variety of possible embodiment solutions, all of which can be considered as the embodiment solutions disclosed and made public by the embodiments of the present invention.

[0077] Although the embodiments of the present invention are disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A boundary scan circuit, characterized in that, Comprising: A test access port controller, connected to the boundary scan chain, for providing serial input data to be tested for the boundary scan chain and receiving serial test result data output by the boundary scan chain; A user-defined register for providing selection control signals for the selection terminals of a plurality of multiplexers; A boundary scan chain having a plurality of stages connected in series, wherein each stage further comprises: A scan sub-chain comprising a plurality of boundary scan cells connected in series, each boundary scan cell corresponding to one or more pads; wherein, the boundary scan cells comprised in the same-stage scan sub-chain correspond to pads having the same packaging requirements; Scan bypass registers respectively connected in parallel with the scan sub-chain; A multiplexer, whose input terminals are respectively connected to the output terminals of the scan sub-chain and the scan bypass registers, for determining the output mode of the serial input data according to the selection control signal; Wherein, the input terminals of the scan sub-chain and the scan bypass registers of the first-stage boundary scan chain receive the serial input data to be tested, the output terminals of the multiplexers of each stage of the boundary scan chain are respectively connected to the input terminals of the scan sub-chain and the scan bypass registers of the next stage of the boundary scan chain, and the output of the multiplexer of the last stage of the boundary scan chain is used as the serial test result data; The test access port controller has a test signal input terminal and a test signal output terminal, the test signal input terminal provides serial input data to be tested for the boundary scan chain, the test signal output terminal receives the serial test result data output by the boundary scan chain, and the entire boundary scan circuit only requires one serial test input data line and one serial test output data line; When the selection control signal of the multiplexer in the same stage of the scan sub-chain is a first preset signal, the scan sub-chain receives the input data of the test signal input terminal and outputs its own data to the test signal output terminal; the first preset signal is 0 or low level; the scan bypass register is used to receive the input data of the test signal input terminal and output its own data to the test signal output terminal when the selection control signal of the multiplexer in the same stage is a second preset signal; the second preset signal is 1 or high level.

2. The boundary scan circuit according to claim 1, wherein The user-defined register is associated with a user input signal to set the selection control signal of the multiplexer of each stage according to the packaging requirements.

3. The boundary scan circuit according to claim 2, wherein When the packaging requirements specify that the first pad needs to be scanned and tested, determine the first scan sub-chain where the first pad is located and connect the first scan sub-chain to the boundary scan chain.

4. The boundary scan circuit according to claim 3, wherein When the packaging requirements specify that the second pad does not need to be scanned and tested, determine the second scan sub-chain where the second pad is located and bypass the second scan sub-chain from the boundary scan chain.

5. The boundary scan circuit according to claim 4, wherein The scan bypass register includes a bypass enable signal terminal, wherein the bypass enable signal has the same input terminal as the selection control signal of the multiplexer in the same stage.

6. The boundary scan circuit according to claim 1, wherein The type of the boundary scan cell is selected according to the direction or attribute of the corresponding pad.

7. A boundary scan test method for a boundary scan circuit based on claim 1, characterized in that, Comprising: Step S1: According to predefined encapsulation requirements, divide multiple boundary scan cells into different scan sub-chains, and connect each boundary scan cell to one or more pads; Step S2: Determine the arrangement order of multiple scan sub-chains in the boundary scan chain; Step S3: Construct a boundary scan chain according to the determined division method of the scan sub-chains and the arrangement order; Step S4: Provide the serial input data to be tested to the boundary scan chain, perform boundary scan testing on one or more scan sub-chains, and receive the test results output by the boundary scan chain.

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