Extreme ultraviolet lithography mask and method for manufacturing the same

Abstract

An extreme ultraviolet lithography mask and a method for manufacturing the same, the method for manufacturing the extreme ultraviolet lithography mask comprising forming a multi-layer reflective layer, forming a buffer layer on the multi-layer reflective layer, and forming an absorption layer on the multi-layer reflective layer. Before patterning the absorption layer, an outer portion of the absorption layer is removed. Then a photoresist layer is deposited on the top surface of the absorption layer and on the sidewalls of the absorption layer. Then the photoresist layer is patterned, and in the presence of the patterned photoresist layer, the absorption layer is etched by a plasma etching process. During the plasma etching process, the photoresist layer on the sidewalls of the absorption layer helps to improve the uniformity of etching the absorption layer.

Description

Technical Field

[0001] The present disclosure relates to the field of lithography. More specifically, the present disclosure relates to forming a mask for a lithography process. Background Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have produced generations of integrated circuits, each with smaller and more complex circuits than the previous generation. In the course of integrated circuit evolution, the number of interconnected devices per chip area has generally increased, while the minimum component size that can be formed using manufacturing processes has decreased.

[0003] Such scaling down processes generally provide benefits by increasing production efficiency and reducing associated costs. Such scaling down also increases the complexity of integrated circuit processing and manufacturing. To achieve these advances, similar evolutions in integrated circuit processing and manufacturing are required. For example, the demand for performing higher resolution lithography processes is growing.

[0004] EUV lithography is a lithography process that uses a scanner that uses light having a wavelength of about 1 nanometer to 20 nanometers in the extreme ultraviolet region. The EUV scanner provides a desired pattern on an absorber layer formed on a reflective mask. The pattern of the absorber layer is used to form pattern-based features on a semiconductor wafer. Summary of the invention

[0005] According to some embodiments of the present disclosure, an EUV lithography mask is provided, comprising a substrate, a multi-layer reflective layer, a buffer layer, and an absorption layer, wherein the multi-layer reflective layer is located on the substrate and configured to reflect ultraviolet radiation during an EUV lithography process, the buffer layer is located on the multi-layer reflective layer, and the absorption layer is located on the buffer layer and configured to absorb ultraviolet light during the EUV lithography process. At least one peripheral edge of the absorption layer is laterally separated from a corresponding peripheral edge of the buffer layer, so that a peripheral portion of a top surface of the buffer layer is exposed.

[0006] According to some embodiments of the present disclosure, a method of manufacturing an EUV lithography mask is provided, including forming a multi-layer reflective layer on a substrate, the multi-layer reflective layer being configured to reflect ultraviolet radiation during an EUV lithography process. The method includes forming a buffer layer on the multi-layer reflective layer. The method includes forming an absorption layer on the buffer layer, and the absorption layer has a lateral width less than a lateral width of the buffer layer. The absorption layer is configured to absorb ultraviolet light during the EUV lithography process.

[0007] According to some embodiments of the present disclosure, a method for manufacturing an EUV lithography mask is provided, including forming a multi-layer reflective layer on a substrate, the multi-layer reflective layer being configured to reflect ultraviolet light during an EUV lithography process. The method includes forming a buffer layer on the multi-layer reflective layer and forming an absorption layer on the buffer layer. The absorption layer is configured to absorb ultraviolet light during the EUV lithography process. The method includes removing an outer portion of the absorption layer by a first etching process to expose an outer portion of a top surface of the buffer layer. The method includes forming a groove in the absorption layer by a second etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an EUV lithography system according to one embodiment;

[0009] Figure 2 is a cross-sectional view of a lithography mask at an intermediate stage of a process according to one embodiment;

[0010] Figure 3 is a cross-sectional view of a lithography mask at an intermediate stage of a process according to one embodiment;

[0011] Figure 4A is a cross-sectional view of a lithography mask at an intermediate stage of a process according to an embodiment;

[0012] Figure 4B According to one embodiment, Figure 4A Top view of the medium lithography mask;

[0013] Figure 5 is a cross-sectional view of a lithography mask at an intermediate stage of a process according to an embodiment;

[0014] Figure 6 is a cross-sectional view of a lithography mask at an intermediate stage of a process according to one embodiment;

[0015] Figure 7 is a cross-sectional view of a lithography mask at an intermediate stage of a process according to one embodiment;

[0016] Figure 8 is a cross-sectional view of a lithography mask according to one embodiment;

[0017] Fig. 9 is a cross-sectional view of a lithography mask at an intermediate stage of a process according to one embodiment;

[0018] Fig.10 is a flow chart of a method for forming a lithography mask according to an embodiment;

[0019] Fig.11 The present invention is a flow chart of a method for forming a lithography mask according to an embodiment.

[0020]

Explanation of symbols

[0021] 100: Lithography System

[0022] 102: Radiation Source

[0023] 104:Illuminator

[0024] 106: Mask

[0025] 108: Projection optical box

[0026] 110: Target

[0027] 112:Substrate

[0028] 114:Multi-layer reflective layer

[0029] 116: Buffer layer

[0030] 118: Absorption layer

[0031] 120: first absorption layer

[0032] 122: Second absorption layer

[0033] 124: Photoresist layer

[0034] 126: Exposed part

[0035] 128: Photoresist layer

[0036] 130: Groove

[0037] 134: Groove

[0038] 140:Mask

[0039] 1000:Method

[0040] 1002,1004,1006: Steps

[0041] 1100: Method

[0042] 1102,1104,1106,1108,1110: Steps

[0043] W: Width DETAILED DESCRIPTION

[0044] In the following description, a number of thicknesses and materials are described for various layers and structures within the lithography mask. For various embodiments, specific dimensions and materials are given by way of example. Those skilled in the art will appreciate that in view of the present disclosure, other dimensions and materials may be used in many cases without departing from the scope of the present disclosure.

[0045] In order to realize the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components and configurations, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0046] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0047] In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the present disclosure. However, those skilled in the art will appreciate that the present disclosure may be practiced without these specific details. In other examples, well-known structures associated with electronic components and manufacturing techniques are not described in detail to avoid unnecessary confusion in the description of the embodiments of the present disclosure.

[0048] Unless the context requires otherwise, in the specification and claims, the word "comprise" and variations such as "comprises" and "comprising" are to be construed in their open inclusive sense, that is, to mean "including but not limited to."

[0049] The use of ordinal numbers such as first, second, and third does not necessarily indicate an order of ranking, but may simply distinguish between multiple instances of an action or structure.

[0050] References throughout this specification to "one embodiment" or "an embodiment" mean that the particular features, structures, or characteristics described with respect to that embodiment are included in at least one embodiment. Therefore, the appearance of "in one embodiment" or "in an embodiment" in various places throughout this specification does not necessarily all refer to the same embodiment. In addition, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0051] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally used in a sense including "and / or" unless the content clearly dictates otherwise.

[0052] Figure 1 is a block diagram of an EUV lithography system 100 according to one embodiment. The system includes a radiation source 102, an illuminator 104, a mask 106, a projection optics box 108, and a target 110. The components of the system 100 cooperate together to perform an EUV lithography process.

[0053] The radiation source 102 outputs ultraviolet radiation. The ultraviolet radiation has a wavelength of about 1 nanometer to 20 nanometers. The ultraviolet radiation may include other wavelengths without departing from the scope of the present disclosure.

[0054] Illuminator 104 receives ultraviolet radiation from radiation source 102. Illuminator 104 may include refractive optics (e.g., a single lens or a lens system with multiple lenses (zone plates)) and / or reflective optics (e.g., a single mirror or a mirror system with multiple mirrors). Illuminator 104 directs ultraviolet radiation from radiation source 102 onto mask 106.

[0055] The mask 106 receives the ultraviolet radiation from the illuminator 104. The mask 106 can be a transmissive mask or a reflective mask. In one embodiment, the mask 106 is a reflective mask, an example of which will be described in further detail later. The mask 106 can be combined with other resolution enhancement techniques, such as a phase-shifting mask and / or optical proximity correction.

[0056] The projection optical box 108 receives the ultraviolet radiation from the mask 106. The projection optical box 108 may have refractive optics or reflective optics. The radiation (e.g., patterned radiation) reflected from the mask 106 is collected by the projection optical box 108. The projection optical box 108 may include a magnification of less than one (thereby reducing the patterned image included in the radiation). The projection optical box 108 directs the ultraviolet radiation onto the target 110.

[0057] In one embodiment, the target 110 comprises a semiconductor wafer. During EUV lithography, a photoresist layer typically covers the target 110. The photoresist assists in patterning the surface of the semiconductor wafer according to the pattern of the mask 106.

[0058] Projection optics box 108 focuses the EUV light onto target 110. The EUV light illuminates the photoresist with a pattern corresponding to the pattern of mask 106. The exposed portion of the photoresist undergoes a chemical change that removes a portion of the photoresist. This pattern leaves the photoresist on the semiconductor wafer in the pattern of mask 106. In the presence of the patterned photoresist, an etching process, a thin film deposition process, and / or a doping process is performed.

[0059] Generally speaking, a large number of masks 106 are used during the manufacture of a single semiconductor wafer. Each mask 106 has a specific pattern corresponding to a semiconductor manufacturing process. One or more etching, deposition or doping processes are performed according to each mask 106.

[0060] If defects are present in the mask 106, corresponding defects may occur in various semiconductor processes associated with the mask 106. Defects propagating from the mask 106 to the manufacturing processes may result in a semiconductor device that does not function properly. A semiconductor device that does not function properly represents a waste of a large amount of resources, where resources come from the large amount of time, expensive tools, and expensive materials required to manufacture each semiconductor device. Therefore, it is beneficial to minimize defects in the mask 106.

[0061] about Figure 1 The lithography system 100 described is an example of some components in the lithography system. The lithography system may include other components, processes and configurations other than those described above without departing from the scope of the present disclosure.

[0062] According to one embodiment, Figure 2 1 is a cross-sectional view of an EUV lithography mask 106 during an intermediate stage of the process. The mask 106 includes a substrate 112, a multi-layer reflective layer 114 on the substrate 112, a buffer layer 116 on the multi-layer reflective layer 114, and an absorber layer 118 on the buffer layer 116. The manufacturing process of the mask 106 ultimately produces a mask 106 having a selected pattern in the absorber layer 118.

[0063] The substrate 112 includes a low thermal expansion material. The low thermal expansion material substrate 112 can minimize image distortion caused by heating the mask 106. The low thermal expansion material substrate 112 can include a material with a low defect level and a smooth surface.

[0064] In one embodiment, the substrate 112 may include SiO 2 The substrate 112 may be doped with titanium dioxide. The substrate 112 may include other low thermal expansion materials besides those described above without departing from the scope of the present disclosure.

[0065] Although not shown in the figure, in one embodiment, the substrate 112 can be located on a conductive layer. During the manufacture and use of the mask 106, the conductive layer can assist in electrostatically adsorbing the mask 106. In one embodiment, the conductive layer includes chromium nitride. The conductive layer can include other materials without departing from the scope of the present disclosure.

[0066] The mask 106 includes a multi-layer reflective layer 114. The multi-layer reflective layer 114 is located on the substrate 112. The multi-layer reflective layer 114 is configured to reflect extreme ultraviolet light during a lithography process using the mask 106. The reflective properties of the multi-layer reflective layer 114 are described in more detail later.

[0067] In one embodiment, the multi-layer reflective layer 114 operates according to the reflective properties of the interface between two materials. Specifically, when light is incident on the interface between two materials with different refractive indices, reflection of the light will occur. When the difference in refractive index is greater, a larger portion of the light is reflected.

[0068] One technique to increase the proportion of reflected light is to include multiple interfaces by depositing multiple layers of alternating materials. The properties and dimensions of the materials can be chosen so that light reflects from different interfaces and interferes constructively. However, the absorption properties of the materials used in the multiple layers may limit the reflectivity that can be achieved.

[0069] Therefore, the multi-layer reflective layer 114 includes a plurality of paired material layers. Each pair of material layers includes a first material layer and a second material layer. The materials and thicknesses of the material layers are selected to promote reflection and constructive interference of extreme ultraviolet light.

[0070] In one embodiment, each pair of material layers includes a molybdenum layer and a silicon layer. In one example, the thickness of the molybdenum layer is between 2 nanometers and 4 nanometers. In one example, the thickness of the silicon layer is between 3 nanometers and 5 nanometers. The thickness of the material layers in the multilayer reflective layer 114 is selected based on the expected wavelength of the extreme ultraviolet light used in the lithography process and the expected angle of incidence of the extreme ultraviolet light during the lithography process. The wavelength of the extreme ultraviolet light is between 1 nanometer and 20 nanometers. According to one embodiment, the number of pairs of material layers is between 20 pairs and 60 pairs. Other materials, thicknesses, pairs, and configurations of the material layers in the multilayer reflective layer 114 may be used without departing from the scope of the present disclosure. Other wavelengths of extreme ultraviolet light may be used without departing from the scope of the present disclosure.

[0071] In one embodiment, the buffer layer 116 is disposed on the multi-layer reflective layer 114. One purpose of the buffer layer 116 is to protect the multi-layer reflective layer 114 during the etching process of the absorption layer 118. Therefore, the buffer layer 116 includes a material that is resistant to the etching process of the absorption layer 118. The etching process and material of the absorption layer 118 will be described in more detail later.

[0072] In one embodiment, the buffer layer 116 includes ruthenium. The buffer layer 116 may include a compound of ruthenium (including ruthenium boride and ruthenium silicide). The buffer layer 116 may include chromium, chromium oxide, or chromium nitride. The buffer layer 116 may be deposited by a low temperature deposition process to prevent the buffer layer 116 from diffusing into the multilayer reflective layer 114. In one embodiment, the buffer layer 116 has a thickness between 2 nanometers and 4 nanometers. Other materials, deposition processes, and thicknesses may be used for the buffer layer 116 without departing from the scope of the present disclosure.

[0073] Absorber layer 118 is disposed on buffer layer 116. The material of absorber layer 118 is selected so that absorber layer 118 has a high absorption coefficient for the wavelength of EUV radiation used in the lithography process of mask 106. In other words, the material of absorber layer 118 is selected to absorb EUV radiation.

[0074] In one embodiment, the thickness of the absorber layer 118 is between 40 nanometers and 100 nanometers. In one embodiment, the absorber layer 118 comprises a material selected from the group consisting of chromium, chromium oxide, titanium nitride, tantalum nitride, tantalum, titanium, aluminum copper, palladium, tantalum boronitride, tantalum oxyboride, aluminum oxide, molybdenum, or other suitable materials. Other materials and thicknesses may be used for the absorber layer 118 without departing from the scope of the present disclosure.

[0075] In one embodiment, the absorption layer 118 includes a first absorption layer 120 and a second absorption layer 122. The first absorption layer 120 is located on the buffer layer 116. The second absorption layer 122 is located on the first absorption layer 120.

[0076] In one embodiment, the first absorption layer 120 includes tantalum boronitride. The second absorption layer 122 includes tantalum oxyboride. The thickness of the first absorption layer 120 is between 30 nanometers and 80 nanometers. The thickness of the second absorption layer 122 is between 1 nanometer and 40 nanometers. Without departing from the scope of the present disclosure, the absorption layer 118 may include different materials, thicknesses, and numbers of material layers than those described above. In one embodiment, the absorption layer 118 includes only a single absorption layer. Therefore, the absorption layer 118 may be an absorption layer.

[0077] Figure 2 The material layer of the mask 106 shown in the figure may be formed by various thin film deposition processes. The thin film deposition process may include a physical vapor deposition process (e.g., evaporation and DC magnetron sputtering), an electroplating process (e.g., chemical plating or electroplating), a chemical vapor deposition process (e.g., atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, ion beam deposition, spin coating, metal organic decomposition) and / or other methods known in the art.

[0078] Figure 3FIG. 1 is a cross-sectional view of a lithography mask 106 at an intermediate stage of a process according to an embodiment. Figure 3 In FIG. 1 , a photoresist layer 124 has been deposited on the absorber layer 118. Specifically, the photoresist layer 124 has been deposited on the second absorber layer 122. The photoresist layer 124 has been patterned and developed to expose the top surface peripheral edge of the absorber layer 118.

[0079] The photoresist layer 124 may be patterned using conventional lithography techniques, which include exposing the photoresist layer 124 to light or an electron beam through a lithography mask, and developing the photoresist to remove the outer periphery of the photoresist layer 124 according to the pattern of the lithography mask.

[0080] In one embodiment, the width of the exposed portion of the top surface of the second absorption layer 122 is between 0.2 mm and 2 mm. In other words, the distance between the edge of the photoresist layer 124 and the edge of the absorption layer 118 is between 0.2 mm and 2 mm. Figure 3 1, but from a top view, the mask 106 can be substantially rectangular. The exposed portion of the absorbent layer 118 corresponds to the outer edge of the rectangle. In view of the present disclosure, those skilled in the art will appreciate that the exposed portion of the absorbent layer 118 can have other sizes and shapes without departing from the scope of the present disclosure. For example, it is possible for the exposed portion of the top surface of the second absorbent layer 122 to have other widths without departing from the scope of the present disclosure. For example, in other embodiments, the width of the exposed portion of the top surface of the second absorbent layer 122 is between 0.2 mm and 3 mm.

[0081] Figure 4A FIG. 1 is a cross-sectional view of the mask 106 at an intermediate stage of the manufacturing process according to one embodiment. Figure 4A In the illustrated embodiment, the outer portion of the absorber layer 118 has been removed. The outer portion of the absorber layer 118 can be removed by an etching process in the presence of the patterned photoresist layer 124. The photoresist layer 124 is then removed. As a result of the etching process, the outer portion of the top surface of the buffer layer 116, namely the exposed portion 126, is exposed. The exposed portion 126 corresponds to Figure 3 1. The exposed portion 126 has a width W between 0.2 mm and 2 mm. The exposed portion 126 extends around the perimeter of the mask 106. The exposed portion 126 should be wide enough to allow the photoresist to stably cover the sidewalls of the absorber layer 118, for reasons that will be described in more detail later. The exposed portion 126 should be narrow enough to allow the absorber layer 118 to be completely patterned according to the pattern selected for the mask 106 to be used in the EUV lithography process. Therefore, the range of values ​​for the width may be selected based in part on the specific type of photoresist that is used in the patterning of the absorber layer 118.

[0082] In one embodiment, the etching process may include dry plasma etching, wet etching and / or other etching methods. In this embodiment, a multi-step dry etching is performed. In one embodiment, the etching process may include a two-step plasma etching process. The second absorption layer 122 may be etched by a first plasma etching process. The first absorption layer 120 may be etched by a second plasma etching process.

[0083] In view of the present disclosure, those skilled in the art will appreciate that, without departing from the scope of the present disclosure, other than the Figure 3 and Figure 4A Other processes than those described above to form a Figure 4A The mask of the pattern.

[0084] Figure 4B According to one embodiment, Figure 4A A top view of the lithography mask 106. Figure 4B , the absorbent layer 118 is located on the buffer layer 116. The absorbent layer 118 does not completely cover the top surface of the buffer layer 116. The absorbent layer 118 does not cover the external exposed portion 126 of the top surface of the buffer layer 116. The width W of the exposed portion 126 of the top surface of the buffer layer 116 is between 0.2 mm and 2 mm. Other widths are possible for the exposed portion 126 without departing from the scope of the present disclosure. For example, according to other embodiments of the present disclosure, the width W of the exposed portion 126 of the top surface of the buffer layer 116 is between 0.2 mm and 3 mm. Although the width W of the exposed portion 126 is between 0.2 mm and 3 mm, the width W of the exposed portion 126 is between 0.2 mm and 3 mm. Figure 4B The lithography mask 106 is shown to be identical on all sides, but in some embodiments, the exposed portions 126 may have different widths on different sides of the lithography mask 106 .

[0085] In one embodiment, the lateral width of the absorbent layer 118 is less than the lateral width of the buffer layer 116. In one embodiment, the outer periphery of the top surface of the buffer layer 116 is exposed by the absorbent layer 118 because the absorbent layer 118 does not cover the outer periphery of the top surface of the buffer layer 116. In one embodiment, the exposed portion 126 has a frame shape surrounding the absorbent layer 118. The mask 106 is substantially rectangular, but it is possible for the mask 106 to have other shapes without departing from the scope of the present disclosure.

[0086] Figure 5 FIG. 1 is a cross-sectional view of a lithography mask 106 at an intermediate stage of a process according to an embodiment. Figure 51 , a photoresist layer 128 has been deposited on the absorber layer 118. The photoresist layer 128 is located on the top surface of the absorber layer 118, on the side surfaces of the absorber layer 118, and on the exposed portion 126 of the buffer layer 116. The photoresist layer 128 is used to assist in the patterning of the absorber layer 118 according to the final pattern of the mask 106. As described in more detail later, removing the outer perimeter of the absorber layer 118 so that the photoresist layer 128 covers the side surfaces of the absorber layer 118 can produce several benefits.

[0087] Figure 6 is a cross-sectional view of a lithography mask 106 according to one embodiment. Figure 6 In the embodiment of the present invention, the photoresist layer 128 has been patterned. The patterning results in grooves 130 formed in the photoresist layer 128. A portion of the top surface of the absorption layer 118 is exposed to the outside through the grooves 130 formed in the photoresist layer 128.

[0088] In one embodiment, the grooves 130 are formed in the photoresist layer 128 by exposing the photoresist layer 128 to an electron beam passing through a mask. Patterning may include exposing the photoresist layer 128 to the electron beam, baking the photoresist layer 128, and developing the photoresist layer 128, so that the pattern of the grooves 130 remains in the photoresist layer 128. In view of the present disclosure, those skilled in the art will appreciate that many types of lithography and patterning processes may be used to pattern the photoresist layer 128, such as Figure 6 as shown in .

[0089] Figure 7 FIG. 1 is a cross-sectional view of a lithography mask 106 at an intermediate stage of the process according to one embodiment. The mask 106 has been sent to an etching process. Figure 7 The etching process etches the exposed portion of the absorption layer 118 through the groove 130 in the photoresist layer 128. The result of the etching process is Figure 6 The absorber layer 118 is etched in the pattern of the photoresist layer 128. The etching process leaves trenches 134 in the absorber layer 118 in the pattern of the photoresist layer 128.

[0090] In one embodiment, the etching process stops at the buffer layer 116. Therefore, the top surface of the buffer layer 116 is exposed through the trench 134 in the absorber layer 118. The etching process for the absorber layer 118 is selected so that the absorber layer 118 is selectively etched relative to the buffer layer 116. Therefore, the process that etches the absorber layer 118 does not etch the buffer layer 116.

[0091] In one embodiment, the etching process for the absorber layer 118 is a plasma etching process. The plasma etching process includes generating a plasma with a chlorine-containing gas. The chlorine plasma etching process selectively etches the absorber layer 118 relative to the buffer layer 116. In one embodiment, the plasma etching process may begin with a fluorine plasma to etch the second absorber layer 122. The plasma etching process may then switch to a chlorine plasma to etch the first absorber layer 120. Other types of etching processes may be utilized without departing from the scope of the present disclosure.

[0092] Figure 8 is a cross-sectional view of the mask 106 according to one embodiment. Figure 8 , the photoresist layer 128 has been removed. The absorber layer 118 remains patterned with the grooves 134. The top surface of the buffer layer 116 is exposed through the grooves 134 in the absorber layer 118 and along the outer periphery of the mask 106.

[0093] Through Fig. 9 The different processes of mask manufacturing are compared to illustrate Figures 2 to 8 Several benefits of the mask manufacturing process are shown.

[0094] Fig. 9 1 is a cross-sectional view of a lithography mask 140 at an intermediate stage of a process according to an embodiment. The lithography mask 140 includes a substrate 112, a multi-layer reflective layer 114, a buffer layer 116, and an absorption layer 118. A patterned photoresist layer 128 covers the absorption layer 118. A groove 134 has been etched in the absorption layer 118 according to the patterned photoresist layer 128.

[0095] Fig. 9 The lithography mask 140 is similar in many respects to Figure 7 However, the lithography mask 140 is different from Figure 7 One difference between the lithography mask 106 and the lithography mask 106 is that in the mask 140, the photoresist layer 128 does not cover Fig. 9 This is because, unlike the mask 106, the absorption layer 118 of the mask 140 is not patterned to expose the outer periphery of the buffer layer 116. Specifically, Figure 3 and Figure 4A The lithography process etches the outer periphery of the absorption layer 118, thereby exposing the exposed portion 126 of the top surface of the buffer layer 116. Figure 3 and Figure 4A One of the results of the lithography process shown in is, Figures 5 to 7 The photoresist layer 128 covers the side surface of the absorption layer 118 in the mask 106 .

[0096] Therefore, in Figure 7During the described plasma etching process for forming the trench 134 in the absorption layer 118 of the mask 106 , the side surfaces of the absorption layer 118 are covered by the photoresist layer 128 . Fig. 9 The photoresist layer 128 of the middle mask 140 does not cover the side surface of the absorption layer 118. Therefore, the side surface of the absorption layer 118 in the mask 140 is exposed during the plasma etching process of etching the trench 134.

[0097] The absorption layer 118 is relatively conductive compared to the multi-layer reflective layer 114 in the substrate 112. If the side surface of the absorption layer 118 is exposed during the plasma etching process, a relatively high voltage difference may be generated between different regions of the top surface of the absorption layer 118 during the plasma etching process. As a result, during the plasma etching process, the plasma etches different regions of the absorption layer 118 at a faster rate.

[0098] Different regions of the absorber layer 118 are etched at different rates, resulting in differences between the trenches 134 located in different places of the absorber layer 118. This result, in turn, causes differences between sites when the semiconductor wafer is processed using the mask 140. The differences between sites can cause some regions of the semiconductor wafer to have defects. These defects can cause portions of the integrated circuits produced from the semiconductor wafer to be inoperable. As previously described, this can correspond to a huge waste of money, time, and resources.

[0099] Figure 8 The mask 106 is not affected by these disadvantages. Figure 7 During the plasma etching process, the outer side surface or sidewall of the absorption layer 118 in the mask 106 is covered by the photoresist layer 128, so the surface voltage of the absorption layer 118 is stable. Because the surface voltage of the absorption layer 118 is stable, the etching rate of the absorption layer 118 is constant at all exposed positions of the absorption layer 118. Further, the semiconductor wafer processed with the mask 106 will not suffer from the plasma etching process. Fig. 9 The semiconductor wafer processed by the mask 140 may suffer from defects.

[0100] Fig.10 is a flow chart of a method 1000 for forming an EUV lithography mask according to one embodiment. In step 1002, the method 1000 includes forming a multi-layer reflective layer on a substrate, the multi-layer reflective layer being configured to reflect ultraviolet radiation during an EUV lithography process. An example of a substrate is Figure 2 An example of a multi-layer reflective layer is Figure 2 The multilayer reflective layer 114 is formed on the multilayer reflective layer. At step 1004, the method 1000 includes forming a buffer layer on the multilayer reflective layer. An example of a buffer layer is Figure 2At step 1006, the method 1000 includes forming an absorber layer on the buffer layer, wherein the absorber layer has a lateral width less than a lateral width of the buffer layer, wherein the absorber layer is configured to absorb ultraviolet light during an EUV lithography process. An example of an absorber layer is Figure 2 The absorption layer 118 is provided.

[0101] Fig.11 is a flow chart of a method 1100 for forming an EUV lithography mask according to one embodiment. At step 1102, the method 1100 includes forming a multi-layer reflective layer on a substrate, the multi-layer reflective layer being configured to reflect ultraviolet light during an EUV lithography process. An example of a substrate is Figure 2 An example of a multi-layer reflective layer is Figure 2 The multilayer reflective layer 114. At step 1104, the method 1100 includes forming a buffer layer on the multilayer reflective layer. An example of a buffer layer is Figure 2 At step 1106, method 1100 includes forming an absorber layer on the buffer layer, wherein the absorber layer is configured to absorb ultraviolet light during the EUV lithography process. An example of an absorber layer is Figure 2 At step 1108, the method 1100 includes removing an outer portion of the absorber layer by a first etching process to expose an outer portion of the top surface of the buffer layer. At step 1110, the method 1100 includes forming a trench in the absorber layer by a second etching process.

[0102] In one embodiment, an EUV lithography mask includes a substrate and a multi-layer reflective layer, the multi-layer reflective layer is located on the substrate and is configured to reflect ultraviolet radiation during an EUV lithography process. The mask includes a buffer layer and an absorber layer, the buffer layer is located on the multi-layer reflective layer, and the absorber layer is located on the buffer layer and is configured to absorb ultraviolet light during an EUV lithography process. At least one peripheral edge of the absorber layer is laterally separated from a corresponding peripheral edge of the buffer layer, so that a peripheral portion of a top surface of the buffer layer is exposed. In some embodiments, the peripheral edge of the absorber layer is laterally separated from the corresponding peripheral edge of the buffer layer by 0.2 mm to 2 mm. In some embodiments, the absorber layer includes a plurality of grooves, the grooves exposing the top surface of the buffer layer. In some embodiments, the buffer layer includes ruthenium. In some embodiments, the absorber layer includes tantalum. In some embodiments, the lateral width of the absorber layer is less than the lateral width of the buffer layer along the same direction. In some embodiments, the multi-layer reflective layer includes a plurality of paired material layers, the paired material layers are configured to jointly reflect ultraviolet radiation during an EUV lithography process.

[0103] In one embodiment, a method of manufacturing an EUV lithography mask includes forming a multilayer reflective layer on a substrate, the multilayer reflective layer configured to reflect ultraviolet radiation during an EUV lithography process. The method includes forming a buffer layer on the multilayer reflective layer. The method includes forming an absorber layer on the buffer layer, and the absorber layer has a lateral width less than a lateral width of the buffer layer. The absorber layer is configured to absorb ultraviolet light during the EUV lithography process. In some embodiments, forming the absorber layer includes depositing the absorber layer on the buffer layer, and exposing a peripheral periphery of a top surface in the buffer layer by removing an outer portion of the absorber layer. In some embodiments, a photoresist layer is deposited on the top surface of the absorber layer, on the sidewalls of the absorber layer, and on the peripheral periphery of the top surface in the buffer layer, patterning the photoresist layer and performing plasma etching to form a groove in the absorber layer when the photoresist layer covers the sidewalls of the absorber layer. In some embodiments, the plasma etching includes chlorine gas. In some embodiments, the plasma etching selectively etches the absorber layer at a faster rate relative to the buffer layer. In some embodiments, the substrate includes silicon dioxide. In some embodiments, the multi-layer reflective layer includes a plurality of paired material layers, and the paired material layers are configured to jointly reflect ultraviolet light during an EUV lithography process.

[0104] In one embodiment, a method for manufacturing an EUV lithography mask includes forming a multilayer reflective layer on a substrate, the multilayer reflective layer configured to reflect ultraviolet light during an EUV lithography process. The method includes forming a buffer layer on the multilayer reflective layer and forming an absorber layer on the buffer layer. The absorber layer is configured to absorb ultraviolet light during the EUV lithography process. The method includes removing an outer portion of the absorber layer by a first etching process to expose an outer portion of a top surface of the buffer layer. The method includes forming a groove in the absorber layer by a second etching process. In some embodiments, the sidewalls of the absorber layer are covered with a photoresist layer after the first etching process, and the second etching process is performed while the photoresist layer covers the sidewalls of the absorber layer. In some embodiments, covering the sidewalls of the absorber layer with the photoresist layer includes covering an outer portion of the top surface in the buffer layer with the photoresist layer. In some embodiments, the second etching process selectively etches the absorber layer at a faster rate relative to the buffer layer. In some embodiments, the second etching process is a plasma etching process. In some embodiments, the plasma etching process includes etching the absorber layer with chlorine gas.

[0105] The various embodiments described above may be combined to provide additional embodiments. Aspects of the embodiments may be modified, if necessary, to employ concepts of various patents, applications, and publications to provide yet further embodiments.

[0106] In light of the above detailed description, these and other changes may be made to the embodiments. In general, in the above claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to which the claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. An extreme ultraviolet lithography mask, It is characterized in that include: a substrate; a multi-layer reflective layer disposed on the substrate and configured to reflect ultraviolet radiation during an EUV lithography process; a buffer layer, located on the multi-layer reflective layer; as well as an absorber layer disposed on the buffer layer and configured to absorb ultraviolet radiation during an EUV lithography process, wherein a first peripheral edge of the absorber layer is laterally separated from a first peripheral edge corresponding to the buffer layer by a first distance, and a second peripheral edge of the absorber layer is laterally separated from a second peripheral edge corresponding to the buffer layer by a second distance, such that a peripheral portion of a top surface of the buffer layer is exposed, The first peripheral edge of the absorption layer is directly connected to the second peripheral edge of the absorption layer, and the first distance and the second distance are greater than or equal to 0.2 mm.

2. The EUV lithography mask according to claim 1, It is characterized in that The first distance and the second distance are between 0.2 mm and 2 mm.

3. The EUV lithography mask according to claim 1, It is characterized in that The absorption layer includes a plurality of grooves, and the grooves expose the top surface of the buffer layer.

4. The EUV lithography mask according to claim 1, It is characterized in that The buffer layer includes ruthenium.

5. The EUV lithography mask according to claim 1, It is characterized in that The absorber layer includes tantalum.

6. The EUV lithography mask according to claim 1, It is characterized in that A lateral width of the absorption layer is smaller than a lateral width of the buffer layer along the same direction.

7. The EUV lithography mask according to claim 1, It is characterized in that The multi-layer reflective layer includes a plurality of paired material layers configured to collectively reflect ultraviolet radiation during an EUV lithography process.

8. A method for manufacturing an extreme ultraviolet lithography mask, It is characterized in that include: forming a multi-layer reflective layer on a substrate, the multi-layer reflective layer being configured to reflect ultraviolet radiation during an EUV lithography process; forming a buffer layer on the multi-layer reflective layer; forming an absorption layer on the buffer layer, wherein the absorption layer has a lateral width smaller than a lateral width of the buffer layer along the same direction, wherein the absorption layer is configured to absorb ultraviolet light during an EUV lithography process; and A photoresist layer is deposited to cover the sidewalls of the peripheral edges of the absorption layer, and a plasma etching is performed using the photoresist layer to form a plurality of trenches in the absorption layer, wherein the photoresist layer after the plasma etching exposes the sidewalls of the plurality of trenches.

9. The method according to claim 8, It is characterized in that Forming the absorption layer includes: depositing the absorber layer on the buffer layer; and A peripheral perimeter of a top surface in the buffer layer is exposed by removing an outer portion of the absorbent layer.

10. The method according to claim 8, It is characterized in that Depositing the photoresist layer includes: Depositing the photoresist layer on the top surface of the absorption layer, on the sidewalls of the peripheral edges of the absorption layer, and on a peripheral periphery of a top surface of the buffer layer; patterning the photoresist layer; and When the photoresist layer covers the top surface of the absorption layer, the side walls of the peripheral edges of the absorption layer, and the peripheral periphery of the top surface in the buffer layer, the plasma etching is performed to form the grooves in the absorption layer.

11. The method according to claim 10, It is characterized in that The plasma etch includes chlorine gas.

12. The method according to claim 10, It is characterized in that The plasma etch selectively etches the absorber layer at a faster rate relative to the buffer layer.

13. The method according to claim 8, It is characterized in that The substrate includes silicon dioxide.

14. The method according to claim 8, It is characterized in that The multi-layer reflective layer includes a plurality of paired material layers, and the paired material layers are configured to jointly reflect ultraviolet light during an extreme ultraviolet lithography process.

15. A method for manufacturing an extreme ultraviolet lithography mask, It is characterized in that include: forming a multi-layer reflective layer on a substrate, the multi-layer reflective layer being configured to reflect ultraviolet light during an EUV lithography process; forming a buffer layer on the multi-layer reflective layer; forming an absorption layer on the buffer layer, wherein the absorption layer is configured to absorb ultraviolet light during an EUV lithography process; Exposing an outer portion of a top surface of the buffer layer by removing an outer portion of the absorber layer using a first etching process of a first photoresist layer; as well as A second etching process using a second photoresist layer is used to form a plurality of grooves in the absorption layer, wherein the second photoresist layer covers a plurality of sidewalls of a plurality of peripheral edges of the absorption layer, and the second photoresist layer after the second etching process exposes a plurality of sidewalls of the plurality of grooves.

16. The method according to claim 15, It is characterized in that Covering the plurality of sidewalls of the plurality of peripheral edges of the absorption layer with the second photoresist layer includes covering the outer portion of the top surface in the buffer layer with the second photoresist layer.

17. The method according to claim 15, It is characterized in that The second etching process selectively etches the absorber layer at a faster rate than the buffer layer.

18. The method according to claim 15, It is characterized in that The second etching process is a plasma etching process.

19. The method according to claim 18, It is characterized in that The plasma etching process includes etching the absorber layer with chlorine gas.

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