Clock tree layout method, device, electronic device and storage medium

Abstract

The present application provides a clock tree layout method, device, electronic device and storage medium, which relates to the field of clock tree technology. First, the tap units are hierarchically connected according to the preset positions of the tap units to form a clock network, and then the buffers are arranged according to the preset positions, and the connection from the clock input port to the clock network is formed through the buffers, and then the tap units that are not connected to the load are deleted, and then some or all of the network segments that are not connected to the tap units are deleted, and finally the delay deviation of each tap unit is determined, and when the delay deviation is greater than the threshold, the tap units and network segments that are not connected to the load are deleted again, until the delay deviation of the tap unit is less than or equal to the threshold, so as to complete the clock tree layout. The clock tree layout method, device, electronic device and storage medium provided by the present application have the advantages of shortening the line length of the clock network, reducing the capacitance between the lines and reducing the clock power consumption.

Description

Technical Field

[0001] The present application relates to the technical field of clock trees, and in particular to a clock tree layout method, device, electronic device and storage medium. Background Art

[0002] Clock tree technology is one of the high-speed clock tree implementation technologies in the field of integrated circuit design. This technology can transmit clock signals over a large area through large drive units and high-level metal routing, reduce the number of integrated circuit devices on the clock trunk path, reduce the line delay on the clock tree trunk path, and thus reduce the total delay of the clock tree. In addition, this technology moves the bifurcation point of the clock path backward, thereby reducing the on-chip error (OCV, On-Chip Variation), which is conducive to improving design performance.

[0003] In order to achieve fast transmission of clock signals, mesh clock tree structures generally use large driver buffers and high-level metal wide lines. Tap units are pre-placed in the design module to connect to it, and the clock signal is transmitted through these tap points, which is conducive to timing convergence, but the mesh clock structure will take up a lot of winding resources. Since the design of CPU and GPU needs to support high-frequency clock signals, and the overall power consumption of the chip is closely related to voltage, capacitance and frequency, reducing the capacitance of the clock network becomes an effective means of low-power design. In terms of physical implementation, due to the use of high-width high-level metal routing, when connected to the clock tap unit inside the module, a huge metal to device gate area ratio will be formed, causing an antenna effect violation. In order to fix this violation, designers need to insert a large number of redundant devices to further compress the effective area of ​​the chip.

[0004] In summary, the mesh clock tree structure provided in the prior art has the problems of high power consumption, high resource occupation and physical design violation. Summary of the invention

[0005] The purpose of the present application is to provide a clock tree layout method, device, electronic device and storage medium to solve the problems of high power consumption, high resource occupation and physical design violation in the mesh clock tree structure in the prior art.

[0006] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0007] In a first aspect, an embodiment of the present application provides a clock tree layout method, the method comprising:

[0008] hierarchically connecting the tap units according to the preset positions of the tap units to form a clock network;

[0009] Arrange buffers at preset positions, and form connections from clock input ports to the clock network through the buffers;

[0010] Delete the tap unit that is not connected to the load;

[0011] Delete some or all network segments that are not connected to tap units;

[0012] Determine the delay deviation of each tap unit, and when the delay deviation is greater than a threshold, delete the tap unit and the network segment that are not connected to the load again until the delay deviation of the tap unit is less than or equal to the threshold, so as to complete the clock tree layout.

[0013] Optionally, when the delay deviation is greater than a threshold, the step of re-deleting the tap unit and the network segment that are not connected to the load includes:

[0014] When the delay deviation is greater than a threshold, restoring at least one tap unit that is not connected to a load and a corresponding network segment;

[0015] The delay deviation of each tap unit is re-determined, and when the delay deviation is greater than a threshold, the tap unit and the network line segment that are not connected to the load are deleted again until the delay deviation of the tap unit is less than or equal to the threshold.

[0016] Optionally, when the delay deviation is greater than a threshold, the step of re-deleting the tap unit and the network segment that are not connected to the load includes:

[0017] When the delay deviation is greater than a threshold, determining a target area with a maximum delay deviation;

[0018] Restoring some or all of the tap units that are not connected to the load in the target area;

[0019] The delay deviation of each tap unit is re-determined, and when the delay deviation is greater than a threshold, the tap unit and the network line segment that are not connected to the load are deleted again until the delay deviation of the tap unit is less than or equal to the threshold.

[0020] Optionally, the step of determining the delay deviation of each tap unit includes:

[0021] Take any tap unit as the target tap unit;

[0022] The delays of the tap units adjacent to the target tap unit are compared with the delay of the target tap unit to determine the delay deviation of each tap unit.

[0023] Optionally, the step of deleting some or all of the network segments that are not connected to the tap units includes:

[0024] The network segments that need to be deleted are determined based on the preset layout rules and antenna effects.

[0025] Optionally, the step of hierarchically connecting the tap units according to preset positions of the tap units includes:

[0026] The tap units are connected in layers using metal lines, wherein the number of layers, width, and spacing of the metal lines are associated with the performance of the buffer and the resistance and capacitance between the metal lines.

[0027] In a second aspect, an embodiment of the present application further provides a clock tree layout device, the device comprising:

[0028] A connection unit, used for connecting the tap units in layers according to the positions of the preset tap units to form a clock network;

[0029] The connection unit is further used to arrange the buffer at a preset position and form a connection from the clock input port to the clock network through the buffer;

[0030] Delete unit, used to delete the tap unit that is not connected to the load;

[0031] Deleting a unit is also used to delete some or all network segments that are not connected to the tap unit;

[0032] The deletion unit is also used to determine the delay deviation of each tap unit, and when the delay deviation is greater than a threshold, the tap unit and the network segment that are not connected to the load are deleted again until the delay deviation of the tap unit is less than or equal to the threshold to complete the clock tree layout.

[0033] Optionally, the deletion unit is used to restore at least one tap unit and a corresponding network segment that are not connected to the load when the delay deviation is greater than a threshold; re-determine the delay deviation of each tap unit, and when the delay deviation is greater than the threshold, re-delete the tap unit and the network segment that are not connected to the load until the delay deviation of the tap unit is less than or equal to the threshold.

[0034] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a memory for storing one or more programs; a processor; and when the one or more programs are executed by the processor, the above method is implemented.

[0035] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon, which implements the above-mentioned method when executed by a processor.

[0036] Compared with the prior art, this application has the following beneficial effects:

[0037] The present application provides a clock tree layout method, device, electronic device and storage medium. First, the tap units are hierarchically connected according to the preset positions of the tap units to form a clock network. Then, buffers are arranged according to the preset positions, and a connection is formed from the clock input port to the clock network through the buffers. Then, the tap units that are not connected to the load are deleted, and then some or all of the network segments that are not connected to the tap units are deleted. Finally, the delay deviation of each tap unit is determined, and when the delay deviation is greater than a threshold, the tap units and network segments that are not connected to the load are deleted again until the delay deviation of the tap unit is less than or equal to the threshold to complete the clock tree layout. Since the present application deletes redundant tap units and network segments when performing clock tree layout, it can effectively shorten the length of the clock network line, reduce the capacitance between lines, and thus reduce clock power consumption. At the same time, due to the reduction in the area of ​​the metal layer, antenna effect violations will also be significantly reduced.

[0038] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 A schematic diagram of a module of an electronic device provided in an embodiment of the present application.

[0041] Figure 2 A flowchart of a clock tree layout method provided in an embodiment of the present application.

[0042] Figure 3 A connection diagram of the tap unit provided in an embodiment of the present application.

[0043] Figure 4 A schematic diagram of the connection between the tap unit and the buffer provided in an embodiment of the present application.

[0044] Figure 5 This is a connection diagram of a tap unit without a load provided in an embodiment of the present application.

[0045] Figure 6 A schematic diagram of a module of a clock tree layout device provided in an embodiment of the present application.

[0046] In the figure: 100 - electronic device; 101 - processor; 102 - memory; 103 - communication interface; 200 - clock tree layout device; 210 - connection unit; 220 - deletion unit. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0048] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0049] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0050] As described in the background technology, at present, while the mesh clock tree structure brings convenience to timing convergence, it also introduces a series of problems such as high power consumption, high resource usage and physical design violations. It is necessary to reduce redundant units and reduce the overall capacitance of the clock structure by optimizing the clock network structure and design process.

[0051] In view of this, the present application provides a clock tree layout method, which reduces power consumption, resource usage and physical design violations by deleting redundant tap units and network segments.

[0052] It should be noted that the clock tree layout method provided in the present application is applied to electronic devices, such as computers, servers and other intelligent terminal electronic devices. Figure 1 A schematic structural block diagram of an electronic device provided in an embodiment of the present application is shown, where the electronic device 100 includes a memory 102, a processor 101, and a communication interface 103. The memory 102, the processor 101, and the communication interface 103 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses or signal lines.

[0053] The memory 102 can be used to store software programs and modules, such as program instructions or modules corresponding to the clock tree layout device 200 provided in the embodiment of the present application. The processor 101 executes various functional applications and data processing by executing the software programs and modules stored in the memory 102, thereby executing the steps of the clock tree layout method provided in the embodiment of the present application. The communication interface 103 can be used to communicate signaling or data with other node devices.

[0054] Among them, the memory 102 can be, but is not limited to, random access memory 102 (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable programmable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0055] The processor 101 may be an integrated circuit chip with signal processing capability. The processor 101 may be a general-purpose processor 101, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0056] Understandably, Figure 1 The structure shown is for illustration only. The electronic device 100 may also include Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown. Figure 1 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0057] The clock tree layout method described in this application is exemplarily described below:

[0058] As an implementation, see Figure 2, the clock tree layout method includes:

[0059] S102, hierarchically connecting the tap units according to preset positions of the tap units to form a clock network.

[0060] S104, arranging buffers at preset positions, and forming a connection from the clock input port to the clock network through the buffers.

[0061] S106, deleting the tap unit that is not connected to the load.

[0062] S108, deleting some or all network segments that are not connected to the tap units.

[0063] S110, determining the delay deviation of each tap unit, and when the delay deviation is greater than a threshold, deleting the tap unit and the network segment that are not connected to the load again, until the delay deviation of the tap unit is less than or equal to the threshold, so as to complete the clock tree layout.

[0064] Among them, the tap unit described in the present application refers to the terminal part of the clock tree, and its back end can be connected to the load. Through the tap unit, the delay function can be realized, and the delay of the units of different modules may be different.

[0065] It should be noted that delay refers to the speed of change of the rising edge and the falling edge in the PWM pulse, that is, the speed of change from 0 to 1, or from 1 to 0.

[0066] The location of the tap unit is generally fixed according to the design requirements. Under different design requirements, the location and number of the tap unit may change. Therefore, when performing clock tree layout, the location of the tap unit can be fixed according to the design requirements, and then the tap units can be hierarchically connected. For example, see Figure 3 , connect horizontally so that the tap units are arranged in rows, or connect vertically so that the tap units are arranged in columns to form a clock network. Figure 3 As shown, the tap unit can also be divided into different modules, and different modules can perform different functions.

[0067] Of course, the clock network also includes the trunk ( Figure 3 The vertical line in the middle is the trunk, which is connected to the clock network, and one end of the trunk is connected to the clock input port. In addition, the trunk and the metal wires connecting the tap units together form a high-level metal wire, and then a mesh clock tree structure is formed through this implementation method.

[0068] It can be understood that as the trunk extends, the farther away from the clock input port, the higher the delay of the tap unit. Therefore, in order to reduce the delay of the tap unit, a buffer needs to be arranged. The buffer can act as a middleware to reduce the delay of the tap unit far away from the clock input port.

[0069] The buffers also need to be arranged at the preset positions according to the design requirements, for example, see Figure 4 In a certain area, two buffers need to be arranged, or in a certain module, three buffers need to be arranged, and the connection from the clock input port to the clock network is formed through the buffer. Of course, other numbers of buffers can also be arranged, and no limitation is made here.

[0070] In actual use, the tap unit can be connected to a load and provide a clock signal to the load. Of course, some of the tap units may not be connected to a load. On this basis, in order to reduce clock power consumption, the present application deletes the tap units that are not connected to the load. The structure after deletion is as follows: Figure 5 shown.

[0071] At the same time, after deleting the tap unit, the network segment connected to the deleted tap unit will be in a "hanging" state. Therefore, in order to shorten the clock network line length, this application will also delete some or all of the network segments that are not connected to the tap unit.

[0072] Of course, the above deletion action is not the final result, because the redundant tap unit can play a role in balancing the clock network. Therefore, after executing the deletion action, the formed clock tree needs to be verified. As an implementation method, the delay deviation of each tap unit can be analyzed to determine whether to retain the deletion action. For example, when the delay deviation of a tap unit is greater than the threshold, the tap unit and network segment that are not connected to the load are deleted again, and then verification is performed again until the delay deviation of the tap unit is less than or equal to the threshold to complete the clock tree layout.

[0073] In other words, during the verification process, it is necessary to cyclically execute the actions of re-deletion and determination of delay deviation until the delay deviation of the tap unit is less than or equal to the threshold, and then the loop can be exited. It can be understood that at this time, the tap unit and the network segment are the shortest clock network and the least number of tap units that meet the constraints.

[0074] Through the above implementation, redundant tap units and clock network segments are deleted to form a fishbone network structure. This structure can effectively shorten the length of the clock network line, reduce the capacitance between lines, and thus reduce clock power consumption. At the same time, due to the reduction in the area of ​​the metal layer, the antenna effect violation will also be significantly reduced. Designers do not need to fix the physical design violation by inserting a large number of redundant diodes, which increases the effective design area of ​​the chip to a certain extent.

[0075] As an implementation method, the step of S102 includes:

[0076] The tap units are connected in layers using metal lines, wherein the number of layers, width, and spacing of the metal lines are related to the performance of the buffer and the resistance and capacitance between the metal lines.

[0077] As the tap unit extends away from the clock input port, its delay will become higher and higher. Therefore, the performance of each buffer is not the same, and the distance between adjacent metal wires is also not the same. As the distance increases, the resistance between metal wires decreases and the capacitance increases. The number of layers, width and spacing of metal wires are determined by the driving capability of the buffer and the resistance and capacitance of the metal wires.

[0078] As an implementation method, the step of S108 includes:

[0079] The network segments that need to be deleted are determined based on the preset layout rules and antenna effects.

[0080] When deleting network segments, it is necessary to retain the shortest segment connecting the tap units without violating the physical design rules, thereby forming a fishbone network structure. The physical design rules described in this application include but are not limited to preset layout rules and antenna effects.

[0081] It should be noted that the deletion of network segments described in the present application can be to delete the entire suspended network segment, or to delete only part of the suspended network segment. On this basis, the suspended network segment can be completely deleted, or the network segment can be shortened to meet the physical design rules. For example, for a certain network segment, the tap unit connected to it has been deleted. According to the physical design rules, its length is shortened by half, or it is completely deleted.

[0082] Through this implementation, it can be ensured that all redundant tap units are deleted, and at the same time, the network segments can achieve the shortest segment effect while meeting the physical design rules.

[0083] As an implementation method, the step of S110 includes:

[0084] S1101, taking any tap unit as a target tap unit.

[0085] S1102, comparing the delay of the tap unit adjacent to the target tap unit with the delay of the target tap unit to determine the delay deviation of each tap unit.

[0086] That is, when determining the delay deviation of each tap unit, in order to make the determination more convenient, the delay of each tap unit can be subtracted from the delay of the adjacent tap unit, and the absolute value of the difference is used as the delay deviation. Of course, the present application does not limit the number of adjacent tap units. For example, the delay deviation can be determined for the target tap unit and one adjacent tap unit, or for two or more adjacent tap units. No specific limitation is made here.

[0087] It should also be noted that when the delay deviation is determined by multiple adjacent tap units, the target tap unit can be subtracted from the adjacent tap units in turn, and then the absolute value of the difference can be determined. In addition, when determining the delay deviation, the maximum value among all absolute values ​​can be used as the delay deviation, or the sum of all absolute values ​​can be used as the delay deviation, or the average of all absolute values ​​can be used as the delay deviation, which is not limited here.

[0088] By determining the delay deviation, it is possible to determine whether the layout of the clock tree at this time meets the constraint conditions by comparing it with the threshold. If so, the layout of the clock tree is used as the final layout; if not, continue to perform iterative analysis using steps S106-S110 until the conditions are met.

[0089] As an implementation method, S110 further includes:

[0090] S1103: When the delay deviation is greater than a threshold, restore at least one tap unit that is not connected to a load and a corresponding network segment.

[0091] S1104, re-determine the delay deviation of each tap unit, and when the delay deviation is greater than a threshold, delete the tap unit and the network segment that are not connected to the load again until the delay deviation of the tap unit is less than or equal to the threshold.

[0092] When analyzing the delay deviation, if the delay deviation does not meet the constraint conditions, it means that some tap units and / or some network segments cannot be deleted. On this basis, the delay deviation of each tap unit can be re-determined by restoring the tap units that are not connected to the load and the corresponding network segments, and then the delay deviation analysis can be performed.

[0093] For example, a deleted tap unit may be restored one at a time, or multiple deleted tap units may be restored at a time. Of course, deleted tap units may also be restored randomly, and then delay deviation analysis is performed to determine whether it is necessary to continue the iterative analysis step.

[0094] Here, it should be noted that when there are multiple restored tap units and the delay deviation constraint is still not met after delay deviation analysis, some of the restored tap units and network segments can be deleted, and then the recovery and deletion steps are continuously performed until the delay deviation of the tap unit is less than or equal to the threshold, and the clock tree layout is completed.

[0095] In another implementation, S110 includes:

[0096] S1105: When the delay deviation is greater than the threshold, determine the target area with the largest delay deviation.

[0097] S1106, restore some or all of the tap units that are not connected to the load in the target area.

[0098] S1107, re-determine the delay deviation of each tap unit, and when the delay deviation is greater than a threshold, delete the tap unit and the network segment that are not connected to the load again until the delay deviation of the tap unit is less than or equal to the threshold.

[0099] In this implementation, the area with the largest delay deviation can be determined. For example, if the sum of the delay deviations of the tap units in this area is the largest, then the delay deviation of this area is determined to be the largest, and then some or all of the tap units are restored according to the area.

[0100] With this implementation, iterative analysis can be performed from the area with the largest delay deviation, so it is more efficient.

[0101] Based on the above implementation, please refer to Figure 6 The embodiment of the present application further provides a clock tree layout device 200, and the clock tree layout device 200 includes:

[0102] The connection unit 210 is used to connect the tap units in layers according to the preset positions of the tap units to form a clock network.

[0103] It can be understood that S102 can be executed by the connection unit 210 .

[0104] The connection unit 210 is further used to arrange the buffers at preset positions and form a connection from the clock input port to the clock network through the buffers.

[0105] It can be understood that S104 can be executed by the connection unit 210 .

[0106] The deletion unit 220 is used to delete the tap unit that is not connected to the load.

[0107] It can be understood that S106 can be executed by the deleting unit 220 .

[0108] The deleting unit 220 is further used to delete part or all of the network segments that are not connected to the tap units.

[0109] It can be understood that S108 can be executed by deleting the single.

[0110] The deletion unit 220 is also used to determine the delay deviation of each tap unit, and when the delay deviation is greater than a threshold, the tap unit and the network segment that are not connected to the load are deleted again until the delay deviation of the tap unit is less than or equal to the threshold, so as to complete the clock tree layout.

[0111] It can be understood that S110 can be executed by deleting a single item.

[0112] In addition, the deletion unit 220 is used to restore at least one tap unit and the corresponding network segment that are not connected to the load when the delay deviation is greater than a threshold; re-determine the delay deviation of each tap unit, and when the delay deviation is greater than the threshold, delete the tap unit and the network segment that are not connected to the load again until the delay deviation of the tap unit is less than or equal to the threshold.

[0113] In summary, the present application provides a clock tree layout method, device, electronic device and storage medium. First, the tap units are hierarchically connected according to the preset positions of the tap units to form a clock network, and then the buffers are arranged according to the preset positions, and the connection from the clock input port to the clock network is formed through the buffers. Then, the tap units that are not connected to the load are deleted, and then some or all of the network segments that are not connected to the tap units are deleted. Finally, the delay deviation of each tap unit is determined, and when the delay deviation is greater than the threshold, the tap units and network segments that are not connected to the load are deleted again until the delay deviation of the tap unit is less than or equal to the threshold to complete the clock tree layout. Since the present application deletes redundant tap units and network segments when performing clock tree layout, it can effectively shorten the length of the clock network line, reduce the capacitance between lines, and thus reduce the clock power consumption. At the same time, due to the reduction in the area of ​​the metal layer, the antenna effect violation will also be significantly reduced.

[0114] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods may also be implemented in other ways. The device embodiments described above are merely schematic, for example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the embodiments of the present application. In this regard, each box in the flowchart or block diagram may represent a module, a program segment or a part of a code, and the module, program segment or a part of a code includes one or more executable instructions for implementing a specified logical function.

[0115] It should also be noted that in some alternative implementations, the functions marked in the blocks may also occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the opposite order, depending on the functions involved.

[0116] It should also be noted that each box in the block diagram and / or flowchart, and combinations of boxes in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0117] In addition, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0118] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk, or an optical disk.

[0119] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A clock tree layout method, characterized in that: The method comprises: hierarchically connecting the tap units according to the preset positions of the tap units to form a clock network; Arrange buffers at preset positions, and form connections from clock input ports to the clock network through the buffers; Delete the tap unit that is not connected to the load; Delete some or all network segments that are not connected to tap units; Determine the delay deviation of each tap unit, and when the delay deviation is greater than a threshold, delete the tap unit and the network segment that are not connected to the load again until the delay deviation of the tap unit is less than or equal to the threshold, so as to complete the clock tree layout.

2. The clock tree layout method according to claim 1, characterized in that: When the delay deviation is greater than a threshold, the step of re-deleting the tap unit and the network segment that are not connected to the load comprises: When the delay deviation is greater than a threshold, restoring at least one tap unit that is not connected to a load and a corresponding network segment; The delay deviation of each tap unit is re-determined, and when the delay deviation is greater than a threshold, the tap unit and the network line segment that are not connected to the load are deleted again until the delay deviation of the tap unit is less than or equal to the threshold.

3. The clock tree layout method according to claim 1, characterized in that: When the delay deviation is greater than a threshold, the step of re-deleting the tap unit and the network segment that are not connected to the load comprises: When the delay deviation is greater than a threshold, determining a target area with a maximum delay deviation; Restoring some or all of the tap units that are not connected to the load in the target area; The delay deviation of each tap unit is re-determined, and when the delay deviation is greater than a threshold, the tap unit and the network line segment that are not connected to the load are deleted again until the delay deviation of the tap unit is less than or equal to the threshold.

4. The clock tree layout method according to claim 1, wherein: The steps to determine the delay skew of each tap unit include: Take any tap unit as the target tap unit; The delays of the tap units adjacent to the target tap unit are compared with the delay of the target tap unit to determine the delay deviation of each tap unit.

5. The clock tree layout method according to claim 1, characterized in that: The step of deleting some or all of the network segments that are not connected to the tap units comprises: The network segments that need to be deleted are determined based on the preset layout rules and antenna effects.

6. The clock tree layout method according to claim 1, characterized in that: The step of hierarchically connecting the tap units according to the preset positions of the tap units comprises: The tap units are connected in layers using metal lines, wherein the number of layers, width, and spacing of the metal lines are associated with the performance of the buffer and the resistance and capacitance between the metal lines.

7. A clock tree layout device, characterized in that: The device comprises: A connection unit, used for connecting the tap units in layers according to the positions of the preset tap units to form a clock network; The connection unit is further used to arrange the buffer at a preset position and form a connection from the clock input port to the clock network through the buffer; Delete unit, used to delete the tap unit that is not connected to the load; Deleting a unit is also used to delete some or all network segments that are not connected to the tap unit; The deletion unit is also used to determine the delay deviation of each tap unit, and when the delay deviation is greater than a threshold, the tap unit and the network segment that are not connected to the load are deleted again until the delay deviation of the tap unit is less than or equal to the threshold to complete the clock tree layout.

8. The clock tree layout device according to claim 7, characterized in that: The deletion unit is used to restore at least one tap unit and a corresponding network segment that are not connected to the load when the delay deviation is greater than a threshold; to redetermine the delay deviation of each tap unit, and to delete the tap unit and the network segment that are not connected to the load again when the delay deviation is greater than the threshold, until the delay deviation of the tap unit is less than or equal to the threshold.

9. An electronic device, characterized in that: include: A memory for storing one or more programs; processor; When the one or more programs are executed by the processor, the method according to any one of claims 1 to 6 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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