Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided. In an embodiment, a memory array is formed by manufacturing portions of a word line in different and independent processes, thereby allowing the first formed portion to be used as a structural support in a later process that would otherwise cause undesirable damage to the structure.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Semiconductor memory is used in integrated circuits for electronic applications including radios, televisions, cell phones and personal computing devices. Semiconductor memory includes two main categories. One is volatile memory; the other is non-volatile memory. Volatile memory includes random access memory (RAM), which can be further divided into two subcategories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they lose the stored information when power is removed.

[0003] On the other hand, non-volatile memory can store data on it. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). The advantages of FeRAM include its faster write / read speed and smaller size. Summary of the invention

[0004] Some embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: etching a first trench in a multilayer stack, the multilayer stack comprising alternating dielectric layers and sacrificial layers; depositing a first conductive material in the first trench; filling a remaining portion of the first trench with the first dielectric material; after filling the remaining portion of the first trench, etching a second trench in the multilayer stack; depositing a second conductive material in the second trench; filling the remaining portion of the second trench with the second dielectric material; etching the first conductive material and the second conductive material; and after etching the first conductive material and the second conductive material, depositing a channel material in the first trench.

[0005] Other embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: forming an alternating stack of a first dielectric material and a sacrificial material; forming a first portion of a first word line in the alternating stack, the forming of the first portion of the first word line comprising: etching a first trench in the alternating stack; forming a first recess by recessing the first portion of the sacrificial material in the first trench; depositing a first conductive material in the first recess; and depositing a second dielectric material to fill a remaining portion of the first trench; and forming a second portion of the first word line in the alternating stack, the forming of the second portion of the first word line comprising: etching a second trench in the alternating stack; forming a second recess by removing a second portion of the sacrificial material exposed in the second trench; depositing a second conductive material in the second recess; and depositing a third dielectric material to fill a remaining portion of the second trench.

[0006] Still other embodiments of the present application provide a semiconductor device, comprising: a ferroelectric material extending away from a substrate; a channel material located on a first side of the ferroelectric material; a first dielectric material extending away from a second side of the ferroelectric material opposite to the first side; a second dielectric material extending away from the second side of the ferroelectric material; a first conductive material extending away from the second side of the ferroelectric material between the first dielectric material and the second dielectric material, the first conductive material comprising a first bulk material and a first adhesive layer; and a second conductive material extending away from the first conductive material between the first dielectric material and the second dielectric material, the second conductive material comprising a second bulk material and a second adhesive layer, the second adhesive layer being in physical contact with the first adhesive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be increased or reduced at will for clarity of discussion.

[0008] Figure 1 is a block diagram of a random access memory according to some embodiments.

[0009] Figure 2A and Figure 2B are various views of a memory array according to some embodiments.

[0010] FIG. 3A to FIG. 15B are various views of intermediate stages in the fabrication of a memory array according to some embodiments.

[0011] Fig.16A and Fig. 16Bare various views of a memory array according to some embodiments.

[0012] Fig.17A and Fig. 17B are various views of a memory array according to some embodiments.

[0013] Fig.18A and Fig.18B are various views of a memory array according to some embodiments.

[0014] FIG. 19A to FIG. 19B are various views of intermediate stages in the fabrication of a memory array according to some embodiments.

[0015] FIG. 20A to FIG. 22B are various views of intermediate stages in the fabrication of a memory array according to some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0018] According to various embodiments, word lines of a memory array are formed by a multiple patterning process, wherein a first portion of the word lines and a first subset of transistors of the memory array are formed in a first patterning process, and wherein a second portion of the word lines and a second subset of transistors of the memory array are subsequently formed in a second patterning process. Thus, the aspect ratio of the columns of the memory array can be increased while avoiding distortion or collapse of components during the formation process.

[0019] Figure 1is a block diagram of a random access memory 50 according to some embodiments. The random access memory 50 includes a memory array 52, a row decoder 54, and a column decoder 56. Each of the memory array 52, the row decoder 54, and the column decoder 56 can be part of the same semiconductor die, or can be part of different semiconductor dies. For example, the memory array 52 can be part of a first semiconductor die, and the row decoder 54 and the column decoder 56 can be part of a second semiconductor die.

[0020] Memory array 52 includes memory cells 58, word lines 62, and bit lines 64. Memory cells 58 are arranged in rows and columns. Word lines 62 and bit lines 64 are electrically connected to memory cells 58. Word lines 62 are conductive lines extending along rows of memory cells 58. Bit lines 64 are conductive lines extending along columns of memory cells 58.

[0021] The row decoder 54 may be, for example, a static complementary metal oxide semiconductor (CMOS) decoder, a pseudo N-type metal oxide semiconductor (NMOS) decoder, etc. During operation, the row decoder 54 selects a desired memory cell 58 in a row of the memory array 52 by activating a word line 62 of the row. The column decoder 56 may be, for example, a static CMOS decoder, a pseudo NMOS decoder, etc., and may include a write driver, a sense amplifier, a combination thereof, etc. During operation, the column decoder 56 selects a bit line 64 for a desired memory cell 58 from a column of the memory array 52 in the selected row, and reads data from or writes data to the selected memory cell 58 using the bit line 64.

[0022] Figure 2A and Figure 2B are various views of memory array 52 according to some embodiments. Figure 2A is a circuit diagram of the memory array 52. Figure 2B is a three-dimensional view of a portion of memory array 52 .

[0023] The memory array 52 is a flash memory array such as a NOR flash memory array, a high-speed memory array such as a DRAM or SRAM, a non-volatile memory such as a resistive RAM (RRAM) or a magnetic RAM (MRAM), etc. Each memory cell 58 is a flash memory cell including a thin film transistor (TFT) 68. The gate of each TFT 68 is electrically connected to a corresponding word line 62, the first source / drain region of each TFT 68 is electrically connected to a corresponding bit line 64, and the second source / drain region of the TFT 68 is electrically connected to a corresponding source line 66 (which is electrically grounded). The memory cells 58 in the same row of the memory array 52 share a common word line 62, and the memory cells in the same column of the memory array 52 share a common bit line 64 and a common source line 66.

[0024] The memory array 52 includes a plurality of arranged conductive lines (eg, word lines 62) with a dielectric layer 72 located between adjacent ones of the word lines 62. The word lines 62 extend in a first direction D1 parallel to a major surface of an underlying substrate (in a direction D2). Figure 2B Not shown, but will be referred to below FIG. 3A to FIG. 21B ). The word lines 62 may have a stepped arrangement such that the lower word lines 62 are longer than the upper word lines 62 and extend laterally beyond the endpoints of the upper word lines 62. For example, in Figure 2B , multiple stacked layers of word lines 62 are shown, wherein the topmost word line 62A is the shortest line and the bottommost word line 62B is the longest line. The lengths of the respective word lines 62 increase in a direction extending toward the underlying substrate. In this manner, a portion of each word line 62 may be accessed from above the memory array 52 so that a conductive contact may be formed to the exposed portion of each word line 62.

[0025] The memory array 52 also includes multiple arranged conductive lines, such as bit lines 64 and source lines 66. The bit lines 64 and source lines 66 extend in a second direction D2 perpendicular to the first direction D1 and the main surface of the underlying substrate. A dielectric layer 74 is disposed between and isolates adjacent ones of the bit lines 64 and source lines 66. The boundaries of each memory cell 58 are defined by pairs of bit lines 64 and source lines 66 and intersecting word lines 62. A dielectric plug 76 is disposed between and isolates adjacent pairs of bit lines 64 and source lines 66. Although Figure 2A and Figure 2B A particular position of bit line 64 relative to source line 66 is shown, but it should be noted that in other embodiments, the positions of bit line 64 and source line 66 may be reversed.

[0026] Memory array 52 also includes ferroelectric strip 84 and semiconductor strip 82. Ferroelectric strip 84 contacts word line 62. Semiconductor strip 82 is disposed between ferroelectric strip 84 and dielectric layer 74.

[0027] Semiconductor strip 82 provides a channel region for TFT 68 of memory cell 58. For example, when an appropriate voltage (e.g., higher than a corresponding threshold voltage (V th )), the area where semiconductor strip 82 intersects word line 62 may allow current to flow from bit line 64 to source line 66 (eg, in the D1 direction).

[0028] The ferroelectric strip 84 is a data storage layer that can be polarized in one of two different directions by applying an appropriate voltage difference across the ferroelectric strip 84. Depending on the polarization direction of a particular region of the ferroelectric strip 84, the threshold voltage of the corresponding TFT 68 changes and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the ferroelectric strip 84 has a first polarization direction, the corresponding TFT 68 may have a relatively low threshold voltage, and when a region of the ferroelectric strip 84 has a second polarization direction, the corresponding TFT 68 may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as a threshold voltage shift. A larger threshold voltage shift may make it easier (e.g., less prone to errors) to read the digital value stored in the corresponding memory cell 58. Accordingly, the memory array 52 may also be referred to as a ferroelectric random access memory (FERAM) array.

[0029] In order to perform a write operation on a specific memory cell 58, a write voltage may be applied to a region of the ferroelectric strip 84 corresponding to the memory cell 58. For example, the write voltage may be applied by applying appropriate voltages to the word line 62, the bit line 64, and the source line 66 corresponding to the memory cell 58. By applying the write voltage to a region of the ferroelectric strip 84, the polarization direction of the region of the ferroelectric strip 84 may be changed. Thus, the corresponding threshold voltage of the corresponding TFT 68 may be switched from a low threshold voltage to a high threshold voltage (or vice versa), so that a digital value may be stored in the memory cell 58. Because the word line 62 and the bit line 64 intersect in the memory array 52, a single memory cell 58 may be selected and written.

[0030] To perform a read operation on a particular memory cell 58, a read voltage (a voltage between the lower and upper threshold voltages) is applied to the word line 62 corresponding to the memory cell 58. Depending on the polarization direction of the corresponding region of the ferroelectric strip 84, the TFT 68 of the memory cell 58 may or may not be turned on. Thus, the bit line 64 may or may not be discharged (e.g., to ground) via the source line 66, thereby determining the digital value stored in the memory cell 58. Because the word lines 62 and the bit lines 64 intersect in the memory array 52, individual memory cells 58 may be selected and read from.

[0031] FIG. 3A to FIG. 15B5 are various views of intermediate stages of fabricating a memory array 52 according to some embodiments. A portion of the memory array 52 is shown. For clarity of illustration, some components are not shown, such as the staircase arrangement of word lines (see FIG. Figure 2B ). Figure 3A , 4A , 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A are three-dimensional views of memory array 52. Figure 3B , 4B , 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B and 15B are along Fig.13A A cross-sectional view shown in reference section BB.

[0032] exist Figure 3A and Figure 3B In the embodiment, a substrate 102 is provided. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., doped with a p-type or n-type dopant) or undoped. The substrate 102 may be a wafer, such as a silicon wafer. In general, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates may also be used. In some embodiments, the semiconductor material of the substrate 102 may include silicon; germanium; a composite semiconductor containing silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor containing silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or a combination thereof. The substrate 102 may include a dielectric material. For example, substrate 102 may be a dielectric substrate, or may include a dielectric layer on a semiconductor substrate. Acceptable dielectric materials for dielectric substrates include oxides such as silicon oxide, nitrides such as silicon nitride, carbides such as silicon carbide, and the like, or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, and the like. In some embodiments, substrate 102 is formed of silicon carbide.

[0033] A multilayer stack 104 is formed over the substrate 102. The multilayer stack 104 includes alternating first dielectric layers 104A and second dielectric layers 104B. The first dielectric layers 104A are formed of a first dielectric material, and the second dielectric layers 104B are formed of a second dielectric material. The dielectric materials may each be selected from candidate dielectric materials of the substrate 102. In some specific embodiments, the first dielectric layers 104A may be any suitable material, as long as the material of the first dielectric layers 104A etches at a slower etching rate than the material of the second dielectric layers 104B in a subsequent process (described further below) during removal of the material of the second dielectric layers 104B.

[0034] In the illustrated embodiment, the multilayer stack 104 includes five first dielectric layers 104A and four second dielectric layers 104B. It should be noted that the multilayer stack 104 may include any number of first dielectric layers 104A and any number of second dielectric layers 104B.

[0035] The multilayer stack 104 will be patterned in subsequent processing. In this way, the dielectric material of the first dielectric layer 104A and the dielectric material of the second dielectric layer 104B both have a high etching selectivity compared to the etching of the substrate 102. The patterned first dielectric layer 104A will be used to isolate the TFT formed subsequently. The patterned second dielectric layer 104B is a sacrificial layer (or dummy layer), which will be removed in subsequent processing and replaced by the word line of the TFT. In this way, the second dielectric material of the second dielectric layer 104B also has a high etching selectivity compared to the etching of the first dielectric material of the first dielectric layer 104A. In an embodiment where the substrate 102 is formed of silicon carbide, the first dielectric layer 104A can be formed of an oxide such as silicon oxide, and the second dielectric layer 104B can be formed of a nitride such as silicon nitride. Other combinations of dielectric materials with acceptable etching selectivity to each other can also be used.

[0036] Each layer of the multilayer stack 104 can be formed by an acceptable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The thickness of each layer can be in the range of about 15nm to about 90nm. In some embodiments, the first dielectric layer 104A is formed to be different from the thickness of the second dielectric layer 104B. For example, the first dielectric layer 104A can be formed to have a first thickness t1, and the second dielectric layer 104B can be formed to have a second thickness T2, and the second thickness T2 is smaller [larger / smaller] than the first thickness T1 by about 0% to about 100%. In addition, the multilayer stack 104 may have any suitable number of pairs of the first dielectric layer 104A and the second dielectric layer 104B, such as more than 20 pairs, and the multilayer stack 104 may have a total height H1 in the range of about 1000nm to about 10000nm (such as about 2000nm).

[0037] As will be discussed in more detail below, 4A to 14B A process is shown in which trenches are patterned in the multilayer stack 104 and TFTs are formed in these trenches. Specifically, a multiple patterning process is used to form the TFTs. The multiple patterning process may be a double patterning process, a quadruple patterning process, etc. 4A to 14B In the double patterning process, a first trench 106 is patterned in the multilayer stack 104 using a first etching process (see FIG. Figure 4A and Figure 4B ), and elements of a first subset of TFTs are formed in the first trenches 106. Then, a second trench 120 is patterned in the multilayer stack 104 using a second etching process (see Fig. 8A and Figure 8B ), and a second subset of TFTs are formed in the second trenches 120. Forming the TFTs using a multiple patterning process allows each patterning process to be performed at a low pattern density, which can help reduce defects while still allowing the memory array 52 to have a sufficient memory cell density, while also helping to prevent the aspect ratio from becoming too high and causing structural instability.

[0038] exist Figure 4A and Figure 4B , a first trench 106 is formed in the multilayer stack 104. In the illustrated embodiment, the first trench 106 extends through the multilayer stack 104 and exposes the substrate 102. In another embodiment, the first trench 106 extends through some layers in the multilayer stack 104, but not through all layers. The first trench 106 can be formed using acceptable photolithography and etching techniques, such as using an etching process that is selective to the multilayer stack 104 (e.g., a process that etches the dielectric material of the first dielectric layer 104A and the dielectric material of the second dielectric layer 104B at a faster rate than the material of the substrate 102). The etching can be any acceptable etching process, such as reactive ion etching (PIE), neutral atom beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic. In an embodiment where the substrate 102 is formed of silicon carbide, the first dielectric layer 104A is formed of silicon oxide, and the second dielectric layer 104B is formed of silicon nitride, the first trench 106 can be formed by dry etching using a fluorine-based gas (e.g., C4F6) mixed with hydrogen (H2) or oxygen (O2) gas.

[0039] A portion of the multilayer stack 104 is disposed between each pair of first trenches 106. Each portion of the multilayer stack 104 may have a width W1 that is approximately three times greater than the desired final width of the word line, such as in a range of about 50 nm to about 500 nm (such as about 240 nm), and has a reference width W1. Figure 3A and Figure 3BThe height H1 described. Moreover, each portion of the multilayer stack 104 is separated by a separation distance S1, which may be in a range of about 50 nm to about 200 nm (such as about 80 nm). The aspect ratio (AR) of each portion of the multilayer stack 104 is the ratio of the height H1 to the width of the narrowest component of the portion of the multilayer stack 104, which is the width W1 in this processing step. According to some embodiments, when the first trench 106 is formed, the aspect ratio of each portion of the multilayer stack 104 is in a range of about 5 to about 15. Forming each portion of the multilayer stack 104 with an aspect ratio less than about 5 may not allow the memory array 52 to have a sufficient memory cell density. Forming each portion of the multilayer stack 104 with an aspect ratio greater than about 15 may cause distortion or collapse of the multilayer stack 104 in subsequent processing.

[0040] exist Figure 5A and Figure 5B , the first trench 106 is extended to form a first sidewall recess 110. Specifically, the portion of the sidewall of the second dielectric layer 104B exposed by the first trench 106 is recessed to form the first sidewall recess 110. Although the sidewalls of the second dielectric layer 104B are shown as being straight, the sidewalls may be concave or convex. The first sidewall recess 110 may be formed by an acceptable etching process, such as an etching process that is selective to the material of the second dielectric layer 104B (e.g., a process that selectively etches the material of the second dielectric layer 104B at a faster rate than the material of the first dielectric layer 104A and the material of the substrate 102). The etching may be isotropic. In an embodiment where the substrate 102 is formed of silicon carbide, the first dielectric layer 104A is formed of silicon oxide, and the second dielectric layer 104B is formed of silicon nitride, the first trench 106 may be extended by wet etching using phosphoric acid (H3PO4). However, any other suitable etching process such as dry selective etching may also be used.

[0041] After formation, the first sidewall recess 110 has a depth D3 that extends beyond the sidewall of the first dielectric layer 104A. After the first sidewall recess 110 reaches the desired depth D3, a timed etching process may be used to stop etching of the first sidewall recess 110. For example, when phosphoric acid is used to etch the second dielectric layer 104B, etching may be performed for a sufficiently long time so that the first sidewall recess 110 has a depth D3 in the range of about 10 nm to about 60 nm, such as about 40 nm. Forming the first sidewall recess 110 reduces the width of the second dielectric layer 104B. Continuing with the previous example, after etching, the second dielectric layer 104B may have a width W2 in the range of about 50 nm to about 450 nm, such as about 160 nm. As described above, the aspect ratio (AR) of each portion of the multilayer stack 104 is the ratio of the height H1 to the width of the narrowest feature of the portion of the multilayer stack 104, which is the width W2 in the processing step. Therefore, forming the first sidewall recess 110 increases the aspect ratio of each portion of the multilayer stack 104. According to some embodiments, after forming the first sidewall recess 110, the aspect ratio of each portion of the multilayer stack 104 remains within the range described above, such as within the range of about 5 to about 15. Therefore, the advantages of such aspect ratios (described above) can still be achieved.

[0042] exist Fig. 6A and Figure 6B In the embodiment, the first conductive component 112A is formed in the first sidewall recess 110, thereby completing the process of replacing the first portion of the second dielectric layer 104B. The first conductive components 112A may each include one or more layers, such as an adhesive layer, a barrier layer, a diffusion layer, and a filling layer, and the like. In some embodiments, the first conductive components 112A each include an adhesive layer 112A. G and main floor 112A M , although in other embodiments the adhesive layer 112A G Each adhesive layer 112A G Along the corresponding main layer 112A located in the first sidewall groove 110 M The adhesive layer 112A extends along three sides (eg, top surface, sidewall, and bottom surface) of the material. G The main layer 112A is formed of a first conductive material, such as titanium, titanium nitride, tantalum, tantalum nitride, molybdenum, ruthenium, rhodium, hafnium, iridium, niobium, rhenium, tungsten, combinations thereof, oxides thereof, etc. M The adhesive layer 112A may be formed of a second conductive material, such as a metal, such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, molybdenum, ruthenium, molybdenum nitride, alloys thereof, etc. G The material of the main layer 112A is a material having good adhesion to the material of the first dielectric layer 104A, and MThe material is a kind of adhesive layer 112A G In an embodiment where the first dielectric layer 104A is formed of an oxide such as silicon oxide, the adhesive layer 112A G The main layer 112A may be formed of titanium nitride. M It can be formed of tungsten. Adhesive layer 112A G and main floor 112A M Each may be formed by an acceptable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like.

[0043] exist Fig. 7A and Figure 7B In the embodiment, the remaining portion of the first trench 106 is filled and / or overfilled with the first dielectric material 108 without etching back the material of the first conductive feature 112A. In an embodiment, the first dielectric material 108 may be a material deposited using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, a combination thereof, or the like, such as silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, or the like. In some embodiments, the first dielectric material 108 may be a material similar to that of the first dielectric layer 104A, although in other embodiments, the material may be different. Any suitable material and deposition method may be used.

[0044] Once the dielectric material 108 has been deposited to fill and / or overfill the first trench 106, the first dielectric material 108 may be planarized to remove excess material outside of the first trench 106. In one embodiment, a chemical mechanical planarization (CMP) process, for example, may be used to planarize the first dielectric material 108. However, any suitable planarization process, such as a grinding process, may also be used.

[0045] In one embodiment, the first dielectric material 108 and the first dielectric layer 104A are planarized to be flat. Thus, the portion of the first conductive component 112A located outside the first trench 106 is also removed and planarized to be flat with the first dielectric layer 104A and the first dielectric material 108. Thus, the planar first surface includes the first dielectric layer 104A, the first conductive component 112A, and the first dielectric material 108.

[0046] exist Fig. 8A and Figure 8B, a second trench 120 is formed in the multilayer stack 104. In the illustrated embodiment, the second trench 120 extends through the multilayer stack 104 and exposes the substrate 102. In another embodiment, the second trench 120 extends through some layers, but not all layers, of the multilayer stack 104. The second trench 120 can be formed using acceptable photolithography and etching techniques, such as using an etching process that is selective to the multilayer stack 104 (e.g., a process that etches the dielectric material of the first dielectric layer 104A and the dielectric material of the second dielectric layer 104B at a faster rate than the material of the substrate 102). The etching process can be any acceptable etching process, and in some embodiments, can be similar to that described with reference to FIG. Figure 4A and Figure 4B The etching process for forming the first trench 106 is described.

[0047] A portion of the multilayer stack 104 is disposed between each second trench 120 and each first trench 106. Each portion of the multilayer stack 104 may have a width W3 in a range of about 50 nm to about 500 nm and have a width W2 of about 100 nm. Figure 3A and Figure 3B The height H1. Moreover, each portion of the multilayer stack 104 is separated by a separation distance S2, which may be in the range of about 50 nm to about 200 nm. The aspect ratio (AR) of each portion of the multilayer stack 104 is the ratio of the height H1 to the width of the narrowest component of the portion of the multilayer stack 104, which is the width W3 in this processing step. According to some embodiments, when the second trench 120 is formed, the aspect ratio of each portion of the multilayer stack 104 is in the range of about 5 to about 15. Forming each portion of the multilayer stack 104 with an aspect ratio less than about 5 may not allow the memory array 52 to have a sufficient memory cell density. Forming each portion of the multilayer stack 104 with an aspect ratio greater than about 15 may cause distortion or collapse of the multilayer stack 104 in subsequent processing.

[0048] exist Fig.9A and Fig. 9B In the embodiment, the second trench 120 is expanded to form a second sidewall recess 124. Specifically, the remaining portion of the second dielectric layer 104B is removed to form the second sidewall recess 124. Therefore, the second sidewall recess 124 exposes a portion of the first conductive component 112A, such as the adhesive layer 112A. G The second sidewall recess 124 may be formed by an acceptable etching process, such as an etching process that is selective to the material of the second dielectric layer 104B (e.g., a process that selectively etches the material of the second dielectric layer 104B at a faster rate than the material of the first dielectric layer 104A and the material of the substrate 102). The etching process may be any acceptable etching process, and in some embodiments, may be similar to that described with reference to Figure 5Aand Figure 5B The etching for forming the first sidewall recess 110 is described. After formation, the second sidewall recess 124 has a depth D4 extending beyond the sidewall of the first dielectric layer 104A. In some embodiments, the depth D4 is similar to the depth D4 of the reference Figure 5A and Figure 5B In another embodiment, the depth D4 is different from (greater than or less than) the reference depth D3. Figure 5A and Figure 5B The depth D3.

[0049] However, by forming the first conductive component 112A and the second dielectric material 122 before etching the second trench 120 and forming the second sidewall recess 124, the first conductive component 112A is present during the etching of the second trench 120 and the second sidewall recess 124. As such, the unremoved first conductive component 112A and the unremoved second dielectric material 122 can be used as pillars to provide structural support during the high stress release process. The additional support allows problems that may occur during the removal process (e.g., word line swing or word line collapse) to be avoided.

[0050] exist Fig. 10A and Fig. 10B In the embodiment, the first conductive component 112A is formed in the second sidewall recess 124, thereby completing the process of replacing the second portion of the second dielectric layer 104B. The second conductive component 112B can be formed of a material selected from the same group of candidate materials as the first conductive component 112A, and can be formed using a method selected from the same group of candidate methods used to form the material of the first conductive component 112A. The first conductive component 112A and the second conductive component 112B can be formed of the same material, or can include different materials. In some embodiments, the second conductive components 112A each include an adhesive layer 112B. G and main floor 112B M , although in other embodiments the adhesive layer 112B G Can be omitted. The adhesive layer 112B of the second conductive component 112B G and main floor 112B M The adhesive layer 112A may be provided with the first conductive component 112A. G and main floor 112A M In some embodiments, the adhesive layer 112A G and adhesive layer 112B G Formed from similar materials, in this case, adhesive layer 112A G and adhesive layer 112B G The adhesive layer 112A may be fused during the formation process so that there is no discernible interface between them. Gand adhesive layer 112B G Formed of different materials, in this case, the adhesive layer 112A G and adhesive layer 112B G They cannot fuse during formation so that there is a discernible interface between them.

[0051] The first conductive component 112A and the second conductive component 112B are collectively referred to as the word line 112 of the memory array 52. ​​Adjacent pairs of the first conductive component 112A and the second conductive component 112B are in physical contact with each other and are electrically coupled to each other. Therefore, each pair of the first conductive component 112A and the second conductive component 112B functions as a single word line 112.

[0052] FIG. 10A to FIG. 10B It is also shown that once the second conductive feature 112B has been deposited into the second trench 120, and before any etch back of the second conductive feature 112B, a second dielectric material 122 may be deposited over the second conductive feature 112B in order to fill and / or overfill the remaining portion of the second trench 120. In one embodiment, the second dielectric material 122 may be a material similar to the material of the first dielectric material 108 deposited within the first trench 106, and may also be similar to the first dielectric layer 104A, and may be deposited in a manner similar to the material of the first dielectric material 108. However, any suitable material and any suitable deposition method may be used.

[0053] Once the dielectric material 122 has been deposited to fill and / or overfill the first trench 120, the second dielectric material 122 may be planarized to remove excess material outside the second trench 120. In an embodiment, the second dielectric material 122 may be planarized using, for example, a chemical mechanical planarization process, but any suitable process may be used. In addition, the planarization process may also remove any material of the second conductive component 112B located outside the second trench 120, thereby forming a planar surface including the first dielectric layer 104A, the first conductive component 112A, the second conductive component 112B, the first dielectric material 108, and the second dielectric material 122.

[0054] FIG. 11A to FIG. 11BThe removal of the top layer of the first dielectric layer 104A (the exposed first dielectric layer 104A) and the first dielectric material 108 within the first trench 106 and the second dielectric material 122 within the second trench 120 is shown. In embodiments, the removal may be performed using one or more chemical dry etching processes, wet etching processes, combinations thereof, and the like. For example, in embodiments where the material of the first dielectric layer 104A is the same as the material of the first dielectric material 108 and the second dielectric material 122, a single etching process may be used that uses an etchant that is selective to the materials of the first dielectric layer 104A, the first dielectric material 108, and the second dielectric material 122. In other embodiments where the materials of the first dielectric layer 104A, the first dielectric material 108, and the second dielectric material 122 are not the same, multiple etching processes may be used in order to sequentially remove these different materials. Any suitable removal process may be used.

[0055] In addition, from Fig. 11B As can be most clearly seen in FIG. 1 , removal of the topmost first dielectric layer 104A leaves first and second conductive features 112A and 112B (which have been fused into a single conductive structure) having a "U" shaped structure having sidewalls including first and second conductive features 112A and 112B. As such, the remaining portion of first conductive feature 112A and the remaining portion of second conductive feature 112B form an "H" shaped structure (at Fig. 11B ), where the adhesive layer 112Ag and the adhesive layer 112Bg are located between the remaining portion of the first conductive component 112A and the remaining portion of the second conductive component 112B.

[0056] FIG. 12A to FIG. 12B An etch-back process is shown to remove excess portions of the first conductive component 112A and the second conductive component 112B and expose the next first dielectric layer 104A. In an embodiment, the etch-back process may be performed using, for example, an anisotropic etching process such as reactive ion etching. However, any suitable etching process may be used.

[0057] In an embodiment, the etch-back process is performed until the material of the first conductive component 112A and the second conductive component 112B that are located within the first trench 106 and the second trench 120 but not located in the first sidewall recess 110 and the second sidewall recess 124 and not covered by the next first dielectric layer 104A has been removed. As such, the remaining material of the first conductive component 112A and the remaining material of the second conductive component 112B have a width similar to the remaining portion of the second dielectric layer 104B (e.g., 80 nm). However, any suitable dimensions may be used.

[0058] FIG. 13A to FIG. 13B A TFT thin film stack is shown formed in the first trench 106 and the second trench 120. Specifically, two ferroelectric strips 114, a semiconductor strip 116, and a dielectric layer 118 are formed in each first trench 106 and each second trench 120. In this embodiment, no other layers are formed in the first trench 106 and the second trench 120. In another embodiment (discussed further below), additional layers are formed in the first trench 106 and the second trench 120.

[0059] The ferroelectric strip 114 for storing digital values ​​is a data storage strip formed of an acceptable ferroelectric material, such as hafnium zirconium oxide (HfZrO); zirconium oxide (ZrO); hafnium oxide (HfO) doped with lanthanum (La), silicon (Si), aluminum (Al), etc.; undoped hafnium oxide (HfO), etc. The material of the ferroelectric strip 114 can be formed by an acceptable deposition process, such as ALD, CVD, physical vapor deposition (PVD), etc.

[0060] The semiconductor strips 116 for providing the channel regions of the TFTs are formed of acceptable semiconductor materials, such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), zinc oxide (ZnO), polycrystalline silicon, amorphous silicon, etc. The material of the semiconductor strips 116 can be formed by an acceptable deposition process, such as ALD, CVD, PVD, etc.

[0061] The dielectric layer 118 is formed of a dielectric material. Acceptable dielectric materials include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; and the like; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, and the like. The material of the dielectric layer 118 can be formed by an acceptable deposition process, such as ALD, CVD, flowable CVD (FCVD), and the like.

[0062] The ferroelectric strips 114, the semiconductor strips 116, and the dielectric layer 118 may be formed by a combination of deposition, etching, and planarization. For example, a ferroelectric layer may be conformally deposited on the multilayer stack 104 and in the first trench 106 and the second trench 120 (e.g., on the sidewalls of the first conductive component 112A and on the sidewalls of the first dielectric layer 104A). Then, a semiconductor layer may be conformally deposited on the ferroelectric layer. Then, the semiconductor layer may be anisotropically etched to remove horizontal portions of the semiconductor layer, thereby exposing the ferroelectric layer. Then, a dielectric layer may be conformally deposited on the remaining vertical portions of the semiconductor layer and on the exposed portions of the ferroelectric layer. Then, a planarization process is applied to each layer to remove excess material above the multilayer stack 104. The planarization process may be chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like. The portion of the ferroelectric layer, the portion of the semiconductor layer, and the portion of the dielectric layer remaining in the first trench 106 respectively form a ferroelectric strip 114, a semiconductor strip 116, and a dielectric layer 118. The planarization process exposes the multilayer stack 104 so that after the planarization process, a top surface of the multilayer stack 104, a top surface of the ferroelectric strip 114, a top surface of the semiconductor strip 116, and a top surface of the dielectric layer 118 are coplanar (within process variations).

[0063] exist Fig.14A and Fig. 14B 1 , a dielectric plug 132 is formed through the dielectric layer 118 and the semiconductor strip 116. The dielectric plug 132 is an isolation column that will be disposed between adjacent TFTs and will physically and electrically separate the adjacent TFTs. In the illustrated embodiment, the dielectric plug 132 does not extend through the ferroelectric strip 114. Different regions of the ferroelectric strip 114 can be individually polarized, so the ferroelectric strip 114 can be used to store values ​​even if adjacent regions are not physically and electrically separated. In another embodiment, the dielectric plug 132 is also formed through the ferroelectric strip 114. The dielectric plug 132 further extends through the first dielectric layer 104A.

[0064] As an example of forming dielectric plugs 132, openings for dielectric plugs 132 may be formed through dielectric layer 118 and semiconductor strips 116. These openings may be formed using acceptable photolithography and etching techniques. Then, one or more dielectric materials are formed in these openings. Acceptable dielectric materials include oxides such as silicon oxide; nitrides such as silicon nitride; carbides such as silicon carbide; and the like; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, and the like. The dielectric material may be formed by an acceptable deposition process, such as ALD, CVD, and the like. In some embodiments, silicon oxide or silicon nitride is deposited in these openings. Then, a planarization process is applied to each layer to remove excess dielectric material remaining above the topmost first dielectric layer 104A. The planarization process may be chemical mechanical polishing (CMP), an etch-back process, a combination thereof, and the like. The remaining dielectric material forms dielectric plugs 132 in the openings.

[0065] Fig.14A and Fig. 14B Also shown are bit lines 134 and source lines 136 formed through dielectric layer 118. Bit lines 134 and source lines 136 extend further through first dielectric layer 104A. Bit lines 134 and source lines 136 serve as source / drain regions of TFTs. Bit lines 134 and source lines 136 are conductive columns formed in pairs, and each semiconductor strip 116 contacts a corresponding bit line 134 and a corresponding source line 136. Each TFT includes a bit line 134, a source line 136, a word line 112, and an area where semiconductor strips 116 and ferroelectric strips 114 intersect with word lines 112. Each dielectric plug 132 is disposed between a bit line 134 of a TFT and a source line 136 of another TFT. In other words, bit lines 134 and source lines 136 are disposed at opposite sides of each dielectric plug 132. Therefore, each dielectric plug 132 physically and electrically separates adjacent TFTs.

[0066] As an example of forming the bit line 134 and the source line 136, the openings for the bit line 134 and the source line 136 can be formed through the dielectric layer 118. These openings can be formed by using acceptable photolithography and etching techniques. Specifically, these openings are formed on opposite sides of the dielectric plug 132. Then, one or more conductive materials, such as adhesive layers and bulk conductive materials are formed in these openings, and acceptable conductive materials include metals such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, their alloys, etc. The conductive material can be formed by an acceptable deposition process such as ALD or CVD, an acceptable plating process such as electroplating or chemical plating, etc. In some embodiments, tungsten is deposited in the opening. Then, a planarization process is used for each layer to remove excess conductive material above the topmost first dielectric layer 104A. The planarization process can be chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The remaining conductive material forms the bit line 134 and the source line 136 in the opening.

[0067] exist Fig.15A and Fig. 15B In FIG. 1 , the interconnect structure 140 is formed above the intermediate structure. Fig.15A Only some components of the interconnect structure 140 are shown in FIG. The interconnect structure 140 may include, for example, a metallization pattern 142 in a dielectric material 144. The dielectric material 144 may include one or more dielectric layers, such as one or more layers of low dielectric constant (LK) or ultra low dielectric constant (ELK) dielectric materials. The metallization pattern 142 may be a metal interconnect (e.g., metal lines and vias) formed in one or more dielectric layers. The interconnect structure 140 may be formed by a damascene process, such as a single damascene process, a dual damascene process, and the like.

[0068] The metallization pattern 142 of the interconnect structure 140 is electrically coupled to the bit lines 134 and the source lines 136. For example, the metallization pattern 142 includes a bit line interconnect 142B (which is electrically coupled to the bit lines 134) and a source line interconnect 142S (which is electrically coupled to the source lines 136). Adjacent bit lines 134 are connected to different bit line interconnects 142B, which helps to avoid short circuits of adjacent bit lines 134 when the common word line 112 of these adjacent bit lines 134 is activated. Similarly, adjacent source lines 136 are connected to different source line interconnects 142S, which helps to avoid short circuits of adjacent source lines 136 when the common word line 112 of these adjacent source lines 136 is activated.

[0069] In this embodiment, the bit lines 134 and the source lines 136 are formed in a staggered layout, wherein adjacent bit lines 134 and adjacent source lines 136 are arranged along a first direction D1 (see FIG. Figure 2B) are laterally offset from each other. Therefore, each word line 112 is laterally disposed between the dielectric plug 132 and the bit line 134 or between the dielectric plug 132 and the source line 136. The bit line interconnect 142B and the source line interconnect 142S are each arranged in the second direction D2 (see Figure 2B ) along the columns of the memory array 52, for example. The bit line interconnects 142B are connected to alternating ones of the bit lines 134 along the columns of the memory array 52. ​​The source line interconnects 142B are connected to alternating ones of the source lines 136 along the columns of the memory array 52. ​​The laterally offset bit lines 134 and source lines 136 eliminate the need for lateral interconnects along the columns of the memory array 52, thereby allowing the bit line interconnects 142B and source line interconnects 142S to be straight conductive segments that can be formed at the lowest level of the interconnect structure 140. In another embodiment (discussed below), the bit lines 134 and source lines 136 are not formed in a staggered layout, but are laterally interconnected in the interconnect structure 140.

[0070] Fig.16A and Fig. 16B 5 are various views of a memory array 52 according to some other embodiments. A portion of the memory array 52 is shown. For clarity of illustration, some components are not shown, such as the staircase arrangement of word lines (see FIG. Figure 2B ). Fig.16A is a three-dimensional view of the memory array 52, Fig. 16B is shown with Fig.13A A cross-sectional view of a cross section similar to reference cross section BB.

[0071] In this embodiment, the ferroelectric strips 114 are omitted and replaced by a plurality of dielectric layers 150, which are data storage strips, thereby transforming the memory cells into flash-like storage elements, thereby permitting the creation of, for example, NOR flash arrays. Specifically, a first dielectric layer 150A is formed on the substrate 102 and contacts the sidewalls of the word lines 112. A second dielectric layer 150B is formed on the first dielectric layer 150A. A third dielectric layer 150C is formed on the second dielectric layer 150B. The first dielectric layer 150A, the second dielectric layer 150B, and the third dielectric layer 150C are each formed of a dielectric material. Acceptable dielectric materials include oxides such as silicon oxide; nitrides such as silicon nitride; carbides such as silicon carbide; and the like; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, and the like. In some embodiments, the first dielectric layer 150A and the third dielectric layer 150C are formed of a first dielectric material (e.g., an oxide such as silicon oxide), while the second dielectric layer 150B is formed of a different second dielectric material (e.g., a nitride such as silicon nitride). The dielectric materials may be formed by an acceptable deposition process, such as ALD, CVD, etc. For example, the first dielectric layer 150A, the second dielectric layer 150B, and the third dielectric layer 150C may be formed by a combination of deposition, etching, and planarization in a manner similar to that described above with reference to the ferroelectric strip 114.

[0072] Fig.17A and Fig. 17B 5 are various views of a memory array 52 according to some other embodiments. A portion of the memory array 52 is shown. For clarity of illustration, some components are not shown, such as the staircase arrangement of word lines (see FIG. Figure 2B ). Fig.17A is a three-dimensional view of the memory array 52, Fig. 17B is shown with Fig.13A A cross-sectional view of a cross section similar to reference cross section BB.

[0073] In this embodiment, conductive strip 160 is formed between ferroelectric strip 114 and semiconductor strip 116. The formation of conductive strip 160 helps to avoid or reduce the formation of interlayer oxide on ferroelectric strip 114 during the formation of semiconductor strip 116. Avoiding or reducing the formation of interlayer oxide can increase the service life of memory array 52.

[0074] The conductive strips 160 may be formed of a metal such as ruthenium, tungsten, titanium nitride, tantalum nitride, molybdenum, etc. The conductive material of the conductive strips 160 may be formed by an acceptable deposition process such as ALD or CVD, an acceptable plating process such as electroplating or chemical plating, etc. The thickness of the conductive strips 160 may be in the range of about 1 nm to about 20 nm. The conductive strips 160 may be formed in a manner similar to the semiconductor strips 116 and may be formed during the formation of the semiconductor strips 116. The dielectric plugs 132 may (or may not) be formed through the conductive strips 160.

[0075] Fig.18A and Fig.18B 5 are various views of a memory array 52 according to some other embodiments. A portion of the memory array 52 is shown. For clarity of illustration, some components are not shown, such as the staircase arrangement of word lines (see FIG. Figure 2B ). Fig.18A is a three-dimensional view of the memory array 52, Fig.18B is shown with Fig.13A A cross-sectional view of a cross section similar to reference cross section BB.

[0076] In this embodiment, the adhesive layer 112A G and adhesive layer 112B G Formed from different materials to help reduce the overall resistivity. For example, adhesive layer 112A G The adhesive layer 112B may be formed of a first adhesive material (eg, titanium nitride). G The adhesive layer 112A may be formed of a second adhesive material (eg, tantalum nitride) having a different resistivity. G and adhesive layer 112B G They may not fuse during formation, making them independent and distinct from each other.

[0077] Fig.19A and Fig.19B 5 are various views of a memory array 52 according to some other embodiments. A portion of the memory array 52 is shown. For clarity of illustration, some components are not shown, such as the staircase arrangement of word lines (see FIG. Figure 2B ). Fig.19A is a three-dimensional view of the memory array 52, Fig.19B is along Fig.19A A cross-sectional view shown in reference section BB.

[0078] In this embodiment, the metallization pattern 142 of the interconnect structure 140 includes only the source line interconnect 142S. Another interconnect structure 170 is formed on the side of the substrate 102 opposite the interconnect structure 140. The interconnect structure 170 can be formed in a similar manner to the interconnect structure 140. The interconnect structure 170 can include, for example, a metallization pattern 172 in a dielectric material 174. Conductive vias 180 can be formed through the substrate 102 and the ferroelectric strips 114 to electrically couple the metallization pattern 172 to the bit line 134 and / or the source line 136. For example, the metallization pattern 172 includes a bit line interconnect 172B (which is electrically coupled to the source line 136 through the conductive via 180).

[0079] Furthermore, in this embodiment, the bit lines 134 and the source lines 136 are not formed in a staggered layout, so adjacent bit lines 134 and adjacent source lines 136 are arranged along the first direction D1 (see FIG. Figure 2B ) are laterally aligned with each other. Therefore, each word line 112 is laterally arranged between a pair of bit lines 134 or between a pair of source lines 136. Because the bit lines 134 and the source lines 136 are not formed in a staggered layout, the lateral interconnections to a subset of the source line interconnects 142S are implemented in the interconnect structure 140, while the lateral interconnections to a subset of the bit line interconnects 172B are implemented in the interconnect structure 170. For example, the source line interconnects 142S are straight conductive segments formed at an intermediate level of the interconnect structure 140. The lateral interconnections 146 between the first subset of the source line interconnects 142S and the first subset of the source lines 136 are formed at a lower level of the interconnect structure 140 than the source line interconnects 142S. The straight interconnections 148 between the second subset of the source line interconnects 142S and the second subset of the source lines 136 are formed at a lower level of the interconnect structure 140 than the source line interconnects 142S. Likewise, bitline interconnects 172B are straight conductive segments formed at an intermediate level of interconnect structure 170. Lateral interconnects 176 between a first subset of bitline interconnects 172B and a first subset of bitlines 134 are formed at a lower level of interconnect structure 170 than bitline interconnects 172B. Straight line interconnects 178 between a second subset of bitline interconnects 172B and a second subset of bitlines 134 are formed at a lower level of interconnect structure 170 than bitline interconnects 172B.

[0080] It should be noted that in other embodiments, the layouts of the interconnect structures 140, 170 may be flipped. For example, the metallization pattern 142 of the interconnect structure 140 may include a bit line interconnect, and the metallization pattern 172 of the interconnect structure 170 may include a source line interconnect.

[0081] FIG. 20A to FIG. 22B5 are various views of intermediate stages of manufacturing a memory array 52 according to some other embodiments. A portion of the memory array 52 is shown. For clarity of illustration, some components are not shown, such as the staircase arrangement of word lines (see FIG. Figure 2B ). Fig. 20A and Fig.21A is a three-dimensional view of memory array 52. Fig. 20B and Fig.21B is along Fig.21A A cross-sectional view shown in reference section BB. Fig.22A and Fig. 22B is a top view of a portion of memory array 52.

[0082] exist Fig. 20A and Fig. 20B In the reference Fig.13A and Fig. 13B The structure described above is similar to that described above, but the ferroelectric strip 114, the semiconductor strip 116, and the dielectric layer 118 are not formed in this processing step. Instead, the first trench 106 (see Figure 4A and Figure 4B ) and the second groove 120 (see Fig. 8A and Figure 8B ) are each filled with a dielectric layer 192. Dielectric layer 192 is formed of a dielectric material. Acceptable dielectric materials include oxides such as silicon oxide, nitrides such as silicon nitride, carbides such as silicon carbide, and the like, or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, and the like. The dielectric material may be formed by an acceptable deposition process, such as ALD, CVD, and the like. In some embodiments, silicon oxide is deposited in the first trench 106 and the second trench 120. A planarization process may be applied to each layer to remove excess dielectric material above the topmost first dielectric layer 104A. The planarization process may be chemical mechanical polishing (CMP), an etch-back process, a combination thereof, and the like. For example, a first planarization process may be performed after filling the first trench 106 to form dielectric layer 192, and a second planarization process may be performed after filling the second trench 120 to form dielectric layer 192.

[0083] exist Fig.21A and Fig.21B In the embodiment, a TFT thin film stack is formed extending through dielectric layer 192. The TFT thin film stacks each include ferroelectric strips 114, semiconductor strips 116, and dielectric layer 118. Then, bit lines 134 and source lines 136 are formed at least through dielectric layer 118.

[0084] Ferroelectric strips 114, semiconductor strips 116, and dielectric layer 118 may be formed by a combination of deposition, etching, and planarization. For example, openings may be formed through dielectric layer 192. These openings may be formed using acceptable photolithography and etching techniques. The ferroelectric layer may be conformally deposited in the openings through dielectric layer 192. Then, a semiconductor layer may be conformally deposited on the ferroelectric layer. Then, the semiconductor layer may be anisotropically etched to remove horizontal portions of the semiconductor layer, thereby exposing the ferroelectric layer. Then, a dielectric layer may be conformally deposited on the remaining vertical portions of the semiconductor layer and on the exposed portions of the ferroelectric layer. Then, a planarization process is applied to each layer to remove excess material above the topmost first dielectric layer 104A. The planarization process may be chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like. The portions of the ferroelectric layer, the portions of the semiconductor layer, and the portions of the dielectric layer remaining in the openings through dielectric layer 192 form ferroelectric strips 114, semiconductor strips 116, and dielectric layer 118, respectively. The planarization process exposes the topmost first dielectric layer 104A such that after the planarization process, the top surface of the topmost first dielectric layer 104A, the top surface of the ferroelectric strips 114, the top surface of the semiconductor strips 116, and the top surface of the dielectric layer 118 are coplanar (within process variations).

[0085] As an example of forming bit line 134 and source line 136, an opening for bit line 134 and an opening for source line 136 can be formed through dielectric layer 118, and optionally also through ferroelectric strip 114 and semiconductor strip 116. These openings can be formed using acceptable photolithography and etching techniques. Specifically, these openings are formed so that they are opposite to the sides of the remaining portion of dielectric layer 118. In some embodiments, the openings extend only through dielectric layer 118, so that bit line 134 and source line 136 extend only through dielectric layer 118 (e.g., Fig.22A104A). In some embodiments, the openings also extend through the ferroelectric strips 114 and the semiconductor strips 116, so that the bit lines 134 and the source lines 136 also extend through the ferroelectric strips 114 and the semiconductor strips 116. Then, one or more dielectric materials are formed in these openings. Acceptable conductive materials include metals such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, their alloys, etc. The conductive material can be formed by an acceptable deposition process such as ALD or CVD, an acceptable plating process such as electroplating or chemical plating, etc. In some embodiments, tungsten is deposited in the openings. Then, a planarization process is applied to each layer to remove excess conductive material above the topmost first dielectric layer 104A. The planarization process can be chemical mechanical polishing (CMP), an etch back process, a combination thereof, etc. The remaining conductive material forms the bit lines 134 and the source lines 136 in the openings. Interconnects may then be formed over (or under) bit line 134 and over (or under) source line 136 using similar techniques as described above, so that bit line 134 and source line 136 may be coupled to the bit line interconnect and source line interconnect, respectively.

[0086] However, by forming the first conductive feature 112A and the second dielectric material 122 before etching the second trench 120 and forming the second sidewall recess 124, the first conductive feature 112A and the second dielectric material 122 are present during subsequent etching processes, such as etching the second trench 120 and the second sidewall recess 124. As such, these unremoved structures can provide structural support during subsequent processes, thereby helping to prevent problems such as wordline swing or even wordline collapse. Avoiding these problems allows for the manufacture of smaller devices with fewer defects, thereby increasing overall yield.

[0087] According to an embodiment, a method for manufacturing a semiconductor device includes: etching a first trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers; depositing a first conductive material in the first trench; filling the remaining portion of the first trench with the first dielectric material; after filling the remaining portion of the first trench, etching a second trench in the multilayer stack; depositing a second conductive material in the second trench; filling the remaining portion of the second trench with the second dielectric material; etching the first conductive material and the second conductive material; and after etching the first conductive material and the second conductive material, depositing a channel material in the first trench. In an embodiment, the method further includes: after filling the remaining portion of the second trench, planarizing the second dielectric material with a portion of the dielectric layer; and before etching the first conductive material, removing the portion of the dielectric layer. In an embodiment, removing the portion of the dielectric layer forms an "H" shaped structure. In an embodiment, the first conductive material includes a first adhesive layer, and wherein depositing the second conductive material may deposit a second adhesive layer in physical contact with the first adhesive layer. In an embodiment, the method further includes recessing the sacrificial layer before depositing the first conductive material. In an embodiment, the method further comprises planarizing the first dielectric material and the first conductive material before etching the second trench. In an embodiment, the method further comprises depositing a ferroelectric material in the first trench.

[0088] According to another embodiment, a method of manufacturing a semiconductor device includes: forming an alternating stack of a first dielectric material and a sacrificial material; forming a first portion of a first word line within the alternating stack, the forming the first portion of the first word line including: etching a first trench in the alternating stack; forming a first recess by recessing a first portion of the sacrificial material exposed within the first trench; depositing a first conductive material in the first recess; and depositing a second dielectric material to fill a remaining portion of the first trench; and forming a second portion of the first word line within the alternating stack, the forming the second portion of the first word line including: etching a second trench in the alternating stack; forming a second recess by removing a second portion of the sacrificial material exposed within the second trench; depositing a second conductive material in the second recess; and depositing a third dielectric material to fill a remaining portion of the second trench. In an embodiment, the method further includes removing a top layer of the first dielectric material after depositing the third dielectric material. In an embodiment, removing the top layer of the first dielectric material leaves a "U"-shaped opening, wherein the sidewalls of the "U"-shaped opening include the first conductive material and the second conductive material. In an embodiment, removing the second portion of the sacrificial material may expose a portion of the first conductive material. In an embodiment, the method further comprises planarizing the third dielectric material after depositing the third dielectric material. In an embodiment, the third dielectric material is different from the second dielectric material. In an embodiment, the method further comprises: removing the second dielectric material and the third dielectric material; etching the first conductive material and the second conductive material; depositing a ferroelectric material adjacent to the first conductive material and the second conductive material; and depositing a channel material adjacent to the ferroelectric material.

[0089] According to yet another embodiment, a semiconductor device includes: a ferroelectric material extending away from a substrate; a channel material located on a first side of the ferroelectric material; a first dielectric material extending away from a second side of the ferroelectric material opposite the first side; a second dielectric material extending away from the second side of the ferroelectric material; a first conductive material extending away from the second side of the ferroelectric material between the first dielectric material and the second dielectric material, the first conductive material including a bulk material and a first adhesive layer; and a second conductive material extending away from the first conductive material between the first dielectric material and the second dielectric material, the second conductive material including a second bulk material and a second adhesive layer, the second adhesive layer being in physical contact with the first adhesive layer. In an embodiment, the semiconductor device also includes a second ferroelectric material in physical contact with the second conductive material. In an embodiment, the semiconductor device further comprises: a third dielectric material extending away from the second side of the ferroelectric material; a third conductive material extending away from the second side of the ferroelectric material between the third dielectric material and the second dielectric material, the second conductive material comprising a third bulk material and a third adhesive layer; and a fourth conductive material extending away from the third conductive material between the third dielectric material and the second dielectric material, the fourth conductive material comprising a fourth bulk material and a fourth adhesive layer, the fourth adhesive layer being in physical contact with the third adhesive layer. In an embodiment, the first conductive material and the second conductive material have a width of about 80 nm in total. In an embodiment, the first conductive material and the second conductive material form a word line of a memory cell. In an embodiment, the memory cell is part of a three-dimensional memory array.

[0090] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: etching a first trench in a multilayer stack comprising alternating dielectric layers and sacrificial layers; depositing a first conductive material in the first trench; filling a remaining portion of the first trench with a first dielectric material; etching a second trench in the multilayer stack after filling the remaining portion of the first trench; depositing a second conductive material in the second trench; filling a remaining portion of the second trench with a second dielectric material; planarizing the second dielectric material with a portion of the dielectric layer after filling the remaining portion of the second trench; removing the portion of the dielectric layer; after removing the portion of the dielectric layer, etching the first conductive material and the second conductive material; as well as After etching the first conductive material and the second conductive material, a channel material is deposited in the first trench.

2. The method according to claim 1, wherein: The first conductive material is in physical contact with the second conductive material.

3. The method according to claim 1, wherein: The portion of the dielectric layer is removed to form an "H" shaped structure.

4. The method according to claim 1, wherein: The first conductive material includes a first adhesive layer, and wherein depositing the second conductive material deposits a second adhesive layer in physical contact with the first adhesive layer. 5 . The method of claim 1 , further comprising recessing the sacrificial layer before depositing the first conductive material. 6 . The method of claim 1 , further comprising planarizing the first dielectric material and the first conductive material before etching the second trench.

7. The method of claim 1, further comprising depositing a ferroelectric material in the first trench.

8. A method for manufacturing a semiconductor device, the method comprising: forming an alternating stack of a first dielectric material and a sacrificial material; forming a first portion of a first word line within the alternating stack, the forming the first portion of the first word line comprising: etching a first trench in the alternating stack; forming a first recess by recessing a first portion of the sacrificial material within the first trench; depositing a first conductive material in the first recess; and depositing a second dielectric material to fill a remaining portion of the first trench; and forming a second portion of the first word line in the alternating stack, the forming the second portion of the first word line comprising: etching a second trench in the alternating stack; forming a second recess by removing a second portion of the sacrificial material exposed within the second trench; depositing a second conductive material in the second groove; depositing a third dielectric material to fill a remaining portion of the second trench; and After depositing the third dielectric material, the top layer of the first dielectric material is removed, wherein the sidewalls of the opening left by removing the top layer of the first dielectric material include the first conductive material and the second conductive material.

9. The method according to claim 8, wherein: The first conductive material is in physical contact with the second conductive material.

10. The method according to claim 8, wherein: The opening left by removing the top layer of the first dielectric material is a "U" shaped opening.

11. The method according to claim 8, wherein: Removing the second portion of the sacrificial material may expose a portion of the first conductive material. 12 . The method of claim 8 , further comprising planarizing the third dielectric material after depositing the third dielectric material.

13. The method according to claim 8, wherein: The third dielectric material is different from the second dielectric material.

14. The method according to claim 8, further comprising: removing the second dielectric material and the third dielectric material; etching the first conductive material and the second conductive material; depositing a ferroelectric material adjacent to the first conductive material and the second conductive material; as well as A channel material is deposited adjacent to the ferroelectric material.

15. A semiconductor device comprising: a ferroelectric material extending away from the substrate; a channel material disposed on a first side of the ferroelectric material; a first dielectric material extending away from a second side of the ferroelectric material opposite the first side; a second dielectric material extending away from the second side of the ferroelectric material; a first conductive material extending away from the second side of the ferroelectric material between the first dielectric material and the second dielectric material, the first conductive material comprising a first bulk material and a first adhesive layer; a second conductive material extending away from the first conductive material between the first dielectric material and the second dielectric material, the second conductive material comprising a second bulk material and a second adhesive layer, the second adhesive layer being in physical contact with the first adhesive layer; as well as a second ferroelectric material in physical contact with the second conductive material, The channel material is also located on the second side of the ferroelectric material, the channel material on the first side and the channel material on the second side have a gap between the first side and the second side, and the ferroelectric material continuously extends across the gap.

16. The semiconductor device according to claim 15, wherein: The first bulk material is formed of tungsten, and the first adhesive layer is formed of titanium nitride.

17. The semiconductor device according to claim 15, further comprising: a third dielectric material extending away from the second side of the ferroelectric material; a third conductive material extending away from the second side of the ferroelectric material between the third dielectric material and the second dielectric material, the second conductive material comprising a third bulk material and a third adhesive layer; as well as A fourth conductive material extends away from the third conductive material between the third dielectric material and the second dielectric material, wherein the fourth conductive material comprises a fourth bulk material and a fourth adhesive layer, and the fourth adhesive layer is in physical contact with the third adhesive layer.

18. The semiconductor device according to claim 15, wherein: The first conductive material and the second conductive material collectively have a width of 80 nm.

19. The semiconductor device according to claim 15, wherein: The first conductive material and the second conductive material form a word line of a memory cell.

20. The semiconductor device according to claim 19, wherein The memory cell is part of a three-dimensional memory array.

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