Reduction of Radio Frequency Loss for Integrated Devices

Abstract

Embodiments of the present disclosure relate to reducing radio frequency (RF) losses for integrated devices. In RF devices integrated on a semiconductor-on-insulator (e.g., silicon-based) substrate, RF losses can be reduced by increasing the resistivity of a semiconductor device layer near (e.g., below and / or wholly or partially surrounding) a metallization structure (e.g., a transmission line, contact, or bond pad) of the RF device. The increased resistivity can be achieved, for example, by ion implantation or by patterning the device layer to create disconnected semiconductor islands.

Description

Technical Field

[0001] The present disclosure relates to reducing radio frequency (RF) losses in RF devices such as high-speed photonic devices and interconnects. Background Art

[0002] High-speed silicon photonic devices (e.g., optical modulators and photodiodes) include optical and electronic components. Many of the optical components are formed in a silicon device layer on top of a buried oxide (BOX) or other insulating layer. Due to increased RF losses and additional parasitic elements, the conductivity of this silicon layer (e.g., a silicon slab in the area remaining around the silicon device structure) can negatively impact the RF performance of the device. Although in some cases this problem can be addressed by removing the silicon slab under the RF metal pads and lines, in many cases this solution is not available due to manufacturing considerations and the requirements of the optical device configuration. For example, in some devices, optical waveguides or other optical structures formed in the silicon layer occupy the substrate surface near the metal pads and lines, significantly restricting the area from which silicon can be removed. Additionally, even in areas without devices, it is not possible to remove silicon across substantial regions because silicon removal has a tendency to disrupt the structural integrity of the substrate. Thus, an alternative to simply removing the silicon under the metal lines and pads is desired. Summary of the Invention

[0003] According to some embodiments, a radio frequency (RF) structure includes: a substrate including a semiconductor device layer disposed on an insulating layer; a semiconductor device structure integrating an RF device, the semiconductor device structure being formed in or on the semiconductor device layer; and at least one metallization structure disposed on the semiconductor device layer, the at least one metallization structure operative to convey an RF signal to or from the integrated RF device, wherein the semiconductor device layer is patterned to form a plurality of disconnected semiconductor islands that extend at least over an area at least partially surrounding the at least one metallization structure.

[0004] According to some embodiments, a method of manufacturing a radio frequency (RF) structure includes: patterning and etching a semiconductor device layer of a semiconductor-on-insulator substrate to create a plurality of disconnected semiconductor islands in the semiconductor device layer; forming a semiconductor device structure integrating an RF device in or on the semiconductor device layer; and disposing at least one metallization structure on the semiconductor device layer, the at least one metallization structure operable to convey an RF signal to or from the integrated RF device, wherein the semiconductor islands are formed at least over an area at least partially surrounding the at least one metallization structure.

[0005] According to some embodiments, a radio frequency (RF) structure includes: a substrate including a semiconductor device layer disposed on an insulating layer; a semiconductor device structure of an integrated RF device formed in or on the semiconductor device layer; and at least one metallization structure disposed above the semiconductor device layer for transmitting RF signals to or from the integrated RF device, wherein the semiconductor device layer above at least the region at least partially surrounding the at least one metallization structure includes implanted ions that increase the resistivity of the semiconductor device layer.

[0006] According to some embodiments, a method of manufacturing a radio frequency (RF) structure includes: increasing the resistivity of a portion of a semiconductor device layer of a semiconductor-on-insulator substrate by ion implantation; forming a semiconductor device structure of an RF device in or on the semiconductor device layer; and depositing at least one metallization structure above the semiconductor device layer, the at least one metallization structure operable to transmit RF signals to or from an RF photonic device, wherein the portion of the semiconductor device layer extends above at least the region at least partially surrounding the at least one metallization structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view of an example RF photonic structure including optical and electronic components according to various embodiments.

[0008] Figure 2 is a schematic top view of an example RF photonic structure including optical and electronic components according to various embodiments.

[0009] Figure 3 is a schematic cross-sectional view illustrating an example p-i-n diode structure of device metallization according to one embodiment.

[0010] Figure 4A and Figure 4B are respectively a schematic top view and a cross-sectional view illustrating an example Mach-Zehnder modulator of a transmission line according to one embodiment.

[0011] Figure 5 is a schematic cross-sectional view illustrating patterning of a silicon device layer of an example RF photonic structure as Figure 1 shown.

[0012] Figure 6 is a schematic top view of an example RF photonic structure according to one embodiment, the top view illustrating a rectangular grid channel pattern of the positions of optical and electronic components in a silicon device layer relative to Figure 2 thereof.

[0013] Figure 7 is a schematic top view of an exemplary RF photonic structure according to one embodiment, the top view illustrating a triangulation channel pattern of the positions of optical and electronic components in a silicon device layer relative to Figure 2 that.

[0014] Figure 8 is a flow chart of a method of fabricating an RF photonic structure according to various embodiments. DETAILED DESCRIPTION

[0015] Described herein are methods for reducing RF losses associated with integrated RF devices by increasing the average resistivity (i.e., decreasing the average conductivity) of a device layer at least near the metallization structure (such as metal lines and pads) of the device and, in some cases, across the entire device layer except for the regions defining the semiconductor device structures. In some embodiments, the increased resistivity is achieved by ion implantation of, for example, hydrogen (H), helium (He), boron (B), lithium (Li), carbon (C), or other suitable materials. In other embodiments, the device layer is patterned to form disconnected islands separated by non-conductive (e.g., dielectric-filled) channels that are used to interrupt eddy currents induced in the device layer. These islands can decrease in size and increase in density towards the edges of the metallization structure, where eddy currents tend to be strongest.

[0016] In the following, RF loss reduction is specifically described for photonic devices implemented in a silicon-on-insulator (SOI) substrate. However, as will be understood by those of ordinary skill in the art, the disclosed RF loss reduction methods are not limited to photonic devices, but are equally applicable to any RF device (including RF electronic devices and sensors) implemented in a semiconductor-on-insulator substrate. Additionally, although integrated devices are typically implemented on an SOI substrate, semiconductor materials other than silicon (e.g., germanium, indium phosphide, gallium arsenide, etc.) can also be used for the device layer and the device structures (such as waveguides) formed therein.

[0017] Figure 1An example RF photonic structure 100 in accordance with various embodiments is illustrated in a schematic cross-sectional view. The structure 100 includes optical and electronic device components that are formed on an SOI substrate that includes a processing layer 102 (e.g., made of silicon, diamond, or another suitable material), and the optical and electronic device components are separated from the processing layer 102 by a buried oxide (BOX) or another dielectric layer (also collectively referred to herein as an “insulating layer”) 104, a silicon device layer 106. Silicon waveguides and / or other silicon device structures 108 may be formed in the silicon device layer 106. As shown, the silicon device structure 108 may result from a partial etch of the silicon device layer 106 that causes the thickness of the silicon slab 110 to be less than the thickness of the original silicon device layer 106 across portions of the substrate. Alternatively, the profile of the silicon device structure 108 may be defined by a channel etched into the silicon device layer 106 down to the insulating layer 104. In addition to any silicon device structure(s) 108 in the silicon device layer, the RF photonic structure 100 may also include other semiconductor device structures (not shown) disposed above the silicon device layer 106, such as made of III-V or other compound semiconductor materials. For example, many laser diodes, photodiodes, optical amplifiers, and optical modulators include an active device layer or a p-i-n layer stack made of III-V materials. The silicon device layer 106 and any semiconductor device structures formed in or above the silicon device layer 106 may be covered in a top cladding layer 112, such as an oxide or other dielectric. To enable the application or readout of RF signals, the RF photonic structure 100 includes one or more metallization structures 114 that are embedded in (or alternatively disposed on) the top cladding layer 112. As shown, the metallization structure 114 may include metal layers 116 at multiple levels above the silicon device layer 106, and the metal layers 116 are connected by vertical metal vias 118.

[0018] Figure 2 An example RF photonic structure 200 in accordance with various embodiments (e.g., Figure 1 of the structure 100) is provided in a schematic top view, Figure 2Various types of metallization structures (e.g., 114) are further illustrated. As shown, the metallization structure can include a type of device metallization 202 (i.e., metal directly disposed on one or more semiconductor device structures of an RF photonic device). Another type of metallization structure is a transmission line, which includes a pair of electrodes 204 connected to two terminals of an RF voltage source. At least a portion of the length of the electrodes 204 can extend along a semiconductor device formed in or on a silicon device layer (e.g., along both sides of the waveguide 206 as shown). Additionally, the RF photonic structure 200 typically includes metal bond pads 208 for wire bonding to a photonic chip, and general metal wires or traces 210 that can establish electrical connections between the metallization structures within the device, or extend across the chip to form interconnections between multiple devices or between a device and a bond pad (e.g., between the transmission line electrodes 204 and the bond pad 208 as shown).

[0019] Figure 3 A p-i-n diode structure 300 that can be used in an RF photonic device such as a laser diode, a photodiode, or an electro-absorption modulator is shown as an example of an RF photonic structure with device metallization. As shown in the cross-sectional view, the p-i-n diode can take the form of a layered structure with a narrower mesa 302 that includes an intrinsic layer 304 and a p-type layer 306 stacked on top of a wider strip of n-type material 308. To establish electrical connections to the p-type layer 306 and the n-type layer 308 of the diode, p-side metal contact vias 310 can be disposed across the top p-type layer 306, and an n-side metal layer 312 can be set on both sides of the mesa 302 on the n-type layer 308, where vertical contact vias 314 in turn extend from the n-side metal layer 312. The contact vias 310, 314 can extend to the top of the top cladding layer, where they can be connected directly or via a metal wire to a metal bond pad (not shown) that constitutes an electrical terminal of the photonic chip.

[0020] Figure 4A and Figure 4B A waveguide-based Mach-Zehnder modulator 400 is shown as an example of an RF photonic structure that includes a transmission line. As Figure 4AAs shown in the top view, the Mach-Zehnder modulator 400 includes an input waveguide 402 that branches into two interferometric waveguide arms 404, 406, which then recombine into an output waveguide 408. Electrodes 410, 412 with opposite polarities are disposed on both sides of the interferometric waveguide arms 404, 406 and are each connected to one of the interferometric waveguide arms 404, 406 via contact traces 414. The RF signal applied between these electrodes 410, 412 can be used to electro-optically modulate the relative optical phase between the light propagating along the two waveguide arms 404, 406, thereby modulating the amplitude of the optical signal in the output waveguide 408. As Figure 4B shown in the cross-sectional view of, each interferometer arm 404, 406 can be implemented as a compound waveguide that includes a silicon rib waveguide 416 formed in a silicon device layer 418 and a III-V waveguide 420 disposed on top of the rib waveguide 416. The contact traces 414 can be connected to device metallization 422 on the III-V waveguide 420.

[0021] In RF photonic devices, the desired electro-optic modulation of the optical properties of semiconductor device structures (such as the refractive index of a waveguide or the absorption edge of an intrinsic diode layer) is typically accompanied by undesirable parasitic currents (including eddy currents induced in the silicon device layer by the changing magnetic field of the RF signal). These parasitic currents cause energy losses, which reduce the device performance, for example, by reducing the modulation amplitude of an optical modulator, the signal strength of a photodiode, etc. According to various embodiments, by modifying the silicon device layer to reduce its conductivity and thus reduce the parasitic currents, the RF losses are reduced and the RF performance of the device is correspondingly increased.

[0022] Figure 5 is a schematic cross-sectional view of an exemplary RF photonic structure 500 according to various embodiments, as Figure 1 shown, in which a silicon (or other semiconductor) device layer 106 is patterned with current-interrupting insulating channels 502 (depicted as vertical lines, only a few are labeled). These channels 502 can be etched into the silicon device layer 106 and, depending on the process details, have a width in the range between 0.5 μm and 2 μm (e.g., approximately 1 μm). For example, due to the deposition of a top cladding layer 112 on top of the patterned silicon device layer 106, the channels 502 can be filled with a dielectric material. As Figure 6 and Figure 7As shown in the top view, the channels can be oriented in multiple directions (in the plane of the silicon device layer 106) so as to intersect or meet each other, and thus form a two-dimensional grid or network of channels. The two-dimensional grid or network of channels forms disconnected regions of silicon (referred to herein as "silicon islands" (or more generally "semiconductor islands")) between the channels. In some embodiments, the silicon islands are sized in the range of from about 1 μm to about 50 μm, or in a narrower range of from about 4 μm to about 20 μm. By "cutting" the silicon device layer 106 in this way, eddy currents across the silicon device layer 106 are interrupted, thereby avoiding large-scale current loops. Referring again to Figure 5 , the channels 502 preferably extend through the silicon device layer 106 all the way to the insulating (e.g., BOX) layer 104 so that the silicon islands are electrically isolated from each other, thereby eliminating current flow between the islands and confining the eddy currents to much smaller regions within each island. However, even partially etched channels will tend to reduce the overall eddy current flow across the silicon device layer 106.

[0023] Figure 6 is a schematic top view of an exemplary RF photonic structure 600 according to one embodiment, Figure 6 illustrating a rectangular grid channel pattern in the silicon device layer with respect to the positions of the metallization structures 202, 204, 208, 210 and the waveguide 206 in Figure 2 . In this example, the silicon device layer includes two parallel sets of straight channels 602, 604 (only a few channels are labeled in each set), and the two sets intersect each other to form a quadrilateral grid. More specifically, in the example shown, the channels 602 of one set are oriented parallel to the waveguide 206, while the channels 604 of the other set are oriented perpendicular to the waveguide 206, such that the channels 602, 604 form a rectangular grid with rectangular silicon islands 606 (only a few are labeled). The channels 602, 604 do not have to intersect at right angles, but can define silicon islands in the shape of a parallelogram. Additionally, a third parallel set of channels can intersect at the intersection of the first and second sets to form a triangular grid. Those of ordinary skill in the art can envision additional configurations of the grid lines.

[0024] As Figure 6As shown, the grid formed by the intersecting channels 602, 604 need not be uniform, but the spacing between the channels can vary, resulting in silicon islands 606 of varying sizes across the silicon device layer. The channels 602, 604 can be spaced particularly densely in the region directly beneath or in the immediate vicinity of the metallization structures 202, 204, 208, 210 and form the smallest silicon islands 606. Towards greater distances from the metallization structures 202, 204, 208, 210, as typically indicated for regions 608 remote from bond pads, transmission lines, and device metallization, the spacing between adjacent channels 602, 604 can increase, or the channels can even disappear completely. This decreasing channel density with increasing distance from the metallization structures reflects, first, that the induced eddy currents have a lower amplitude at greater distances. Additionally, even in proximity to the metallization structures, channels can be omitted from regions of the silicon device layer that define the silicon device structures or include other (e.g., III-V) semiconductor device structures disposed on the silicon to avoid interfering with device functionality. For example, Figure 6 A strip 610 surrounding the waveguide 206 is shown, where the silicon slab remains channel-free.

[0025] Figure 7 is a schematic top view of an exemplary RF photonic structure 700 according to one embodiment, Figure 7 illustrating a triangulated channel patterning with respect to the Figure 2 metallization structures 202, 204, 208, 210 and the waveguide 206 in the silicon device layer. In this example, the channels 702 are formed as short segments in various orientations, meeting in groups of three or more at the vertices of a channel network that divides the region of the silicon device layer into triangles. Similar to the RF photonic structure 600 with a rectangular grid channel pattern, the channel density can be higher near the metallization structures, and the silicon islands are correspondingly smaller. In some embodiments, as Figure 7 most clearly shown, for the metal bond pad 208 and the associated contact trace 210, the islands can be smallest in the region beneath the edge of the metallization structure. Only as Figure 6 shown, the waveguide 206 is joined on both sides by strips of unpatterned channel-free silicon.

[0026] Figure 6 and Figure 7The two channel patterns depicted are of course merely examples, and those of ordinary skill in the art will envision other channel configurations that divide the silicon device layer into multiple disconnected silicon islands. Generally, the silicon islands are located or concentrated in number and density in regions where the RF current is strongest and the insulating channels thus achieve the greatest performance improvement. These regions typically include portions of the silicon device layer that are beneath the metallization structure and / or (laterally) fully or partially surround the metallization structure, particularly regions along the edges of the metallization structure. Due to nearby semiconductor device components, it may not always be possible to fully surround the metallization structure. For example, a silicon waveguide in the region between the electrodes of a transmission line may prevent patterning beneath or between the inner edges of the patterned electrodes, but in such cases, patterning beneath and around the outer edges of the electrodes can still achieve a significant reduction in radio frequency losses.

[0027] As Figures 5 - 7 shown, patterning of the silicon device layer with electrically insulating channels that define disconnected silicon islands can interrupt the free flow of RF-induced eddy currents and thus reduce the average conductivity of the silicon device layer. Advantageously, such a reduction in conductivity (or increase in resistivity) is achieved by removing only a small portion (e.g., less than 10% in some embodiments) of the silicon material in the silicon device layer, thereby maintaining most of the structural support provided by the layer. In some cases, limiting the material removal to a small portion can also serve to meet layer density balance requirements imposed in the manufacturing process.

[0028] An alternative method of increasing the resistivity of the silicon device layer (in regions beneath the metallization structure and / or fully or partially surrounding the metallization structure) is by ion implantation. In this process, ions of a suitable material (e.g., H, He, B, Li, or C) are accelerated towards the SOI substrate into the SOI substrate (usually before any patterning of the silicon device layer), where the ion implantation parameters are selected such that a reduction in the conductivity of the silicon device layer is caused. Generally, ion implantation can result in electrically active crystal defects in the silicon lattice and can increase the resistivity of the silicon layer. In some embodiments, an increase in resistivity of two to three orders of magnitude is achieved. The ion implantation parameters that can be adjusted to achieve the desired resistivity increase include, in addition to the ion type, the ion energy (as they are about to impinge on the substrate), the ion dose, and various annealing parameters (e.g., annealing duration, temperature, temperature ramp, and ambient gas). Suitable combinations of ion implantation parameters are known to those of ordinary skill in the art. Just to provide one example, hydrogen ion implantation can use 100KeV H 14 to 2·10 16 ions / cm 2 between, and H + ions, and H +After implantation, thermal annealing can be carried out in two stages: rapid thermal annealing (e.g., over a period of about one minute, a steep temperature slope of about 50 °C / s, and a plateau of about 900 °C), followed by conventional thermal annealing (e.g., with a duration between a few minutes and two hours and a temperature of about 1200 °C). According to various embodiments, when ion implantation is used to increase the resistivity of a silicon layer, layer regions having a functional role (e.g., including semiconductor device structures) are typically masked before implantation.

[0029] Figure 8 FIG. 800 is a flow chart of a method 800 for fabricating an RF photonic structure. According to various embodiments, method 800 incorporates steps for increasing the resistivity of a silicon device layer at least in the vicinity of a metallization structure. Method 800 begins at step 802 by providing a (generic) SOI substrate (or more generally, a semiconductor-on-insulator substrate). In some embodiments, the resistivity of a silicon (or other semiconductor) device layer is increased by ion implantation. In such cases, a mask layer is first deposited on the silicon device layer and the mask layer is patterned to at least mask regions of the device layer where sensitive structures (e.g., semiconductor device structures) will be placed (803). Then, by ion implantation, the exposed regions of the silicon device, particularly including the regions where the metallization structure will be placed, are processed to increase the resistivity (804). Then, in one or more steps, the silicon device layer is lithographically patterned and etched (collectively referred to herein as "patterning") to form silicon device structures and / or insulating channels that divide regions outside the (multiple) device structures and regions near the location where the metallization structure will be placed into multiple disconnected silicon islands (806). (For substrates in which resistivity-increasing ions are implanted in the silicon device layer, creating insulating channels is optional.) Depending on the specific structure and etch depth of the (multiple) silicon device structures, these structures (or portions thereof) and the insulating channels can be created simultaneously or in separate steps. For example, a ridge waveguide whose sidewalls extend all the way down to the insulating layer of the substrate can be defined and etched in the same step as the insulating channel. On the other hand, a rib waveguide extending from the underlying silicon slab can be created by partially etching the silicon device layer and then lithographically patterning and fully etching the remaining silicon slab to form the insulating channel.

[0030] After patterning of the silicon device layer, additional semiconductor device structures (808) can be created on top of the silicon device layer. For example, in some embodiments, another semiconductor material (e.g., silicon nitride) layer is deposited and patterned to form additional device structures (e.g., silicon nitride waveguides). In other embodiments, compound semiconductor (e.g., III-V) die are bonded to the silicon device layer and then patterned, e.g., to form mesa structures. In some embodiments, the surfaces of some of the semiconductor device structures are metallized, e.g., to form an electrical contact layer (810). A top dielectric cladding can then be disposed over the substrate and the semiconductor device structures (812). Via holes can be formed by lithographic patterning and etching the cladding and then filled with metal to form vertical metal vias (814), and / or by depositing and patterning metal layers to create horizontal metallization structures (816), to create metallization structures in and on the top dielectric cladding. Deposition and patterning of dielectric and metal layers can be alternately repeated to form metallization structures at multiple levels (including, e.g., metal bond pads at the top), where the metal vias connect different levels vertically. Method 800 ends with a completed RF photonic structure within the PIC (at 818), ready for integration and packaging with an electronic circuit chip.

[0031] An overall method for reducing RF losses in integrated devices has been described with reference to the drawings. The following numbered list describes various example embodiments.

[0032] 1. A radio frequency (RF) structure, comprising: a substrate including a semiconductor device layer disposed on an insulating layer; semiconductor device structures of an integrated RF device, the semiconductor device structures being formed in or on the semiconductor device layer; and at least one metallization structure disposed over the semiconductor device layer, the at least one metallization structure configured to convey RF signals to or from the integrated RF device, wherein the semiconductor device layer is patterned to form a plurality of disconnected semiconductor islands that extend at least over an area at least partially surrounding the at least one metallization structure.

[0033] 2. The RF structure of example 1, wherein the disconnected semiconductor islands extend at least over an area completely surrounding the at least one metallization structure.

[0034] 3. The RF structure of example 1 or example 2, wherein the disconnected semiconductor islands extend over the semiconductor device layer except for an area including and adjacent to the semiconductor device structures.

[0035] 4. The RF structure of any one of examples 1 to 3, wherein the plurality of disconnected semiconductor islands are formed between channels etched into the semiconductor device layer.

[0036] 5. The RF structure according to Example 4, wherein the channels form a rectangular grid.

[0037] 6. The RF structure according to Example 4, wherein the channels divide the patterned region into triangles.

[0038] 7. The RF structure according to any one of Examples 4 to 6, wherein the channels have a width between 0.5 μm and 2 μm.

[0039] 8. The RF structure according to any one of Examples 1 to 7, wherein the sizes of the disconnected islands are non-uniform and increase with the increasing distance from the edge of at least one metallization structure.

[0040] 9. The RF structure according to any one of Examples 1 to 8, wherein the semiconductor islands have dimensions between approximately 1 μm and approximately 50 μm.

[0041] 10. The RF structure according to any one of Examples 1 to 9, wherein at least one metallization structure includes at least one of the following: device metallization, electrodes, contact traces, or bond pads.

[0042] 11. The RF structure according to any one of Examples 1 to 10, wherein the semiconductor device structure includes at least one of the following: a semiconductor device structure formed in the semiconductor device layer, or a semiconductor device structure disposed on top of the semiconductor device layer.

[0043] 12. The RF structure according to any one of Examples 1 to 11, wherein the integrated RF device is a photonic device.

[0044] 13. The RF structure according to any one of Examples 1 to 12, wherein the integrated RF device includes at least one of the following: a laser diode, an optical modulator, a photodetector, or an optical switch.

[0045] 14. A method of manufacturing a radio frequency (RF) structure, the method comprising: patterning and etching a semiconductor device layer of a semiconductor-on-insulator substrate to form a plurality of disconnected semiconductor islands in the semiconductor device layer; forming a semiconductor device structure of an integrated RF device in the semiconductor device layer or on the semiconductor device layer; and disposing at least one metallization structure on top of the semiconductor device layer, the at least one metallization structure being operable to transmit RF signals to or from the integrated RF device, wherein the semiconductor islands are formed at least over a region that at least partially surrounds the at least one metallization structure.

[0046] 15. The method according to Example 14, wherein the semiconductor device structure includes a semiconductor device structure formed in the semiconductor device layer simultaneously with the disconnected semiconductor islands by patterning and etching.

[0047] 16. A radio frequency (RF) structure includes: a substrate including a semiconductor device layer disposed on an insulating layer; a semiconductor device structure integrating an RF device, the semiconductor device structure being formed in or on the semiconductor device layer; and at least one metallization structure disposed above the semiconductor device layer, the at least one metallization structure being configured to transmit RF signals to or from the integrated RF device, wherein the semiconductor device layer above at least a region at least partially surrounding the at least one metallization structure includes implanted ions that increase the resistivity of the semiconductor device layer.

[0048] 17. The RF structure according to Example 16, wherein the implanted ions include at least one of the following: hydrogen, helium, boron, lithium, or carbon.

[0049] 18. The RF structure according to Example 16 or Example 17, wherein the metallization structure includes at least one of the following: device metallization, an electrode, a contact trace, or a bonding pad.

[0050] 19. The RF structure according to any one of Examples 16 to 18, wherein the semiconductor device structure includes at least one of the following: a semiconductor device structure formed in the semiconductor device layer, or a semiconductor device structure disposed on the semiconductor device layer.

[0051] 20. The RF structure according to any one of Examples 16 to 19, wherein the integrated RF device is a photon device.

[0052] 21. The RF structure according to any one of Examples 16 to 20, wherein the integrated RF device includes at least one of the following: a laser diode, an optical modulator, a photodetector, or an optical switch.

[0053] 22. A method of manufacturing a radio frequency (RF) structure, the method includes: increasing the resistivity of a portion of a semiconductor device layer of a semiconductor-on-insulator substrate by ion implantation; forming a semiconductor device structure of an RF device in or on the semiconductor device layer; and disposing at least one metallization structure above the semiconductor device layer, the at least one metallization structure being operable to transmit RF signals to or from an RF photon device, wherein the portion of the semiconductor device layer extends above a region at least partially surrounding the at least one metallization structure.

[0054] 23. The method according to Example 22, further including, before the ion implantation: masking the semiconductor device layer at least in a region including the semiconductor device structure.

[0055] 24. The structure according to any one of Examples 1 to 13 or 16 to 21, wherein the semiconductor device layer is a silicon layer.

[0056] 25. A method according to any one of Examples 14, 15, 22 or 23, wherein the semiconductor device layer is a silicon layer.

[0057] Although the subject matter of the present invention has been described with reference to specific exemplary embodiments, it is apparent that various modifications and changes can be made to these embodiments without departing from the broader scope of the subject matter of the present invention. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A radio frequency (RF) structure, comprising: A substrate, the substrate including a semiconductor device layer disposed on an insulating layer; A semiconductor device structure integrating RF devices, the semiconductor device structure being formed in or on the semiconductor device layer; And At least one metallization structure, the at least one metallization structure being disposed above the semiconductor device layer, the at least one metallization structure for transmitting RF signals to or from the integrated RF devices, Wherein the semiconductor device layer is patterned to form a plurality of disconnected semiconductor islands, the disconnected semiconductor islands extending at least over an area at least partially surrounding the at least one metallization structure.

2. The RF structure according to claim 1, wherein the disconnected semiconductor islands extend at least over an area completely surrounding the at least one metallization structure.

3. The RF structure according to claim 1, wherein the disconnected semiconductor islands extend over the semiconductor device layer except for an area including and adjacent to the semiconductor device structure.

4. The RF structure according to claim 1, wherein the plurality of disconnected semiconductor islands are formed between channels etched into the semiconductor device layer.

5. The RF structure according to claim 4, wherein the channels form a rectangular grid.

6. The RF structure according to claim 4, wherein the channels divide the patterned area into triangles.

7. The RF structure according to claim 4, wherein the channels have a width between 0.5 μm and 2 μm.

8. The RF structure according to claim 1, wherein the sizes of the disconnected islands are non-uniform, and the sizes increase with the distance from the edge of the at least one metallization structure.

9. The RF structure according to claim 1, wherein the semiconductor islands have dimensions between approximately 1 μm and approximately 50 μm.

10. The RF structure according to claim 1, wherein the at least one metallization structure includes at least one of the following: device metallization, electrodes, contact traces, or bond pads.

11. The RF structure according to claim 1, wherein the semiconductor device structure includes at least one of the following: a semiconductor device structure formed in the semiconductor device layer, or a semiconductor device structure disposed on the semiconductor device layer.

12. The RF structure according to claim 1, wherein the integrated RF device is a photonic device.

13. The RF structure according to claim 1, wherein the integrated RF device includes at least one of the following: a laser diode, an optical modulator, a photodetector, or an optical switch.

14. A method of manufacturing a radio frequency (RF) structure, the method comprising: Patterning and etching a semiconductor device layer of a semiconductor-on-insulator substrate to create a plurality of disconnected semiconductor islands in the semiconductor device layer; Forming a semiconductor device structure integrating RF devices in or on the semiconductor device layer; And At least one metallization structure is provided over the semiconductor device layer, the at least one metallization structure being operable to convey RF signals to or from the integrated RF device, wherein the semiconductor island is formed at least over an area that at least partially surrounds the at least one metallization structure.

15. The method according to claim 14, wherein the semiconductor device structure comprises semiconductor device structures formed in the semiconductor device layer by patterning and etching simultaneously with the disconnected semiconductor island.

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