Pseudo dual-port memory and control method thereof

Abstract

The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first read result corresponding to the first address and a second read result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data according to a first control signal to generate first data used as a first read result, and the second sense amplifier receives the output data according to a second control signal to generate second data used as a second read result.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to dual-port memories, and more particularly, to a pseudo dual-port memory and a control method thereof. Background Art

[0002] Dual-port memory processes two operations, for example, two read operations, in a single clock cycle. Dual-port memory typically includes two ports that operate with an array of memory cells, which can be accessed from both ports simultaneously. In order to reduce the area occupied by the memory, pseudo dual-port memory is used. Pseudo dual-port memory is designed to perform two operations on a single-port memory in a single clock cycle using a time interleaving mechanism. For example, in a clock cycle, a pseudo dual-port memory can perform a first read operation and then a second read operation.

[0003] Taking the two-read operation of the conventional pseudo dual port as an example, the sense amplifier is enabled twice in a single clock signal to output two read results, and the two read results are temporarily stored in two latches, respectively. Each latch is controlled by a corresponding control signal to output the read result at an appropriate time. However, the control signals of the sense amplifier and the two latches may have a racing issue. Summary of the invention

[0004] Therefore, an object of the present invention is to provide a more robust and efficient pseudo dual-port memory to solve the above problems.

[0005] According to one embodiment of the present invention, a pseudo dual-port memory is disclosed. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing controller and an output circuit. The multiplexer is configured to receive a first address and a second address, and output the first address and the second address to the single-port memory. The timing control circuit is configured to generate a multiplexer control signal to control the multiplexer to sequentially output the first address and the second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first read result corresponding to the first address and a second read result corresponding to the second address. In addition, the output circuit includes a sense amplifier and a demultiplexer. The sense amplifier is configured to receive output data from the single-port memory to generate data according to a control signal, wherein the control signal is generated according to the first control signal and the second control signal generated by the timing control circuit. The demultiplexer is configured to output data to a first latch when a first control signal has an enabled state, and to output data to a second latch when a second control signal has an enabled state, wherein the data stored in the first latch is used as a first read result, and the data stored in the second latch is used as a second read result.

[0006] According to another embodiment of the present invention, a pseudo dual-port memory is disclosed. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing controller and an output circuit. The multiplexer is configured to receive a first address and a second address, and output the first address and the second address to the single-port memory. The timing control circuit is configured to generate a multiplexer control signal to control the multiplexer to sequentially output the first address and the second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first read result corresponding to the first address and a second read result corresponding to the second address. In addition, the output circuit includes a first sense amplifier and a second sense amplifier. The first sense amplifier is configured to receive output data from the single-port memory according to a first control signal to generate first data to a first latch, wherein the first data stored in the first latch is used as the first read result. The second sense amplifier is configured to receive output data from the single-port memory according to a second control signal to generate second data to a second latch, wherein the second data stored in the second latch is used as the second read result.

[0007] According to another embodiment of the present invention, a control method of a pseudo dual-port memory is disclosed, wherein the pseudo dual-port memory includes a single-port memory, a multiplexer and an output circuit. The multiplexer is configured to: receive a first address and a second address, and output the first address and the second address to the single-port memory. The output circuit includes a first sense amplifier and a second sense amplifier. The control method includes the following steps: in the first half of the clock cycle of the pseudo dual-port memory: control the multiplexer to input the first address into the single-port memory; and, enable the first sense amplifier to receive the output data of the single-port memory to generate the first data, wherein the first data is used as the first read result corresponding to the first address; in the second half of the clock cycle of the pseudo dual-port memory: control the multiplexer to input the second address into the single-port memory; and, enable the second sense amplifier to receive the output data of the single-port memory to generate the second data, wherein the second data is used as the second read result corresponding to the first address.

[0008] Those skilled in the art will no doubt understand these and other objects of the present invention after reading the following detailed description of the preferred embodiments shown in the accompanying drawings. The detailed description will be given in the following embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 4 is a schematic diagram of a pseudo dual-port memory according to an embodiment of the present invention.

[0010] Figure 2 A circuit within a portion of a single-port memory and a circuit within a portion of an output circuit are shown according to an embodiment of the present invention.

[0011] Figure 3 A schematic diagram of a sense amplifier is shown according to an embodiment of the present invention.

[0012] Figure 4 According to an embodiment of the present invention, Figure 2 and Figure 3 Timing diagram of some signals shown.

[0013] Figure 5 A circuit within a portion of a single-port memory and a circuit within a portion of an output circuit are shown according to another embodiment of the present invention.

[0014] Figure 6 According to an embodiment of the present invention, Figure 5 and Figure 3 Timing diagram of some signals shown.

[0015] In the following detailed description, for the purpose of illustration, many specific details are set forth so that those skilled in the art can more thoroughly understand the embodiments of the present invention. However, it is apparent that one or more embodiments may be implemented without these specific details, and different embodiments may be combined as needed, and should not be limited to the embodiments listed in the accompanying drawings. DETAILED DESCRIPTION

[0016] The following description is a preferred embodiment of the present invention, which is only used to illustrate the technical features of the present invention, and is not used to limit the scope of the present invention. Certain words are used throughout the specification and claims to refer to specific components. It should be understood by those skilled in the art that manufacturers may use different names to refer to the same components. Therefore, the present specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of the components as a basis for distinction. The terms "component", "system" and "device" used in the present invention can be entities related to computers, wherein the computer can be hardware, software, or a combination of hardware and software. The terms "including" and "comprising" mentioned in the following description and claims are open-ended terms, so they should be interpreted as "including, but not limited to...". In addition, the term "coupled" means an indirect or direct electrical connection. Therefore, if a device is described as coupled to another device, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0017] Corresponding numbers and symbols in the various figures of the drawings generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly illustrate the relevant parts of the embodiments and are not necessarily drawn to scale.

[0018] The term "substantially" or "approximately" as used herein means that within an acceptable range, a person skilled in the art can solve the technical problem to be solved and basically achieve the technical effect to be achieved. For example, "approximately equal to" means that a certain error from "completely equal to" is acceptable to a person skilled in the art without affecting the correctness of the result.

[0019] The present invention provides a time-interleaving sensing scheme for a pseudo dual-port memory. Figure 1 FIG. 1 is a schematic diagram of a pseudo dual-port memory 100 according to an embodiment of the present invention. Figure 1As shown, the pseudo dual-port memory 100 includes a single-port memory 110, a multiplexer 120 (labeled as "Mux"), a timing control circuit 130 and an output circuit 140. The pseudo dual-port memory 100 is designed to perform two operations on the single-port memory 110 using a time-interleaving mechanism within a single clock cycle. For example, Figure 1 It is shown that two read operations are performed within one cycle of the clock signal CK (e.g., marked as "1T" in the figure). In this embodiment, the pseudo dual-port memory 100 is a pseudo dual-port static random access memory (SRAM), that is, the single-port memory 110 includes a plurality of SRAM cells.

[0020] In the operation of the pseudo dual-port memory 100, the multiplexer 120 can receive two addresses A_adr and B_adr. In the first half of the clock cycle, the timing controller 130 generates a multiplexer control signal to control the multiplexer 120 to output the address A_adr to the single-port memory 110, so that the single-port memory 110 selects one memory cell corresponding to the address A_adr to generate output data to the output circuit 140, and then the output circuit 140 outputs the read result ADO according to the output data. Then, in the second half of the clock cycle, the timing controller 130 generates the multiplexer control signal to control the multiplexer 120 to output the address B_adr to the single-port memory 110, so that the single-port memory 110 selects one memory cell corresponding to the address B_adr to generate output data to the output circuit 140, and then the output circuit 140 outputs the read result BDO according to the output data. By utilizing this time interleaving mechanism, the pseudo dual-port memory 100 is able to sequentially perform two read operations (illustrated by “Read” in the figure) within a single clock cycle to output two read results ADO (e.g., a read result “Result (A_adr)” corresponding to address A_adr within a single clock cycle) and BDO (e.g., a read result “Result (B_adr)” corresponding to address B_adr within a single clock cycle).

[0021] Figure 2 According to an embodiment of the present invention, a circuit 210 in a portion of a single-port memory 110 and a circuit 220 in a portion of an output circuit 140 are shown. Figure 2 As shown, the single-port memory 110 includes a memory cell array, each memory cell is used to store one bit. Circuit 210 shows some memory cells belonging to a complementary bit line pair, for example, the complementary bit line pair includes bit lines BL and BLB, and perpendicular to the bit lines are word lines, such as WLi, WLi+1. Circuit 220 in output circuit 140 is coupled to one of the complementary bit line pairs, such as BL and BLB, and circuit 220 is configured to obtain data from bit lines BL / BLB to generate two read results ADO and BDO.

[0022] Specifically, the circuit 220 includes a sense amplifier (SA) 222 , a demultiplexer 226 (shown as “Demux” in the figure), an OR gate, and two latches 228 and 229 . Figure 3 According to an embodiment of the present invention, a sense amplifier 222 is shown, wherein the sense amplifier 222 includes transistors M1-M13, wherein transistor M1 is controlled by a control signal SAE, transistors M4 and M11 are controlled by a signal DLEQ, transistors M5 and M10 are controlled by a signal PBG, which indicates a read operation when set to logic low, and transistors M6 and M9 are controlled by a pre-charge signal PRE. The sense amplifier 222 is configured to receive signals from bit lines BL and BLB to generate signals DL and DLB and generate a signal GBL based on the signals DL and DLB to subsequent circuits (such as Figure 3 ). For example, in the initial state, the signals DL and DLB are both logic high, so that the signal GBL maintains the previous state. During operation, if the signal DL is logic low, the signal GBL is logic low, and if the signal DLB is logic low, the signal GBL is logic high. Since the operation of the sense amplifier 222 is well known to those skilled in the art, a detailed description of the transistors M1-M13 is omitted here. Figure 4 According to an embodiment of the present invention, a timing diagram of some signals in the circuit 210 and the circuit 220 is shown. Figures 1 to 4Regarding the operation of the circuit 210 and the circuit 220, the timing control circuit 130 generates a first control signal A_SAE and a second control signal B_SAE to the circuit 220, wherein the first control signal A_SAE is used to control the circuit 220 to generate a read result ADO corresponding to the first read operation, and the second control signal B_SAE is used to control the circuit 220 to generate a read result BDO corresponding to the second read operation. For example, in the first half of the clock cycle, the timing controller 130 generates a multiplexer control signal to control the multiplexer 120 to output the address A_adr to the single-port memory 110, and the single-port memory 110 selects a memory cell corresponding to the address A_adr to generate output data at the bit lines BL and BLB. Then, the timing control circuit 130 generates a first control signal A_SAE with an enable state, and the OR gate 224 receives the first control signal A_SAE to generate a control signal SAE with an enable state to control the sense amplifier 222 to generate signals DL and DLB to generate and output the signal GBL based on the signals DL and DLB. At this time, the demultiplexer 226 is controlled by the first control signal A_SAE with an enable state to output data A_GBL (e.g., a part of the signal GBL) to the latch 228, wherein the data stored in the latch 228 is used as (serves as) the read result ADO. Then, in the second half of the clock cycle, the timing controller 130 generates a multiplexer control signal to control the multiplexer 120 to output the address B_adr to the single-port memory 110, and the single-port memory 110 selects a memory cell corresponding to the address B_adr to generate output data at the bit lines BL and BLB. Then, the timing control circuit 130 generates a second control signal B_SAE having an enable state, and the OR gate 224 receives the second control signal B_SAE to generate a control signal SAE having an enable state to control the sense amplifier 222 to generate signals DL and DLB to output the signal GBL. At this time, the demultiplexer 226 is controlled by the second control signal B_SAE having an enable state to output data B_GBL (e.g., a portion of the signal GBL) to the latch 229, wherein the data stored in the latch 229 is used as the read result BDO.

[0023] It can be known from the above description that since only the first control signal A_SAE and the second control signal B_SAE are used to control the sense amplifier 222 and the demultiplexer 226 , the new design of the circuit 220 will not have the racing issue that occurred in the previous design.

[0024] However, in Figure 2In the embodiment shown, the timing is dominated or controlled by the pre-charging of the signals DL / DLB, so efficiency may be affected. Specifically, the B-port is triggered after the signal DLB is in the pre-charging state, so switching from the A-port to the B-port requires a longer setup time (i.e., Figure 4 In order to overcome this problem, the A port indicates a read operation corresponding to the first half of the clock cycle, and the B port indicates a read operation corresponding to the second half of the clock cycle. Figure 5 According to another embodiment of the present invention, a circuit 510 in a portion of the single-port memory 110 and a circuit 520 in a portion of the output circuit 140 are shown. Figure 5 As shown, the single-port memory 110 includes a memory cell array, each memory cell is used to store one bit. Circuit 510 shows some memory cells belonging to a complementary bit line pair, for example, the complementary bit line pair includes bit lines BL and BLB, and perpendicular to the bit lines are word lines such as WLi, WLi+1. Circuit 520 in output circuit 140 is coupled to a complementary bit line pair such as BL and BLB, and circuit 520 is configured to obtain data from bit lines BL / BLB to generate two read results ADO and BDO.

[0025] Specifically, circuit 520 includes two sense amplifiers 522 and 524 and two latches 526 and 528, wherein each sense amplifier 522 and 524 may have Figure 3 The structure shown. Figure 6 The timing diagram of some signals in the circuit 510 and the circuit 520 is shown. Figure 1 , Figure 5 and Figure 6 Regarding the operation of the circuit 510 and the circuit 520, in the first half of the clock cycle, the timing controller 130 generates a multiplexer control signal to control the multiplexer 120 to output the address A_adr to the single-port memory 110, and the single-port memory 110 selects a memory cell corresponding to the address A_adr to generate output data at the bit lines BL and BLB. Then, the timing control circuit 130 generates a first control signal A_SAE having an enable state to control the sense amplifier 522 to generate data A_GBL (for example, Figure 6"A_DLB" shown) to latch 526, wherein the data stored in latch 526 is used as the read result ADO; at the same time, the second control signal B_SAE does not have an enabled state, so that when the sense amplifier 522 is enabled, the sense amplifier 524 does not output any valid data. Then, in the second half of the clock cycle, the timing controller 130 generates a multiplexer control signal to control the multiplexer 120 to output the address B_adr to the single-port memory 110, and the single-port memory 110 selects a memory cell corresponding to the address B_adr to generate output data at the bit lines BL and BLB. Then, the timing control circuit 130 generates a second control signal B_SAE with an enabled state to control the sense amplifier 524 to generate data B_GBL (for example, Figure 6 "B_DLB" shown in the figure) to latch 528, wherein the data stored in latch 528 is used as the read result BDO; at the same time, the first control signal A_SAE does not have an enabled state, so that when the read amplifier 524 is enabled, the read amplifier 522 does not output any valid data.

[0026] exist Figure 5 In the embodiment shown, the timing is determined by the precharge of the bit lines BL / BLB, so that Figure 6 As shown in Figure 1, the signal at port B and the signal at port A can partially overlap. Therefore, the setup time for switching from port A to port B (i.e. Figure 6 The "ST" shown) is small, and the circuit 520 can operate at a faster speed to have better efficiency.

[0027] In brief summary, in the pseudo dual-port memory of the present invention, the output circuit is controlled by only two control signals A_SAE and B_SAE to receive the output data from the single-port memory and output two read results in a single clock cycle. Therefore, the present invention does not have the problem of racing between many control signals. In one embodiment, the two sense amplifiers are separately designed to output two read results in one clock cycle to improve the efficiency of the pseudo dual-port memory.

[0028] Although the present invention has been described by way of example and in terms of preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. Instead, it is intended to cover various modifications and similar structures (as will be apparent to those skilled in the art), for example, combinations or replacements of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar structures.

Claims

1. A pseudo dual-port memory, characterized in that: include: Single-port memory; a multiplexer configured to receive a first address and a second address, and output the first address and the second address to the single-port memory; A timing control circuit is configured to generate a multiplexer control signal to control the multiplexer to sequentially output the first address and the second address to the single-port memory; as well as, An output circuit is configured to perform two read operations on a same bit line of the single-port memory in a single clock cycle to generate a first read result corresponding to the first address and a second read result corresponding to the second address; The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier and the second sense amplifier are coupled to a complementary bit line pair of the single-port memory for the same bit line. The first sense amplifier is configured to receive output data from the single-port memory through the complementary bit line pair to generate first data to the first latch according to a first control signal, wherein the first data stored in the first latch is used as the first read result; and the second sense amplifier is configured to receive output data from the single-port memory through the same complementary bit line pair to generate second data to the second latch according to a second control signal, wherein the second data stored in the second latch is used as the second read result.

2. The pseudo dual-port memory according to claim 1, wherein: The timing controller generates the multiplexer control signal to control the multiplexer to sequentially output the first address and the second address to the single-port memory within a single clock cycle, and the timing control circuit also generates the first control signal and the second control signal to sequentially enable the first read amplifier and the second read amplifier.

3. The pseudo dual-port memory according to claim 2, wherein: When the first control signal has an enabled state, the first sense amplifier generates the first data to the first latch; when the second control signal has an enabled state, the second sense amplifier generates the second data to the second latch; and the enable state of the first control signal and the enable state of the second control signal are within the single clock cycle.

4. The pseudo dual-port memory according to claim 1, wherein: The timing of generating the second data partially overlaps with the timing of generating the first data.

5. A control method for a pseudo dual-port memory, characterized in that: The pseudo dual-port memory includes: Single-port memory; a multiplexer configured to receive a first address and a second address, and output the first address and the second address to the single-port memory; and, An output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier and the second sense amplifier are coupled to a complementary bit line pair of the single-port memory for the same bit line; The control method comprises the following steps: In the first half of a single clock cycle of this pseudo-dual-port memory: Controlling the multiplexer to input the first address into the single-port memory; enabling the first sense amplifier to receive the output data of the single-port memory through the complementary bit line pair to generate first data, wherein the first data is used as a first read result corresponding to the first address; and, In the second half of this single clock cycle of the pseudo dual-port memory: Controlling the multiplexer to input the second address into the single-port memory; The second sense amplifier is enabled to receive the output data of the single-port memory through the same complementary bit line pair to generate second data, wherein the second data is used as a second read result corresponding to the second address.

6. The control method according to claim 5, characterized in that: The timing of generating the second data partially overlaps with the timing of generating the first data.

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